Answer 2)

HDL code:
module test(f,fa,a,g,r);
input f;
input fa;
output a;
output g;
output r;
wire y1;
wire y2;
assign y1 = (f)&(fa);
assign y2 = (f)&(~y1);
assign a = y2;
assign g = (~y1)&(~y2);
assign r = y1 | y2;
endmodule
Schematic:

Waveform:

Testbench:
module test_bench();
reg f;
reg fa;

//output pattern;
//output [2:0] count;
wire a;
wire g;
wire r;
test uut(
.f(f),
.fa(fa),
.a(a),
.g(g),
.r(r)
);
initial
begin
f = 1'b0;
fa = 1'b0;
end
initial
begin
#10 f = 1'b1;
fa = 1'b0;
#10 f = 1'b1;
fa = 1'b1;
#10 f = 1'b0;
fa = 1'b1;
end
endmodule
Reports:
****************************************
Report : area
Design : test_1
Version: B-2008.09-SP2
Date : Sun Oct 13 14:50:37 2013
****************************************
Library(s) Used:
class (File: /home/cad/synopsys_2007.12/syn/libraries/syn/class.db)
Number of ports:
Number of nets:
Number of cells:

5
8
6

Number of references:

Combinational area:
10.000000
Noncombinational area:
0.000000
Net Interconnect area: undefined (Wire load has zero net area)
Total cell area:
Total area:

10.000000
undefined

****************************************
Report : power
-analysis_effort low
Design : test_1
Version: B-2008.09-SP2
Date : Sun Oct 13 14:51:10 2013
****************************************

Library(s) Used:
class (File: /home/cad/synopsys_2007.12/syn/libraries/syn/class.db)
Information: The cells in your design are not characterized for internal power. (PWR-229)
Operating Conditions:
Wire Load Model Mode: top
Design
Wire Load Model
Library
-----------------------------------------------test_1
05x05
class

Global Operating Voltage = 5

Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 0.100000ff
Time Units = 1ns
Dynamic Power Units = 100nW (derived from V,C,T units)
Leakage Power Units = Unitless

Cell Internal Power = 0.0000 nW (0%)

Net Switching Power = 1.2550 uW (100%)
--------Total Dynamic Power = 1.2550 uW (100%)
Cell Leakage Power

= 0.0000

****************************************
Report : timing
-path full
-delay max
-max_paths 1
-sort_by group
Design : test_1
Version: B-2008.09-SP2
Date : Sun Oct 13 14:51:53 2013
****************************************
Operating Conditions:
Wire Load Model Mode: top
Startpoint: f (input port)
Endpoint: g (output port)
Path Group: (none)
Path Type: max
Des/Clust/Port Wire Load Model
-----------------------------------------------test_1
05x05
class

Library

Point
Incr
Path
----------------------------------------------------------input external delay
0.00
0.00 f
f (in)
0.00
0.00 f
C9/Z (AN2I)
0.64
0.64 f
I_0/Z (IVI)
0.29
0.93 r
C10/Z (AN2I)
0.40
1.33 r
I_1/Z (IVI)
0.12
1.45 f
C12/Z (AN2I)
0.58
2.03 f
g (out)
0.00
2.03 f
data arrival time
2.03
-----------------------------------------------------------

Answer 3)
HDL Code:
module test4(x3,x2,x1,zout,y1,y2,y3);
input x3;
input x2;
input x1;
output zout;
output y1;
output y2;
output y3;

assign y3 = ~((~((~x3)&(x2)&(~x1)&(~y3)&(y2)&(y1))) & (~((~x3)&(x2)&(~x1)&(y3)&(y2)&(y1))) &

(~((~x3)&(x2)&(~x1)&(y3)&(y2)&(~y1))) &
(~((~x3)&(x2)&(~x1)&(y3)&(~y2)&(~y1))));
assign y2 = ~((~((~x3)&(~x2)&(x1)&(~y3)&(y2)&(y1))) &
(~((~x3)&(x2)&(x1)&(~y3)&(~y2)&(y1))) &
(~((~x3)&(x2)&(x1)&(~y3)&(y2)&(y1))) &
(~((~x3)&(x2)&(~x1)&(~y3)&(y2)&(y1))) &
(~((~x3)&(x2)&(~x1)&(y3)&(y2)&(y1))) &
(~((x3)&(x2)&(x1)&(~y3)&(y2)&(y1)))) ;
assign y1 = ~((~((~x3)&(x2)&(x1)&(~y3)&(~y2)&(y1))) &
(~((~x3)&(x2)&(x1)&(~y3)&(y2)&(y1))) &
(~((~x3)&(x2)&(~x1)&(~y3)&(y2)&(y1))) &
(~((x3)&(x2)&(x1)&(~y3)&(~y2)&(y1))) &
(~((x3)&(~x2)&(x1)&(~y3)&(~y2)&(y1))) &
(~((x3)&(~x2)&(x1)&(~y3)&(~y2)&(~y1)))) ;
assign zout = ~((~((~y1)&(y3))) & (~((y2)&(y3))));
endmodule
Schematic:

Waveform:
I have considered two cases as shown below as seen the ouput is only 1 when the sequence matches.

Testbench:
module test_bench();
reg x3;
reg x2;
reg x1;
wire y1;
wire y2;
wire y3;
wire zout;
test4 uut(
.x3(x3),
.x2(x2),
.x1(x1),
.zout(zout),

.y1(y1),
.y2(y2),
.y3(y3)
);

initial
begin
x3 = 1'b0;
x2 = 1'b0;
x1 = 1'b0;
end
initial
begin
#10 x3 = 1'b1;
x2 = 1'b0;
x1 = 1'b1;
#10 x3 = 1'b1;
x2 = 1'b0;
x1 = 1'b1;
#10 x3 = 1'b1;
x2 = 1'b1;
x1 = 1'b1;
#10 x3 = 1'b0;
x2 = 1'b1;
x1 = 1'b1;
#10 x3 = 1'b0;
x2 = 1'b1;
x1 = 1'b0;
end
endmodule
Reports:
****************************************
Report : area
Design : test4_1
Version: B-2008.09-SP2
Date : Sun Oct 13 23:32:10 2013
****************************************
Library(s) Used:
class (File: /home/cad/synopsys_2007.12/syn/libraries/syn/class.db)

Number of ports:
7
Number of nets:
104
Number of cells:
101
Number of references:
2
Combinational area:
174.000000
Noncombinational area:
0.000000
Net Interconnect area: undefined (Wire load has zero net area)
Total cell area:
Total area:

174.000000
undefined

****************************************
Report : power
-analysis_effort low
Design : test4_1
Version: B-2008.09-SP2
Date : Sun Oct 13 23:32:31 2013
****************************************

Library(s) Used:
class (File: /home/cad/synopsys_2007.12/syn/libraries/syn/class.db)
Information: The cells in your design are not characterized for internal power. (PWR-229)
Operating Conditions:
Wire Load Model Mode: top
Design
Wire Load Model
Library
-----------------------------------------------test4_1
05x05
class

Global Operating Voltage = 5

Power-specific unit information :
Voltage Units = 1V
Capacitance Units = 0.100000ff
Time Units = 1ns
Dynamic Power Units = 100nW (derived from V,C,T units)
Leakage Power Units = Unitless

Cell Internal Power = 0.0000 nW (0%)

Net Switching Power = 9.6666 uW (100%)
--------Total Dynamic Power = 9.6666 uW (100%)

Cell Leakage Power

= 0.0000

****************************************
Report : timing
-path full
-delay max
-max_paths 1
-sort_by group
Design : test4_1
Version: B-2008.09-SP2
Date : Sun Oct 13 23:33:03 2013
****************************************
Operating Conditions:
Wire Load Model Mode: top
Startpoint: x3 (input port)
Endpoint: zout (output port)
Path Group: (none)
Path Type: max
Des/Clust/Port Wire Load Model
-----------------------------------------------test4_1
05x05
class

Library

Point
Incr
Path
----------------------------------------------------------input external delay
0.00
0.00 r
x3 (in)
0.00
0.00 r
I_0/Z (IVI)
0.31
0.31 f
C49/Z (AN2I)
0.64
0.94 f
C51/Z (AN2I)
0.61
1.55 f
C50/Z (AN2I)
0.64
2.18 f
C69/Z (AN2I)
0.61
2.79 f
C68/Z (AN2I)
0.61
3.39 f
I_13/Z (IVI)
0.24
3.64 r
C59/Z (AN2I)
0.34
3.98 r
C58/Z (AN2I)
0.34
4.32 r
C57/Z (AN2I)
0.34
4.66 r
C56/Z (AN2I)
0.34
5.00 r
C55/Z (AN2I)
0.34
5.34 r
I_10/Z (IVI)
0.75
6.10 f
C28/Z (AN2I)
0.64
6.73 f
C40/Z (AN2I)
0.61
7.34 f
I_6/Z (IVI)
0.24
7.58 r
C33/Z (AN2I)
0.34
7.92 r
C32/Z (AN2I)
0.34
8.26 r

C31/Z (AN2I)
0.34
8.60 r
I_3/Z (IVI)
0.38
8.98 f
I_5/Z (IVI)
0.66
9.65 r
C91/Z (AN2I)
0.39 10.04 r
C107/Z (AN2I)
0.34 10.38 r
C106/Z (AN2I)
0.34 10.72 r
I_19/Z (IVI)
0.12 10.85 f
C104/Z (AN2I)
0.61 11.45 f
C103/Z (AN2I)
0.61 12.06 f
C102/Z (AN2I)
0.61 12.66 f
C101/Z (AN2I)
0.61 13.27 f
C100/Z (AN2I)
0.61 13.87 f
I_18/Z (IVI)
0.93 14.80 r
I_2/Z (IVI)
0.31 15.11 f
C131/Z (AN2I)
0.61 15.72 f
I_26/Z (IVI)
0.24 15.96 r
C129/Z (AN2I)
0.34 16.30 r
I_25/Z (IVI)
0.07 16.37 f
zout (out)
0.00 16.37 f
data arrival time
16.37
----------------------------------------------------------(Path is unconstrained)