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Q3. Design a modulo-5 counter using D flip-flop the unused states of which go to one of
the valid counting state at next clock trigger.
Q4. Design a circuit using JK flip-flop that behaves both as a modulo-5 and modulo-3
counter depending on how it is initialized.
Q5. Show how modulo-8 switched tail counter works if is initialized with ‘1001’.
Q6. Design a sequence generator with minimum number of flip-flops that generates
sequence ‘110001’ repetitively.