`include "fifo.

sv" module test2; parameter ADDSIZE=2; parameter WIDTH=32; parameter DEPTH=4; wire [WIDTH-1:0]rdata; wire full,empty; reg [WIDTH-1:0]wdata; reg ren,wen,clk,rst; fifo1 dut(wdata,rdata,full,empty,ren,wen,clk,rst); initial clk=0; always #1 clk=~clk; initial begin $monitor ("clk=%d full=%d empty=%d ren=%d wen=%d rst=%d wdata=%d rdata=%d wptr =%d rptr=%d",clk,full,empty,dut.ren,dut.wen,dut.rst,wdata,rdata,dut.bin_wptr,dut .bin_rptr); #1 write; #2 write; #2 write; #2 write; #20 $stop; end task write; static integer data=0; data=data+1; wdata=data; endtask endmodule