CS 152 Computer Architecture and Engineering Lecture 12: Designing a Multicycle Processor

March 10, 1998 John Wawrzynek (http.cs.berkeley.edu/~johnw) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/

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Administrative Issues
Read Chapter 5 This lecture and next one slightly different from the book Thursday lecture -- Nick Weaver

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Recap: Processor Design is a Process

Bottom-up
assemble components in target technology to establish critical timing

Top-down
specify component behavior from high-level requirements

Iterative refinement
establish partial solution, expand and improve Instruction Set Architecture

=>
datapath

processor

control

Reg. File

Mux

ALU

Reg

Mem

Decoder

Sequencer

Cells
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Gates
SP98, U.CB

Recap: A Single Cycle Datapath

We have everything except control signals (underline)
Todays lecture will show you how to generate the control signals
Instruction<31:0> nPC_sel Rd RegDst Rt Rs 5 5 busA 32 0 Mux ALU Rt Clk ALUctr Instruction Fetch Unit <21:25> <16:20> <11:15> <0:15>

1 Mux 0 RegWr 5

Rt Zero

Rs

Rd

Imm16 MemtoReg 0 Mux

busW 32 Clk

Rw Ra Rb 32 32-bit Registers busB 32 Extender

MemWr

32 32 WrEn Adr

1 32

imm16

Data In 32 Clk

16

Data Memory

ALUSrc ExtOp
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Recap: The Truth Table for the Main Control

RegDst op 6 ALUSrc Main Control func 6 ALU Control (Local) ALUctr 3

:
ALUop 3 00 0000 R-type 1 0 0 1 0 0 0 x R-type 1 0 0

op RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop (Symbolic) ALUop <2> ALUop <1> ALUop <0>
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00 1101 10 0011 10 1011 00 0100 00 0010 ori 0 1 0 1 0 0 0 0 Or 0 1 0 lw 0 1 1 1 0 0 0 1 Add 0 0 0 sw x 1 x 0 1 0 0 1 Add 0 0 0 beq x 0 x 0 0 1 0 x Subtract 0 0 1 jump x x x 0 0 0 1 x xxx x x x
SP98, U.CB

Recap: PLA Implementation of the Main Control

op<5>

..

op<5>

..

op<5>

..

op<5>

..

op<5>

..
<0>

op<5>

..
op<0>

<0>

<0>

<0>

<0>

R-type

ori

lw

sw

beq

jump

RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump ExtOp ALUop<2> ALUop<1> ALUop<0>

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Recap: Systematic Generation of Control

OPcode

Decode Conditions Instruction

Control Logic / Store (PLA, ROM) microinstruction Control Points

Datapath

In our single-cycle processor, each instruction is realized by exactly one control command or microinstruction
in general, the controller is a finite state machine microinstruction can also control sequencing (see later)
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The Big Picture: Where are We Now? The Five Classic Components of a Computer
Processor Input Control Memory Datapath

Output

Todays Topic: Designing the Datapath for the Multiple Clock Cycle Datapath

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cs 152 L12 Multicycle.9 SP98, U.CB

Abstract View of our single cycle processor

nPC_sel

Next PC PC Instruction Fetch fun op

Register Fetch

Equal

Main Control

Ext ALU Mem Access Data Mem Reg. Wrt

ExtOp ALUSrc ALUctr

ALU control

MemRd MemWr

RegDst RegWr MemWr

Result Store

Whats wrong with our CPI=1 processor?

Arithmetic & Logical PC Inst Memory Load PC Store PC Branch PC Reg File ALU
setup

mux

mux

Inst Memory

mux Reg File Critical Path

ALU

Data Mem

mux setup

Inst Memory Inst Memory

Reg File Reg File

mux

ALU

Data Mem

cmp

mux

Long Cycle Time All instructions take as much time as the slowest Real memory is not so nice as our idealized memory
cannot always get the job done in one (short) cycle
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Memory Access Time

Physics => fast memories are small (large memories are slow)
Storage Array selected word line storage cell address bit line address decoder question: register file vs. memory

sense amps

proc. bus

=> Use a hierarchy of memories

mem. bus

Processor

Cache 1 cycle

L2 Cache 2-3 cycles

memory

20 - 50 cycles
SP98, U.CB

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Reducing Cycle Time

Cut combinational dependency graph and insert register / latch Do same work in two fast cycles, rather than one slow one
storage element storage element

Acyclic Combinational Logic

Acyclic Combinational Logic (A)

=>
storage element

storage element Acyclic Combinational Logic (B) storage element

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Basic Limits on Cycle Time

Next address logic
PC <= branch ? PC + 4 + offset : PC + 4

Instruction Fetch
InstructionReg <= Mem[PC]

Register Access
A <= R[rs]

ALU operation
R <= A + B
nPC_sel

Control
MemRd MemWr ALUSrc ALUctr ExtOp MemWr
SP98, U.CB

RegDst RegWr

PC

Exec

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Data Mem

Result Store

Instruction Fetch

Operand Fetch

Next PC

Mem Access

Reg. File

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Add registers between smallest steps

Partitioning the CPI=1 Datapath

Next PC PC Instruction Fetch

nPC_sel

Operand Fetch
ExtOp

Mem Access Data Mem Reg. File

Result Store

Exec

ALUSrc ALUctr MemRd MemWr

RegDst RegWr MemWr

cs 152 L12 Multicycle.15 SP98, U.CB

Critical Path ?

Example Multicycle Datapath

Next PC PC

nPC_sel

Instruction Fetch
IR

Operand Fetch
B Mem Access M Data Mem

Reg File Ext ALU R

MemRd MemWr
MemToReg

Result Store

RegDst Reg. RegWr File Equal

A
ExtOp ALUSrc ALUctr

Recall: Step-by-step Processor Design Step 1: ISA => Logical Register Transfers Step 2: Components of the Datapath Step 3: RTL + Components => Datapath Step 4: Datapath + Logical RTs => Physical RTs Step 5: Physical RTs => Control

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Step 4: R-rtype (add, sub, . . .)

Logical Register Transfer Physical Register Transfers
inst ADDU inst ADDU Logical Register Transfers R[rd] < R[rs] + R[rt]; PC < PC + 4 Physical Register Transfers IR < MEM[pc] A< R[rs]; B < R[rt] S < A + B R[rd] < S; PC < PC + 4

Inst. Mem

Next PC

PC

A B

Exec

Reg File

IR

S Mem Access M Data Mem

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Reg. File

Equal

Step 4:Logical immed

Logical Register Transfer Physical Register Transfers
inst ADDU inst ADDU Logical Register Transfers R[rt] < R[rs] OR zx(Im16); PC < PC + 4 Physical Register Transfers IR < MEM[pc] A< R[rs]; B < R[rt] S < A or ZeroExt(Im16) R[rt] < S; PC < PC + 4

Inst. Mem

Next PC

PC

A B

Exec

Reg File

IR

S Mem Access M Data Mem

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Reg. File

Equal

Step 4 : Load
Logical Register Transfer Physical Register Transfers
inst LW Logical Register Transfers R[rt] < MEM(R[rs] + sx(Im16); PC < PC + 4 inst LW Physical Register Transfers IR < MEM[pc] A< R[rs]; B < R[rt] S < A + SignEx(Im16) M < MEM[S] R[rd] < M; PC < PC + 4

Inst. Mem

Next PC

PC

A B

Exec

Reg File

IR

S Mem Access M Data Mem

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Reg. File

Equal

Step 4 : Store
Logical Register Transfer
inst SW Logical Register Transfers MEM(R[rs] + sx(Im16) < R[rt]; PC < PC + 4 inst Physical Register Transfers IR < MEM[pc] SW A< R[rs]; B < R[rt] S < A + SignEx(Im16); MEM[S] < B PC < PC + 4

Physical Register Transfers

Inst. Mem

Next PC

PC

A B

Exec

Reg File

IR

S Mem Access M Data Mem

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Reg. File

Equal

Step 4 : Branch
Logical Register Transfer
inst BEQ Logical Register Transfers if R[rs] == R[rt] then PC <= PC + sx(Im16) || 00

Physical Register Transfers

inst Physical Register Transfers IR < MEM[pc] BEQ|Eq PC < PC + 4 inst

else PC <= PC + 4 Physical Register Transfers IR < MEM[pc] BEQ|Eq PC < PC + sx(Im16) || 00

Inst. Mem

Next PC

PC

A B

Exec

Reg File

IR

S Mem Access M Data Mem

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Reg. File

Equal

Alternative datapath (book): Multiple Cycle Datapath

Miminizes Hardware: 1 memory, 1 adder
PCWr IorD PC
32 32 32 0 RAdr

PCWrCond Zero MemWr

32 Rs 32 Rt Rt 0 Rd 1 1 Mux 0 5 5 0

PCSrc IRWr RegDst RegWr ALUSelA

1

BrWr Target

Mux
0 32 0 1 2 3 32

32

Zero ALU Out ALU

Mux

Instruction Reg

Ra Rb Rw busW busB 32 busA 32

32 32

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Mux
1

Ideal Memory
WrAdr 32 Din Dout

Reg File

Mux

32

<< 2

ALU Control

Imm 16

Extend

32

ALUOp ALUSelB
SP98, U.CB

ExtOp

MemtoReg