ic Circui tal Log gi A. P. Godse ical Publications Pune” hn Bisfet Digital Logic Circuits ISBN 9788184317602 Al rights reserved with Technical Publications. No part ofthis book should be reproduced in any form, Electronic, Mechanical, Photocopy or any information storage ond retrieval system without prior permission in writing, from Technical Publications, Pune, Published by : ‘Technical Publications Pune® ‘#1, Amit Residency, 412, Shaniwer Peth, Pune - 411 030, India. Printer : ‘Alert DTPvioters Sino. 10/3,Sinhnged Roed, Pine - 411.041CChapter-1 Review of Binary Number Systems (1-1) to(1-86) Chapter-2 Boolean Algebra (2-1) to (2-84) Chapter-3 Logic Gates (8-1) to(3-42) Chapter-4 Combinational Crcuts (4-1) to (4-96) Chapter-§ Flip-Flops 5-1) to (5 - 100) Chapter-6 Analysis & Dasign of Synchronous Sequential Circuits (6-1)to @- 104) Chapter-7 Asynchronous Sequential Circuits (7-1) to(7-40) Chapter-8 Memories (8-1) to (8-6) Chapter-9 Programmable Logic Devices (PLDs) (@-1)t0 (9-56) Chapter-10 Logic Families ; (10-1) to (10-58) Chapter-14 RTL Design (14-1) to (14 ~58) Chapter-12 Introduction to VHDL (12- 4)t0 (12-88) Appendix-A Typical Digital ICs (A - 1) to (A - 4) Appendix-B Data Sheets for Commonly used Digital ICs (8-1) to (8-32) Appendix-C Glossary (C-1}to(C-10) Marks Questions and Answers (P= 1) to P -20) | & Stepwise procedure for problem solution. ' %* Number of solved examples to understand procedural steps. | * Catalogue of typical Digital ICs. | & Data sheets of commonly used Digital ICs. | & 2 Marks Questions and Answers. iiiBoolean Algebra and Combinational Circuits (Chapters - 1,2, 3, 4) Boolean algebra : De-Morgan's theorem, Switching functions and simplification using K-maps and Quine Me-Cluskey method, Design of adder, Subtractor, Comparators, Code converters, Encoders, Decoders, Multiplexers and demultiplexer Synchronous Sequential Circuits (Chapters - 5, 6) Flip-Flops : SR, D, JK and T. Analysis of synchronous sequential circuits; Design of synchronous sequential circuits - Counters, State diagram; State reduction; State assignment. Asynchronous Sequential Circuits (Chapter -7) Analysis of asynchronous sequential machines, State assignment, Asynchronous design problem. Programmable Logic Devices, Memory and Logic Families (Chapters - 8, 9, 10) Memories : ROM, PROM, EPROM, PLA, PLD, FPGA, Digital logic families : TTL, ECL, CMOS. VHDL (Chapters - 11, 12) RTL Design - Combinational logic - Types - Operators - Packages - Sequential circuit - Subprograms - Test benches. (Examples : Adders, Counters, Flip-flops, FSM, Multiplexers/Demultiplexers)Table of Contents (Detail) 1.1 Number Systems 1.1.1 Decimal Number System . 1.4.2 Binary Number System. 1.4.3 Octal Number System... 1.1.4 Hexadecimal Number System 41.1.5 Counting in Radix (Base) r.. 1.2 Number Base Conversion 1.2.1 Binary to Octal Conversion 1.2.2 Octal to Binary Conversion. 1.2.3 Binary to Hexadecimal Conversion 1.2.4 Hexadecimal to Binary Conversion 1.2.5 Octal to Hexadecimal Conversion . 1.2.6 Hexadecimal to Octal Conversion . 1.2.7 Converting any Radix to Decimal 1.2.8 Conversion of Decimal Numbers to Any Radix Number. 1.3 Complements..... 1.3.4 1's Complement Representation 4.3.2 2's Complement Representation 1.4 Signed Binary Numbers 1.5 Sign Extension... 1.6 Binary Arithmetic... 1.6.1 Binary Arithmetic - Negative Numbers in 1's Complement Form . 1.6.2 Binary Arithmetic - Negative Numbers in 2's Complement Form . 1.7 Octal Arithmetic. 1.8 Hexadecimal Arithmetic1.9 Binary Codes 1.9.1 Classification of Binary Codes 4.9.2 BCD (Binary Coded Decimal) Codes ..........0.ccecccsesteseeteeeseeseenes 1-33 1.9.2.1 BCD Addition... 1.9.22 BCD Subtraction... . . 1.9.3 Other 4-bit BCD Codes. 1.9.3.1 2-4-2-1 Codes . se 1.9.3.2 Other Weighted BCD Codes... ee 1-43 1.9.4 Excess-3 Code 1.9.4.1 Excess-3 Addition 41-46 WAR GceeS Subba eon toed es oe es oe 41-46 1.9.5 Gray Code .. + 1-48 1.95: Appleton of Gray Cae, ee ee eee 1-49 1.9.5.2 Gray to Binary Conversion. 2. eee 1-50 1.9.5.3 Binary to Gray Code Conversion. 2. ee eee 1-51 1.9.6 Five-bit BCD Codes... 2... eevee eee eee eeeecstseeeeeteeeeeenes 1-52 1.9.7 Biquinary Code... 1-53 1.9.8 Alphanumeric Codes . 1-54 1984 ASCH... EON g 1-54 FOBZEBODICS. 2 occ xv nese one « Bate wn Kom © RIN 1-55 1.10 Error Detecting and Correcting Codes 1-57 1.10.1 Parity Bit a 1-57 1.40.2 Block Parity. ........cececceeeeeeeeeeeeeeeeeeeceeeeseeeee see eneeneeees 1-59 | 1.10.3 Hamming Code. . . 1-60 1.10.4 Linear Block Codes . beeeee 1-66 | 1.104.1 Matrix Representation ofLinear BlockCodes. .. .. 2... ee 1-68 | 1.10.4.2 Generalized Steps for Construction of Code. 4-68 1.104.3 Decoding the Received Codewords. ss ait wan oven 198 ' 11044 EnorComection 2 ee se 4-73 1.10.5 Cyclic Codes .. 1-75 | Review Questions . 1-77 University Questions with Answers.. 1-792.1 Introduction ... 2.2 Boolean Algebra ..... 2.3 Fundamental Postulates of Boolean Algebra... 2.4 Laws of Boolean Algebra..... 2.5 Basic Theorems and Properties of Boolean Algebra 2.5.2 Basic Theorems ....... 2.5.3 DeMorgan's Theorems... . 2.5.4 Consensus Theorem ..... 2.5.5 Dual of Consensus Theorem 2.6 Boolean Expression... 2.6.1 Sum of Product Form 2.6.2 Product of Sum Form 2.7 Standard SOP and POS Forms.. 2.7.1 Standard SOP Form or Minterm Canonical Form 2.7.2 Standard POS Form or Maxterm Canonical Form 2.7.3 Converting Expressions in Standard SOP or POS Forms 2.7.4 MNotations : Minterms and Maxterms. 2.7.5 Complements of Canonical Formulas 2.8 Minimization of Boolean Expression... 2.9 Karnaugh Map (Map) Method of Minimization 2.9.1 One-Variable, Two-Variable, Three-Variable and Four-Variable Maps . 2.9.2 Plotting a Karmaugh Map 2.9.2.1 Representation of Truth Table on Karmaugh Map... 2.8.2.2 Representing Standard SOP on K-Map 2.9.2.3 Representing Standard POSonK-Map.. 2... - 2.9.3 Grouping Cells for Simplification... 2.9.3.1 Grouping Two Adjacent Ones (Pair) 2.9.3.2 Grouping Four Adjacent Ones (Quad). . 2.9.3.3 Grouping Eight Adjacent Ones (Octet). 2.9.4 Illegal Grouping ...2.10 Simplification of SOP Expressions... 2.10.1 Essential Prime Implicants 2.10.2 incompletely Specified Functions (Don't Care Terms)... 2-48 2.10.2.1 Describing Incomplete Boolean Functon. ee ee ee BAD 2.10.2.2 Don't Care Conditions in Logic Design . er re ee, 2.49 2.10.2.3 Minimization of incompletely Specified Functions. . . . Jp x x «0 Example 1.1: Represent decimal number 98.72 in power of 10. Solution : N = 9x10! + 8x 10° + 7x 10°! + 2x 10"? The digit 9 has a weight of 10, the digit 8 has a weight of 1, the digit 7 has a weight of 1/10 and the digit 2 has a weight of 1/100. 1.1.2 Binary Number System We know that decimal system with its ten digits is a base-ten system. Similarly, binary system with its two digits is a base-two system. The two binary digits (bits) are 1 and 0. Like digital system, in binary system each binary digit commonly known as bit, has its own value or weight. However in binary system weight is expressed as a power of 2, as shown in Fig. 1.2. MSB ~ Binary point Fig. 1.2 Binary position values as a power of 2 wm Example 1.2: Represent binary nwnber 1101.101 in power of 2 and find its decimal equivalent. Solution : Representing given binary number in power of 2 we have, N = 1x2941x274 0x 2'41x29+ 1x2) 0x22 41273 = 8+44+0+1+05+0+ 0.125 = 13.6254Digital Logic Circuits 1-3 Review of Binary Number Systems 1.1.3 Octal Number System We know that the base of the decimal number system is 10 because it uses the digits 0 to 9, and the base of binary number system is 2 because it uses digits 0 and 1. The octal number system uses first eight digits of decimal number system : 0, 1, 2, 3, 4,5, 6, and 7. As it uses 8 digits, its base is 8 wm Example 1.3: Represent octal number 567 in power of 8 and find its decimal equivalent. Solution : The given octal number 567 can be represented in power of 8 as = 5x64 + 6x8 +7Xx1= 320+ 4847 = 375; 1.1.4 Hexadecimal Number System ‘The hexadecimal number system has a base of 16 having 16 digits : 0, 1, 2,3, 4, 5, 6,7, 8,9, A,B, C, D, Band F. It is another number system that is particularly useful for human communications with a computer. Although it is somewhat more difficult to interpret than the octal number system, it has become the most popular. Since its base is a power of 2 (2%), it is easy to convert hexadecimal numbers to binary and vice versa. Table 1.1 shows the relationship between decimal, binary and hexadecimal. Note that each hexadecimal digit represents a group of four binary digits, called nibbles, that are fundamental parts of larger binary words. Decimal Binary Hexadecimal 3 3090) 0 1 0001 1 2 0010 2 3 0011 3 4 0100 4 5 0101 5 6 0110 6 7 OT 7 3 7000 3 | 3 700% 3 70 7010 K 4 4011 B 12 1100 c 13 1104 D 14 1110 E 15 att E Table 1.1 Relation between decimal, binary and hexadecimal numbersDigital Logic Circuits 1-4 Review of Binary Number Systems mm> Example 1.4: Represent hexadecimal number 3FD in power of 16 and find its decimal equivalent. Solution : The given hexadecimal number 3FD,, can be represented in power of 16. B se 3FD = 3x256 + F(15)x16 + D(13)x1 768 + 240 + 13 = 21, 1.1.5 Counting in Radix (Base) r In previous sections we have seen number systems with radix (base) r equal to 10, 2, 8 and 16. Each number system has r set of characters. For example, in decimal number system r equals to 10 has 10 characters from 0 to 9, in binary number system r equals to 2 has 2 characters 0 and 1 and so on. In general we can say that, a number represented in radix r, has r characters in its set and r can be any value. This is illustrated in Table. 1.2. Radix (Base) r Characters in set 2 (Binary) 8 (Octal) 10 (Decimal) 1,2, 3,4, 5, 6,7, 8,9 16 (Hexadecimal) 0, 1, 2,3, 4, 5, 6, 7, 8, 9, A,B, C, D, EF Table 1.2 Radix and character setDigital Logic Circuits 1-5 Review of Binary Number Systems nm Example 1.5 : Find the decimal equivalent of (231.23), Solution : N=2xP43xae1xse2xe 43x47? = 32+ 12+1+05 + 0.1875 = 45.6875, ‘=p Example 1.6 : Count from 0 to 9 in radix 5. Solution ; The Table 1.2 indicates that radix 5 has 5 characters. A count sequence from 0 decimal to 9 decimal is 00, 01, 02, 03, 04, 10, 11, 12, 13, 14. 1.2 Number Base Conversion The human beings use decimal number system while computer uses binary number system. Therefore, it is necessary to convert decimal number into its equivalent binary while feeding number into the computer and to convert binary number into its decimal equivalent while displaying result of operation to the human beings. However, dealing with a large quantity of binary numbers of many bits is inconvenient for human beings. Therefore, octal and hexadecimal numbers are used as a shorthand means of expressing large binary numbers. But it is necessary to keep in mind that the digital circuits and systems work strictly in binary; we are using octal and hexadecimal only as a convenience for the operators of the system. Before going to see conversions between binary, octal and hexadecimal numbers we see the number of digits in several number systems. Table 1.3 shows the decimal, binary, octal and hexadecimal numbers. HexadecimalDigital Logic Circuits 1-6 Review of Binary Number Systems "1 10411 13 B 2 1100 14 c 3 1101 15 D “4 1110 16 E 15. 4111 7 FE Table 1.3 Decimal, binary, octal and hexadecimal numbers 1.2.1 Binary to Octal Conversion We know that base for oclal numbers is 8 and the base for binary numbers is 2. The base for octal number is the third power of the base for binary numbers. Therefore, by grouping 3 digits of binary numbers and then converting each group digit to its octal equivalent we can convert binary number to its octal equivalent. ‘> Example 1.7: Convert (111 101 16 0), to octal equivalent. mm 7 5 4 Solution : Octal number = (754), 1.2.2 Octal to Binary Conversion Conversion from octal to binary is a reversal of the process, explained in the previous section. Each digit of the octal number is individually converted to its binary equivalent to get octal to binary conversion of the number isp Example 1.8: Convert (634), to binary. ee] Bee 140 on 100 Solution : Binary number = 110 011 100 wm Example 1.9 ; Convert (72563)s to binary. Solution : 111 010 101s 110° ont Binary number = 111010101 . 110 011Digital Logic Circuits 1-7 Review of Binary Number Systems 1.2.3 Binary to Hexadecimal Conversion We know that base for hexadecimal numbers is 16 and the base for binary numbers is 2. The base for hexadecimal number is the fourth power of the base for binary numbers. Therefore, by grouping 4 digits of binary numbers and then converting each group digit to its hexadecimal equivalent we can convert binary number to its hexadecimal equivalent. yum Example 1.10: Convert (11011000 10011011), to hexadecimal equivalent. D 8 9 B Hexadecimal number = (D89B)); Solution : 1.2.4 Hexadecimal to Binary Conversion Conversion from hexadecimal to binary is a reversal of the process explained in the previous section. Each digit of the hexadecimal number is individually converted to its binary equivalent to get hexadecimal to binary conversion of the number. imp Example 1.14 : Convert (3FD)p, to binary. 0014 4411 1101 Solution = Binary number = 0011 1111 1101 yum Example 1.12: Convert (5A9.B4),, to binary. 0101 «1010 1001S» = 1011-0100 Solution : Binary number = 0101 1010 1001 . 1011 0100 1.2.5 Octal to Hexadecimal Conversion The easiest way to convert octal number to hexadecimal number is given below. 1. Convert octal number to its binary equivalent. 2. Convert binary number to its hexadecimal equivalent.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digital Logic Circuits 1-16 Review of Binary Number Systems pecima | Sianed-2's | Signed-t's | Signed complement | complement | magnitude +7 ont ot ont +8 O10 0110 o1t0 +5 0101 0101 0101 +4 0100 o100 0100 *3 0011 0017 0011 +2 0010 0010 0010 Zz 001 0001 oot +0 0000 (0000 0000 -0 = 1111 1000 -1 1141 1110 1001 | -2 1110 1401 1010 -3 1101 1100 1014 -4 1100 1011 1100 -5 1011 1010 1101 -6 1010 1001 1110 any 1001 1000 111 8 41000 - = | Table 1.4 The Table 14 lists all possible 4-bit signed binary numbers in the three representations. Looking at the Table 1.4 we understand following points : * Positive numbers in all three representations are identical and have 0 in the leftmost position. © All negative numbers have a 1 in the leftmost bit position. © The signed-2's complement system has only one representation for 0, which is always positive. © The signed-magnitude and 1's complement systems have either a positive 0 or a negative 0. © With four bits, we can represent 16 binary numbers. The sign-magnitude representation requires separate handling for sign and magnitude during arithmetic operations and hence it is suitable in computer arithmetic. Therefore, the signed complement numbers are normally used in computer arithmetic. The 1's complement imposes some difficulties and is seldom used for arithmetic operations. It is used as a logical operation since the change of 1 to 0 or 0 to 1 is equivalent to a logical complement operation. The signed-2's complement system is commonly used in computer arithmetic.Digital Logic Circuits 1-17 Review of Binary Number Systems 1.5 Sign Extension We have seen that how to represent binary number in 1's complement and 2's complement form. In this representation it is important to see how such numbers are represented. When we add two binary numbers the result may extend by 1-bit ie. the binary number may need one more bit if there is a carry after addition of most si bit. To represent such result in correct format we have to allocate the additional bit for representing the magnitude of the numbers which are to be added. This is illustrated in Fig. 1.4. o 4 0 0 oO ay +9) + 0 0 0 14 (47) Fig. 1.4 In case of positive binary number we extend the bit by appending bit-0 (sign-bit for positive number) to the left of the most-significant bit of the number. In case of negative binary number can extend the bit by appending bit-1 (sign-bit for negative number) to the left of the most-significant bit of the number. This is illustrated in the Fig. 1.5. In both the case sign-bit of the original number is extended and hence such extension is known as sign-extension of the number. 1. Original number represented 1 0 41 0 0 (20) using 6-bits. wong x ‘Sign-bit Same number represented using = 0 1 0 1:0 0 an 7-bits x Sign-extension ‘Same number represented using B-bits 0 0 1 0 1 0 oO (20) X_ Sign-extension 2. Original number represented 0 0 20) using 6-bits in 2's complement form ‘Same number represented using 7-bits in 2's complement form 0 0 (20) Same number represented using: 1 8-bits in 2's complement form : 0 0 |20) \_ Sign-extension Fig. 1.5Digital Logic Circuits 1-18 Review of Binary Number Systems 1.6 Binary Arithmetic We can relate addition and subtraction operations of numbers by the following relationship : (£ A) - GB) = (¢ A) + CB) and (4 A) ~ CB) = @ A) + (4B) Therefore, we can change subtraction operation to an addition operation by changing the sign of the subtrahend. Hence, the binary addition is the key to binary subtraction, multiplication, and division. So, let us see rules for binary addition. Rules for Binary Addition 1.6.1 Binary Arithmetic - Negative Numbers in 1's Complement Form Case 1 (Both Positive) : Add (28), and (15) 15 2 28 oO LSD 2 1 LSD 2 14 oO 2 1 Ly: 2 1 GI: 5 1 | MSD a 0 +. (011100), 9 (28)yy (01111)) > 15)i9 Addition of 28 and 15: 4 4 1 «Cary + o 1 4 4 0 0 (28) oo 4 1 (15)10 1 oO 1 0 (43hi0aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digital Logic Circuits 1-27 Review of Binary Number Systems 1.8.2 Subtraction Subtraction with 15's Complement The 15's complement of a hexadecimal number is found by subtracting each digit from 15, as illustrated in example 1.40. ime» Example 1.40 : Find 15’s complement of A9Byg. Solution : 15 1515 cd A 9 B 5 6 4g The steps for hexadecimal subtraction using 15's complement method are as_given below : Step 1: Find 15's complement of subtrahend. Step 2: Add two hexadecimal numbers (first number and 15's complement of the second number). Step 3: If carry is produced in the addition, add carry to the least significant bit of the sum; otherwise find 15's complement of the sum as a result with a negative sign. ‘mb Example 1.41: Use the 15's complement method of subtraction to compute BO2g ~ 98F 6. Solution : Step 1: 15 1518 - 9 8 F 6 7 0 © 15's complement Step 2: BOO (2 +6 7 0Digital Logic Circuits 1-28 Step 3: 1¢2 + 1 17 3 . BO2 6 - 98Fie 3 17346 wum> Example 1.42: Use the 15’s complement method of subtraction to compute 69B yg - Cidyg Solution : Step 1: 15 15 15 - Cc 1 4 3. EB © 15% complement Stop 2: 69 B + 3 EB A 8B 6 Step 3: No carry, hence take 15's complement 15 15 15 - A 8 6) 5 7 9 € 15's complement of sum 69By — C141, > — 57% Subtraction with 16's complement The 16's complement of a hexadecimal number is found by adding a 1 to the least significant bit of the 15's complement of a hexadecimal number, as illustrated in the example 1.43.Digital Logic Gircutts 1-29 Review of Binary Number Systems ‘mp Example 1.43 : Find the 16's complement of ASC, Solution : 6 1 15 -A 8 C 5 7 3 © 15's complement +0 0 7 «© Addi 5.7 4 © 16's complement The steps for hexadecimal subtraction using 16's complement method are as given below : Step 1: Find 16's complement of subtrahend. Step 2: Add two hexadecimal numbers (first number and 16's complement of the second number). Step 3: If carry is produced in the addition it is discarded; otherwise find 16's complement of the sum as a result with negative sign. mm) Example 1.44: Use the 16's complement method of subtraction to compute CB2yq - 97246. Solution : Step 1: Bb Bb 5 - 9 7 2 6 8 D © 15s complement + 1 « Add 1 6 8 &£ © 16's complement a & < Carry Step 2: c eB 2 +6 8 &E Cary> M3 4 0 Step 3: Carry is ignored * CByg ~ 972g —> 3406aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digital Logic Circuits 1-44 Review of Binary Number Systems wump Example 1.52 : Represent (7),o using all the weighted 4bit BCD codes listed in the Table 1.9. Solution : 1. 3321 code Mo= 3+3+Z+1 tat GMMR = (119 Doreen 2. 4221 code Ow= 4+Z+2+1 teed GROTGS = (101 Nersen 3. 5211 code (o= 5+2+a+7 tite MEC8 =(1100)21ecp 4, 5311 code ()o= 5+B+1+1 1 ROMA = 101 Don un 5. 5421 code Mo= pesaed GORA) = (10105100 6. 6311 code Oo = =(100 Donen 7. 7421 code 1 FEUOMOMG = (1000150 Oo= 7 +A+2+h t+ 8.742 1 code = (1000)u37coDigital Logic Circuits 1-45 Review of Binary Number Systems 1.9.4 Excess-3 Code Excess-3 code is a modified form of a BCD number. The excess-3 code can be derived from the natural BCD code by adding 3 to each coded number. For example, decimal 12 can be represented in BCD as 0001 0010. Now adding 3 to each digit we get Excess-3 code as 0100 0101 (12 in decimal}. It is a non-weighted code. Table 1.10 shows excess-3 codes to represent single decimal digit. It is sequential code because we get any code word by adding binary 1 to its previous code word as shown in the Table 1.10. Table 1.10 Excess-3 code We have seen that in BCD subtraction we have to compute 9's (or 10's) complement of the number before subtraction. In excess-3 code we get 9's complement of a number by just complementing each bit. Due to this excess-3 code is called self-complementing code or reflective code. ‘mp Example 1.53: Find the excess-3 code and its 9's complement for following decimal numbers. a) 592—_b) 403 Solution : a) By referring Table 1.10. 5929 = 1000 1100 ort) Complement of 9's complement of 592, = 0111 0011 1010 add 3(0 011); to the sum of two digits. = 0 — subtract 3 (0.01 1), from the sum. mm> Example 1.54 : Perform the excess-3 addition of .a) 8, 6b) 1, 2. Solution : a) 8 +6 10 1 1 — Excess-3 for’ + 1.0 0 1 —* Excess-3 for 6 Carry ff] 0 1000 Add 3 oott oor) DAO ONAN —- Encess-3 for 14 1 4 by 142 10 0 —© Excess-3 for 1 + 0 10 1 —® Excess-3 for? Cary M1001 Sub3 - 0011 KOUPRAO —~ Excess-3 for3 3 1.9.4.2 Excess-3 Subtraction To perform excess-3 subtraction we have to © Complement the subtrahend. Add complemented subtrahend to minuend. © Ifcarry =1 Result is positive. Add 3 (0 011), and end-around carry. If carry = 0 Result is negative. Subtract 3 (0 01 1).aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digital Logic Circuits 1-68 Review of Binary Number Systems 1 0:11 tu [0 1:0 ‘| = [1-1+1-0 1-041-1 1-141-0 1-14+1-1] =[1110] The above calculations give the block codes for all messages and are listed in Table 1.19 Case 4: Message ‘1 1" £ Table 1.19 The (4, 4) code constructed from a specified G matrix 1.10.4.2 Generalized Steps for Construction of Code 1. Construct G matrix as G=[iA kxn where I, : Identity matrix of order k A: Axbitrary matrix 100 ... 0 Aggy Aya es Ay O10..0 Ata Aan Ara [Cy Cp... Cg] = [dy oda, Gd 001.0 Aga Mag. Arg sole ee, y n-code bits k - message bits i g 000.1 Any zg = Ark he ken 2. Determine all possible combinations of code using c=pDG In general for this can be written asDigital Logic Circuits 1-69 Review of Binary Number Systems Note : We have seen that for matrix multiplication we have to use MOD 2 arithmetic, ie. 1+ 1=0. For multiple additions this can be generalized as 1®1=0,or1@1@1=1or 1616161=0 ium Example 1.70: The generation matrix for a [ 6, 3] block code is given below 10 00 G=|o1 01 oo1f1i41 Determine all possible code combinations for this code. Solution : Here n = 6 and k = 3. Therefore message code is 3 bit having eight combinations (000 - 111). As n = 6, check bits are n - k = 3. Code for message 000: We know that, 10 0:100 Cc = DG=[000] 01 0:101 oo1li1ii1 = [0-160-060-0 0-:0@0-1 @0-0 0-060-0@0-1 0-180-1 60-1 0-060-0@0-1 0:081-1 60-1] [000000] Similarly we have, Code for message 00 1: Cc = (003) Hoo 0 1] = 001111 1 Code for message 010: 10 0:1 00 Cc = [010] 01 0:1 01}/+010101 oo uilid Code for message 011: 10 0:100 c= [011] 01 0:1 01] 011010Digital Logic Cireuits 4-70 Review of Binary Number Systems Code for message 100: 10 0:100 c = 100] 01 0:1 01]/=100100 oo1fiidt Code for message 101: 10 0:100 C= [101] [01 0:1 01]=101011 oolilaid Code for message 110: 100:100 c= 10} [01 0:1 01) =110 001 oo1:114 Code for message 111: 10 00 c = fi11) o1 0 1j=+111110 00 11 Message Code words Message Check bits Py | Pp | Py 0 0 0 0 0 oO 0 0 o o oO 4 o oO 1 1 1 1 0 1 0 0 1 oO 1 0 < 0 1 1 0 1 A 0 1 QO 1 o oO q oO oO 1 oO o { 0 1 1 0 4 0 1 1 1 1 0 1 4 0 0 oO 4 4 1 1 1 1 A 0 4 o Table 1.20 1.10.4.3 Decoding the Received Codewords At the receiving end the receiver does not know the transmitted word. However, it knows A matrix used for generation of code words. Its function is to check the message bits using check bit along with it. This can be done with the following procedure.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digital Logic Circuits 4-75 Roview of Binary Number Systems Refer H? we can see that S, ie. [1 0 1] matches with second row of H". Therefore, second bit of received code is in error. By inverting second bit of received code we get, Corrected received code = Rc = [100100] This answer can be varied by referring Table 1.20. 1.10.5 Cyclic Codes Binary cyclic codes are simply linear block codes with an added restrictions. Cyclic codes must still meet the addition and multiplication restrictions describe before, while also meeting the shift function. This means that any valid code word, can be shifted any number of times and remain a valid codeword. TE [Cy Cy Cy Ce Cs) is the valid code word then (C5.C, GC Cy] and [Cy Cs C, Cy Cy] should also be valid code words. This places special restrictions on the generator matrix, and brings it together with the generator polynomial. If a generator polynomial has a form g(x) = 1-x° 6 0-x @1- x ®1, we have 4 message bits ie. k = 4 and we can take r = 3, therefore n = 7. For this generator matrix can be formed as follows. Step 1: k" row of G>[0001011] Step 2: Shift left by 1 to get k — 1 row of G, ie. G > (0010119 We know that G = [J, ! A]. Here k = 4. Therefore, first four bits represent row of identity matrix and here first four bits are 0010 which are valid bits for one row of identity matrix. Hence the code generated in valid. Step 3: Shift left by 1 to get k - 2 row of G, ie. G3 [0101100] For identity matrix row can't have more than one 1. Hence this is not a valid identity matrix row. Hence code is not valid. To form a valid code g(x) is added with the help of MOD 2 addition (ie. 1 + 1 = 0) in the current invalid code. 0101100 +0001011 0100111 Now first four bits is valid row for identity matrix and hence code is valid.Digital Logic Circuits 1-76 Review of Binary Number Systems Step 4: Shift left by 1 to get k — 3 row of G, ie. G >[1001110] Again code is not valid. Therefore add g(x) 1001110 + 0001011 1000101 This is valid code. Therefore, the generation matrix is 1000101 o1daoirid S=loo10110 ooo01011 Above procedure of forming generation matrix can be written in generalized form as given below. 1. Use g(x) to form the k" row of G. 2. Use k™ row to form (k — 1) row by a shift left, or xg(x). 3. If (k -1) row in not in standard form then add k™ row to shifted row, ie., (k -1) row becomes xg(x) + g(x). 4. Continue to form rows from the row below. 5. If the (k —j) row not in standard form the add g(x) to the shifted row. Features of Binary Cyclic Codes * Detects all single errors * Detects all double errors * Detects all odd number of error bits * Detects all burst errors of 16 or fewer bits * Detects 99.997 % of all burst of 17 or fewer bits.Digital Logic Circuits 1-77 Review of Binary Number Systems Review Questions 1. What weight does the digit 5 have in each of the following decimal numbers ? (a) 1530 (8) 1.059 (c) 3258 (a) 5679 2. Express following decimal numbers as a sum of the products of each digit and its appropriate weight : (a) 1234.5 (b) 7085 (c) 434.87 (d) 0.02456 3. Convert following hexadecimal numbers to decimal. (a) F286 (b) BC2 yg 4. Convert following decimal numbers to hexadecimal. (a) 1259) 5768 5. Convert 1001001 110101101, to hexadecimal. 6. Convert 35 7 6 g to hexadecimal 7. Convert 10010001011.00101110 to hexadecimal. 8. Convert (725.25)x to its decimal, binary and hexadecimal equivalent. (Ans, : 469,328125,, (111010101 . 010101)., E5.54y,] 9. Convert (11001011. 01110) into decimal. TAns.: 203 . 4375;¢) 10. Convert decimal number 61.3 to binary tAns. : (111101 , 010011001) ,] 11. Convert octal number 574 to binary and decimal. TAns. : i) (101111100), ii) 380,91 12, Convert A92H to octal. TAns. :5222,] 13. Convert the following numbers to hexadecimal. 1) (360)5 #) (22.6219 Hi) (10011.1101). #2) (101), TAns +i) FO;y if) 16.9 iii) 13.Dy, iv) 2.8.9) 14. Convert following numbers to it’s octal equivalent. i) (1100801011 1110), fi) 37.2949 iti) 672 H. TAns. : i) 1453.1, i) 45.224, iii) 31625] 15. Using 2's complements method perform. DEM -(2Bho i) (432):9- C790 16, Convert (268.75)yo to binary, octal and hexadecimal. [Ans.: i) (100001100. 11), i) 414.6, iii) 10C.C] 17. Convert the following hexadecimal numbers into their equivalent decimal and octal numbers i) (23867), ii) (368170. AB), tAns. i) 71783, and 214147, ii) 3572080 . 601562,. and 15500560 . 4317,] 18. Convert the following decimal numbers into binary numbers. i) -128 i) 257 tAns. : 1) 1000 0000 (in 2’s complement form) ii) 10000 000 1] 19. Assuming 8-bit word length, express the following decimal numbers in 4) Sign magnitude ii) One's complement and iii) Two's complement form a) ~ 39 b) ~ 120 [Ans. :a) 10100111 ii) 11011000 ii) 1101 1001 b) 11111000 4) 1000 0111 iii) 1000 1000} 20. Convert the following decimal numbers to 10-bit binary i) 37.31 ii) 6.215. [Ans. ; i) 100101.0100 ii) 110.0011011}Digital Logic Circuits 1-78 Review of Binary Number Systems: 21. 22, 25. 26. 30. 31. 32. SSRRES 39. 23. 24, 2. 28. 29, Perform ench of the following decimal additions in 8 - 4-2 - 1 BCD. 298 ) To) 186 a) 579 +02 +29 + 237+ O12 Perform each of the following decimal subtractions in 8 - 4 - 2-1 BCD using 9's complement method. aj78 b) 64 c) Std) 34 -15 - %@ -B -2 Find the excess-3 code and its 9's complement for following decimal numbers. a) 392 b) 712 [Ans. : a) 0120 1100 0101, 1001 0011 1010 b) 1010 0100 0101, 0101 1011 1010) Perform each of the following decimal additions in excess-3 code. 9 6) 17 ©) 205 +20 +31 + 569 [Ans.: a) 0100 0100 b) 0111 1011) 1010 1010 0121) Perform exch of the following decimal subtractions in excess-3 code. 9)29 6) 205°) 471 -4 1% = -352 — TAns. +a) 0100 1000 b) 1100 c) 0100 0100 1100) Represent 54 using 3321, 5211 and 6311 BCD codes. (Ans. :1010 0101, 1000 0111, 0111 0101] Write a short note on five bit codes. What is the speciality of unit-distance code ? State where they are used. Write a short note on gray code. Convert (101011), to gray code. Tans. : (111110)] Convert gray code 110011 into its equivalent binary. [Ans. : (100010) Write a note on error detecting and correcting codes. What is hamming code ? Write short note on Linear block codes. Explain the generalized steps for construction of linear block code. Explain the detection process in the linear black code. ‘How error correction is done in the linear block code ? What is syndrome ? Write a short note on Binary cyclic code. Explain the procedure for generation matrix in binary cyclic codes.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digital Logic Circuits 2-24 Boolean Algebra Step 2: Search for common terms for factorization and apply Boolean rules Z = AB+ABA+ABC = AB+AB+ABC Theorem 1(b) ; [AA = A] = AB+ABU+0Q) = AB+AB Theorem 2(a) :[ 1+ C= 1] = A(B+B) Postulate 5(a) : [A+ A = 1] =A ‘mp Example 2.8 : Simplify the following three variable expression using Boolean algebra. Y= Ym(1,3,5,7) Solution : Step 1 : From the minterms we can write expression in sum of products form as follows. oo _ Y = ABC+ABC+ABC+ABC Step 2: Search for common terms for factorization and apply Boolean rules. Y = ABC+ABC+ABC+ABC = AC @+B)+ACG+B) Distributive = AC+AC Postulate 5(a) : [A + A = 1] = C(A+A) Distributive =C Postulate 5(a) : [A + A = 1] imp Example 2.9 : Convert the expression given in the previous example into minterms using complementary property and simplify the expression using Boolean algebra. Solution : Y = IIM@G,5,7) Y = Ym(0,1, 2, 4, 6) Step 1: From the minterms write expression in SOP form. Y = AB = ABC+ABC+ABC+ABC+ABC Rearranging terms C+ABC+ABC+ABC+ABC = BC(A+A)+ BC(A+A)+ABC = BC+BC+ABC Postulate 5(a) : [A + A = 1] = CB+B)+ABC Distributive = C+ABC Postulate 5(a) :[A + A = 1] = C+AB Theorem 5(a) : [A + A B= A +B]Digital Logic Circuits 2-25 Boolean Algebra 2.9 Karnaugh Map (Map) Method of Minimization In the previous section we have seen that for simplification of Boolean expressions by Boolean algebra we need better understanding of Boolean iaws, rules and theorems. During the process of simplification we have to predict each successive step. For these reasons, we can never be absolutely certain that an expression simplified by Boolean algebra alone is the simplest possible expression. On the other hand, the map method gives us a systematic approach for simplifying a Boolean expression. The map method, first proposed by Veitch and modified by Kamaugh, hence it is known as the Veitch diagram or the Karnaugh map. 2.9.1 One-Variable, Two-Variable, Three-Variable and Four-Variable Maps The basis of this method is a graphical chart known as Karnaugh map (K-map). It contains boxes called cells. Each of the cell represents one of the 2" possible products that can be formed from n variables. Thus, a 2-variable map contains 2=4 cells, a 3-variable map contains 2° = 8 cells and so forth. Fig. 2.3 shows outlines of 1, 2, 3 and 4-variable maps. Crnssorummmre, Values of CD in gray code 00 sequence Bo, AX00_01 11 40 Ot Votes ° " | ofA 1 10 | 1-Variable map 2-Variable map ——_-3-Variable map 4-Variable map (2 cals) (4 calls) (8 cells) (16 cells) Fig. 2.3 Outlines of 4, 2, 3 and 4-variable Karnaugh maps Product terms are assigned to the cells of a Karnaugh map by labelling each row and each column of the map with a variable, with its complement, or with a combination of variables and complements. The product term corresponding to a given cell is then the product of all variable in the row and column where the cell is located. Fig. 2.4 shows the way to label the rows and columns of a 1, 2,3 and 4-variable maps and the product terms corresponding to each cell. (See Fig. 24 on next page) It is important to note that when we move from one cell to the next along any row or from one cell to the next along any column, one and only one variable in the product term changes (to a complemented or to an uncomplemented form). For example, in Fig. 2.4 (b) the only change that occurs in moving along the bottom row from AB to AB is the change from B to B. Similarly, the only change that occurs in moving down the right column from AB to AB is the change from A to A. Irrespective of number of variables the labels along each row and column must conform to the single-change rule. We know that the gray code has same properties (only one variable change when we proceed to next number or previous number) hence gray code is used to label the rows and columns of K-map as shown in Fig. 2.5. eerDigital Logic Circuits Boolean Algebra (@) 4-Variable map (d) 4-Variable map Fig. 2.4 1, 2, 3 and 4-variable maps with product terms yee — Gray code sequence A a] m 1 {a) *-Variable map (b) 2-Variable map (c) 3-Variable map —> _ Gray cote sequence CD spans EEG aD te a0) Gray code sequence (d) 4-Variable map Fig. 2.5 Another way to represent 1, 2, 3 and 4-variable maps for SOP expressionsDigital Logic Circuits 2-27 Boolean Algebra ‘The Fig. 25 shows label of the rows and columns of a 1, 2, 3 and 4-variable maps using gray code and the product terms corresponding to each cell. Here, instead of writing actual product terms, corresponding shorthand minterm notations are written in the cell and row and columns are marked with gray code instead of variables. In case of POS expressions we assign maxterms (sum terms) to the cells of a Karnaugh map. The Fig. 2.6 shows the way to label the rows and columns of a 1, 2, 3 and 4-variable maps and the sum terms corresponding to each cell. The Fig. 2.6 shows label of the rows and columns of 1, 2, 3 and 4variable maps using gray code and the sum terms corresponding to each cell. Here, instead of writing actual sum terms, correspondirig shorthand maxterm notations are written in the cell and row and columns are marked with gray code instead of variables. ASBHC | A+BsC| K+B+C| A+B+C} A+B+C} ABs >I (a) 1-Variable map (b) 2Variable map (c) 3-Variable map Fig. 2.6 A+B+T+0) A+B /A+8+C+D] A+B+C+0 ANB | At5+C+D] A+B C+D] AvB+T+D) AtBsT+) ASB /AtB+C+D/A A+B+C+D A+B+E+5) A+B |A+8+C+D]A+B+c4D| (d) 4-Variable map Fig. 2.6 1, 2, 3 and 4-variable maps with sum termsaa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digita! Logic Circuits 2-53 Boolean Algebra Solution : > ee YZ YZ YZ YZ % wee FG x Woo me ° ror Wz wren > £ wy 1 wif hl 4 tb) Fig. 2.29 In this example all don't cares are replaced by 1s and we get, F(W,X,Y,Z) = XZ+WXZ+WY mm Example 2.25 : Using K-map find the minimized expression for the following function and implement it using basic gates : F (A,B, C, D) = Ym (2, 4, 1, 15) + d{1, 10, 12, 13). Solution : F (A, B,C, D) = ¥ m(2,4,8, 11, 15) + d(1, 10, 12, 13) cD x a ABN 00 of 1110 sf )- Lo B oo} 0 | x | o fuaZ Bed A S| ==-—>-+ a= oiffti} o}o]|o o _ ald] x HY o eq] acd a & TOA O Mt EEX e{ )— & 3 ACD F(A, B.C,D)= BCD +AcD +BTD +ATB. Fig. 2.30 2.11 Simplification of POS Expressions In the above discussion, we have considered the Boolean expression in sum of products form and grouped 2, 4, and 8 adjacent ones to get the simplified Boolean expression in the same form. In practice, the designer should examine both the sum of products and product of sums reductions to ascertain which is more simplified. We have already seen the representation of product of sums on the Karnaugh map. Once the expression is plotted on the K-map instead of making the groups of ones, we have to make groups of zeros. Each group of zero results a sum term and it is nothing but the prime implicate. The technique for using maps for POS reductions is a simple step by step process and it is similar to the one used earlier.Digital Logic Circuits 2-54 Boolean Algebra 1. Plot the K-map and place 0s in those cells corresponding to the Os in the truth table or maxterms in the product of sums expression. 2. Check the K-map for adjacent 0s and encircle those 0s which are not adjacent to any other 0s. These are called isolated 0s. . Check for those Os which are adjacent to only one other 0 and encircle such pairs. |. Check for quads and octets of adjacent Os even if it contains some 0s that have already been endrcled. While doing this make sure that there are minimum number of groups. bo g . Combine any pairs necessary to include any Os that have not yet been grouped. 6. Form the simplified POS expression for F by taking product of sum terms of all the groups. To get familiar with these steps we will solve some examples. mm Example 2.26 : Minimize the expression. Y=(A+B+C)(A+B+O)(A+B+C)(A+B+C)(A+B+C) Solution: (A+B+C)=M,,(A+B+C)=M,,(A+B+C)=M,, (A+B+C) =My,(A+B+OQ)=M, BC Bic Bit BAS Bec Step 1: Fig. 2.31 (a) shows the K-map for three variable and it is plotted according to given maxterms. Step 2: There are no isolated Os. Step 3: 0 in the cell 4 is adjacent only to 0 in the cell 0 and 0 in the cell 7 is adjacent only to 0 in the cell 3. These two pairs are combined and referred to 40 fey] o fo rill] hell as group 1 and group 2 respectively. Step 4: There are no quads and octets. Fig. 2.31 (b) Step 5: The 0 in the cell 1 can be = Group 3 > A'S combined with 0 in the cell 3 to form a pair. This pair is referred to as group 3. Step 6: In group 1 and in group 2, A is eliminated, whereas in group 3 variable B is eliminated and we get, = (B+C) (B+ C)(A+ 6) Group 2 B+C Group 1 > B+C Fig. 2.34 (c)Digital Logic Circuits 2-55 Boolean Algebra wm Example 2.27 : Minimize the following expression in the POS form D) ) ¥=(A+B+C+D)(A+B+C 4+ D)(AtB + (A+B+C4D) (A+B+C+D)(A4+B+C+D) (A+B (A+B+C+D) Solution : +0 + C+D (A+B+C+D) = My, (A+B+C +D)=My, (A+B+C+D)=™M, (A+B+C+D) = My, (A+B+C+D)=M,,(A+B+C+D)=M, (A+B+C+D) = Mand(A +B+C+D)=M, Step 1: Fig. 2.32 (a) shows the K-map for four variable and it is plotted according to given maxterms. C0 c+D C+D C+D T+ oo 01 1110 AB Step 2: There are no isolated Os. Step 3: 0 in the cell 0 is adjacent only to 0 in the cell 8. This pair is combined and referred to as group 1. Step 4: There are two quads. Cells 12, 13, 14 and 15 forms a quad 1 and cells 6, 7, 14, 15 forms a quad 2. These two quads are referred to as group 2 and group 3, respectively. Step 5: All 0s have already been grouped. Fig. 2.32 (b) Group 4 7 (B+C+D) Step6: In group 1, variable A is eliminated. In group 2, variable C and D are eliminated and in group 3 variables A and D are eliminated. Therefore we get simplified POS expression as, Group 3 +(B +) Fig. 2.32 (c)Digital Logic Circuits 2-56 Boolean Algebra Y = (B+C+D)(A+ B)(B+Q mm> Example 2.28 : Reduce the following function using K-map technique f(A B,C,D)=IIM (0, 2, 3, 8 9, 12, 13, 15) Solution : cD 5 mea S Step 1: Fig.233(a) shows the K-map for four ABN GO OD xD GD variables and it is plotted according to given maxterms. 4, asd 01 ae A+B 10 Step 2: There are no isolated 0s. Step 3: The 0 in the cell 15 is adjacent only to 0 in the cell 13 and 0 in the cell 3 is adjacent only to 0 in the cell 2. These two pairs are combined and referred to as group 1 and group 2, respectively. Fig. 2.33 (c) Step 4: The cells 8, 9, 12 and 13 form a quad which is referred to as group 3.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digital Logic Circuits 2-73 Boolean Algebra 16. Use a Kamaugh map to reduce each expression to a mirtinum sum of products form: a Ans.: ABC+ABC ii) ¥ = AB(CD+CD)+ AB(CD+CD)+ ABCD Ans.:Y=BE+AE€D 17. What are don't care conditions 7 18, Use the Quine- McCluskey method to simplify the following function if, (A,B,C DE) = Sm, 9, 10, 11, 13, 15, 16, 18, 21, 24, 25, 26, 27, 30, 31) Ans.:f =ABE+ACE+ABD+BC+A BC DE i) ffA, B,C, D) = Sym, 3, 5, 8, 9, 11, 15) +d (2, 13) Ans.:f) =A +CD+BD+AD University Questions with Answers QA Define canonical form. Express F = BC’+AC in a canonical SOP form. [Dec.-2003, 2 Marks] Ans. : F = BC+AC = (A+A)BC+AC(B+B) = ABC+ABC+ABC+ABC Q2 State and prove DeMorgan's theorem and expand the function F =((A +B) C+C’D] . [Dec.-2003, 5 Marks] Ans. : Refer section 2. Q.3 Simplify the following switching function using Karnaugh map F(A,B,C,D) =E (05,7,8,9,10,11,14,15) + $ (1,4,13). (Dec.-2603, 11 Marks} Ans. : Refer section 2.10. Q4 Minimize FA, B, C, D) = ¥(0,1,5,7,8,9,10,11,14,15) using Quine-McCluskey method. [Dec.-2003, 16 Marks] ‘Ans. : Refer section 2.15. Q.5 State two absorption properties of Boolean algebra. [Dec.-2004, 2 Marks] Ans. : Refer Table 27. Q.6 State two significant features of tabular method of minimization of Boolean functions. {Dec.-2004, 2 Marks] ‘Ans. : Refer section 2.15. Q.7 How many inputs are required for W = ABD + ACD +EF ? [Dec.-2004, 2 Marks} Ans. : 6-inputs.Digital Logic Circuits 2-74 Boolean Algebra Q.8 Simplify the following Boolean expressions to a minimum number of literals : a) (X+Y) (x+¥) b) XY+XZ+¥Z (Dec.-2005, 2 Marks] Ans. : a) (XY) (X+¥) = XX4XY+XY+0 = X+Xx(¥+Y) = X+X =X b) XY+XZ+YZ = X¥(Z+Z)+XZ(Y+Y)+(X+ XYZ = XYZ+XYZ+XYZ+XYZ+XYZ+ XYZ = XYZ+XYZ+XYZ+ XYZ = x¥(Z+Z)+Xz(¥+¥) = XV+KZ Q.9 What are prime implicants ? {Dec.-2005, 2 Marks} Ans. : Refer section 2.10.1. Q.10 Simplify the following Boolean function in (1) Sum of products and (2) Product of sums. F(A,B,C,D) = 2(0,1,2,5,8,9,10) (Dec-2005, 10 Marks) ‘Ans. : Refer sections 2.10 and 2.11. Q.11 Plot the following Boolean function on a Karnaugh map and simplify it. F(w,x,y,2) =¥(0,1,2,4,5,6,8,9,12,13,14) [Dec.-2005, 6 Marks} ‘Ans. : Refer section 2.10. QA2 Determine the prime implicants of the given function using Tabulation method. F(w, x,y,2) =2(0.1,2,67,8,9,10,11,13) [Dec.-2005, 10 Marks] Ans. : Refer section 2.15. Q.13 Simplify the following Boolean expression. ab ceabe + abe. (May-2005, 2 Marks] Ans. : abc+abctabe = abc +ac(btb) = abctac = abe+o) = ab+o A+AB= A+B = ab +acDigital Logic Circuits 75 Boolean Algebra Q.44 Express the function {(x,y,2) = xy+¥z as a product of sum terms form. [May-2005, 4 Marks] Ans.: Refer section 2.6. Q.15 Express the following function as the minimal sum of products using a K-map. f(a.b, c,d) =2(0,2,4,5,6,8,10,15) + 24(7,13,14) [May-2005, 12 Marks] Ans. : Refer section 2.10. Q416 Simplify the following function by tabulation method : f(ab,c,d) =2(1,4,6,7 8,9,10,11,15) [May-2005, 12 Marks] Ans. : Refer section 2.15. Q17 > Show the Karnaugh map with the encircled groups for the Boolean function, F=C+AD+ABD. [May-2006, 2 Marks] Ans. : Fig. 2.42 QA8 Using K-map simplify the expression Y(A,B,C,D) = 1h +15 +1 + mt, +Mig +nty +My +My +My +My +My. Indicate the prime implicants, essential and non-essential prime implicants. Draw the logic circuit using AND-OR-INVERT gates and also using NAND gates. [May-2006, 16 Marks] Fig. 2.43Digital Logic Circuits 2-76 Boolean Algebra Ans. : Prime implicants : AB, AD, AT, B Essential prime implicants : AD, AT, B Non-essential prime implicant : AB Logic circuit : Using AND-OR-INVERT gates Logic circuit : Using NAND gate s———_>t_—________ or lot YYY. t—4 Fig. 2.44 We can implement AND-OR logic by using NAND-NAND logic k K D: = Y c Fig. 2.45aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.ital Logic Circuits 3-20 Logic Gates In the previous examples we have seen that simplified SOP Boolean expression can be implemented using AND-OR gates. The AND-OR implementation is a two-level implementation. In the first level we implement all product terms using AND gates and in the second level all product terms are logically ORed using OR gate. In case of POS expression we use OR-AND implementation. Here, we implement all sum terms using OR gates in the first level and all sum terms are logically ANDed using AND gate, to get product of sum, in the second level. We know that, the logic gates are available in the integrated circuit (IC) packages. When we implement logic circuit using basic gates, we require ICs for AND, OR and NOT gates. Many times it may happen that all gates from the IC packages are not required to build the circuit and thus remaining gates are unused. Consider a combinational circuit which requires two 2-input AND gates and one 2-input OR gate as shown in Fig. 3.32. To implement such a circuit we require IC 7408 (Four 2-input AND gates) and IC 7432 (Four 2-input OR gate). When we use these two ICs we find that two 2-input AND gates are unused and three 2-input OR gates are unused. Thus, the utility factor is very poor. This utility factor can be increased by using universal gates to implement logic functions. Let us study how to implement logic circuits using universal gates. >1»— i errr (2) Fig. 3.32 3.4.3 NAND-NAND Implementation ‘The implementation of a Boolean function with NAND-NAND logic requires that the function be simplified in the sum of product form. The relationship between AND-OR logic and NAND-NAND logic is explained using following example. Consider the Boolean function : Y= ABC+DE+F. This Boolean function can be implemented using AND-OR logic, as shown in Fig, 3.33 (a). m {a) AND-OR (b) NAND-Bubbled ORDigital Logic Circuits 3-21 Logic Gates (c) NAND-NAND Fig. 3.33 NAND-NAND implementation Fig. 3.33 (b) shows the AND gates are replaced by NAND gates and the OK gate is replaced by a bubbled OR gate. The implementation shown in Fig. 3.33 (b) is equivalent to implementation shown in Fig. 3.33 (a), because two bubbled on the same line represent double inversion (complementation) which is equivalent to having no bubble on the line. In case of single variable, F, the complemented variable is again complemented by bubble to produce the normal value of F. In Fig. 3.33 (¢), the output NAND gate is redrawn with the conventional symbol. The NAND gate with same inputs gives complemented result, therefore F is replaced by NAND gate with F input to its both inputs. Thus all the three implementations of Boolean function are equivalent. From the above example we can summarize the rules for obtaining the NAND-NAND logic diagram from a Boolean function as follows : 1. Simplify the given Boolean function and express it in sum of product form (SOP form). 2. Draw a NAND gate for each product term of the function that has two or more literals. The inputs to each NAND gate are the literals of the term. This constitutes a group of first-level gates. 3. If Boolean function includes any single literal or literals draw NAND gate for each single literal and connect corresponding literal as an input to the NAND gate. 4, Draw a single NAND gate in the second level, with inputs coming from outputs of first level gates. => Example 3.2: Implement the following Boolean function with NAND-NAND logic Y=AC+ABC+ ABC+AB+D Solution : Step 1: Simplify the given Boolean function. Y = AC+ABC+ABC+AB+D = AC+BC(A+A)+ABt+D = AC+BC+AB+DDigital Logic Circuits 3-22 Logic Gates Step 2: Implement using AND-OR logic. — c 8 <1 LT =p B Fig. 3.34 (a) Step 3 : Convert AND-OR logic to NAND-NAND logic. ——D— La pp 4D Fig. 3.34 (b) wum> Example 3.3 : Implement the following Boolean function with NAND-NAND logic F = AB+AC+BC Solution : Step 1: Implement Boolean function with AND-OR logic. 5 Fig. 3.35 (a)aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a 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page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digital Logic Circuits 4-22 Combinational Circuits equal to zero (ie. when sum <9 and C,y = 0) nothing (zero) is added to the binary sum. When it is equal to one (i.e. when sum > 9 or Coy = 1), binary 0110 is added to the binary sum through the bottom 4-bit binary adder. The output carry generated from the bottom binary adder can be ignored, since it supplies information already available at the output-carry terminal. imp Example 4.6: Design an 8-bit BCD adder using IC 74283. Solution : To implement 8-bit BCD adder we have to cascade two 4-bit BCD adders. In cascade connection carry output of the lower position (digit) is connected as a carry input of the higher position (digit). Fig. 4.34 shows the block diagram of 8-bit BCD adder. % x Oo Oo < < < & “ & < £8 -—| 224 reaA 34% 2 a} 255) ry ssorn{é - goa goa oa + mt a or < we a) 3 £ 38 - a . e—+| 55 a -—| 32 a + ot Cs Digit 2 Fig. 4.34 8-bit BCD adder using IC 74283Digital Logic Circuits 4-23 Combinational Circuits 4.11 BCD Subtractor Addition of signed BCD numbers can be performed by using 9's or 10’s complement methods. A negative BCD number can be expressed by taking the 9's or 10's complement. Let us see the implementation of subtraction process using 9's and 10's complement methods. 4.11.1 Subtraction using 9's complement method The steps for 9's complement BCD subtraction as follows : Find the 9's complement of a negative number « Add two numbers using BCD addition © If carry is generated add carry to the result otherwise find the 9’s complement of the result. Fig. 4.35 shows the logic diagram of the circuit to implement above mentioned steps to perform BCD subtraction using 9's complement method. As shown in the Fig. 4.35, first binary adder finds the 9's complement of the negative number. It does this by inverting each bit of BCD number and adding 10 (1 01 0,) to it, Let us find the 9’s complement of 2 0 0 1 0 © BCD for2 1 1 0 1 € Inverting each bit + 10 1 0 & Add 10 (1010,) Ignore carry->/f) 0 1 1 1 « 9's complement for 2 Next two 4-bit binary adders perform the BCD addition. The last adder finds the 9’s complement of the result if carry is not generated after BCD addition otherwise it adds carry in the result. 4.11.2 Subtraction using 10's complement method The steps for 10’s complement BCD subtraction as follows. © Find the 10’s complement of a negative number * Add two numbers using BCD addition * If carry is not generated find the 10’s complement of the result. Fig. 4.36 shows the logic diagram of the circuit to implement above mentioned steps to perform BCD subtraction using 10's complement method. As shown in the Fig. 4.36, first binary adder finds the 10’s complement of the negative number (9's complement + 1). Next two 4-bit binary adders perform the BCD addition. Finally, last 4-bit binary adder finds the 10’s complement of the number if carry is not generated after BCD addition.Digital Logic Circuits 4-24 Combinational Circuits BCD input (operand 2) B o+5V Ex-OR gates act as inverters [| inveteascn | 9S complement fou circuit Court Ignored 107483 — 9's complement of BCD input B BCD Adder cireuit <— Sum of Aand 9's complement of B Hoary = 4 circuit adds 1 in the result Weary =0 circuit finds the 9's complement of the result 4-bit Adder S3 Sz Sy So 1C7463 Sign BCD output (magnitude) Fig. 4.35 4-bit BCD subtractor using 9's complement methodDigital Logic Circuits 4-25 Combinational Circuits BCD input (operand 2) B By By By By BCD input (operand 1) A it sabi Sum of A and 10's +— complement of B Sign BCD output (magnitude) Fig. 4.36 4-bit BCD subtractor using 10's complement methodaa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable 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for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digital Logic Circuits 5-6 Flip-Flops s — Q EN—* a R (a) SR latch with enable input using NAND gates (b) Logic symbol Fig. 5.7 EN s R Q, Quer State 1 0 ° ° ° No change (NC) 1 oO o 4 1 1 oO 1 Oo oO Reset 1 o 1 1 Q 1 4 oO Oo 1 Set i 1 o 1 1 1 1 1 0 x Indeterminate 4 1 1 1 x 0 x x ° 0 | No change (NC) oO x x 4 1 Table 5.2 Truth table for SR latch with enable input 5.2.2 Gated D Latch Looking at the truth table of the SR latch we can realize that when both inputs are same the output either does not change or it is invalid (Inputs —> 00, no change and inputs — 11, invalid). In many practical applications, these input conditions are not required. These input conditions can be avoided by making them complement of each other. This modified SR latch is known as D latch. Fig. 5.8 shows the D latch. The NAND gates 1, 2, 3 and 4 form the basic SR latch with enable input. The fifth NAND gate is used to provide the complemented inputs. i. Ss Q R (a) D latch (b) Logic symbol Fig. 5.8Digital Logic Circuits 5-7 Flip-Flops As shown in the Fig. 5.8, D input goes directly to the S input, and its complement is applied to the R input, through gate 5. Therefore, only two input conditions exists, either S=0 and R = 1 or S = 1 and R = 0. The truth table for D latch is as shown in the Table 5.3. Reset Set No change (NC) Table 5.3 Truth table for D latch As shown in the truth table, the Q output follows the D input. For this reason D latch is sometimes called transparent latch. Looking at the truth table for D latch with enable input and simplifying Q,4, function by k-map we get the characteristic equation for D latch with enable input as Fig. 5.9 Characteristic equation Q,,,; = EN-D+EN-Q,,. This is illustrated in Fig. 5.9. 5.2.3 Latches Vs Flip-Flops Latches and flip-flops are the basic building blocks of the most sequential circuits. The main difference between latches and flip-flops is in the method used for changing their state. A simple latch forms the basis for the flip-flop. We have seen SR and D latches with Enable input. Latches are controlled by enable signal, and they are level triggered, either positive level triggered or negative level triggered. The output state is free to change according to the S and R input values, when active level is maintained at the enable input. Flip-flops are different from latches. Flip-flops are pulse or clock edge triggered instead of level triggered. 5.2.4 Level and Edge Triggering Level Triggering In the level triggering, the output state is allowed to change according to input(s) when active level (either positive or negative) is maintained at the enable input. There are two types of level triggered latches : * Positive level triggered : The output of latch responds to the input changes only when its enable input is 1 (HIGH).Digital Logic Circuits 5-8 Flip-Flops ‘SR latch is enabled only when the level Of E input is HIGH Fig. 5.10 Positive level triggering The SR latch shown in the Fig. 5.7 is a positive level triggered SR latch. © Negative level triggered : The output of latch responds to the input changes only when its enable input is 0 (Low). SR latch is enabled ‘only when the level of E input is LOW Fig. 5.11 Negative level triggering The Fig. 5.12 shows the circuit and symbol for negative level triggered SR latch. s (set) Q E (Enable) a R (Reset) Bubble represents negative level triggering {a) Negative level triggered SR latch {b) Logic symbot Fig. 5.12 Edge triggering In the edge triggering, the output responds to the changes in the input only at the positive or negative edge of the clock pulse at the clock input. There are two types of edge triggering. * Positive edge triggering : Here, the output responds to the changes in the input only at the positive edge of the clock pulse at the clock input.Digital Logic Circuits 5-9 Flip-Flops Vv Clock input 1 t t Output responds only at the positive edges of the pulse Fig. 5.13 Positive edge triggering © Negative edge triggering : Here, the output responds to the changes in the input only at the negative edge of the clock pulse at the clock input. v Output responds TT ari atte negative ae ‘edges of the pulse input | | 9 Fig. 5.14 Negative edge triggering 5.2.5 Clocked SR Flip-Flop Positive edge triggered SR flip-flop The Fig. 5.15 shows the positive edge triggered clocked SR flip-flop. The circuit is similar to SR latch except enable signal is replaced by the clock pulse (CP) followed by the positive edge detector circuit. The edge detector circuit is a differentiator. The Fig. 5.17 shows input and output waveforms for positive edge triggered clocked SR flip-flop. As shown in Fig. 5.17 the circuit output responds to the S and R inputs only at the positive edges of the clock pulse. At any other instants of time, the SR flip-flop will not respond to the changes in input. Gated SR latch Fig. 5.15 Clocked SR flip-flop The Fig. 5.16 shows the logic symbol and truth table of clocked SR flip-flop, and Fig. 5.17 shows input and output waveforms.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digital Logic Circuits 5-31 Flip-Flops K-map simplification Logic diagram ForJ Fig. 5.50 Fig. 5.51 JK to D flip-flop conversion 5.4.6 D Flip-Flop to T Flip-Flop The excitation table for above conversion is as shown in the Table 5.16. Input Present state Next state Flip-flop input Table 5.16 K-map simplification Logic diagram ForD Fig. 5.52 Fig. 5.53 D to T flip-flop conversion D = TQ,+TQ, = TQ, yum Example 5.4 : Analyze the circuit and prove that it is equivalent to T flip-flop. Solution : To analyze the circuit means to derive the truth table for it.Digital Logic Circuits 5-32 Flip-Flops a Output Fig. 5.54 We have, D = Input © Q, D = inputoa, When input is 0 output does not change ‘When input is 1 output toggles Table 5.17 Truth table for given circuit In the above circuit, output does not change when input is 0 and it toggles when input is 1. This is the characteristics of T flip-flop. Hence, the given circuit is T flip-flop constructed using D flip-flop. 5.4.7 T Flip-Flop to D Flip-Flop The excitation table for above conversion is as shown in the Table 4.18. Input Present state | Next state | Flip-flop input Qa st Table 5.18 K-map simplification Logic diagram ForT Fig. 5.56 T to D flip-flop conversionDigital Logic Circuits 5-33 Flip-Flops 5.4.8 JK Flip-Flop to SR Flip-Flop The excitation table for above conversion is as shown in Table 5.19 Inputs Present | Next | Flip-flop inputs state Q, | state s R Qa. J kK ° o 0 0 0 x o 0 1 1 x 0 oO ¥ o oO oO x 0 1 1 0 x 1 1 0 0 1 1 x 1 o 1 1 x oO 1 4 oO x x x 1 1 a: x x Table 5.19 Excitation table for JK to SR conversion K-map simplification Fig. 5.57 Logic diagram Fig. 5.58 JK to SRDigital Logic Circuits 5-34 Flip-Flops 5.4.9 D Flip-Flop to SR Flip-Flop The excitation table for above conversion is as shown in the Table 5.20. Inputs Present state | Next state | Flip-flop input s R Q, Quast D 0 o oO o o o o 1 1 1 0 1 0 0 1 1 1 o o 1 oO 1 ° Table 5.20 Excitation table for D to SR conversion K-map simplification ForD "00 of 14 10 D=RQ,+S Logic diagram SR Flip-Flop cP Fig. 5.60 D to SR flip-flop conversionaa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is 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unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digital Logic Circuits 5-77 Flip-Flops HIGH —J cp TLL} Fig. 5.121 MOD-5 counter using RESET input 1 2 3 4 5 6 7 8 9 10 cP Fig. 5.122 Waveforms for MOD-5 counter Any desired MOD number’ can be obtained by changing the NAND gate inputs. The Table 5.29 shows the NAND gate inputs and corresponding MOD-N counter. NAND Gate inputs Counter MOD-1 Counter MOD-3 Counter MOD-4 Counter - MOD-7 Counter c Table 5.29 NAND gate inputs for MOD-n counter ium Example 5.24: A certain counter is being pulsed by a 256 kHz clock signal. The output frequency from the last flip-flop is 2 kHz : i) Determine the MOD number. ii) Determine the counting range. Solution : Clock frequency = 256 kHz Output frequency = 2 kHz 256 3 128 Mod number = n= +. Counter is Mod-128 counter Mod-128 counter can count the numbers from 0 to 127. 5.5.11 Decade Counters The binary counter has maximum number of states equal to 2", where n is the number of flip-flops in the counter. Counters can also be designed to have a number of states in their sequence that is less than 2". In decade counters the sequence is truncated upto ten states, 0000 (0 in decimal) through 1001 @ in decimal). These type of counters are very useful in display applications in which BCD numbers are used. The truncation in the count sequence is achieved by resetting the counter at particular count instead of going through all of its normal states. In case of BCD decade counter is reset back to the 0000 state after the 1001 state.The resetting of counter is done with the help of reset inputs of each flip-flop. These inputs are activated when desired state is reached. In case of BCD decade counter, reset input is activated using NAND gate when 1010 state is reached. This is illustrated in Fig. 5.123 (a). Fig. 5.123 (b) shows the timing diagram for circuit shown in Fig. 5.124 (a). 10 decod aR H3h— [A crDigital Logic Circuits 5-79 Flip-Flops ote tt Ls fs ee ogee eft a + 7 1e_o Jo agus) — 22 oo o o o of? 7 fo ys ee ll coum [eaae [oor [cove [on [ove [over [oa [ovr | oo] vor | 0 | (b) Fig. 5.123 (a) and (b) An asynchronously clocked decade counter with asynchronous resetting §.5.11.1 IC 7490 (Decade Binary Counter) IC 7490 is a decade binary counter. It consists of four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three stage binary counter for which the count cycle length is divide by five INPUT. NCQ, Q) GND ag jr fe fro | fio fo |e B F INPUT Ry Ray NO Veo Sy Sa) NeN comacton Fig. 5.124 Connection diagram for 7490 Since the output from the divide-by-two section is not internally connected to the succeeding stages, the devices may be operated in various counting modes. 1. BCD Decade (8421) Counter : The B input must be externally connected to the Q, output and A input receives the incoming count and a BCD count sequence is produced.Digital Logic Circuits 5-80 Flip-Flops 2, Symmetrical Bi-quinary Divide-by-Ten Counter : ‘The Qp output must be externally connected to the A input. The input count is then applied to the B input and a divide-by-ten square wave is obtained at output Qy. 3, Divide-by-Two and Divide-by-Five Counter : No external interconnections are required. The first flip-flop is used as a binary element for the divide-by-two function (A as the input and Q, as the output). The B input is used to obtain binary divide-by-five operation at the Qp output Table 5:30 shows function tables and Fig. 5.125 shows logic diagram for C7490. Table 5.30 (a) BCD count sequences (Note 1) a ae zBrrtrarrre er |e eer ee ron x = Table 5.30 (b) BCD Bi-quinary (5-2) (Note 2)aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digital Logic Circults 4 5-99 Flip-Flops Q45 Explain the working of JK flip-flop. What is race around condition and how is it overcome? Explain these concepts with relevant timing diagrams. [May-2006, 16 Marks) Ans.: Refer section 5.2.7. Q.16 Define a state. [Dec.-2006, 2 Marks] Ans.: Refer section 5.1. Q.17 Give the meaning for edge triggering in flip-flops. [Dec.-2006, 2 Marks] Ans. : Refer section 5.2.4. QA8 If the input frequency of a T FF is 1600 kz, what will be the output frequency ? Give reason for your answer. [Dec.-2006, 2 Marks} ‘Ans. : "800 kHz, because it toggles at every clock pulse. Q19 Give the state diagram of JK FF. [May-2007, 2 Marks} Ans. : Refer example 53.2. Q.20 Convert JK FF to DFF. [May-2007, 2 Marks} Ans.: Refer section 5.4.5 Q.21 What is edge triggering. {Dec.-2007, 2 Marks} Ans.: Refer section 5.2.4. Q.22 What is the difference between serial and parallel transfer? What type of register is used in each case? [Dec.-2007, 2 Marks] Ans. : When data is transferred one bit at a time, the process of transfer is known as serial transfer. When multiple bits of data are transferred at a time, the process is known as paral. transfer. For parallel transfer, we can use parallel in and parallel out register. For serial transfer we can use left shift or right shift register. Q.23. Show that the characteristic equation of Qts.x of IK flip-flop is Qian =J'Q’+ KQ. {Dec.-2007, 4 Marks] Ans. : From Fig. 5.150 we can write truth table for JK flip flop as shown below. as Ka, | OQ, ooo oO 4 o.0 1 oO ¥ o10 1 oO o17 1 Oo 100 1 oO 104 oO 4 110 1 oO5-100 Flip-Flops For Qe) aX 00__o1_ tt 10 Fig. 5.150 Quy = JQ+KQ Q.24 Design a asynchronous decade counter using JK flip-flop. Ans.: Refer section 5.5.7. Q.25 Draw the logic circuit of a clocked JK flip-flop. Ans.: Refer section 5.2.7 Q.26 Define a sequential logic circuit. Give an example: Ans.: Refer section 5.1. Q.27 Explain the working of a master-slave JK flip-flop. Ans.: Refer section 5.2.8. Q.28 What is a race condition ? Ans.: Refer section 5.2.7.2. Q.29 Differentiate between combinational and sequential circuits. Ans.: Refer section 5.1. Q.30 Convert a SR flip-flop into a D flip-flop. Ans.: Refer section 5.4.1. Q.31 Explain the working of a master-slave JK flip-flop. State its advantage. Ans.: Refer section 5.2.8. Q.32 How can race condition be avoided in flip-flop ? Ans. : Refer sections 5.2.7.2 ard 5.2.8. [Dec.-2007, 16 Marks] [May/June-2008, 2 Marks] [May/June-2008, 2 Marks] {May/June-2008, 6 Marks) {Nov/Dec.-2008, 2 Marks] [Nov/Dec.-2008, 2 Marks} [Nov/Dec.-2008, 8 Marks] {NovJDec.-2008, 8 Marks] gooAnalysis and Design of Synchronous Sequential Circuits 6.1 Introduction We have already introduced to synchronous sequential circuits. These circuits are further classified depending on the timing of their signals : Synchronous sequential circuits and Asynchronous sequential circuits. In synchronous sequential circuits, signals can affect the memory elements only at discrete instants of time. In asynchronous sequential circuits change in input signals can affect memory element at any instant of time, Synchronous sequential circuits Asynchronous sequential circuits In synchronous circuits, memory elements, ate clocked fiip-fops. In asynchronous circuits, memory elements are either unclocked flip-flops or time delay elements. In synchronous circuits, the change in input signals can affect memory element upon activation of clock signal. in asynchronous circuits change in input signals can affect memory element al any instant of time. ‘The maximum operating speed of clock depends on time delays involved. Because of absence of clock, asynchronous circuits can operate faster than synchronous circuits. *: Easier to design. More difficult to design Table 6.1 Comparison between synchronous and asynchronous sequential circuits In this chapter, we are going to study the analysis and design of synchronous sequential circuits and design of synchronous counters. 6.1.1 Synchronous or Clocked Sequential Circuits In synchronous or clocked sequential circuits, clocked flip-flops are used as _ memory elements, which change their individual states in synchronism with the periodic clock signal. Therefore, the change in states of flip-flops and change in state of the entire circuit occurs at the transition of the clock signal. (6-1)Analysis & Design of Synchronous Digital Logic Circuits 6-2 Sequential Circuits The synchronous or clocked sequential circuits are represented by two models. © Moore circuit : The output depends only on the present state of the flip-flops © Mealy circuit : The output depends on both the present state of the flip-flop(s) and on the inputis). Sequential circuits are also called finite state machines (FSMs), which is more formal name that is often found in technical literature. The name derives from the fact that the functional behaviour of these circuits can be represented using a finite number of states. 6.1.2 Moore Circuit As mentioned earlier, when the output of the sequential circuit depends only on the present state of the flip-flop, the sequential circuit is referred to as Moore Circuit. Let us see one example of Moore circuit. Fig. 6.1 shows a sequential circuit which consists of two JK flip-flops and AND gate. The circuit has one input X and one output Y. Fig. 6.1 Example of Moore circuit As shown in the Fig. 6.2, input is used to determine the inputs of the flip-flops. It is not used to determine’ the output. The output is derived using only present states of the flip-flops or combination of it (in this case Y = Qu Qp)- In general form the Moore circuit can be represented with its block schematic as shown in Fig, 62 (a) and (b). Inputs Fig. 6.2 (a) Moore circuit modelaa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Analysis & Design of Synchronous Digital Logic Circuits 6-9 Sequential Circuits Fig. 6.10 shows the example for Rule 1. As shown in the Fig. 6.10, there are four states whose next state is same. Thus states assignments for these states are 100, 101,110 and 111, which can be grouped into logically adjacent cells in a K-map. Rule 2: States that are the NEXT STATES of a single state should have assignment which can be grouped into logically adjacent cells in a K-map. Fig. 6.11 shows the example for C000) Rule 2. As shown in the Fig. 6.11, for state 000, there are four next states. These states are assigned as 100, 101, 110 and 111 so that they can be grouped into logically adjacent cells in a K-map and table Cio God God Gnd shows the state table with assigned states. Fig. 6.11 Example of using Rule 2 Present Next state Output State x=0 xe1 x=0 xe1 00 01 10 0 0 01 "1 10. 1 0 {10 10 1 0 1 " 00 1 0 a Table 6.6 State table with assigned states 6.2.5 Choice of Flip-Flops and Derivation of Next State and Output Expressions From the state assigned state table shown in Table 6.6, we can derive the logic expression for the next state and output functions. But first we have to decide on the type of flip-flops that will be used in the circuit. The most straightforward choice is to use D flip-flops, because in this case the values of next state are simply clocked into the flip-flops to become the new values of present state. For other types of flip-flops, such as JK, T and RS the relationship between the next-state variable and inputs to a flip-flop is not as straightforward as D flip-flop. For other types of flip-flops we have to refer excitation table of flip-flop to find flip-flop iputs. This is illustrated in the following example. ium Example 6.1: A sequential circuit has one input and one output. The state diagram is shown in Fig. 6.12. Design the sequential circuit with a) D-flip-flops b) T flip-flops ) RS flip-flops, and d) JK- flip-flops.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Analysis & Design of Synchronous Digital Logic Circuits 6-11 Sequential Circuits K-map Simplification For fllp - flop A For flip-flop B For output Y = ABX+AX With these flip-flop input functions and circuit output function we can draw the logic diagram as follows ea ate Fig. 6.14 Logic diagram of given sequential circuit using D flip-flopaa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Analysis & Design of Synchronous Digital Logic Circuits 6-37 Sequential Circuits wm Example 6.6: Design a MOD-5 synchronous counter using JK flip-flops and implement it. Also construct a timing diagram. Solution : Flip-flops required are 2 2N Here N=5 n=3 ie. three flip-flops are required. Excitation table for JK State table Present Stato Next State Sa +4 Flip-flop Inputs Ke Qnet x x 0 1 x x x x xx xXx +20co°o 5 gAnalysis & Design of Synchronous Digital Logic Circuits 6-39 Sequential Circuits wimp Example 6.7 : Design divide by 6 counter using T-flip-flop. Write state table and reduce the expression using K-map. Solution : For designing mod 6 counter using the formula 22 >N Here N=6 n = 3 ie 3 flip-flops are required. Excitation table for T-flip-flop a ned rE oO 0 0 0 4 1 1 oO 1 4 1 oO Table 6.24 State Table cp | a | Oe | Om | ce | Qo | Ores 0 °o oO oO ° oO 1 0 oO 1 0 1 oO 2 0 1 0 0 1 1 3 0 % 1 1 0 0 4 1 0 0 1 0 1 5 4 0 1 0 0 0 Table 6.25 K-Map Simplification Forte Fors 06 or 11 10 0 xAnalysis & Design of Synchronous Digital Logic Circuits Sequential Circuits Logic Diagram Fig. 6.54 6.4.14 Synchronous Decade Counter We know that in the decade counters we have to truncate normal counter sequence. Therefore, it is also called MOD-10 counter. Let us design the synchronous decade counter. Here, we will not use clear input to reset the counter after state 1010. Table 6.26 shows the excitation table for synchronous decade counter using T flip-flops. Excitation Table Flip-lop Inputs Te BR [x |x 1x] }< |x Jo |e fo |= |= fole/+|alo Table 6.26Analysis & Design of Synchronous Digital Logic Circuits 6-44 ‘Sequential Circuits 6.5 Sequence Generator using Counters A sequential circuit which generates a prescribed sequence of bits, in synchronism with a clock, is referred to as a sequence generator. Fig. 657 shows the basic structure of a sequence generator using counters. Flip-Nop inputs Flip-top outputs Fig. 6.57 Basic structure of a sequence generator For the design of sequence generator we must determine the required number of flip-flops and the logic circuit for next state decoder. Number of flip-flops required Number of flip-flops required to generator particular sequence can be determined as follows : * Find the number of Is in the sequence * Find the number of 0s in the sequence * Take the maximum out of two © If N is the required number flip-flop, choose minimum value of n to satisfy equation given below max (0s, 1s) < 2"-! hump Example 6.8: Find the number of flip-flops required to generate the sequence 1101011. Solution : The given sequence number of 0s are 2 and number of Is are 5. Therefore equation becomesAnalysis & Design of Synchronous Digital Logic Circuits 6-45 Sequential Circuits max (2,5) <2"! 5 < ant n=4 Once the number of flip-flops are decided, we have to assign unique states corresponding to each bit in the given sequence such that flip-flop representing least significant bit generates the given sequence. (Usually, the output of the flip-flop representing least significant bit is used to generate the given sequence). imu Example 6.9: Find the state assignments for sequence 1101011 Solution : We have already seen that this sequence requires four flip-flops. Assuming the output of D flip-flop as a desired sequence state assignments are shown in Table 6.29. A B Cc D ‘States | 0 0 0 1 1 | o oO 0 oO 0 1 0 oO o 41 0 Table 6.29 ‘mp Example 6.10: Referring Table 6.29, draw state diagram and implement the sequence generator. Solution : Fig. 6.58 State diagram‘Sequential Circuits Analysis & Design of Synchronous 6-46 Digital Logic Circuits Flip-flop Inputs Next stato Prosont stato Qa | Qe | Qe | Qo [Qa+i/ Quer fQe+1/Qo+i| Ja | Ka | Ja | Ke | Jo | Ke ve | Kp Table 6.30 K-map Simplification Please Fig. 6.59 on next page. Logic Diagram Fig. 6.60aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Analysis & Design of Synchronous Digital Logic Circuits 6-64 Sequential Circuits 110, D = 011, E = 100. Three D Solution : State assignments are A = 000, B = 001, C flips-flops are required. x Present state Next state Output Oy Oy Qe Es O51 cos ¥ ° ° ° 0 o o o ° o o ° 1 ° 1 ° ° o ° 1 0 o 1 1 0 ° ° 1 1 ° ° ° ° 0 1 ° 0 0 1 o i 1 0 o 0 0 0 1 0 1 o ° 1 ° 0 1 ° 1 0 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 0 0 oO 1 Table 6.42 The flip-flop inputs D4, Dg and Dg are not included in the excitation table as they equal to the next state. Dy = Qari Da = Quer and De = Qesi Dg=XQgQct XQqOg Fig. 6.81\ Analysis & Design of Synchronous Digital Logic Circuits 6-68 Sequential Circuits Logic Diagram “Tse +— t + Qa, GA am Lt Q QQ aa [on Lt Output & Fig. 6.84 (a) mmp Example 6.22: Construct the transition table, state table and state diagram for the Mealy sequential circuit given in Fig. 6.85 (a).Analysis & Design of Synchronous Digital Logic Circuits 6-69 Sequential Circuits Fig. 6.85 (a) Example of a Mealy model Solution : 1. Determine the flip-flop input equations and the output equations from the sequential circuit Y = XAB Jn = XB Ky = XB XA Kp = XA 2. Derive the transition equations The transition equations for JK flip-flops can be derived from the characteristic equation of JK flip-flop as follows : We know that for JK flip-flop, Q = JG+kQ SATS QE = JaQa +KaQa = XBO, +XBQa = XBA+(X+B)A and B= Q5 = JsQg+KeQsAnalysis & Design of Synchronous Digital Logic Circuits 6-70 Sequential Circuits 3. Plot a next-state maps for each flip-flop. The next-state maps are : For A A =XBA+(X+B)A B= KAB+ K+A)B Fig. 6.85 (b) 4, Plot the transition table. The transition table can be formed by combining the above two maps. The table 6.46 shows the transition table. Present State Next state Output AB x=0 | x=1 Y = XAB a’e’ | a’Bt | x=0 | x= 00 00 10 ° 0 o1 o4 00 0 o 10 14 10 0 1 o1 Table 6.46 (a) Transition table Note : For Mealy sequential circuit output depends on present state as well as on input.Analysis & Design of Synchronous Digital Logic Circ 6-71 Sequential Circuits . Draw the state table By assigning a = 00, b = 01, c = 10 and d = 11 we can write state table from the transition table as shown below. Present State Next state Output AB x=0 xsd Y BY | ate’ | x=0 xX=1 a (00) a c oO 0 b (01) b a 0 0 ¢ (10) d e oO 1 (11) b 4 0 0 Table 6.46 (b) State table 6. Draw the state diagram From the state table we can draw the state diagram as shown in Fig, 6.86. 1" Fig. 6.86 State diagram mm Example 6.23: Derive the transition table, state table and state diagram for Moore sequential circuit shown in Fig. 6.87. Fig. 6.87Analysis & Design of Synchronous Digital Logic Circuits 6-72 ‘Sequential Circuits Sol 1. Determine the flip-flop input equations and the output equations from the sequential circuit = XB = X®A 2. Derive the transition equations. The transition equations for JK flip-flops can be derived from the characteristic equation of JK flip-flop as follows : We know that for JK flip-flop, Q = J0+KO s AT=QK = Ja Ga +KaQa = BO, + XBQa = BA+(X+B)A and BY =Q% = JnOp+RoQx =XO, +X®A-On = XB+ XOAB 3. Plot a next-state maps for each flip-flop. The next-state maps are : A eBR+ + BA B+ XGA-8 Fig. 6.88 Next state maps 4 Plot the transition table. The transition table can be formed by combining the above two maps. The Table 6.47 (a) shows the transition table. Prosent State Noxt stato Output AB X=0 | x=1 |Y¥= aos atee | att 00 01 oo 0 04 W 10 1 10 oe 10 1 i oo 44 o Table 6.47 (a) Transition tableAnalysis & Design of Synchronous Digital Logic Circuits 6-73 Sequential Circuits Note : For Moore sequential circuit output depends only on present state and not on an input. 5. Draw the state-table By assigning a = 00, b = 01, c = 10 and d = 11, we can write state table from the transition table as shown below. Present State Next state Output AB xX=0 xed Y A’B’ | A’B” a (00) b a 0 bot 4 © 1 c (10) d ‘ 1 a (11) a d 0 Table 6.47 (b) State table 6. Draw the state diagram From the state table we can draws the state diagram as shown in Fig. 6.89. Fig. 6.89 State diagramAnalysis & Design of Synchronous Digital Logic Circuits 6-76 Sequential Circuits 15. Analyze the given circuit and obtain the transition table. Table 6.49 16. Obtain the transition table for the given state diagram and design the sequential network using JK Slp-fiop. Fig. 6.95 State diagramaa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digital Logic Circuits Analysis & Design of Synchronous: 6-92 Sequential Circuits Ans.: Excitation Table Present state Q.27 Design a synchronous decade counter using D flip flop. [Dec-2007, 16 Marks} Q | % | Ox | O+1| A+1|An+1] Wave 0 ° 0 0 1 alolslo alolololololololo K - map simplification : For Qp 4 x|x]o}+f+lelelololelolo Fig. 6.107Analysis & Design of Synchronous Digital Logic Circuits 6-93 ‘Sequential Circuits Qoa1 = QQq +QcQsQn ear = QWcBptQcGq +QcQuQy Qeer = BpOsQa +QnQq Qe = A Logic diagram cu Fig. 6.108Analysis & Design of Synchronous Digital Logic Circuits 6-95 Sequential Circuits K-map simplification : Tp = Aq Op +O, Gy Qe Fig. 6.109 Logic diagram : Fig. 6.110 Fig. 6.111 shows the timing diagram for the synchronous decade counter. Timing diagram : oP Fig. 6.111 Timing diagramAnalysis & Design of Synchronous Digital Logic Circuits 6-96 ‘Sequential Circuits Q.29 For a four bit even parity bit generator, inputs come serially. The four bits of the input sequence are to be examined by the circuit and circuit produces a parity bit which is to be added in the original sequence. The circuit should get ready for receiving another four bits after producing a parity bit for the last sequence. Draw the state diagram and write down the state transition table. (May/June-2008, 10 Marks] Ans. : The state diagram for given problem is as shown in the Fig. 6.112. State diagram : Fig. 6.112 State table : Next state x=0 xa z s & 85 Ss, % 8 Table 6.52Digital Logi Analysis & Design of Synchronous cuits 6-98 Sequential Circuits Q.31 Q.32 Ans. : Ans. = Next state decoder is a combinational circuit which accepts external inputs and inputs from the present state and derives inputs for the memory elements (fip-flops) to generate desired next state. Memory elements are nothing but the flip-flops. They change their outputs upon activation of clock pulse The output of the circuit is derived from the combination of present state of flip-flops and input(s) to the circuit. Changes occuring in a circuit in a single clock pulse cannot affect the state of flip-flop. But they can affect the output of the circuit. Thus, if input does not vary in synchronism with the dock, the derived output will also not be synchronized with the clock. This may lead to a false output in case of Mealy model. Design a mod-7 counter using JK flip-flops. INov-/Dec.-2008, 6 Marks] Refer example 6.13. Design a BCD up/iown counter using SR flip-flops. INov./Dec.-2008, 6 Marks] Excitation table ve | Present state Next state Flip-flop Inputs vA Bc D| A+ Bt C+ De |S RalSa RolSc Re[SoRo| o}o 0 1 of 0 0 o 14 Jo xfo xJo 1]1 0 ojo 0114} 0 0 4 0 Jo xJo x}x ofo 4 o}o 10 0/0 o 4 4 }o xfo t]4 of1 0 ofo 14 0] 0 4 0 14 }0 x}x ofo 1)14 0 o}o 147 4/0 4 4 0 |o x}x o]x ofo 4 oj1 00 0} 0 4 4 1 |o 4/1 of1 o]4 0 o}1 0 0 4} 4 0 0 0 |x ofo x}o x}o4Analysis & Design of Synchronous Digital Logic Circuits 6-99 Sequential Circuits Table 6.54 K-map simplification For S, _ M=u/D=0 Meu/D=1 Ra=MAD+MADAnalysis & Design of Synchronous Digital Logic Circuits 6-101 ‘Sequential Circuits For Sp M=0 Mat aC 00 a 10 ad ooo: 110 cof 1] 0 | o [fa of] ty of o fa of solo ta orf tof o fa na} xix | x dix an] xi x | x fix to} sf] 0 | x fix 1 x fix M=0 M=1 10 Q.33 What is a state ? Ans.: Refer section 6.1. Q.34 Why is state reduction necessary Ans.: Refer section 6.2.3. 3, 1, 5, 0, 7. Ans.: Since 2° > 7, three flip-flops + 1y 0 1[ aio x |x|} x a | xf x Fig. 6.114 Logic diagram (Please see Fig. 115 on next page) (May/June-2009, 2 Marks} ? [May/June-2009, 2 Marks] Q.35 Design a synchronous counter using JK flip-flop to count the following sequence 7, 4, [May/June-2009, 16 Marks] are required state aT Be Te Th [os He oc Re 1 i 7 [|x| -« | o- 1 oO 1 1x Ox ‘xO x |x | «x | xm |x | «x oO o 4 ox x1 x0. 0 1 1 |x [| ™ | ox oO oO oO xt Ox x4 x x x xx xx xx 1 0 o | xo | x | xaa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digital Logic Circuits 7-1 Asynchronous Sequential Circuits unequal delays, a race condition may cause the state variables to change in an unpredictable manner. For example, if there is a change in two state variables due to change in input variable such that both change from 00 to 11. In this situation, the difference in delays may cause the first variable to change faster than the second resulting the state variables to change in sequence from 00 to 10 and then to 11. On the other hand, if the second variable changes faster than the first, the state variables change from 00 to 01 and then to 11. If the final stable state that the éircuit reaches does not depend on the order in which the state variable changes, the race condition is not harmful and it is called a noneritical race. But, if the final stable state depends on the order in which the state variable changes, the race condition is harmful and it is called a critical race. Such critical races must be avoided for proper operation. Let us see the examples of noncritical races and critical races. Noncritical Races Fig. 7.12 illustrates noncritical races. It shows transition tables in which X is a input variable and y, y, are the state variables. Consider a circuit is in a stable state y,y>x = 000 and there is a change in input from 0 to 1. With this change in the input there are three possibilities that the state variables may change. They can either change simultaneously from 00 to 11, or they may change in sequence from 00 to Oland then to 11, or they may change in sequence from 00 to 10 and then to 11. In all cases, the final stable state is 11, which results in a noncritical race condition. In Fig. 7.12 (b) final stable state is yayxx = 101. Possible transitions : Possible transitions oo 1 00 > 11-10 00 = 0111 00 = 10 00 > 10-11 00 = 01-11 10 (a) ) Fig. 7.12 Examples of noncritical races Critical Races Fig, 7.13 illustrates critical race. Consider a circuit is in a stable state y,y;x = 000 and there is a change in input from 0 to 1. If state variables change simultaneously, the final stable state is yyyox = 111. If Y) changes to 1 before Y, because of unequal propagationDigital Logic Circuits 7-12 Asynchronous Sequential Circuits delay, then the circuit g2°s to the stable state 011 and remain there. On the other hand, if Y, changes faster than Y,, then the circuit goes to the stable state 101 and remain there. Hence, the race is critical because the circuit goes to different stable states depending on the order in which the state variables change. Possible transitions : 00 11 00 01 00 —= 10 Fig. 7.13 Example of critical race Cycles A cycle occurs when an asynchronous circuit makes a transition through a series of unstable states. When a state assignment is made so that it introduces cycles, care must be taken to ensure that each cycle terminates on a stable state. If a cycle does not contain a stable state, the circuit will go from one unstable state to another, until the inputs are changed. Obviously, such a situation must always be avoided when designing asynchronous circuits. Two techniques are commonly used for making a critical-race free state assignment. 1. Shared row state assignment. 2. One hot state assignment. 7.4.3.2 Shared Row State Assignment Races can be avoided by making a proper binary assignment to the state variables. Here, the state variables are assigned with binary numbers in such a way that only one state variable can change at any one time when a state transition occurs. To accomplish this, it is necessary that states between which transition occur be given adjacent assignments. Two binary values are said to be adjacent if they differ in only one variable. For example, 110 and 111 are adjacent because they differ only in the third bit. Fig. 7.14 shows the transition diagram. The transition diagram shows that there is transition from state a to state b and transition from state a to state c. The state a is assigned binary value 00 and state c is assigned binary value 11. This assignment will cause a critical race during the transition from a to c because there are two changes in the binary state variables. A race free assignment can be obtained by introducing additionDigital Logic Circuits 7-14 Asynchronous Sequential Circuits ae oO or 1 10 000% A |®@ 8 c c 0010 B a@®c o 0 100 c 18 ©© 1000 o |®@ 8 c © Fig. 7.16 Flow table which contains 1s where both states A and B have 1s. We require only one state variable change from transition A to E and then from transition E to B. This permits the race-free transition between A and B. In general, we can say that, in row i of the table, state variable F, is 1 and all other state variables are 0. When a transition between row i and row j is required, first state variable Fis set to 1 (so that both R and f are 1), and then F, is set to 0. Thus each transition between two rows in the flow table goes through one intermediate row. This permits the race-free transition but requires two state transition times. The Fig. 7.17 shows the complete one hot state assignment flow table. When X;X2 =01 the transition from A to B is passing through the dummy state E. Similarly, when X1Xz =00 the transition from C to A is passing through the dummy state F and so on. The original table thus gets modified and it is as shown in Fig. 7.17. State variables Fa Fy Fo 0 Original 1 table Added rows Fig. 7.17 One hot state assignment flow tableaa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digital Logic Circuits 7-417 Asynchronous Sequential Circuits There are two methods to implement a circuit representing the transition table : Traditional method and implementation using SR latch. 7.4.44 Implementation using Traditional Method In traditional method, the Boolean expressions for function and the output are derived using K-map simplification. Then each boolean expression is implemented using logic gates, as shown below. K-map simplification For F FA 00044440 Fig. 7.23 Note : In K-map for Z, to make F* = Z we have purposely taken don't care in the 2! row as 0. Logic diagram Fig. 7.24 7.4.4.2 Implementation using SR Latch We can also implement the circuit represented by transition table using SR latch. In this case we have to derive the input expressions for S and R inputs of SR latch. To derive the input expressions first we have to obtain the K-map for S and R by referring the excitation table of SR latch and then solve the K-map for $ and R, individually. This is illustrated in Fig, 7.25. Here, we have to see the transition from transition table and obtainAsynchronous Sequential Circuits Fig. 7.26 State diagram for given problem A primitive flow table is constructed from the state diagram shown in Fig. 7.27. Next state Output Z forX,X, Inputs Fig. 7.27 Primitive flow table for given problemDigital Logic Circuits Fig. 7.28 Merger graph The merger graph gives the two compatible pairs as a set of maximal compatibles. (A, B) > So (CE) > (D, F) > S2 This set of maximal compatible covers all of the original states resulting in the reduced flow table as shown in Fig. 7.29. Next state, Output Z for XX, Inputs 01 1 S .- Fig. 7.29 Reduced flow table Now if we assign Sy -»00, S; 01 and S; -»10 then we need one more state S3 -+11 to prevent critical race during transition of $;>S, or S2 +S. By introducing $3 the transitions $; -»S: and Sz -»$; are routed through Ss. Thus, after state assignment the flow table can be given as shown in Fig. 7.30.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digital Logic Circuits 9-7 Programmable Logic Devices (PLDs) 9.3 Programmable Logic Array (PLA) The combinational circuit do not use all the minterms every time. Occasionally, they have don’t care conditions. Don’t care condition when implemented with a PROM becomes an address input that will never occur. The result is that not all the bit patterns available in the PROM are used, which may be considered a waste of available equipment. OE {ouput enabe) Fig. 9.7 Block diagram of a PLA For cases where the number of don’t care conditions is excessive, it is more economical to use a second type of LSI component called a Programmable Logic Array (PLA). A PLA is similar to a PROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the PROM. The PLA replaces decoder by group of AND gates, each of which can be programmed to generate a product term of the input variables. In PLA, both AND and OR gates have fuses at the inputs, therefore in PLA both AND and OR gates are programmable. Fig. 9.7 shows the block diagram of PLA. It consists of n inputs, output buffer with m outputs, m product terms, m sum terms, input and output buffers. The product terms constitute a group of m AND gates and the sum terms constitute a group of m OR gates, called OR matrix. Fuses are inserted between all n inputs and their complement values to each of the AND gates. Fuses are also provided between the outputs of the AND gates and the inputs of the OR gates. The third set of fuses in the output inverters allows the output function to be generated either in the AND-OR form or in the AND-OR-INVERT form. When inverter is bypassed by link we get AND-OR implementation. To get AND-OR-INVERTER implementation inverter link has to be disconnected. 9.3.1 Input Buffer Input buffers are provided in ! ' the PLA to limit loading of the a ‘oot T*'0 sources that drive the inputs. They u ' TT also provide inverted and non-inverted form of inputs at its output. The Fig. 9.8 shows two Fig. 9.8 Input buffer for single input line ways of representing input buffer for single input. @ ©)Digital Logic Circuits 9-8 Programmable Logic Devices (PLDs) 9.3.2 AND Matrix ‘The Fig. 9.9 shows the AND matrix. It is used to form product terms. It has m AND gates with 2n inputs and m outputs, one for each AND gate. The Fig. 9.9 shows the AND Ver Outputs Fig. 9.9 Internal structure of AND matrix gates formed by diodes and resistors structure. Each AND gate has all the input variables in complemented and uncomplemented form. There is a nichrome fuse link in series with each diode which can be burn out to disconnect particular input for that AND gate. Before programming, all fuse links are intact and the product term for each AND gate is given by P = To-lo-li-h Ty Tat The Fig. 9.10 shows the simplified and equivalent representation of input connections for one AND gate. The array logic symbol shown in Fig. 9.10 (b) uses a single horizontal line connected to the gate input and multiple vertical lines to indicate the individual inputs. Each intersection between horizontal line and vertical line indicates the fuse connection.Digital Logic Circuits 9-9 Programmable Logic Devices (PLDs) les Toot ') ——1.»—__ iy ——r.-———_} = X indicates oo fuse link (@) we Fig. 9.10 Equivalent representation of AND gate The Fig. 9.11 shows the simplified representation of AND matrix with input buffer. No To ty Teen tes Tet Fig. 9.11 Simplified representation of AND matrix with input buffer 9.3.3 OR Matrix The OR matrix is provided to produce the logical sum of the product term outputs of the AND matrix. The Fig. 9.12 shows the OR gates formed by diodes and resistors, structure. Each OR gate has all the product terms as input variables. There is a nichrome fuse link in series with each diode which can be burn out to disconnect particular product term for that OR gate. Before programming, all fuse link in OR matrix are also intact and the sum term for each OR gate is given by S = Potht Pm-2 + PrtDigital Logic Circuits 9-10 Programmable Logic Devices (PLDs) Fig. 9.12 The Fig. 9.13 shows the simplified and equivalent representation of input connections for one OR gate. The Fig. 9.13 shows the simplified representation of OR matrix. Po Py Pz Pet Po. Py 8 8 Pra Pat X indicates fuse link Fig. 9.13 Equivalent representation of OR gate Py Py Pa Paws Fig. 9.14 Simplified representation of OR matrixaa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.Digital Logic Circuits 10-24 Logic Families Similarly, when the output is low, each load supplies current to the totem pole, so Q, must be capable of sinking the sum of these currents. In this case, fanout is defined as Kouimay Fanout = Mima | For standard TTL, louima = 16 MA and Iejnsx) = -16mA lomA [-lémA] 10 Therefore, Fanout = We have seen that fanout can be determined in two ways. Here, in both cases fanout is 10. But if they differ, the actual fanout is always the smaller of the two computations. 10.3.5 Wired Logic Until now we have seen totem pole output. One problem with totem pole output is that two outputs cannot be tied together. See the Fig. 10.20 , where the totem pole outputs of two separate gates are connected together at point X. Suppose that the output of gate A is high (Qs, ON and Qy, OFF ) and the output of gate B is low (Q33 OFF and Quy ON ). In this situation transistor Qyy acts as a load for Qsq. Since Qyy is a low resistance load, it draws high current around 55 mA. This current might not damage Qs, or Qus immediately, but over a period of time can cause overheating and deterioration in performance and eventual device failure. +5V +5V Totem pole Totem pole output stage —- [output stage of Gate A i a of GateB Fig. 10.20 Totem-pole outputs tied together can produce harmful currentDigital Logic Circuits 10-25 Logic Families both transistors, transistors Q; and Q, in the totem pole arrangement are turned OFF. As a result, the output is open or floating, i is neither LOW nor HIGH. 114 7401 — s— 11a 7404 9%ec R 116 1408 A 16 7405 B—_ C =A+B+C 11s 7408 c— >>> (a) Wire-ANDed output of NAND gates (b) Wire-ANDed output of inverters 114 7433 14 7433 Veo R [b- (A+B) (C+D) aco AtB+C70 (c) Wire-ANDed output of NOR gates Fig. 10.23 The wired-AND connectionsDigital Logic Circuits 10-26 Logic Families Fig. 10.24 shows the simplified circuit for tristate inverter. It has two inputs A and E. o+5 V © Output Enable(E) Fig. 10.24 Tristate TTL inverter A is the normal logic input whereas E is an ENABLE input. When ENABLE input is “HIGH, the circuit works as a normal inverter. Because when E is HIGH, the state of the transistor Q; (either ON or OFF) depends on the logic input A, and the additional component diode is open circuited as its cathode is at logic HIGH. When ENABLE. input is LOW, regardless of the state of logic input A, the base-emitter junction of Q; is forward biased and as a result it turns ON. This shunts the current through Ri away from Qz making it OFF. As Q: is OFF, there is no sufficient drive for Q4 to conduct and hence Qy tums off. The LOW at ENABLE input also forward-biases diode Dz, which shunt the current away from the base of Q3, making it OFF. In this way, when ENABLE input is LOW, both transistors are OFF and output is at high impedance state, Fig. 10.25 shows the logic symbols for tristate inverter. In above case circuit operation is enabled when ENABLE input is HIGH. Therefore, ENABLE input is active high. The logic symbol for active high enable input is shown in Fig, 10.25 (a). In some circuits ENABLE input can be active LOW, ie. circuit operates when ENABLE input is LOW. The logic symbol for active low ENABLE input is shown in the Fig. 10.25 (b). As mentioned earlier, tristate outputs can be connected together. This is illustrated in Fig. 10.26. When CONTROL input is LOW, upper NAND gate is enabled and its output| Logic Circuits 10-27 Logic Families iF A a ENABLE: ENABLE {a) Logic symbol for active (b) Logic symbol for active high enable input low enable input Fig. 10.25 (A.B) is available on the output terminal. The output of Jower NAND gate is in the tristate. When CONTROL input is high, the output of upper gaie is in the tristate while output of lower NAND gate (CD) is available on the output terminal. The same concept is used when two or more device shares a common bus (A bus is a set of conducting paths). This is illustrated in Fig. 10.26. As shown in the Fig, 10.27 there are two output devices which can te, give data to the one input device. Oupur These three devices are connected together with a common data bus. The common data bus is shared by the two output devices. When CONTROL signal is LOW device 1 is enabled and device 2 is disabled. As a result the data (8-bit) from device 1 is available on the data bus, as shown in the Fig. 10.27 (a). When CONTROL signal is HIGH device 1 is disabled and device 2 is enabled. In this case the data from the device 2 is available on the data bus as shown in the Fig. 10.27 (b). Fig. 10.26 Tristate outputs connected together CONTROL =9 9, Device 1 fouput) Device 2 Device 3 (ouput) ‘lnput) Fig. 10.27 (a)aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.ital Logic Circuits 10 -37 10.4 CMOS Logic Digital circuits with MOSFETs can be grouped into three categories : © PMOS - uses only P-channel enhancement MOSFETs, * NMOS - uses only N-channel enhancement MOSFETs, and * CMOS (complementary MOS) - uses both P- and N-channel devices. PMOS and NMOS digital ICs are economical than CMOS ICs because they have greater packing density than CMOS. NMOS has twice the packaging density than PMOS. Further more, NMOS can operate at about three times faster than their PMOS counterparts. This is because NMOS has faster moving current carriers (electrons) whereas PMOS has slower moving current carriers (holes). CMOS has the greatest complexity and lowest packaging density; however, it has important advantages of high speed and much lower power dissipation. NMOS and CMOS are widely used in the digital ICs, but PMOS ICs are no longer part of new designs. CMOS circuits contain both NMOS and PMOS devices to speed the switching of capacitive loads. It consumes low power and can be operated at high voltages, resulting in improved noise immunity. 10.4.1 CMOS Inverter Fig. 10.34 shows the basic CMOS inverter circuit. It consists of two MOSFETs in series in such a way that the P-channel device has its source connected to + Vpp (a positive voltage) and the N-channel device has its source connected to ground. The gates of the two devices are connected together as the common input and the drains are connected together as the common output. peYo0 Is P-channeKQ,) |_) N-channeW(Q,) Fig. 10.34 CMOS inverter circuitDigital Logic Circuits 10 - 38 Logic Families When input is HIGH, the gate of Q, (P-channel) is at OV relative to the source of Qi ie. Ves =0V. Thus, Q; is OFF. On the other hand, the gate of Qz2 (N-channel) is at + Von relative to its source ie. Ves: = + Von. Thus, Q2 is ON. This will produce Vour = 0 V, as shown in the Fig. 10.34 (a). When input is LOW, the gate of Q; (P-channel) is at a negative potential relative to its source while Q2 has Vcs = 0 V. Thus, Q; is ON and Q2 is OFF. This produces output voltage approximately + Vpo, as shown in the Fig. 10.34 (b). +Vpp, *Vpp Geert os i Input =1 o—+ Output =0 Output =1 (+Vpp) ' L-Fa, (a) Input = 4 (b) Input = 0 Fig. 10.34 Operation of CMOS inverter for both input conditions Table 10.7 summarizes the operation of CMOS inverter circuit Table 10.7 Truth table of inverter 10.4.2 CMOS NAND Gate Fig. 10.35 (See Fig. on next page) shows CMOS 2-input NAND gate. It consists of two P-channel MOSFETs, Qi and Qz, connected in parallel and two N-channel MOSFETs, Q3 and Qy connected in series. * P-channel MOSFET is ON when its gate voltage is negative with respect to its source whereas N-channel MOSFET is ON when its gate voltage is positive with respect to its sourceDigital Logic Circuits 10-40 Logic Families output is therefore connected to +Vpp (HIGH) through Q; and Q> and is disconnected from ground, as shown in the Fig. 10.35 (b). Fig. 10.35 (c) shows the equivalent switching circuit when A = 0 and B = +Vpp. In this case, Q: is on because Vas, = -Vpn and Qs is ON because Ves; = +Vpo. MOSFETs Q2 and Q; are off because their gate-to-source voltages are 0 V. Since Q; is ON and Q3 is OFF, the output is connected to + Vpp and it is disconnected from ground. When A=+Voo and B = OV, the situation is similar (not shown) ; the output is connected to + Vpp through Q2 and it is disconnected from ground because Q, is OFF. Finally, when both inputs are high (A +Vpp), MOSFETs Q; and Q2 are both OFF and Q; and Qy, are both ON. Thus, the output is connected to the ground through Q3 and Q, and it is disconnected from +Vpp. The Table 10.8 summarizes the operation of 2-input CMOS NAND gate. A B a Q@ & a Output 0 0 ON | ON | OFF | OFF 1 0 1 on | orF | oFrF | ON 4 1 0 corr | on | on | OFF 1 1 1 orF | orF | ON | ON 0 Table 10.8 Truth table of NAND gate 10.4.3 CMOS NOR Gate Fig. 10.36 shows 2-input CMOS NOR gate. Here, P-channel MOSFETs Q; and Q2 are connected in series and N-channel MOSFETs Q3 and Qs are connected in parallel. Like NAND circuit, this circuit can be analyzed by realizing that a LOW at any input turns ON its corresponding P-channel MOSFET and tums OFF its corresponding N-channel MOSFET, and vice versa for a HIGH input. This is illustrated in Fig. 10.36. The Table 10.9 summarizes the operation of 2-input NOR gate. A 8 a Q Qs a Output ° ° on | ON | oFF | OFF 1 0 1 ON | OFF | OFF | ON 0 1 0 OFF | ON | ON | OFF | 1 1 orF | OFF | ON | ON Table 10.9 Truth table for NOR gateDigital Logic Circuits 10 -42 Logic Families Parameter CMOS series 4000 B 74 HC 74 HCT 74 AC 74 ACT Megeiny 35 35 20 35 20 Verma) 15 10 08 15 08 Vowt(rin) 4.95 49 49 49 49 Votmax) 0.05 04 0.4 01 04 Vu 1.45 14 29 14 29 Ma 1.45 09 07 14 07 Table 10.10 Fanout : The CMOS inputs have an extremely large resistance (10%) that draws essentially no current from the signal source. Each CMOS input, however, typically presents a 5 pF load to ground as shown in the Fig. 10.37. This input capacitance limits the number of CMOS inputs that one CMOS output can drive. Fig. 10.37 One GMOS output driving several CMOS inputs The CMOS output has to charge and discharge the parallel combination of all the input capacitances. This charging and discharging time increases as we increase number of loads. Typically, each CMOS load increases the driving circuit's propagation delay by 3 ns. Thus, fan-out for CMOS depends on the permissible maximum propagation delay. Typically, CMOS outputs are limited to a fan-out of 50 for low-frequency operation (< 1 MHz). Of course, for high-frequency operation the fan-out would have to be less. Power Dissipation (P,) : The power dissipation of a CMOS IC is very low as long as it is in a de condition. Unfortunately, power dissipation of CMOS IC increases in proportion to the frequency at which the circuits are switching states. For example, a CMOS NAND gate that has Pp =10 nW under DC conditions will have Pp) = 0.1 mW at a frequency of 100 kHz, and 1 mW at 1 MHz.Digital Logic Circuits 10 - 43 Logic Families When CMOS output switches from LOW to HIGH, a transient charging current has to be supplied to the load capacitance. Therefore, as the switching frequency increases, the average current drawn from Vpp also increases, resulting increase in power dissipation. Propagation Delay :The propagation delay in CMOS is the sum of delay due to internal capacitance and due to load capacitance. The delay due to internal capacitance is called the intrinsic propagation delay. The delay due to load capacitance can be approximated as follows : tC) ~ 0.5 R, C, seconds where t,(C;) is either tou OF thir, R, is the output resistance of the gate, and C,, is the total load capacitance. The R, depends on the supply voltage and it can be approximated as R, + Me Tos where I,, is the short circuit output current. Unused Inputs : CMOS inputs should never be left disconnected. All CMOS inputs have to be tied either to a fixed voltage level (OV or Vpp) or to another input. This rule applies even to the inputs of extra unused logic gates on a chip. An unused CMOS input is susceptible to noise and static charges that could easily bias both the P-and N-channel MOSFETs in the conductive state, resulting in increased power dissipation and possible overheating Static-charge Susceptibility (CMOS Hazards) : Every CMOS device is vulnerable to the building up of electrical charge on its insulated gate. Recall that the relationship between charge Q and voltage V on a capacitor having capacitance C is Since the input capacitance at the gate is usually quite small (a few picofarads), a relatively small amount of charge can create a large voltage which may be greater than the breakdown voltage of a MOS gate (typically 100 V). The primary source of charge +Vop i is “static” electricity, usually produced by handling and the motion of various kinds of 150.2 502 plastics and textiles. The CMOS Input terminal Togale input devices are protected against this static charge by on-chip diode-resistor network, as shown in the Fig. 10.38. These diodes are designed to tum ON and Fig. 10.38 Typical network used to protect CMOS from static chargesDigital Logic Circuits 10 - 45 Logic Families Table 10.11 indicates that the input current values for CMOS are extremely low compared with the output current capabilities of any TTL series. Thus, TTL has no problem meeting the CMOS input current requirements. _ But when we compare the TTL output voltages with the CMOS input voltage requirements we find that : Vou (min) for TTL << Vay (ain) for CMOS for these situations TTL output must be raised to an acceptable level for CMOS. This can be done by connecting pull-up resistor _. at the output of TTL, as shown in the Fig. 10.39. The pull-up resistor causes the Fig. 10.39 TTL driving CMOS using exter- TTL output to rise to approximately 5 V in Nal: PU-Up resistor the HIGH state, thereby providing an adequate CMOS input voltage level. TTL Driving HIGH Voltage CMOS : When output. CMOS circuit is operating with Vpp greater than 5V, the situation becomes more difficult. The outputs of many TTL devices cannot be operated at more than 5V. In such cases some alternative arrangement are made. Two of them are discussed below : 1. When the TTL output cannot be pulled up to Vpp, one can use open collector buffer as an interface between totem-pole TTL output and CMOS operating at Vpp 2 5V, as shown in the Fig. 10.40. +10V +5V 10kQ TH TTL (Open collector cmos (Totem-pole output) output) = Fig. 10.40 Open collector buffer used as interface circuit Pet10V cmos Fig. 10.41 Level shifter used as interface circuitDigital Logic Cir 10-47 Logic Famities HIGH Voltage CMOS Driving TTL : Some IC mariufacturers have provided several 7ALS TTL devices that can withstand input voltages as high as 15V. These devices can be driven directly from CMOS outputs operating at Vpp = 15 V. However, most TTL inputs cannot handle more than 7 V, and so interface is necessary if they are to be driven from high-voltage CMOS. In such situations voltage level translators are used. They convert the high voltage input to a 5V output that can be connected to TTL. Fig. 10.43 shows how the 4050B can be used to perform this level translation between 15 V and 5 V. Vpp=15V 15 45V 45V wt ot B 40508 c = ~ TIL gate CMOS gate (CMOS Buffer Fig. 10.43 Level translation using CMOS buffer 10.4.6 Comparison of CMOS and TTL Families Propagation Delay 8 105 0 10 15 4 (ns) Power per gate 017 04 10 2 85 1 (mw) Speed power prod- 14 pd 10.5 ps 100ps | 20ps | 128p) | 4 ps luct or figure of meritDigital Logic Circuits 10-48 Logic Families Input connection | Input cannot be lef open. it has | input can be left open. It ts treated as logic to be connected to 0, or to Vin | high input. or to the another input, Power dissipation | Very less, but increases with ~ | More than CMOS. It is constant, doos not increase in switching speed depend on switching speed. Fan-out is more than TTL Fan-out for TTL is 10. typically 50 More susceptible to noise Less susceptible to noise Table 10.13 10.5 Emitter Coupled Logic The TTL family uses transistors operating in the saturation mode. As a result, their switching speed is limited by the storage delay time associated with a transistor that is driven into saturation. Another logic family has been developed that prevents transistor saturation, thereby increasing overall switching speed by using a radically different circuits structure, called current mode logic (CML). This logic family is also called emitter-coupled logic (ECL). Unlike TTL and CMOS families, ECL does not produce a large voltage swing between the LOW and HIGH levels. It has a small voltage swing, less than a volt, and it internally switches current between two possible paths, depending on the output state. 10.5.1 ECL Characteristics 1. It is the fastest of logic families. The popular 10K and 100K ECL families offer propagation delays as short as Ins. The latest ECL family, ECL in PS (ECL in picoseconds), offers maximum delays under 0.5 ns (500 ps). Transistors are not allowed to go into complete saturation and thus eliminating storage delays. To prevent transistors from going into complete saturation, logic levels are kept close to each other. Due to this transistor is not driven into saturation when its input switches from low to high. . As logic levels are kept close to each other, noise margin is reduced and it is difficult to achieve good noise immunity. Another disadvantage of this approach is that power consumption is more because transistors are not completely saturated. Switching transients are less because power supply current is more stable than in TTL and CMOS circuits. x » = >| | Digital Logic Circuits 10-50 Logic Families OUT! (NOR Output) Ao © OUT2(OR Ouut) Vee 20 Fig. 10.45 2Input ECL OR/NOR gato We can observe that the input and output LOW and * oun HIGH voltage levels for basic ECL family are not same, ain it has 0.6 V difference. This is a problem. This problem can not be solved by connecting diode in series with ‘output to lower its voltage by 0.6 volt because if we Fig. 10.46 Logic symbol aces this, it results poor fanout. Another problem occurs input. when output is HIGH and it drives an another ECL ‘This HIGH output has to drive base current of another ECL input, resulting drop across R, or Rp, reducing the output voltage. These problem of basic ECL are solved by 10 K ECL family. 10.5.4 ECL 10 K Family Improvement Over Basic ECL Family An emitter follower output stage is added to shift the output and input levels and to provide very high current-driving capacity, upto 50mA per output. An internal bias network is added to provide Vyg without the need for a separate, external power supply. It is designed to operate with Voc = 0 and Vgp = - 5.2 V, to improve noise immunity. Parts with a 10H prefix are fully voltage compensated, so they will work properly with power supply voltages other than Vg = ~ 5.2 V.Logic Families 10.47 shows the The DC noise margins for ECL Digital Logic Circuits 10-51 Voltage Levels and Noise Margin a e The Fig. voltage levels and noise margin provided by 10 K ECL family. As Wieeg «OW £0318 Verne shown in the Fig. 10.47, eventhough =0.980 Vorimin power supply is ECL negative Veimin = 1.405 HIGH State assigns the names LOW and HIGH ow margin to the algebrically lower and higher Low sate . Vimax ~ 1.475 DCnoise margin Voltages, respectively. =1690 Vounax Yamin - 1850 -1850 Vounin are 0.155 V in the low state and Fig. 10.47 ECL 10 K 2-input OR/NOR Gate 0.125 V in the high state. These noise margins are much less than TIL and CMOS noise margins. The Fig. 10.48 shows the 10 K ECL 2-input OR/NOR Gate. As mentioned earlier it has two additional components : bias network and complementary emitter-follower pair. The pull-down resistors are provides at the two inputs of OR/NOR gate. They ensures that if the input is left unconnected, it is treated as LOW. The bias network component values are selected to provide. Vg = — 1.29 V. The complementary emitter-follower outputs shift the output voltage levels down by 0.6 volts matching input and output voltage levels and increase the current sourcing capacity. As shown in the Fig. 10.48, the emitter follower outputs used in ECL 10 K requires external pull-down resistors. Differential ‘Amplifier Multiple inputs Veo =0V Bias Complementary Emitter Follower Outputs Vee 2-52V Fig. 10.48 Two input 10 K ECL ORINOR gateDigital Logic Circuits 10-53 Logic Families 10.5.7 Comparison between TTL, CMOS and ECL Families cmos Tm ECL n-channel and | Bipolar junction | Bipolar junction p-channol transistor transistor MOSFET 2 | Vein) 35V 2v -12V 2% | Vigan 15V o8v -14V 4 | Vowimin) 4.95. V 27V -09V 5 | Votan 0.005 V o4v -17N 6 | High level noise] Vy = 145V | 04V 03v magrin 7. | Low level noise] Vy =145V | O4V o3v margin 8 Noise immunity | Better than TTL} Less than More vulnerable Mos to noise 9 | Propagation 70 ns 10 ns 500 ps delay 10. | Switching speed] Less than TTL | Faster than Fastest cmos 11. | Power 0.4 mw 10 mw 25 mw dissipation per gate 12. | Speed power | 0.7 pd 100 pd 05 pd product 13, | Fan-out 50 10 25 14. | Power suppy | 3-15 V Fixed 5 V -45-52V voltage 48. | Application Portable Laboratory High speed instrument instruments. instruments. where battery supply is used.Digital Logic Circuits 10-54 Logic Families Review Questions 1. Define following parameters a) Current and voltage) Fan-out ©) Noise margin 4) Propagation delay ©) Power dissipation P) Speed-power product 2. Drmw the circuit diagram and explain the operation of 2 input TTL NAND gate with totem-pole output. Write a note on multiple emitter transistor. Describe the difference between current sinking and current sourcing. State advantages and disadvantages of totem-pole output. Describe the characteristics of TTL family. Give the comparison of TTL series characteristics. Explain the operation of low and medium power TTL NAND gate. Draw the circuit diagram and explain the operation of 2 input TTL NAND gate with open collector output. 10, Explain the wired-AND connection. 11. Compare the totem-pole and open-collector outputs. 12. Draw and explain the circuit for tri-siate TTL inverter. 13. Draw and explain the internel diagram of typical bus driver. 14, Drew and explain the basic CMOS inverter circuit. 15. Draw and explain the circuit of two input CMOS NAND gate. 16. Drew and explain the circuit of two input CMOS NOR gate. 17. Discuss the characteristics of CMOS family. 18. Explain with neat diagram interfacing of a TTL gate driving CMOS gates and vice-versa. 19. Give the characteristics of ECL family. 20. Draw the circuit diagram of a ECI. NOR / OR gate. Explain the circuit operation. 21. Discuss the advantages of i) Complement output ii) Connecting pull-down resistor at the input of ECL gate. PON anew University Questions with Answers Q.1 List the advantages of ECL as compared to TTL logic family. [Dec.-2003, 2 Marks] Ans. : Refer section 10.5. 2 Draw the circuit of a CMOS two input NAND gate and explain its operation. [Dec.-2003, 8 Marks} Ans. : Refer section 10.42. Q3 Define noise margin. [Dec.-2004, May-2007, 2008, Nov./Dec.-2008, 2 Marks] Ans. : Refer section 10.33.Digital Logic Circuits 10-55 Logic Families Q4 Discuss about the TTL parameters. [Dec.-2004, 10 Marks} Ans. : Refer section 10. QS Draw the TTL inverter circuit. {[Dec.-2004, 10 Marks} Ans, : Refer section 10.3.5. Q6 What is fan-out of a gate? (Dec.-2005, 2 Marks] Ans. ; Refer section 10.2.1. Q7 Draw the circuit of TTL NAND gate and explain its operation. [Dec.-2005, 8 Marks} Ans. : Refer section 10.3.1. Q8 Define pawer dissipation and propagation delay. [May-2005, 2 Marks] Ans. : Refer sections 10.2.4 and 10.25. Q9 Distinguish between 7400 series and 5400 series. [May-2004, 2 Marks] Ans. : Refer section 103.6. Q.10 Draw and explain the circuit diagram of a CMOS NOR gate. {May-2004, 12 Marks) Ans.: Refer section 10.4.3. QA4 Sketch the typical transfer characteristics of a CMOS inverter. (May-2004, 4 Marks] Ans. Vout Yop a7 ceean, : Vn Low " Undefined High Fig. 10.50 CMOS inverter transfer characteristicsDigital Logic Circuits 10-56 Logic Families Q12 Classify the basic families that belong to the bipolar families and to the MOS families. [May-2006, 2 Marks] Ans. : Logic tamities Bipolar MOS I I T l I T 1 TH oon RTL EOL cmos NMOS PMOS Fig. 10.51 Q13 Name and explain the characteristics of TTL family. [May-2006, 8 Marks] Ans. : Refer section 103.10. Q.14 What is the major difference between ECL and TTL ? (Dec.-2006, 2 Marks) Ans. : Refer section 10.5. Q.15 Why does the propagation delay occur in logic circuits ? 1Dec.-2006, 2 Marks] Ans. : Refer section 10.2.4. Q.16 Explain the characteristics and implementation of the following digital logic families. i) CMOS ii) ECL. [Dec.-2006, 16 Marks] Ans. : Refer sections 10.4 and 10.5. Q.17 What is meant by iristate capability? [May-2007, 2 Marks] ‘Ans, : Refer section 10.3.6 Q.18 Differentiate : Source and sink current. [May-2007, 2 Marks} Ans.: — Refer section 10.3.4. Q.19 Give any two applications of open collector logic. (May-2007, 2 Marks] Ans.: © It is used when we require to connect outputs of two or more gates. * It is used when sourcing current requirements is larger than the standard totem-pole output. Q.20 Explain the characteristics and implementation of the following digital logic families. i) TTL. ii) CMOS. {May-2007, 16 Marks] Ans. : i) TTL: Refer section 10.4.6. ii) CMOS : Refer section 10.4.6.Digital Logic Circuits 10 -57 Logic F: iS Q.21 Which is faster TTL or ECL? Which requires more power to operate?[Dec.-2007, 2 Marks] Ans. : ECL is faster and requires more power to operate. Q.22 Wrile notes on : TTL, ECL and CMOS digital logic families. [Dec.-2007, 16 Marks] Ans. : Refer sections 10.3, 10.4 and 105. Q.23 Write note on : ECL family. IMay/fune-2008, 4 Marks] Ans. : ECL family : Refer section 10.5. Q.24 Explain the working of 2 input TTL totem-pole NAND gate circuit. (May/June-2008, § Marks] Ans. : Refer section 10.3.2. Q.25 Explain the working of 2 input CMOS NAND gate circuit, — IMay/June-2008, 8 Marks} Ans. : Refer section 10.4.2. Q.26 Define fan-out. [Nov /Dec.-2008, 2 Marks] Ans. : Refer section 10.2.1. Q.27 Explain the working of a 3-input TTL totem-pole NAND galelNov/Dec.-2008, 10 Marks} Ans, : 3-Input TTL NAND Gate : The Fig. 10.52 shows the three input TTL NAND gate. It is same as that of two input TTL NAND gate except that its Qi (NPN) transistor o+5V om> 10.52 Three input TTL NAND gateDigital Logic Circuits 14-2 RTL Design 2. Information : The information is stored in the registers. The information may be binary numbers, BCD numbers, alphanumeric characters, control information or any other binary coded information. 3. Operations : The operations performed on the information stored in the registers. ‘The operations performed on the data stored in registers are called micro-operations and it is performed in one clock cycle. The operation may be arithmetic operation or logical operation. A statement that requires a sequence of micro-operations for its implementation is called a macro-operation. 4. Control function : The control functions that activate operations and control the sequence of operations. They consists of timing signals that sequence the operations one at a time. The control function is basically a binary variable, when it is logic 1 it initiates the operation; otherwise it inhibits the operation. Register transfer language A micro-operation is an elementary operation performed on the information stored in one or more registers. The result of micro-operation may be stored in source register or it may be stored in the another register. Examples of micro-operation are load, store, clear, shift, count and so on. A sequence of micro-operations are performed to perform one complete operation. For example, to add two numbers following micro-operation sequence has to be performed. 1. Load first number in register 1. 2. Load second number in register 2. 3. Perform add micro-operation. 4. Store the result in the destination register. As shown above it is possible to specify the sequence of micro-operation in a words, but it involves lengthy descriptive explanation. Hence, it is preferred to use symbolic notations to describe the micro-operations. These symbolic notations are also called a register transfer language or computer hardware description language. The micro-operations used in the digital system can be classified as : © Inter-register or register transfer micro-operations They copy information from one register to another. The information does not change during this operation.Digital Logic Circuits 11-4 RTL Design signal depending on the circuit. The Fig. 11.1 shows two 3-bit registers A and B. Each bit storage in the register is implemented by one flip-flop. As shown in the Fig. 11.1, the individual bits in the registers are denoted by register name along with the bit position in the brackets. For example, bit 2 in the register A is denoted as A(2). As shown in the Fig. 11.1, the rightmost bit is always bit 0, with the bit numbers RegisterB increasing from right to left. Thus if register contains n bits, the leftmost bit is numbered n- 1. Therefore, 3-bit A and B registers can be represented as, Register A A = A(2), A(1), A(O) Fig. 11.1 Implementation of a register transfer and B = B(2), B(1), B(O) When we apply clock pulse to all the three flip-flops of B register, the value of the flip-flops of A register will be transferred to (copied into) the corresponding flip-flops of B register. This transfer can be represented by RTL statements as, BQ) — AQ) Bl) — AC); BQO) < A) or simply BOA The above implementation of register transfer without condition can be shown in the generalized form with the help of block diagram. The Fig. 11.2 (a) shows the block diagram representation of statement T : R, € R, in the register transfer language. Here, n represents the number of bits in the registers. The register R, has a load input that is activated by the control variable T. It is synchronized with the clock signal. The Fig. 11.2 (b) shows the timing diagram for the register transfer operation. Control circuit Fig. 11.2 (a) Block diagram representing T : R, <- R, micro-operationDigital Logic Circuits 11-5 RTL Design Fig. 11.2 (b) Timing diagram for T : R; < R, micro-operation It is important to note that the clock is not included as a variable in the register transfer statements. It is assumed that all transfers occur during a clock edge transition either positive or negative. If hardware permits two micro-operations can be executed at the same time. For example, statement exchanges the contents of two registers, they perform R, < R, and R, « R, micro-operations simultaneously they are separated by comma in a statement. T:R,=—R, Ry +— Ry Consider following two statements. TR cA Hh:k @B The first statement transfers the contents of register A to register R; at timing Tj. At timing 1, the contents of register B are transferred to register R,. This is stated by statement 2. The two statements have the same destination register, but have different source registers and timing variable. The Fig. 11.3 shows the block diagram for 3 o Register A, Fig. 11.3 Use of multiplexer to transfer information from two source registers to one destination registerDigital Logic Circuits 1-6 RTL Design implementing above two statements. As shown in the Fig. 11.3, each register has 4-bits and quadruple 2 to 1 multiplexer is used to select the source register either A or B. When T; = 1, register A is selected and when T, = 1, register B is selected. The Table 11.1 summarizes the basic symbols used for register transfers. Symbol Description Examples Letters or letters with numerals | Denotes a register. MAR, R,, PC. Parentheses () Denotes part of register. R, (7 = 0) : bits 7 - 0 of register Ry R,(H) : most significant half of register Ry Denotes transfer of information. | Rp < Ry ‘Separates two micro-operations | Ry < Ry, Ry — that are performed ae Rae ‘simultaneously Colon : Terminates the control function. | T, : ‘Square brackets [ ] ‘Specifies an address for OR & MIAR] memory transfer. Table 11.1 11.2.1 Bus Transfer A digital computer has many registers and it is necessary to provide data path between them to transfer information from one register to another. If separate lines are used between each register, there will be excess number of wires and controlling of those wires make circuit complex. Therefore, in multiple-tegister configuration a common bus system is used to transfer information between two registers. A common bus consists of a set of common lines, one for each bit of a register, through which binary information is transferred one at a time. Control signals are used to determine which is the source register and which is a destination register for that particular transfer. The common bus scheme can be implemented in two ways - «Using multiplexers © Using tri-state bus buffers Implementation of common bus using multiplexers The Fig. 11.4 shows the implementation of common bus system for four registers using multiplexers. Each register has four bits, numbered 0 through 3 and they are routed through multiplexers to the common bus. Here, four multiplexers are used to select four bits of the source register. Each multiplexers has four input lines, two select lines and oneDigital Logic Circuits 41-11 RTL Design available on the common data bus is loaded into register R;. Similarly, when R; .. is set to 1, the contents of register R, are placed on the common data bus. The signals R,,, and R; ow are commonly known as input enable and output enable signals of registers, respectively. Let us see how we can transfer the data from register R, to register Ry Activate the output enable signal of Ry, Ry gu = 1. This places the contents of R, on the common bus. © Activate the input enable signal of R, R, 4, = 1. This loads data from the common bus into the register Ry. All operations and data transfers within the processor take place in synchronization with the clock signal. The control signals which controls a particular transfer are activated either at the rising edge or at the falling edge of the clock cycle. The Fig. 11.8 shows the implementation of one bit register. The edge triggered D flip-flop which stores the one-bit data is connected to the common bus through tri-state buffers. Input D is connected through input tri-state buffer and output Q is connected through output tri-state buffer. The control signal R,, enables the input tri-state buffer and the data from common bus is loaded into the D flip-flip in synchronization with clock input when R,, is active. This is implemented using AND gate as shown in the Fig. 11.8. The control signal R,y: is activated to load data from Q output of the D flip-flop onto the common bus by enabling the output tri-state buffer. ‘Common bus Input tristate switch Output tristate switch i> > Dilip-fop Fig. 11.8 One-bit register It is important to note that when two or more output tri-state buffers are active at a time, there is bus contention. To avoid bus contention no more than one output buffer may be in the active state at any given time. This means that the connected buffers must be controlled such that only one output tri-state buffer has access to the bus line while all other buffers are maintained in a high impedance state. One way to ensure that no more than one output control input is active at any given time is to use a decoder. Let us assume that four registers are connected to the commonDigital Logic Circuits 11-12 RTL Design bus and we have four output control signals one for each register. For such system we requires 2 : 4 decoder. The four outputs of decoder act as four control signals, as shown in the Fig, 11.9. When enable input of the decoder is 0, all of its four outputs are 0 and the bus line is in a high-impedance state because all four output tri-state buffers are disabled. When the enable input is active, one of the output tri-state buffers will be active, depending on the binary values at the select inputs of the decoder. {> Common bus line for bit R Ry Ry 8, Select inputs Enable 2:4 So Decoder — Fig. 11.9 Use of decoder to avoid bus contention 11.2.2 Memory Transfer A memory is a collection of storage cells. Each cell store 1-bit of information. The memory stores binary information in groups of bits called words. To access information from a particular word from main memory each word in the main memory has a distinct address. This allows to access any word from the main memory by specifying corresponding address. The transfer of information from a memory word to the outside environment is called a read operation. The transfer of new information to be stored into the memory is called a write operation. The number of words in the memory decides the size of the memory and the number of address bits. For example, 8-bit address can access upto 2° = 256 different words. The number of information bits can be read or written at a time is decided by the word length (numbers of bits in one word) of the memory. The Fig. 11.10 shows the typical connectionDigital Logic Circuits 11-14 RTL Design DReR, Write: M [AR] © DR The Fig. 11.11 shows the communication between memory unit and multiple registers. As shown in the Fig. 11.11, register Ag through A, are the address registers. The MUX 1 selects one of the address source for memory. The MUX 2 selects one of data source for write operation of memory. The decoder selects the destination register to read data from memory. Input A select | Decoder datasource), (Selects the 8 destination register) Fig. 11.11 Communication between memory unit and multiple registers 11.3 Arithmetic, Logic and Shift Micro-operations 11.3.1 Arithmetic Micro-operations ‘The basic arithmetic operations are : + Add © Subtract * Increment © Decrement © Arithmetic shiftDigital Logic Circuits 1-15 RTL Design Let us see the representation and description of first four arithmetic micro-operations; the arithmetic shift. micro-operation is explained later in conjunction with the shift operation. The Table 11.3 shows the operation. its representation and description. Operation Representation Description Add Rg CR; + Rp Contents of R, and R, are added and result is transferred to Ry. Subtract Ry CR, —Ry Content of Ry are subtracted from content of R, and result is transferred to Rg 1's complement R, Complement the content of Ry. 2's complement. R+d Complement the contents of Ry and add 1 in it. 2's complement subtraction Rj eR, +R +1 Add R, and the 2's complement of Rp. Increment Ry eR, +1 Increment the contents of Ry by one. Decrement Ry eR, -1 Decrement the contents of Ry by one. po Od Table 11.3 Arithmetic micro-operations 11.3.2 Logic Micro-operations Logic micro-operations perform logic operations such as AND, OR, complement and XOR on the strings of bits stored in registers. These operations consider each bit of the register separate'y and treat them as binary variables. Special symbols are used for the logic micro-operations OR, AND and complement to distinguish them from the corresponding symbols used to express Boolean functions. The Table 11.4 gives the list of logic micro-operations and their symbols. Logic micro-operation Symbol OR v AND i Complement Bar(~) EX-OR e Table 11.4 Basic logic micro-operations and symbolsDigital Logic Circuits 11-18 RTL Design The Table 11.8 shows the operation symbols used for two binary variables of a control function and symbols used to specify the operation between two registers. Operation _| Symbols used in control function | Symbol used in register operation AND A OR + v XOR e ® Table 11.8 Symbols With two binary variables and four logic micro-operations we can perform sixteen logic micro-operations. These are listed in Table 11.9. Boolean function | Micro-operation Name of operation Fy=0 Feo Clear FeAAB ‘AND FeAAB AND with second operand complemented FA ‘Transfer A FeAAB AND with first operand complemented Fes Transfer B FeA@B Exclusive OR: FeAve oR FeAve NOR FeA@B Exclusive-NOR FEB Complement B FeAve ‘OR with second operand complemented FeA Complement A FeAvB OR with first operand complemented F AaB NAND Set to all Table 11.9 List of logic micro-operationsDigital Logic Circuits 11-19 RTL Design 11.3.3 Shift Micro-operations Shift micro-operations are used to shift the contents of a register to the left or the tight. This functionality of shift micro-operation is useful for serial transfer of data. When the bits are shifted, first flip-flop in the register receives its binary information from the serial input and the last flip-flop of register gives the information to the serial output. During, a shift left operation the serial input transfers a bit into the rightmost position. During a shift right operation the serial input transfers a bit into the leftmost position. There are three types of shift operations : ‘+ Logical shift © Arithmetic shift * Circular shift or rotate 11.3.3. Logical Shift In logical shift operation the serial input is 0 i.e, the vacant position created within the register due to shift operation is filled with zero, This is illustrated in Fig. 11.12, There are two logical shift micro-operations logical shift left (LShL) and logical shift right (LShR). For example, R, €LSAL R, R, B This is illustrated using following examples : Example 1: A=0100andB=0010.ie. A>B 1 0100 + 1110 2's complement of 0010 1 0010 F= 0010 . Z=0, S=QandV=1@1=0 Example 2: A=0100and B=1011(-5),ie A>B * 1 0100 + 0101 2’scomplement of (-5) 1011 1001 F=1001 «Z=0, S=landV=0@1=1 Case3: S=1,V=00rS=0,V=1,AB Z=OandC=1 2 =O and ($= 0V=00rS=1V=1) ASB Z=OandC =0 S=1V=00rS=0,V=1 Table 11.18 Status bit and relation between A and B 11.10 Design of Shifter The shift register or shifter is a part of processor unit which accepts output of ALU as a data input and may or may not shift this data according to control inputs SHO and SHI. ‘The Table 11.19 shows operations that shifter perfoms according to SH inputs. It may transfer data directly without a shift, or it may shift the data to the right or left or it may give output zero. SH1 SHO | Microoperation Function oo | seF No shift, transfer output of ALU directly. 0 1 | SqshrF Shift right the output of ALU. 1 o | scsnF Shift left the output of ALU. Seo Make output zero. Table 11.19 Function table of shifter Such a +bit shift can be implemented using four 4 : 1 multiplexers. This is shown in the Fig. 11.25. According to SH inputs multiplexers selects the source such that the combinational circuit performs the corresponding function listed in the Table 11.19.Digital Logic Circuits 11-40 RTL Design The Table lists the functions of all selection variables. The table also gives the 3-bit binary code for each of the five fields A, B, D, F and SH. Function of selection variables code A B D | F with, = 0] F with, =4 SH 0.09. Re Fo Ro A CeO Att No Shift oot R Rx Rg A+B A+Btt Shift right, Ip = 0 010 R R R A-B-1 A-B Shift left, |, = 0 ott Ry Ry Ry A-1 ACet O's to output bus 100 R R R AvB 2 = 101 R R, R A@B i Rotate loft with C a) Ry R Re AaB : Rotate right with © 1 1 1 Input Data | Input Data | None A 2 * Table 11.20 Function of control variables for the processor All selection variable collectively forms the 16-bit control word shown in Fig, 11.26 (b). This control word is used to specify a micro-operation for the processor unit. The Table 11.21 list some examples of micro-operations and corresponding control word for processor, Micro-operation Control word | Code in Function BH Cc, F D B A ae R,-R, +R, |000 0 001 000 a10 oot | o2tt AddR, and and R, and store result in Ry Ro-R ooo 1 010111001010 | IEC Compare Ry and Ry RR, | 000 0 000 101 111 101 | 0170 Transfer R, to Ry Roo 011 0 000011 000 000 | _s0co Clear Ry Re snr, [or 0 000 100 111 100 | 4136 Shift Jeft Ry with | Ree RRR, [110 0 100 110 110 110 | C9B6 | Rotate right R with camy Table 11.21 Examples of micro-operations for processor 11.12 Design of Accumulator An accumulator is a multifunction register that, itself, can be made to perform all of the micro-operations in processor unit. The micro-operations included in an accumulator depend on the operations that must be included in the particular processor. To demonstrate the logic design of a multipurpose operational register such as accumulator, we will design the circuit with nine micro-operations, shown in the Table 11.22.Digital Logic Circuits 11-44 RTL Design Control variable Microoperation Function Te AcCAtB Add th Aco Clear % Ack ‘Complement Ty ACAAB AND T AcAvB OR a ACA@B Exclusive-OR % AcshlaA Shiftien ty AcshraA Shifttight te AcAtt Increment if (A = 0) thon (Z = 1) Check for zero Table 11.22 List of micro-operations in which accumulator is involved The block diagram of an accumulator that forms a sequential circuit is shown in Fig. 11.27. The combinational circuit replaces the ALU but cannot be separated from the register, since it is only the combinational-circuit part of a sequential circuit. The A register is referred to as the accumulator register and is sometimes denoted by the symbol AC. Data input ‘Combinational eat Convo! variables Register A Fig. 11.27 Block diagram of accumulator Design specifications 1. The accumulator consists of n-bits. Each bit is represented by one JK flip-flop.Digital Logic Circuits 14-42 RIL Design ~ Partitioning of accumulator in n similar stages n-bit Accumulator Stagen-1 Siagen-2 Stage1 Stage 0 Fig. 11.28 2. As shown above each stage Aj is interconnected with the neighbouring stage A,.1 on its right and stage A,, , on its left. 3. Each control variable T;, i = 0, 1, 2, ..., 8 initiates a particular micro-operation. Only one control variable is enabled at any given time. e . For simplicity, here we will design only one stage of accumulator. Once we obtain one typical stage of the accumulator, we can combine n such stages to get n-bit accumulator. Let us consider micro-operations one by one and derive the flip-flop inputs to implement each of them. Micro-operation Add : TO:A< A+B For this micro-operations, A; (present state) represents one input and B, represents second input and C, represent the previous carry input for the full adder. The output of our sequential circuit should give the same output that of full adder. Thus A,,; (Next state) should represent sum output of full adder and C,,, output should represent carry cutput of full adder. Considering this we can tabulate excitation table for add micro-operation as shown in Table 11.23. Prosont| inputs Next | Flip-flop state state inputs A Bo GS | Aaa | K o 0 0 ° ° x 0 0 4 1 1 x. 0 1 0 1 1 x 0 1 1 0 o x 4 0 0 1 x a 0 1 ° 1 ° x 1 1 1 1 0 ° x 1 1 1 a 1 Table 11.23 Excitation table for add micro-operationDigital Logic Circuits RTL Design Present Input state B 4 o 0 1 Table 11.24 Excitation table for AND micro-operation K-map simplification Fig. 11.30 Therefore, considering control vasisble Ty, the part of the combinational circuit associated with the AND microoperation can be expressed with : J, = 0-T; =0 K = B-T; Micro-operation OR: T,: A<-Av B For this micro-operation, A, (Present state) represents one input and B, represents the second input for OR operation. Thus A;,; (Next state) should represent the output of OR operation. Considering this we can tabulate excitation table for OR micro-operation as shown in the Table 11.25. Flip-flop inputs Table 11.25 Excitation table for OR micro-operation| Digital Logic Circuits 11-50 RTL Design By cascading the n-stages of accumulator we can build n-bit accumulator. The Fig. 11.36 shows the 4-bit accumulator by cascading 4-stages. The control variables Ty to Ty are applied to each stage. We know that the increment operation is enabled with control variable Ty in the first stage. Thus T, control variable is only connected to first stage. The other inputs and outputs in each stage are connected in cascade to form a complete accumulator. Solved Examples wm) Example 11.1: Show the block diagram that executes the statement ly: AB, BOA Solution : fe] a 73 Fig. 11.37 Load wm) Example 11.2: An 8-bit register A has one input q. The register operation is described symbolically as Y : Ay @ 4, Aig, © Ay i= 1, 2,3 ...7 Solution : The register operation described symbolically can be drawn as follows : The Fig. 11.38 shows that it is shift left register with serial input q and control input Y. Fig. 11.38 Imm Example 11.3: Show the hardware implementation for the following statements. The registers are 4-bit in length. TACR, TyACR, TyACR, Ty:ACR; Solution : The given statements can be implemented by two methods : using multiplexer and using enable signals of registers.Digital Logic Circuits 11-51 RTL Design a) Using multiplexer : Load Fig. 11.39 The excitation table for timing encoder is as follows oO oO 0 1 oo} 0 ofo]i}ofof4 oO 1 O 0 1 oO 1 oO oO 0 4 #: (@) 8, =T, 1,7, T)+T; 727M = (OTT = (TOT) (To #7) Fig. (b) Sp =T, 7,1, T)+T; 1,7, To = T@TY)TT = (T3@ 7) (ToT) 11.40| Digital Logic Circuits 41-52 RTL Design Therefore, hardware implementation for timing encoder is as follows : To To Te % a) ,db- Fig. 11.41 b) Using enable signals of registers : Fig. 11.42 mm> Example 11.4: Show the hardware required to implement the following logic micro-operations : _ - @)T,:FEAAB W)T):GeCVD oT,:ECE Solution : mi {e) Fig. 11.43Digital Logic Circuits 11-53 RTL Design imap Example 11.5 : Show the hardware implementation for following statement. X Y Ty + Ty +X): ACA+B Solution : Y wt)OF STD_LOGIC; In this case, the range of the array is unspecified but it is the subrange of defined type, natural. 12,6 Sequential and Concurrent Statements ‘There are two main types of assignment statements in VHDL, sequential statements and concurrent statements. 12.6.1 Sequential Statements While using these statements, the ordering of the statements is important because ordering may affect the meaning of the code, As name suggests, the sequential statements are evaluated in the order in which they appear in the code. Features of Sequential Statements ‘* The sequential statements execute one after another as per the writing oraer. * They must be placed inside a ‘process statement’, Variables are only used in sequential statements. Sequential statements do not generate sequential hardware. 12.6.1.1 Process Statement Process is main concurrent statement in VHDL code which describe the sequential behavior of design. All statements within process execute sequentially in zero time. Only one driver is placed on a signal. The signal is updated with the last value assigned to it within the process. Syntax : PROCESS (sensitivity list) BEGIN: Sequential statements END PROCESS; Example : PROCESS (en, a, b, c, d) BEGIN if en ='1' then a AND b;12-22 Introduction to VHDL END if; END PROCESS; Here ‘en’ signal is in sensitivity list. If en = 00, signal ‘a’ is assigned to output ‘c. Similarly if ‘en’ = 'O1' then 'b' is assigned to ‘c’ else '0' value is assigned to ‘c’. 12.6.1.3 Case Statement The case statement selects one of the branches for execution based on the value of the expression. The expression value must be of a discrete type of a one dimensional array type. Choice may be expressed as single values, as a range of values, by using a | vertical bar : represents an “or” choice, or by using the others clause (when others). You can not overlap the range. Syntax : CASE expression IS WHEN choicel => (statements) WHEN choice 2 => (statements) WHEN OTHERS (statements) END CASE; END PROCESS; Here in this example when x gets value between 0 to 3, a is assigned to z. When x has value 4 then b is assigned to z. Similarly for remaining conditions. 12.6.1.4 Comparison between CASE and IF Statement IF statement produces priority encoded logic. Example : PROCESS (sel, a, b, c, d) BEGIN IF sel = '00' THEN op B, A=Band A Example 12.12 : Write a VHDL source code for full adder. Solution : The Fig. 12.19 shows the circuit diagram of full adder. Fig. 12.19 Implementation of full-adder LIBRARY IEEE ; USE IEEE.std_logic_1164.all ; ENTITY fulladd Is PORT (Cin, A, B : IN STD_LOGIC ; Sum, Cout +: OUT STD_LOGIC) ; END fulladd ; ARCHITECTURE LogicFunc OF fulladd 1S BEGIN sum < = A XOR B XOR Cin ; Cout < = (A AND B) OR (Cin AND A) OR (Cin AND B) ; END LogicFune ; ‘ep Example 12.13 : Write a VHDL source code for 4-bit adder. Solution : The Fig. 12.2 shows the block diagram of 4-bit full adder. LIBRARY IEEE ; USE IEEE.std_logic_1164.all; ENTITY adder4 Is PORT (CIN : IN STD_LOGIC; A3, A2, Al, AO: IN STD_LOGIC;aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this 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book.aa You have either reached a page that is unavailable for viewing or reached your viewing limit for this book.2 Boolean Algebra and Combinational Circuits Boolean algebra : De-Morgan's theorem, Switching functions and simplification using K-maps and Quine Mc-Cluskey method, Design of adder, Subtractor, Comparators, Code converters, Encoders, Decoders, Multiplexers and demultiplexers. © Synchronous Sequential Circuits Fip-Fops: SR, D, JK and T, Analysis of synchronous sequential citcuts; Design of sunchronous sequential circuits - Couniers, State diearam; State reduction; State assignment. © Asynchronous Sequential Circuits Analysis of asynchronous sequential machines, State assignment, Asynchronous design problem. © Programmable Logic Devices, Memory and Logic Families Memories : ROM, PROM, EPROM, PLA, PLD, FPGA, Digital logic families : TTL, ECL, CMOS. ¢ VHDL RTL Design - Combinational logic - Types - Operators - Packages - Sequential circuit benches. (Examples : Adders, Counters, Flip-flops, FSM, Multiplexers/Demultiplexers) Subprograms - Test First Edition : 2010 Technical Publications rune #1, Amit Residency, 412 Shaniwar Peth, Pune - 411030, M.S., India. Telefax : +91 (020) 24495496/97, Email : technical@vtubooks.com Visit us at : www.vtubooks.com