`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:35:20 11/11/2013
// Design Name:
// Module Name: d_flipflop
// Project Name:
// Target Devices:
// Tool versions:
// Description:
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// Dependencies:
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// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module d_flipflop(output reg q, input d, clk);
always @(posedge clk) q <= d;
endmodule
timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:40:56 11/11/2013
// Design Name:
// Module Name: falling_edge_detector

// Project Name:
// Target Devices:
// Tool versions:
// Description:
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// Dependencies:
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// Revision:
// Revision 0.01 - File Created
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//
//////////////////////////////////////////////////////////////////////////////////
module falling_edge_detector(input edge_in,
output detected,
input clock);
wire q0, q1;
d_flipflop dff0(.q(q0), .d(edge_in), .clk(clock));
d_flipflop dff1(.q(q1), .d(q0), .clk(clock));
assign detected =q0 & ~q1;
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:42:22 11/11/2013
// Design Name:
// Module Name: automatic_lock_timer
// Project Name:
// Target Devices:
// Tool versions:

// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module automatic_lock_timer(input Clock, Start, output Timeout);
localparam NUMCLKS =350;
reg [8:0] q;
always @(posedge Clock)
begin
if (!Start||(q ==NUMCLKS))
q<=9'b0;
else
q <= q + 1;
end
assign Timeout =(q ==NUMCLKS);
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:43:26 11/11/2013
// Design Name:
// Module Name: controller_digital_lock_system
// Project Name:
// Target Devices:

// Tool versions:
// Description:
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// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module controller_digital_lock_system(input clock, reset,codesw, anysw,
output reg [1:0] selsw,
output locked, alarm, entimer,
input timeout);
localparam s0=3'b000, s1=3'b001, s2=3'b010,
s3=3'b011,
wrong=3'b100, unlock=3'b101;
reg [2:0] lockstate;
always @(posedge clock or posedge reset)
begin
if (reset == 1'b1)
lockstate <= s0;
else
case (lockstate)
s0 : if (anysw & codesw)
lockstate <=s1;
else if (anysw)
lockstate <= wrong;
else
lockstate <= s0;
s1 : if (anysw & codesw)

lockstate <= s2;

else if (anysw)
lockstate <= wrong;
else
lockstate <=s1;
s2: if (anysw & codesw)
lockstate <= s3;
else if (anysw)
lockstate <= wrong;
else
lockstate <= s2;
s3: if (anysw & codesw)
lockstate <= unlock;
else if (anysw)
lockstate <= wrong;
else
lockstate <= s3;
wrong: lockstate <= wrong;
unlock: if (timeout)
lockstate <= s0;
else
lockstate <= unlock;
default: lockstate <= 3'bx;
endcase
end
always @(lockstate)
begin
case(lockstate)
s0: selsw =0;
s1: selsw = 1;
s2: selsw = 2;

s3: selsw = 3;
wrong: selsw =0;
unlock: selsw = 0;
default: selsw = 2'bx;
endcase
end
assign locked = (lockstate == unlock) ? 0: 1;
assign alarm = (lockstate == wrong) ? 0: 1;
assign entimer = (lockstate == unlock) ? 1: 0;
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:44:18 11/11/2013
// Design Name:
// Module Name: seven_segment_display
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
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// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module seven_segment_display(input locked,alarm,

output A,B,C,D,E,F,G);
reg [6:0] seg;
always @(locked or alarm)
begin
if (alarm == 0)
seg = 7'b0001000; //display ?A?
else if (locked == 0)
seg = 7'b1000001; //display ?U?
else
seg =7'b1110001; //display ?L?
end
assign {A, B, C, D, E, F, G} = seg;
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:45:57 11/11/2013
// Design Name:
// Module Name: digital_lock_system
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:

//
//////////////////////////////////////////////////////////////////////////////////
module digital_lock_system(input clock, clear,
input [6:0] switches,
output alarm, locked,
output A, B, C, D, E, F, G);
wire mux_out, anysw, codesw,
allsw, entimer, timeout;
wire [1:0] selsw;
assign mux_out = selsw[1]?(selsw[0]?switches[6]:switches[0]):(selsw[0]?switches[3]:switches[5]);
assign allsw = &switches;
falling_edge_detector detector1(.edge_in(mux_out),
.detected(codesw),
.clock(clock));
falling_edge_detector detector2(.edge_in(allsw),.detected(anysw),.clock(clock));
automatic_lock_timer timer(.Clock(clock),.Start(entimer),.Timeout(timeout));
controller_digital_lock_system controller_digital_lock_system(.clock(clock),
.reset(clear),
.codesw(codesw),
.anysw(anysw),
.selsw(selsw),
.locked(locked),
.alarm(alarm),
.entimer(entimer),
.timeout(timeout));
seven_segment_display segment_7(.locked(locked),.alarm(alarm),
.A(A),
.B(B),
.C(C),
.D(D),
.E(E),

.F(F),
.G(G));
endmodule