CONTENTS:

Abstract..5 1. Introduction6 2. Design of STACK..7 2.1 Working of STACK. !. "eri#og Source code...11 $. S%nt&esi'ing t&e design.. ....1! 5.(enerating Test benc&

)a*efor+s...16 6. Si+u#ation ,esu#ts. ..27.A..#ications...2 1 . Conc#usion2$ /.,eferences..2 5

ABSTRACT

Design Implementation of Stack(LIFO) Memory Block

A reserved area of memory used to keep track of a program's internal operations, including functions, return addresses, passed parameters, etc. A stack is usually maintained as a "last in, first out" (LIF ! data structure, so t"at t"e last item added to t"e structure is t"e first item used.#"is pro$ect presents an encompassing description of t"e motivation and design decisions for a ro%ust and scala%le &#A'( arc"itecture. In t"is pro$ect t"e o%$ective is to design, synt"esi)e and verify a &#A'( memory %lock using %inary coded read and *rite pointers to address t"e memory array. #"e +#L description for t"e &#A'( is *ritten using ,erilog -.L, and design is simulated and synt"esi)ed using /ILI0/ I&1 2.1i .

1.INTRODUCTION:
MTech VLSI & S!" SIT!BS# "age $

Design Implementation of Stack(LIFO) Memory Block

WHAT IS A STACK (last in first out) &tack is used to store your local varia%les and is used for passing arguments to t"e functions along *it" t"e return address of t"e instruction *"ic" is to %e e3ecuted after t"e function call is over. 4"en a ne* stack frame needs to %e added (as a result of a ne*ly called function!, t"e stack gro*s do*n*ard. #"e stack and "eap are traditionally located at opposite ends of t"e process5s virtual address space. #"e stack gro*s automatically *"en accessed, up to a si)e set %y t"e kernel. Implementation of %ot" t"e stack and "eap is usually do*n to t"e runtime6 &. ften games and ot"er applications t"at are performance critical create t"eir o*n memory solutions t"at gra% a large c"unk of memory from t"e "eap and t"en dis" it out internally to avoid relying on t"e & for memory. &tacks in computing arc"itectures are regions of memory *"ere data is added or removed in a last7in7first7out manner. In most modern computer systems, eac" t"read "as a reserved region of memory referred to as its stack. 4"en a function e3ecutes, it may add some of its state data to t"e top of t"e stack8 *"en t"e function e3its it is responsi%le for removing t"at data from t"e stack. At a minimum, a t"read5s stack is used to store t"e location of function calls in order to allo* return statements to return to t"e correct location, %ut programmers may furt"er c"oose to e3plicitly use t"e stack. If a region of memory lies on t"e t"read5s stack, t"at memory is said to "ave %een allocated on t"e stack. 9ecause t"e data is added and removed in a last7in7first7out manner, stack allocation is very simple and typically faster t"an "eap7%ased memory allocation (also kno*n as dynamic memory allocation!. Anot"er feature is t"at memory on t"e stack is automatically, and very efficiently, reclaimed *"en t"e function e3its, *"ic" can %e convenient for t"e programmer if t"e data is no longer re:uired. If "o*ever, t"e data needs to %e kept in some form, t"en it must %e copied from t"e stack %efore t"e function e3its. #"erefore, stack %ased allocation is suita%le for temporary data or data *"ic" is no longer re:uired after t"e creating function e3its.A call stack is composed of stack frames (sometimes called activation records!. #"ese are mac"ine dependent data structures containing su%routine state information. 1ac" stack frame corresponds to a call to a su%routine *"ic" "as not yet terminated *it" a return.

!.DESI"N O# STACK:

clk pop

count;1<=>
tos;?<=> empty

MTech VLSI & S!" SIT!BS#

pus"@data;?<=> "age % pus"

full

reset

Design Implementation of Stack(LIFO) Memory Block

Figure 1< 9lack%o3 diagram of &#A'(

I$%l&$&ntin' a (I#O s)oul* +& %r&tt, $u-) t)& sa$& as i$%l&$&ntin' a #I#O. .ou )a/& a r&a* %oint&r an* a 0rit& %oint&r an* a *ual %ort RA1. H&r& is a fi'ur& of a (I#O 0it) t0o &ntri&s.

Figure2< A LIF *it" t*o entries.

Aou can see *e *ill read from location 2 if necessary and *e *ill *rite to location ?. -o*ever, unlike a FIF , a pop operation *ill affect t"e *rite pointer, and *orse yet, it *ill affect t"e *rite pointer %efore t"e *rite takes place. In t"is e3ample, if *e *ere to perform a pop and pus" operation simultaneously, t"en *e *ould need to *rite to location t*o after doing t"e read. After*ards, t"e read and *rite pointers *ould "ave t"e same values as %efore. Anot)&r t)in' to t)in2 a+out is t)at it s&&$s 0ast&ful to us& a *ual %ort RA1 )&r&. W& -oul* us& a sin'l& %ort RA1 if it 0&r&n3t for t)& %&s2, -as& of si$ultan&ous %us)&s an* %o%s. Ho0&/&r4 0)&n 0& *o a si$ultan&ous %us) an* %o%4 t)& %oint&rs *on3t -)an'&. W& onl, r&a* an* 0rit& t)& lo-ation %oint&* to +, t)& r&a* %oint&r4 ta2in' -ar& to *o t)& r&a* o%&ration +&for& t)& 0rit& o%&ration. Also4 if ,ou t)in2 a+out it4 0& *on3t n&&* t0o %oint&rs &it)&r. T)&, r&all, n&&* to $o/& in lo-2 st&% 0it) &a-) ot)&r. T)& 0rit& %oint&r is al0a,s t)& r&a* %oint&r if ,ou ar& %us)in' an* %o%%in'4 an* t)& r&a* %oint&r %lus on& if ,ou ar& 5ust %us)in'. A +&tt&r a%%roa-):
MTech VLSI & S!" SIT!BS# "age &

Design Implementation of Stack(LIFO) Memory Block

#"e critical memory location is t"e top of t"e stack. 4e need to read and *rite t"is location if *e are pus"ing and popping at t"e same time. t"er*ise *e only need to read or *rite t"e +AB, never %ot". If *e keep t"e top of t"e stack in a register instead of t"e +AB, t"en *e can do a simultaneous pus" and pop *it"out using t"e memory at all. If *e do $ust a pus", t"en *e need to *rite t"e top of t"e stack register to t"e +AB and store t"e pus"ed value in t"e top of stack register. For a pop *it"out a pus", *e $ust need to read t"e +AB and store t"e result in t"e top of stack register, *"ile providing t"e current top of stack register value as t"e pop result. #"e figure %elo* s"o*s a stack *it" t*o entries using a top of stack register.

Figure ?<A stack *it" t*o entries using a top of stack register

!.1 WORKIN" O# STACK((I#O):

Figure C< data pus" and pop order

Dorts for t"e LIF

are t"e usual clock and reset. 4e "ave status outputs empty and full as

*ell as a count of t"e num%er of data items in t"e LIF . #"en *e "ave a signal indicating a push *it" its associated data, and anot"er indicating a pop. A top of stack value rounds out t"e ports. 0e3t *e use a flag to tell *"en *e are 0ritin'. #"at is *"en *e are asked to pus" and *e "ave room for t"e data. #"is means t"at eit"er *e are not full, or if *e are full, *e are also
MTech VLSI & S!" SIT!BS# "age '

Design Implementation of Stack(LIFO) Memory Block

popping. +eading is similar %ut a little simpler. 4e are r&a*in' if asked to pop and t"ere is data availa%le. 0o* for counting t"e data. 4e compute a com%inational next_count value %ecause t"at allo*s us to register t"e empty and full outputs. #"e logic is really :uite simple. #"e count goes up *"en *e *rite and don5t read, it goes do*n if *e read and don5t *rite. t"er*ise it $ust stays t"e same.For t"e memory pointer, if *e are *riting, t"en *e use t"e location pointed to %y t"e count and if *e are reading t"en *e *ill use t"e location one %efore. 4riting to t"e memory is simple enoug". If *e are *riting and not reading t"en *e *rite t"e current top of stack into t"e +AB. #"e top of stack *ill %e replaced *it" *"at *e are pus"ing onto t"e stack. If *e are *riting and reading, *e don5t *ant to *rite anyt"ing. #"e top of stack register *ill do all t"e *ork in t"is case. For reading, first *e $ust use a simple register t"at can map onto t"e read output register. #"en *e create a top of stack Es"ado*F register. #"is *ill "old t"e value %eing *ritten to t"e top of t"e stack since *e can5t store it in t"e +AB output register. nly t"e +AB can do t"at. Finally *e need a BG/ to select *"o really "olds t"e top of stack value.

Ta+l& 1:6ORT (IST:

DI0 0 . 1 clk active "ig" input clock signal is provided to sync"ronise all operations in t"e &#A'(. 2 reset active "ig" input t"is signal *"en asserted "ig", resets t"e stack. All data cleared and flags set to =. ? C I J K L 2 pus"@data;?<=> pus" pop count;1<=> full empty tos;?<=> C7%it input active "ig" input active "ig" input 27%it output active "ig" output active "ig" output C7%it output
"age (

DI0 0AB1

&IAH0AL #AD1

I0.I'A#I 0

it is a C7%it data input into &#A'(. *rite into &#A'( signal read from &#A'( signal indicates num%er of values stored. signal indicating t"at &#A'( is full. signal indicating t"at &#A'( is empty. indicates t"e last value stored onto &#A'(.

MTech VLSI & S!" SIT!BS#

Design Implementation of Stack(LIFO) Memory Block

7.8ERI(O" SOURCE CODE #OR #I#O DESI"N:

`timescale 1ns/1ns module lifo #( parameter depth = 4, parameter width = 4, parameter log2_depth = 2, parameter log2_depthp1 = 2 ) (

MTech VLSI & S!" SIT!BS#

"age )

Design Implementation of Stack(LIFO) Memory Block

input clk, input reset, output reg empt , output reg full, output reg !log2_depthp1"1#$% count, input push, input !width"1#$% push_data, input pop, output !width"1#$% tos )& // 'e are writing if we are asked to push and are not full or we are also popping wire writing = push (( (count ) depth ** pop)& // 'e are reading if we are asked to pop and there is data in the stack wire reading = pop (( count + $& // , count of the num-er of items in the ./01 is useful and we can use this later // as -oth our read and write pointer2 3eg !log2_depthp1"1#$% ne4t_count& alwa s 5(6) if (reset) ne4t_count = $& else if (writing (( 7reading) ne4t_count = count81& else if (reading (( 7writing) ne4t_count = count"1& else ne4t_count = count& alwa s 5(posedge clk) count )= ne4t_count& // 0ull is eas when ou ha9e the count

alwa s 5(posedge clk) full )= ne4t_count == depth& // ,s is empt alwa s 5(posedge clk) empt )= ne4t_count == $& // :his is the read/write pointer2 /f we are writing we use the count 9alue2 // 1therwise we read from one location -efore2 'ire !log2_depth"1#$% ptr = writing ; count !log2_depth"1#$% # (count !log2_depth"1#$%)"1& // <ere=s the 3,> that holds the data reg !width"1#$% mem !depth"1#$%&

MTech VLSI & S!" SIT!BS#

"age *

Design Implementation of Stack(LIFO) Memory Block

// 'riting is so eas alwa s 5(posedge clk) if (writing (( 7reading) mem!ptr% )= tos& // 0or reading, first, a memor into the -lock 3,> reg !width"1#$% mem_rd& alwa s 5(posedge clk) if (reading) mem_rd )= mem!ptr%& // ?e4t, we need to keep a shadow register that will stand in for // the top of stack if we don=t need the 3,> output reg !width"1#$% tos_shadow& alwa s 5(posedge clk) if (writing) tos_shadow )= push_data& // ?ow, we need a flag to track whether or not we need to use the // 3,> output register or the shadow register reg use_mem_rd& alwa s 5(posedge clk) if (reset) use_mem_rd )= $& else if (writing) use_mem_rd )= $& else if (reading) use_mem_rd )= 1& // ,nd finall a mu4 to select the correct output output register that it can fold

assign tos = use_mem_rd ; mem_rd # tos_shadow& endmodule

9.S.NTHESI:IN" THE DESI"N:

Reading design: lifo.prj * HDL Compilation Compiling verilog file stack2.v in librar !ork "od#le $lifo% compiled &o errors in compilation 'nal sis of file $lifo.prj% s#cceeded. * Design Hierarc( 'nal sis *

MTech VLSI & S!" SIT!BS#

"age +

Design Implementation of Stack(LIFO) Memory Block

'nal )ing (ierarc( for mod#le $lifo% in librar $!ork% !it( parameters. Dept( * +++++++++++++++++++++++++++++,++ log2-dept( * ++++++++++++++++++++++++++++++,+ log2-dept(p, * ++++++++++++++++++++++++++++++,+ !idt( * +++++++++++++++++++++++++++++,++ * HDL 'nal sis * 'nal )ing top mod#le $lifo%. Dept( * .2/sb+++++++++++++++++++++++++++++,++ !idt( * .2/sb+++++++++++++++++++++++++++++,++ log2-dept( * .2/sb++++++++++++++++++++++++++++++,+ log2-dept(p, * .2/sb++++++++++++++++++++++++++++++,+ "od#le $lifo% is correct for s nt(esis. * HDL 0 nt(esis *

1erforming bidirectional port resol#tion2 0 nt(esi)ing 3nit $lifo%. Related so#rce file is stack2.v. 4o#nd 5657bit single7port R'" $"ram-mem% for signal $mem%. 8'R&9&::;st < 1ropert #se-dsp5= is not applicable for t(is tec(nolog . 8'R&9&::;st < 1ropert #se-dsp5= is not applicable for t(is tec(nolog . 4o#nd 27bit register for signal $co#nt%. 4o#nd ,7bit register for signal $empt %. 4o#nd 57bit register for signal $mem-rd%. 4o#nd 27bit adder for signal $ne6t-co#nt>adds#b++++% created at line .5. 4o#nd 27bit s#btractor for signal $ne6t-co#nt>s#b++++% created at line .?. 4o#nd 27bit comparator greater for signal $reading>cmp-gt++++% created at line 2?. 4o#nd 57bit register for signal $tos-s(ado!%. 4o#nd ,7bit register for signal $#se-mem-rd%. 0#mmar : inferred , R'"@sA. inferred ,2 D7t pe flip7flop@sA. inferred 2 'dderB0#btractor@sA. inferred , Comparator@sA. 3nit $lifo% s nt(esi)ed.

HDL 0 nt(esis Report "acro 0tatistics C R'"s 5657bit single7port R'" C 'ddersB0#btractors 27bit adder 27bit s#btractor C Registers ,7bit register 27bit register 57bit register C Comparators 27bit comparator greater * :, :, :2 :, :, :D :2 :, :2 :, :, *

'dvanced HDL 0 nt(esis

MTech VLSI & S!" SIT!BS#

"age ,-

Design Implementation of Stack(LIFO) Memory Block

Loading device for application Rf-Device from file E.s5++.np(/ in environment C:F;ilin6G,i. 9&4H:;st:25D2 < 3nit $lifo% : I(e small R'" $"ram-mem% !ill be implemented on L3Is in order to ma6imi)e performance and save block R'" reso#rces. 9f o# !ant to force its implementation on blockJ #se optionBconstraint ram-st le. 77777777777777777777777777777777777777777777777777777777777777777777777 K ram-t pe K Distrib#ted K K 77777777777777777777777777777777777777777777777777777777777777777777777 K 1ort ' K K aspect ratio K 57!ord 6 57bit K K K clk' K connected to signal $clk% K rise K K !e' K connected to signal $-and++++% K (ig( K K addr' K connected to signal $ptr% K K K di' K connected to signal $tos% K K K do' K connected to internal node K K 77777777777777777777777777777777777777777777777777777777777777777777777 'dvanced HDL 0 nt(esis Report "acro 0tatistics C R'"s 5657bit single7port distrib#ted R'" C 'ddersB0#btractors 27bit adder 27bit s#btractor C Registers 4lip74lops C Comparators 27bit comparator greater * Lo! Level 0 nt(esis :, :, :2 :, :, : ,2 : ,2 :, :, *

Hptimi)ing #nit $lifo% 2 "apping all eL#ations2 M#ilding and optimi)ing final netlist 2 4o#nd area constraint ratio of ,++ @N DA on block lifoJ act#al ratio is +. 4inal "acro 1rocessing 2 4inal Register Report "acro 0tatistics C Registers 4lip74lops * 1artition Report : ,2 : ,2 *

1artition 9mplementation 0tat#s &o 1artitions !ere fo#nd in t(is design.

4inal Report

Clock 9nformation: 77777777777777777777777777777777777N777777777777777777777777N7777777N Clock 0ignal K Clock b#ffer@44 nameA K Load K

MTech VLSI & S!" SIT!BS#

"age ,,

Design Implementation of Stack(LIFO) Memory Block

77777777777777777777777777777777777N777777777777777777777777N7777777N clk K M34:1 K ,? K 77777777777777777777777777777777777N777777777777777777777777N7777777N 's nc(rono#s Control 0ignals 9nformation: &o as nc(rono#s control signals fo#nd in t(is design Iiming 0#mmar : 0peed :rade: 75 "inim#m period: D.GD?ns @"a6im#m 4reL#enc : ,?O.=G="H)A "inim#m inp#t arrival time before clock: ?.+.Dns "a6im#m o#tp#t reL#ired time after clock: G.+5=ns "a6im#m combinational pat( dela : &o pat( fo#nd

1rocess 0 nt(esi)e completed s#ccessf#ll

;."ENERATIN" TEST BENCH WA8E#OR1:

MTech VLSI & S!" SIT!BS#

"age ,$

Design Implementation of Stack(LIFO) Memory Block

Figure I<test %enc" *aveforms

DESI"N SU11AR.:

MTech VLSI & S!" SIT!BS#

"age ,%

Design Implementation of Stack(LIFO) Memory Block

Figure J<.esign summary

RT( SCHE1ATIC 8IEW:

MTech VLSI & S!" SIT!BS#

"age ,&

Design Implementation of Stack(LIFO) Memory Block

Figure K<stack %lack%o3

MTech VLSI & S!" SIT!BS#

"age ,'

Design Implementation of Stack(LIFO) Memory Block

Figure L< +#L sc"ematic of stack

MTech VLSI & S!" SIT!BS#

"age ,(

Design Implementation of Stack(LIFO) Memory Block <.SI1U(ATION WA8E#OR1S:

Figure 2< &imulation *aveforms

MTech VLSI & S!" SIT!BS#

"age ,)

Design Implementation of Stack(LIFO) Memory Block

=.A66(ICATIONS:
1.&tack structures in computing are e3tremely fundamental and important. It is fair to say t"at *it"out t"e a%ility to organi)e data %y order rearrangement, including links to e3ecuta%le code, computers *ould not %e t"e fle3i%le tools t"ey are today, and e3ist solely as e3pensive special purpose calculators like t"e 10IA' of 4orld 4ar II "aving limited a%ilities and scope of application. 2.In suc" *ata or*&rin's, t"e stack is used as a dynamic memory element *"erein an a%stract conceptMa mac"ine dependent &tack frame is used to contain copies of data records or parts t"ereofM%e t"ey actual memory addresses of a data element (&ee parameters pass7 %y7reference!, or a copy of t"e data (pass7%y7value!. In list processing, t"e most common need is sorting (alp"a%etically, greatest to smallest, etcetera.! *"ere t"e mac"ine is limited to comparing only t*o elements at a time, out of a list t"at likely "olds millions of mem%ers. ,arious strategies (computer algorit"ms! e3ist *"ic" optimi)e particular types of data sorting, %ut in implementation all *ill resort to a su%7program and or su%7routines t"at generally call t"emselves or a part of t"eir code recursively in eac" call adding to t"e list temporarily reordered in stack frames. It is for t"is reason, stacks and recursion are usually introduced in parallel in data structures coursesMt"ey are interdependent.;I> ?.Sat-2 fra$&s<It is t"roug" t"e fle3i%ility of t"is access to data %y stack7frames *it" t"eir data re7groupings (in a%stract a LIF organi)ed %lock of data *"ic" seems only to allo* data some improvement on ordering fle3i%ility! t"at su%7programs and su%7routines receive t"eir input, do t"e task t"ey are optimi)ed to perform, and pass information %ack to t"e program segment currently in c"arge.;?> #"e stack frame in actual cases includes t"e address of t"e ne3t instruction of t"e calling program segment, *"ic" ordinarily t"en does somet"ing *it" t"e data "ans*er" processed %y t"e su%routines or su%program. In a recursive call, t"is is generally an instruction to c"eck t"e ne3t list element versus t"e returned "ans*er" (e.g. largest of t"e last t*o compared!, until t"e list is e3"austed. C.Auto$ati- /aria+l&s: may %e allocated in t"e stack frame of t"e procedure in *"ic" t"ey are declared8 t"is "as t"e useful effect of allo*ing recursion and re7entrancy. (For efficiency, t"e optimi)er*ill try to allocate some of t"ese varia%les in processor registers.! #"e term #oca# *ariab#e is usually synonymous *it" automatic varia%le, since t"ese are t"e same t"ing in many programming languages, %ut local is more general N most local varia%les are
MTech VLSI & S!" SIT!BS# "age ,*

Design Implementation of Stack(LIFO) Memory Block

automatic local varia%les, %ut static local varia%les also e3ist, nota%ly in '. For a static local varia%le, t"e allocation is static (t"e lifetime is t"e entire program e3ecution!, not automatic, %ut it is only in scope during t"e e3ecution of t"e function I.Call sta-2< In computer science, a call stack is a stack data structure t"at stores information a%out t"e active su%routines of a computer program. #"is kind of stack is also kno*n as an e3ecution stack,control stack, run7time stack, or mac"ine stack, and is often s"ortened to $ust "t"e stack". Alt"oug" maintenance of t"e call stack is important for t"e proper functioning of most soft*are, t"e details are normally "idden and automatic in "ig"7level programming languages. A call stack is used for several related purposes, %ut t"e main reason for "aving one is to keep track of t"e point to *"ic" eac" active su%routine s"ould return control *"en it finis"es e3ecuting. An active su%routine is one t"at "as %een called %ut is yet to complete e3ecution after *"ic" control s"ould %e "anded %ack to t"e point of call. &uc" activations of su%routines may %e nested to any level (recursive as a special case!, "ence t"e stack structure. If, for e3ample, a su%routine .ra*&:uare calls a su%routine .ra*Line from four different places, .ra*Line must kno* *"ere to return *"en its e3ecution completes. #o accomplis" t"is, t"e address follo*ing t"e call instruction, t"e return address, is pus"ed onto t"e call stack *it" eac" call J.Sta-2 +as&* $&$or, allo-ation< 9ecause t"e data is added and removed in a last7in7first7 out manner, stack7%ased memory allocation is very simple and typically faster t"an "eap7 %ased memory allocation (also kno*n asdynamic memory allocation!. Anot"er feature is t"at memory on t"e stack is automatically, and very efficiently, reclaimed *"en t"e function e3its, *"ic" can %e convenient for t"e programmer if t"e data is no longer re:uired. If "o*ever, t"e data needs to %e kept in some form, t"en it must %e copied from t"e stack %efore t"e function e3its. #"erefore, stack %ased allocation is suita%le for temporary data or data *"ic" is no longer re:uired after t"e creating function e3its.

K.Sta-2 $a-)in&< In computer engineering and in programming language implementations, a stack mac"ine is a real or emulated computer t"at uses a pus"do*n stack rat"er t"an individual mac"ine registers to evaluate eac" su%7e3pression in t"e program. A stack computer is programmed *it" a reverse Dolis" notation instruction set. #"e common

MTech VLSI & S!" SIT!BS#

"age ,+

Design Implementation of Stack(LIFO) Memory Block

alternative to stack mac"ines are register mac"ines, in *"ic" eac" instruction e3plicitly names t"e specific registers to use for operand and result values.

MTech VLSI & S!" SIT!BS#

"age $-

Design Implementation of Stack(LIFO) Memory Block

>.CONC(USION:
#"e main o%$ective of t"e pro$ect *as to "ave a *orking LIF memory %lock t"at functions correctly as per it5s specification O intent, t"e same *as ac"ieved simulating t"e LIF design using /ILI0/ I&1 2.1i # %y designing and L&.#"is design *as verified for it5s

correct functionality %y providing test%enc" *aveforms, simulating O analy)ing t"e response against e3pected one from simulation *aveforms.

MTech VLSI & S!" SIT!BS#

"age $,

Design Implementation of Stack(LIFO) Memory Block

?.RE#ERENCES:
1. "ttp<66en.*ikipedia.org6*iki6Bemory@leak 2. "ttp<66***.cs.$cu.edu.au6&u%$ects6cp2==?6122K6foils6"eapAnd&tack6"eapAnd&tack."t ml ?. "ttp<66en.*ikipedia.org6*iki6&tack@%uffer@overflo* C. "ttp<66stackoverflo*.com6:uestions6K222?6*"at7and7*"ere7are7t"e7stack7and7 "eap6121??J=P121??J= I. "ttp<66stackoverflo*.com6:uestions6K222?6*"at7and7*"ere7are7t"e7stack7and7 "eap6K22LLPK22LL J. "ttp<66stackoverflo*.com6:uestions6K222?6*"at7and7*"ere7are7t"e7stack7and7 "eap6JJ2KL?PJJ2KL? K. "ttp<66en.*ikipedia.org6*iki6&tack7%ased@memory@allocation L. "ttp<66en.*ikipedia.org6*iki6'all@stack 2. "ttp<66stackoverflo*.com6:uestions6K222?6*"at7and7*"ere7are7t"e7stack7and7 "eap6L=11?PL=11? 1=. "ttp<66122.1=K.I2.K6cseI?1K6notes6node??."tml 11. "ttp<66***.%oundsc"eck.com6kno*ledge7%ase6c7cpp6memory7layout7in7c6?C26

MTech VLSI & S!" SIT!BS#

"age $$