MOS Inverters

Digital Electronics - INEL 4207

Prof. Manuel Jimnez

With contributions by: Rafael A. Arce Nazario

Objectives: Introduce MOS Inverter Styles Resistor Load Enhancement Load Saturated / Linear Depletion Complementary (CMOS) Perform DC analysis of the circuits

Ideal Inverter

MOS Devices
Operation regions (Enhancement)
VGS<VT:cutoff ,Vout=VDD VGS>VT ,VDS>VGS-VT: saturation VGS>VT ,VDS<VGS-VT: linear

MOS Devices
Operation regions
VGS<VT:cutoff ,Vout=VDD

ID 0

VGS>VT ,VDS<(VGS-VT): linear

ID = k 2 2(VGS VT )VDS VDS 2
ID = k (VGS VT ) 2 2

VGS>VT ,VDS>(VGS-VT): saturation

ID =
K=device transconductance = channel-length modulation

k (VGS VT ) 2 (1 + VDS ) 2

Static Parameters
Vout VOH=VDD

VM

VOL VM VIL

Vin
VIH

VOH = max output voltage when output is 1 VOL = min output voltage when output is 0 VIL = max input voltage which can be interpreted as 0 VIH = min input voltage which can be interpreted as 1

MOS Inverter - Resistor Load

Vout
VDD

VOH=VDD
RL

Vout=Vin

Vout=Vin-VT VM
OUT

IN

VOL VT VIL |VGS| <VT device is open circuit | VGS| > VT device conducts with resistance RON VM VIH VOH=VDD

Vin

MOS Inverter - Resistor Load : Parameters

VOH

VOH = VDD
Assumption: Must verify latter

VOL

I D (lin ) = I R
2 VDD VOL VOL k (VDD VT )VOL = 2 RL VDD VOL 1 + kRL (VDD VT )

MOS Inverter - Resistor Load : Parameters - VIL

VDD Vout k 2 (VGS VT ) = RL 2 dVout = 1 dVin

dVout dI dVout = D = 1 dVin dVin dI D dI D d k (Vin VT )2 = k (Vin VT ) = dVin dVin 2 dVout dI D = dI D dVout dVout dI D = dVin dVin VIL = VT + 1 kRL d VDD Vout = RL = dV R out L dVout = k (Vin VT )RL = 1 dI D
1 1

MOS Inverter - Resistor Load : Parameters - VIH

V V k 2 2(VIH VT )Vout Vout Vout = DD out RL 2

(1)

dVout dI D dVout = = 1.0 dVin dVin dI D dVout kVDS dI D dVDS = = = 1.0 dVin dVGS dI D k [VGS VT VDS ]

(V V ) Vout = in T 2 substitute in (1)

2 VIH VT 1 VIH VT VDD VIH VT k (VIH VT ) = 2 2 2 2 RL RL solve quadratic expression by VIH

MOS Inverter - Resistor Load : Parameters - VM

VM
VDD VDS k 2 I DS = (VGS VT ) = I R = R 2 k VDD VM 2 (VM VT ) = R 2 1 2 2VDD 2 VM 2VM VT kR + VT kR =0 L L

1 + 2kRL (VDD VT ) 1 2(VDD VT ) VM = VT + VT + kRL kRL

Effect of RL on VTC

As RL increases

But putting a larger resistance would also mean: larger resistor length greater switching delays main disadvantage of resistor load: occupies to much chip area (10s or 100s times the area of a single transistor!)

Using enhancement transistors as load devices

Justification: Since VLSI resistors occupy to much chip space use transistor in either saturation or linear region instead of resistor
VDD

VGG

VDD

Vout Vin

Vin

VOUT

Saturated enhancement load

VDD

Enhancement NMOS with VGS = VDS while VOUT < VDD VT the transistor will be in saturation because VGS > VT & VDS > VGS-VT
Vout

Vin

If VOUT tries to go above VDD-VT , transistor goes cutoff (because VGS < VT)

Saturated enhancement load - VTC

VOUT
Slope =
VOH =VDD- VT(VOH)

KR
KR =

(W / L) inverter (W / L) load

Slope = -1
V DD VOL VIL = VT
VT = VT 0 +

VIN
VIH V out
SB + 2 F 2 F

(V

V in

Linear enhancement load

VGG VDD

Enhancement NMOS with VGG > VDD+VT since VDS = VDD-VOUT and VGS = VGG-VOUT > VDD+VT VOUT VDS < VGS - VT

Vin

VOUT

since VGS > VT : the load is always on linear region

Linear enhancement load - VTC

Pro: VOH = VDD

Disadvantage: Additional voltage source KR must be even larger than for saturated load for decent slope

Depletion load
VDD

Depletion NMOS with VGS = 0 VGS > VT : always conducting

Vout Vin

Good: VOH = VDD no additional V source Bad: addit. fab. process steps

Complementary MOSFET inverter

Features: Complementary MOS (CMOS) Inverter analysis makes use of both NMOS and PMOS transistors in the same logic gate. + All static parameters of CMOS inverters are superior to those of NMOS inverters + CMOS is the most widely used digital circuit technology in comparison to other logic families. lowest power dissipation highest packing density -Increased process complexity (to provide isolated transistors of both polarity types)

Complementary MOSFET (CMOS) inverter

Intuitively: VIN 0 NMOS open ckt. (VGSn <VTn) PMOS conducting (VGSp > VTp) VOUT = VDD VOH = VDD (Good!) VIN VDD NMOS conducting PMOS open ckt. VOUT = 0 VOL = 0 (Great!)

S D D S

CMOS inverter - VTC

1. 2. 3. 4. 5. PMOS linear, NMOS off PMOS linear, NMOS sat PMOS, NMOS both sat PMOS sat, NMOS linear PMOS off, NMOS linear

CMOS inverter Region 2

Region 2

Vout
VOH=VDD

VIN=VTn+

2 PMOS linear, NMOS saturation 3 4 5

VM -VTp

VOL=0

VTn

VM VDD-VTp VOH=VDD

CMOS inverter Param. Calculation Example

Calculate VIH

kn 2 I Dn = 2(VIH VTn )VOUT VOUT 2 kp I Dp = (| VGSp | | VTp |) 2 2

NMOS linear, PMOS saturation

(1)

dI Dp dI Dn dVout dVout = = 1 dVin dVin dI Dp dI Dn k nVOUT + k p (VDD VIH VTp ) dVout = = 1 dVin k n (VIH VOUT VTn ) VIH = 2VOUT + VTn + (k p / k n )(VDD | VTP |) 1 + (k p / k n )

Substitute in (1), then solve for VOUT, finally obtain VIH

CMOS inverter Param. Calculation Example

Calculate VM

NMOS & PMOS saturation

kn I Dn = (| VGSn | | VTn |) 2 2 kp I Dp = (| VGSp | | VTp |) 2 2 kp kn 2 (| VM | | VTn |) = (VDD VM | VTp |) 2 2 2

.. Solve for VM

Summary
CMOS inverter most used, smallest, lowest power dissipation, best inverter characteristics. base for more complex logic gates Calculation of static parameters: VIH, VIL, VOH, VOL, VM. Important: Deduce the region of operation of the transistors (verify later) VIH, VIL slope = -1, use chain rule to simplify calculations VTC affected by R, KR

Recordatorio
Buscar copias de Dr. Jimenez en Reproducciones ($1-$2) Digital circuits using MOS transisitors