Hardware

HARDWARE PROGRAMS
7 Segment Display
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity seg7dec is
port ( Q : in STD_LOGIC_VECTOR(3 downto 0);
AtoG : out STD_LOGIC_VECTOR(6 downto 0));
end seg7dec;
architecture seg7dec_arch of seg7dec is
begin
process(Q)
begin
case Q is
when "0000" => AtoG <= "0000001";
when "0001" => AtoG <= "1001111";
when "0010" => AtoG <= "0010010";
when "0011" => AtoG <= "0000110";
when "0100" => AtoG <= "1001100";
when "0101" => AtoG <= "0100100";
when "0110" => AtoG <= "0100000";
when "0111" => AtoG <= "0001101";
when "1000" => AtoG <= "0000000";
when "1001" => AtoG <= "0000100";
when "1010" => AtoG <= "0001000";
when "1011" => AtoG <= "1100000";
when "1100" => AtoG <= "0110001";
when "1101" => AtoG <= "1000010";
when "1110" => AtoG <= "0110000";
when others => AtoG <= "0111000";
end case;
end process;
end seg7dec_arch;
VHDL File Name: keypad_led_display.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity keypad_led_display is
Port ( clk : in STD_LOGIC;
key_rl : in BIT_VECTOR (3 downto 0);
key_sc : out BIT_VECTOR (3 downto 0);
digit : out STD_LOGIC_VECTOR (5 downto 0);
seg_out : out STD_LOGIC_VECTOR (6 downto 0));
end keypad_led_display;
architecture Behavioral of keypad_led_display is
signal clk_div:std_logic_vector(12 downto 0);
-- 2 msec delay, 4Mhz clock source / 8 KHz = 500Hz

-- ( = 2 msec)
signal key_sc_temp :bit_vector(3 downto 0):="0001";
-- 2 ^ 13 = 8KHz, 12 downto 0
begin
digit <= "111110";
process(clk)
begin
--active low enable
if(clk'event and clk = '1') then

clk_div <= clk_div + '1';
end if;
end process;
process(clk_div(12))
begin
if (clk_div(12)'event and clk_div(12) = '1') then
key_sc_temp <= key_sc_temp rol 1;
end if;
key_sc <= key_sc_temp;
end process;
begin
if (clk_div(12)'event and clk_div(12) = '1') then --gfedcba
if (key_sc_temp="0001" and key_rl="0001") then seg_out <= "0111111";
elsif (key_sc_temp="0001" and key_rl="0010") then seg_out <= "0000110";
end if;
end if;
end process;
end Behavioral;
VHDL File Name: stepper_motor.vhd

library IEEE;
entity stepper_motor is
Port ( d_out : out std_logic_vector(3 downto 0);
C_A : in std_logic;
clk_4M: in std_logic);
end stepper_motor;
architecture Behavioral of stepper_motor is
signal clk_div: std_logic_vector ( 21 downto 0 );
signal clk_Hz: std_logic;
type step_type is array (natural range <>) of std_logic_vector ( 3 downto 0);
constant step_aclk : step_type( 0 to 3):=("0110","1010","1001","0101");
constant step_clk : step_type( 0 to 3):=("0101","1001","1010","0110");
begin
process(clk_4M)
begin
if rising_edge(clk_4M) then
--0
--1
--2
--3
--4
--5
--6
--7
--8
--9
--A
--b
--C
--D
--E
--F
clk_div <= clk_div + 1;

end if;
clk_Hz <= clk_div(18);
end process;
process(clk_Hz)
variable a : integer range 0 to 3:=0;
begin
if rising_edge(clk_Hz) then
if (C_A = '1') then
d_out <= step_clk(a);
else
d_out <= step_aclk(a);
end if;
a := a + 1;
end if;
end process;
end Behavioral;
VHDL File Name: dcmotor.vhd

-- dcmotor.vhd
-- DC motor Behavioral
library IEEE;
entity dcmotor is
Port ( clk : in STD_LOGIC;
spd_cnt : in STD_LOGIC_vector(3 downto 0);
cl : out STD_LOGIC;
acl : out STD_LOGIC);
end dcmotor;
architecture Behavioral of dcmotor is
signal clk_div : std_logic_vector(21 downto 0);
begin
process(clk)
begin
if(rising_edge(clk)) then
clk_div <= clk_div + '1' ;
end if;
end process;
process(clk_div(19))
begin
case (spd_cnt) is
when "0001" => cl <= clk_div(19) and clk_div(15);
acl <= '0';
acl <= '0';
acl <= '0';
when "1000" => cl <= '1';
acl <= '0';
when "0000" => cl <= '0';
acl <= '1';
when others => null;
end case;
end process;
end Behavioral;
VHDL File Name: relay_drive.vhd

library IEEE;
entity relay_drive is
Port ( relay_out : out STD_LOGIC_vector(3 downto 0));
end relay_drive;
architecture DataFlow of relay_drive is
begin
relay_out(0) <= '0'; --relay1 device(led) is off
relay_out(1) <= '1'; --relay2 device(led) is on
relay_out(2) <= '1'; --relay3 device(led) is on
relay_out(3) <= '0'; --relay4 device(led) is off
end DataFlow;
VHDL File Name: DAC_Sine.vhd

library IEEE;
entity DAC_Sine is
Port ( clk : in STD_LOGIC; -- 4MHz XTL_CLK
rst : in STD_LOGIC;
dac_out : out STD_LOGIC_VECTOR ( 7 downto 0 ));
end DAC_Sine;
architecture Behavioral of DAC_Sine is
signal c1 : std_logic_vector (3 downto 0);
signal i : integer range 31 downto 0;
type sine is array (0 to 31) of integer range 0 to 255;
constant value : sine := ( 128, 146, 164, 182, 200, 218,236, 246, 255, 246, 236, 218,200, 182, 164, 146,
128, 110, 92, 74, 56, 38, 20, 06, 00,06, 20, 38, 56, 74, 92, 110);
begin
process (clk, rst)
begin
if(rst='1') then
c1 <=(others => '0');
elsif (clk'event and clk = '1') then
c1 <= c1 + 4;
end if;
end process;
process (c1(3))
begin
if rising_edge (c1(3)) then
dac_out <= conv_std_logic_vector ( value (i), 8 );
i <= i + 1;
if (i = 31) then
i <= 0;
end if;
end if;
end process;
end Behavioral

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Hardware

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HARDWARE PROGRAMS

VHDL File Name: keypad_led_display.vhd

-- 2 msec delay, 4Mhz clock source / 8 KHz = 500Hz

--active low enable

if(clk'event and clk = '1') then

VHDL File Name: stepper_motor.vhd

clk_div <= clk_div + 1;

VHDL File Name: dcmotor.vhd

VHDL File Name: relay_drive.vhd

VHDL File Name: DAC_Sine.vhd

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