R07

Code: R7210504 B.Tech II Year I Semester (R07) Supplementary Examinations December/January 2013/14 DIGITAL LOGIC DESIGN
(Common to CSE, IT & CSS)

Time: 3 hours Answer any FIVE questions All questions carry equal marks *****
1 (a) Solve for X: (i) (AE232)16 = (X)10 (ii) (5CA2)16 = (X)3 Differentiate hexadecimal codes and alpha numeric codes.

Max. Marks: 80

(b)
2 (a) (b)

Define canonical form, standard form, minterm, maxterm with an example. Derive Boolean expression for a 2 input Ex-OR gate realize with 2 input NAND gates without using complemented variables and draw the circuit.

3 (a) (b)

Explain how you convert sum of the products into product of sums. Give with example. Map the following function and simplify using K-Map: F = (A+B+C)(A+B+C)(A+B+C)(A+B+C)
Design a 2 bit comparator using gates. What is a decoder? Draw the circuit of 3-to-8 line decoder with the help of a truth table. Give different latches and Illustrate SR latch with example. Explain about HDL for sequential circuits. Write the HDL behavioral description of the 4- bit universal shift register. Draw the 4-bit binary ripple counter with D flip-flops. Explain PLA in detail. Design a random access memory having 8K bytes. Explain about the procedure for designing sequential circuits. Explain about the types of hazards in detail.

4 (a) (b) 5 (a) (b) 6 (a) (b) 7 (a) (b) 8 (a) (b)

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