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COMPUTER ARCHITURE OBJECTIVE TYPE QUESTIONS

1. How are data and instructions stored in the Von Neumann architecture? A. In separate memories C. Unified read-write memory Ans. C 2. Which of the following depicts an embedded system? A. Multi-core processor unit. B. Application specific Core C. Hardware Software Combination to perform specific application D. All of the above Ans. C 3. The performance of a processor can be measured using A. Clock period C. Throughput Ans. D 4. The Memory Address register stores the address of the word stored in which part of the architecture? A. I/O C. Memory Buffer Register Ans. C B. Program Counter D. None of the above B. Cycles per Instruction D. All of the above B. Dual ported memory D. None of the above

5. What are the parts of an instruction cycle? A. Fetch and Execute Cycle C. Decode and Store cycle Ans. A B. Fetch, decode and execute cycles D. Fetch, decode, execute and store.

6. Which of the following is not a state of the instruction cycle? A. Operand address calculation C. Instruction fetch Ans. B 7. Which of the following approach is used to handle multiple interrupts? A. Parallel interrupt processing B. Disable interrupts and priority assignment C. Interrupt wait D. None of the above. Ans. B 8. What are the interconnection wires not in the bus structure? A. Data lines C. Address lines Ans. B B. Instruction lines D. Control lines B. Data write back D. None of the above.

9. In which type of timing does the clock act as a reference? A. Interrupt timing C. Synchronous timing Ans.C 10. Which of the following is a bus arbitration scheme? A. Round-robin C. First come first serve Ans. D B. Priority D. All of the above B. Asynchronous timing D. Sequential timing

11. Performance of the memory is decided by which of the following parameters A. Transfer rate C. Cycle time Ans. D 12. When is a cache block is written into the main memory A. Valid bit is not set B. Every cycle C. Dirty bit is set D. None of the above Ans. C 13. An important attribute of RAM memories is A. Random access & non-volatile C. Sequential access Ans. B 14. How often/how is data written into the ROM? A. Anytime/when required B. Before use by microprogramming C. During manufacturing D. All of the above Ans. C 15. Redundancy is a built-in feature here A. Magnetic disks C. Serial I/O tapes Ans.B B. RAID D. Optical disks B. Volatile D. None of the above B. Latency D. All of the above

16. RAID level 0 is primarily used in applications where A. Cost is a priority B. Reliability is a priority C. Area is a priority D. All of the above Ans. A

17. Bit density is more in which device A. Compact disk C. DVD Ans. C 18. Which of the following is an example for a communication I/O? A. Monitor C. Modem Ans. C 19. This technique for data transfer does not involve the processor A. Direct Memory access C. Memory-mapped I/O Ans. A 20. What part of the OS stores utilities or frequently accessed functions? A. Memory C. Kernel Ans: C B. Registers D. None of the above B. Programmed I/O D. All the above B. Mouse D. USB B. Magnetic tape D. Magnetic disk

Q.21 In a virtual memory system, the addresses used by the programmer belongs to (A) Memory space. (C) Address space. Ans: C Q.22 The method for updating the main memory as soon as a word is removed from the Cache is called (A) Write-through (B) write-back (C) protected write Ans: B (D) cache-write (B) Physical addresses. (D) Main memory address.

Q.23 A control character is sent at the beginning as well as at the end of each block in the synchronous-transmission in order to (A) Synchronize the clock of transmitter and receiver. (B) Supply information needed to separate the incoming bits into individual character. (C) Detect the error in transmission and received system. (D) Both (A) and (C). Ans B Q.24 In a non-vectored interrupt, the address of interrupt service routine is (A) Obtained from interrupt address table. (B) Supplied by the interrupting I/O device. (C) Obtained through Vector address generator device. (D) Assigned to a fixed memory location. Ans: D Q.25 Divide overflow is generated when (A) Sign of the dividend is different from that of divisor. (B) Sign of the dividend is same as that of divisor. (C) The first part of the dividend is smaller than the divisor. (D) The first part of the dividend is greater than the divisor. Ans: B Q.26 Which method is used for resolving data dependency conflict by the compiler itself? (A) Delayed load. (B) operand forwarding. (C) Pre fetch target instruction. (D) loop buffer. Ans: A

Q.27 Stack overflow causes (A) Hardware interrupt. (B) External interrupt. (C) Internal interrupt. (D) Software interrupt. Ans: C Q.28 Arithmetic shift left operation (A) Produces the same result as obtained with logical shift left operation. (B) Causes the sign bit to remain always unchanged. (C) Needs additional hardware to preserve the sign bit. (D) Is not applicable for signed 2's complement representation. Ans: A Q.29 Zero address instruction format is used for (A) RISC architecture. (B) CISC architecture. (C) Von-Neuman architecture. (D) Stack-organized architecture. Ans: D Q.30 Address symbol table is generated by the (A) memory management software. (B) assembler. (C) match logic of associative memory. (D) generated by operating system Ans: B Q.31 How many different addresses are required by the memory that contain 16K words? (A)16,380 (B) 16,382 (C)16,384 (D) 16,386 Ans. (C) Q.32 DMA interface unit eliminates the need to use CPU registers to transfer data from (A) MAR to MBR (B) MBR to MAR (C) I/O units to memory (D) Memory to I/O units Ans. (D) Q.33 How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes? (A) 8 (B) 16 (C) 24 (D) 32 Ans. (B)

Q.34 In 8085 microprocessor how many I/O devices can be interfaced in I/O mapped I/O technique? (A) Either 256 input devices or 256 output devices. (B) 256 I/O devices. (C) 256 input devices & 256 output devices. (D) 512 input-output devices. Ans. (C) Q.35 Which of the following technology can give high speed RAM? (A) TTL (B) CMOS (C) ECL (D) NMOS Ans. (C) Q.36 Which is true for a typical RISC architecture? (A) Micro programmed control unit. (B) Instruction takes multiple clock cycles. (C) Have few registers in CPU. (D) Emphasis on optimizing instruction pipelines. Ans. (A) Q.37 When an instruction is read from the memory, it is called (A) Memory Read cycle (B) Fetch cycle (C) Instruction cycle (D) Memory write cycle Ans. (B) Q.38 Which activity does not take place during execution cycle? (A) ALU performs the arithmetic & logical operation. (B) Effective address is calculated. (C) Next instruction is fetched. (D) Branch address is calculated & Branching conditions are checked. Ans. (D) Q.39 How many memory chips of (128 x 8) are needed to provide a memory capacity of 4096 x 16? (A)64 (B) 16 (C)32 (D) None Ans. (A) Q.40 Pseudo instructions are (A) Machine instructions (B) Logical instructions (C) Micro instructions (D) instructions to assembler. Ans. (A)

Q.41 An attempt to access a location not owned by a Program is called (A) Bus conflict (B) Address fault (C) Page fault (D) Operating system fault Ans. (B) Q. 42 Dynamic RAM consumes ________ Power and ________ then the Static RAM. (A) more, faster (B) more, slower (C) less, slower (D) less, faster Ans. (C) Q.43 Cache memory works on the principle of (A) Locality of data. (B) Locality of reference (C) Locality of memory (D) Locality of reference & memory Ans. (B) Q.44 An interrupt for which hardware automatically transfers the program to a specific memory location is known as (A) Software interrupt (B) Hardware interrupt (C) Maskable interrupt (D) Vector interrupt Ans. (B) Q.45 Cycle stealing technique is used in (A) Interrupt based data transfer (B) Polled mode data transfer (C) DMA based data transfer (D) None of these Ans. (C) Q.46 When CPU is not fully loaded, which of the following method of data transfer is preferred (A) DMA (B) Interrupt (C) Polling (D) None of these Ans. (D) Q.47 Associative memory is sometimes called as (A) Virtual memory (B) Cache memory (C) Main memory (D) Content addressable memory Ans. (D)

Q.48 A more efficient way to organize a Page Table is by means of an associative memory having (A) Number of words equal to number of pages (B) Number of words more than the number of pages (C) Number of words less than the number of pages (D) Any of the above Ans. (A) Q.49 CPU checks for an interrupt signal during (A) Starting of last Machine cycle (B) Last T-State of instruction cycle (C) First T-State of interrupt cycle (D) Fetch cycle Ans. (B) Q.50 Which flag of the 8085's flag register is not accessible to programmer directly? (A)Zero flag (B)Carry flag (C)Auxiliary carry flag (D)Parity flag Ans. (C)