TABLE 6.

1 FET Bias Configurations Type

JFET Fixed-bias

Configuration
VDD RD VGG RG

Pertinent Equations
VGSQ VGG VDS VDD IDRS

Graphical Solution
ID IDSS Q-point VP VGG 0 VGS ID IDSS

+
VDD RD RG

JFET Self-bias

VGS IDRS VDS VDD ID(RD RS)

RS VDD

Q-point VP V' 0 GS

I'D VGS

JFET Voltage-divider bias

R1 R2

RD

R2VDD VG R1 R2 VGS VG IDRS VDS VDD ID(RD RS)

Q-point VP

ID IDSS VG RS 0 ID IDSS VG VGS

RS VDD RD

JFET Common-gate

RS VSS VDD RD

VGS VSS IDRS VDS VDD VSS ID(RD RS)

Q-point VP Q-point 0

VSS RS VSS VGS

JFET (VGSQ 0 V)

VGSQ 0 V IDQ IDSS

VP

ID IDSS VGS = 0 V
Q

0 ID IDSS

VGS

JFET (RD 0 )
RG

VDD

RS

VGS IDRS VD VDD VS IDRS VDS VDD ISRS

Q-point VP V'GS 0

I'D VGS

Depletion-type MOSFET Fixed-bias

VGG

VDD RD RG

ID Q-point

VGSQ VGG VDS VDD IDRS

VP VDD

IDSS

0 VGG ID Q-point

VGS

Depletion-type MOSFET Voltage-divider bias

R1 R2

RD RS

R2VDD VG R1 R2 VGS VG ISRS VDS VDD ID(RD RS)

VG RS IDSS

VP VDD RD ID

VG VGS

Enhancement type MOSFET Feedback configuration

VDD RD RG

VGS VDS VGS VDD IDRD

ID(on)

Q-point 0 VGS(Th) ID VGS(on) VDD VGS

Enhancementtype MOSFET Voltage-divider bias

VDD R1 R2 RD RS

R2VDD VG R1 R2 VGS VG IDRS

VG RS

Q-point 0 VGS(Th) VG VGS

281