1.3.

OVERLOADED OPERATORS
Description bitwise-and bitwise-or bitwise-xor bitwise-not Left u/l,uv,lv u/l,uv,lv u/l,uv,lv Operator and or xor not Right u/l,uv,lv u/l,uv,lv u/l,uv,lv u/l,uv,lv

2.4. CONVERSION FUNCTIONS

From un,lv sg,lv un,sg un,sg na in To sg un lv in un sg Function SIGNED(from) UNSIGNED(from) STD_LOGIC_VECTOR(from) TO_INTEGER(from) TO_UNSIGNED(from) TO_SIGNED(from)

1164 PACKAGES QUICK REFERENCE CARD

REVISION 1.0
() {} bold b u/l bv uv lv un sg na in sm
c

1.4. CONVERSION FUNCTIONS

From u/l uv,lv b bv,ul bv,lv To b bv u/l lv uv Function TO_BIT(from, [xmap]) TO_BITVECTOR(from, [xmap]) TO_STDULOGIC(from) TO_STDLOGICVECTOR(from) TO_STDULOGICVECTOR(from)

3. IEEES NUMERIC_BIT
3.1. PREDEFINED TYPES
UNSIGNED(na to | downto na) Array of BIT SIGNED(na to | downto na) Array of BIT

Grouping Repeated As is ::= ::= ::= ::= ::= ::= ::= ::= ::= ::= ::=

[] | CAPS

Optional Alternative User Identifier

BIT STD_ULOGIC/STD_LOGIC BIT_VECTOR STD_ULOGIC_VECTOR STD_LOGIC_VECTOR UNSIGNED SIGNED NATURAL INTEGER SMALL_INT (subtype INTEGER range 0 to 1) commutative

3.2. OVERLOADED OPERATORS

Left Op Right Return abs sg sg sg sg +,-,*,/,rem,mod un un +,-,*,/,rem,mod sg sg +,-,*,/,rem,mod c na un +,-,*,/,rem,mod c in sg <,>,<=,>=,=,/= un bool <,>,<=,>=,=,/= sg bool <,>,<=,>=,=,/= c na bool <,>,<=,>=,=,/= c in bool

1.5. PREDICATES
RISING_EDGE(SIGID) Rise edge on signal ? FALLING_EDGE(SIGID) Fall edge on signal ? IS_X(OBJID) Object contains X ? un sg un sg un sg un sg

2. IEEES NUMERIC_STD
2.1. PREDEFINED TYPES
UNSIGNED(na to | downto na) SIGNED(na to | downto na) Arrays of STD_LOGIC

1. IEEES STD_LOGIC_1164
1.1. LOGIC VALUES
U X/W 0/L 1/H Z - Uninitialized Strong/Weak unknown Strong/Weak 0 Strong/Weak 1 High Impedance Dont care

3.3. PREDEFINED FUNCTIONS

SHIFT_LEFT(un, na) SHIFT_RIGHT(un, na) SHIFT_LEFT(sg, na) SHIFT_RIGHT(sg, na) ROTATE_LEFT(un, na) ROTATE_RIGHT(un, na) ROTATE_LEFT(sg, na) ROTATE_RIGHT(sg, na) RESIZE(sg, na) RESIZE(un, na) un un sg sg un un sg sg sg un

2.2. OVERLOADED OPERATORS

Left Op Right Return abs sg sg sg sg +,-,*,/,rem,mod un un +,-,*,/,rem,mod sg sg +,-,*,/,rem,mod c na un +,-,*,/,rem,mod c in sg <,>,<=,>=,=,/= un bool <,>,<=,>=,=,/= sg bool <,>,<=,>=,=,/= c na bool <,>,<=,>=,=,/= c in bool

1.2. PREDEFINED TYPES

STD_ULOGIC Subtypes: STD_LOGIC X01 X01Z UX01 UX01Z Base type Resolved STD_ULOGIC Resolved X, 0 & 1 Resolved X, 0, 1 & Z Resolved U, X, 0 & 1 Resolved U, X, 0, 1 & Z

un sg un sg un sg un sg

3.4. CONVERSION FUNCTIONS

From un,bv sg,bv un,sg un,sg na in To sg un bv in un sg Function SIGNED(from) UNSIGNED(from) BIT_VECTOR(from) TO_INTEGER(from) TO_UNSIGNED(from) TO_SIGNED(from)

2.3. PREDEFINED FUNCTIONS

SHIFT_LEFT(un, na) SHIFT_RIGHT(un, na) SHIFT_LEFT(sg, na) SHIFT_RIGHT(sg, na) ROTATE_LEFT(un, na) ROTATE_RIGHT(un, na) ROTATE_LEFT(sg, na) ROTATE_RIGHT(sg, na) RESIZE(sg, na) RESIZE(un, na) un un sg sg un un sg sg sg un

STD_ULOGIC_VECTOR(na to | downto na) Array of STD_ULOGIC STD_LOGIC_VECTOR(na to | downto na) Array of STD_LOGIC

1995 Qualis Design Corporation. Permission to reproduce and distribute strictly verbatim copies of this document in whole is hereby granted. See reverse side for additional information.

1995 Qualis Design Corporation

1995 Qualis Design Corporation

4. SYNOPSYS STD_LOGIC_ARITH
4.1. PREDEFINED TYPES
UNSIGNED(na to | downto na) SIGNED(na to | downto na) Arrays of STD_LOGIC SMALL_INT Integer, 0 or 1

6. SYNOPSYS STD_LOGIC_UNSIGNED
6.1. OVERLOADED OPERATORS
Left lv lv lv lv lv Op Right Return + lv lv +,-,* lv lv +,-c in lv +,- c u/l lv <,>,<=,>=,=,/= lv bool <,>,<=,>=,=,/= c in bool

9. CADENCES STD_LOGIC_ARITH
9.1. OVERLOADED OPERATORS
Left Op Right Return + uv uv + lv lv +,-,*,/ u/l u/l +,-,*,/ lv lv +,-,*,/c u/l lv +,-c in lv +,-,* uv uv +,-,*c u/l uv +,-c in uv <,>,<=,>=,=,/= c in bool <,>,<=,>=,=,/= c in bool

4.2. OVERLOADED OPERATORS

Left Op Right Return abs sg sg,lv + un un,lv +,sg sg,lv +,-,*,/ un un,lv +,-,*,/ sg sg,lv +,-,*,/ c un sg,lv +,- c in un,lv +,- c in sg,lv +,- c u/l un,lv +,- c u/l sg,lv <,>,<=,>=,=,/= un bool <,>,<=,>=,=,/= sg bool <,>,<=,>=,=,/= c in bool <,>,<=,>=,=,/= c in bool

6.2. CONVERSION FUNCTIONS

From lv To in Function CONV_INTEGER(from)

un sg sg un sg un sg un sg un sg

u/l lv lv lv uv uv uv lv uv

7. SYNOPSYS STD_LOGIC_SIGNED
7.1. OVERLOADED OPERATORS
Left Op abs +,+,-,* +,-c +,- c <,>,<=,>=,=,/= <,>,<=,>=,=,/= c Right Return lv lv lv lv lv lv in lv u/l lv lv bool in bool

9.2. PREDEFINED FUNCTIONS

C-like ?: replacements: COND_OP(bool, lv, lv) COND_OP(bool, uv, uv) COND(bool, u/l, u/l) Shift operations: SH_LEFT(lv, na) SH_LEFT(uv, na) SH_RIGHT(lv, na) SH_RIGHT(uv, na) Resize functions: ALIGN_SIZE(lv, na) ALIGN_SIZE(uv, na) ALIGN_SIZE(u/l, na) ALIGN_SIZE(u/l, na) lv uv u/l lv uv lv uv lv uv lv uv

4.3. PREDEFINED FUNCTIONS

SHL(un, un) SHR(un, un) SHL(sg, un) SHR(sg, un) EXT(lv, in) SEXT(lv, in) un un sg sg lv lv

lv lv lv lv lv

7.2. CONVERSION FUNCTIONS

zero-extend sign-exten From lv To in Function CONV_INTEGER(from)

4.4. CONVERSION FUNCTIONS

From To Function un,lv sg SIGNED(from) sg,lv un UNSIGNED(from) sg,un lv STD_LOGIC_VECTOR(from) un,sg in CONV_INTEGER(from) in,un,sg,u un CONV_UNSIGNED(from, size) in,un,sg,u sg CONV_SIGNED(from, size) in,un,sg,u lv CONV_STD_LOGIC_VECTOR(from, size)

8. SYNOPSYS STD_LOGIC_TEXTIO
Read/write binary values READ(line, u/l, [good]); READ(line, uv, [good]); READ(line, lv, [good]); WRITE(line, u/l, [justify], [width]); WRITE(line, uv, [justify], [width]); WRITE(line, lv, [justify], [width]); Read/write octal values OREAD(line, uv, [good]); OREAD(line, lv, [good]); OWRITE(line, uv, [justify], [width]); OWRITE(line, lv, [justify], [width]); Read/write hexadecimal values HREAD(line, uv, [good]); HREAD(line, lv, [good]); HWRITE(line, uv, [justify], [width]); HWRITE(line, lv, [justify], [width]);

9.3. CONVERSION FUNCTIONS

From lv,uv,u/l in in To Function in TO_INTEGER(from) lv TO_STDLOGICVECTOR(from, size) uv TO_STDULOGICVECTOR(from, size)

5. SYNOPSYS STD_LOGIC_MISC
5.1. PREDEFINED FUNCTIONS
AND_REDUCE(lv | uv) OR_REDUCE(lv | uv) XOR_REDUCE(lv | uv) u/l u/l u/l

1995 Qualis Design Corporation. Permission to reproduce and distribute strictly verbatim copies of this document in whole is hereby granted. Qualis Design Corporation Beaverton, OR USA Phone: +1-503-531-0377 FAX: +1-503-629-5525 E-mail: info@qualis.com Also available: VHDL Quick Reference Card Verilog HDL Quick Reference Card

1995 Qualis Design Corporation

1995 Qualis Design Corporation