VLSI IEEE PROJECT TITLES LIST

TECHNONLOGY DOMAIN
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: VLSI : IEEE TRANSACTIONS ON LOW POWER VLSI

TITLES IMPACT OF RANDOM DOPANT FLUCTUATIONS ON THE TIMING CHARATERISTICS OF FLIP-FLOPS LOW POWER DUAL EDGE TRIGGERED FLIP-FLOP IMPLEMENTATION OF FULL ADDER CELLS USING NP-CMOS AND MULTI-OUTPUT LOGIC STYLES IN 90NM TECHNOLOGY DESIGN OF LOW POWER HIGH SPEED VLSI ADDER SUBSYSTEM DELAY BASED DUAL RAIL PRECHARGE LOGIC AN ENERGY EFFICIENT SECURE LOGIC TO PROVIDE RESISTANCE AGAINST DIFFERENTIAL POWER ANALYSIS ATTACKS POWER-EFFICIENT EXPLICIT-PULSED DUAL-EDGE TRIGGERED SENDEAMPLIFIER FLIP-FLOPS PERFORMANCE ANALYSIS OF POWER GATING DESIGNS IN LOW POWER VLSI CIRCUITS LOW POWER VLSI CIRCUIT IMPLEMENTATION USING MIXED STATIC CMOS AND DOMINO LOGIC WITH DELAY ELEMENTS ENERGY RECOVERY PERFORMANCE OF QUASI-ADIABATIC CIRCUITS USING LOWER TECHNOLOGY NODES POWER COMPARISON OF CMOS AND ADIABATIC FULL ADDER CIRCUITS DESIGN OF SEQUENTIAL ELEMENTS FOR LOW POWER CLOCKING SYSTEM LOW-VOLTAGE AND LOW-POWER CONSUMPTION 0.35UM CMOS VOLTAGE-MODE DEFUZZIFIER ENERGY EFFICIENT ADIABATIC LOGIC FOR LOW POWER VLSI APPLICATIONS BZ-FAD: A LOW-POWER LOW-AREA MULTIPLIER BASED ON SHIFT-AND-ADD ARCHITECTURE

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LOW-POWER AES DESIGN USING PARALLEL ARCHITECTURE

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LOW POWER FFT DESIGN FOR WIRELESS COMMUNICATION SYSTEMS ESTIMATING POWER CONSUMPTION FOR FIR FILTER IMPLEMENTATION ON FPGA A BIST TPG FOR LOW POWER DISSIPATION AND HIGH FAULT COVERAGE LOW POWER STATE-PARALLEL RELAXED ADAPTIVE VITERBI DECODER DESIGN AND IMPLEMENTATION FPGA IMPLEMENTATION OF LOW POWER PARALLEL MULTIPLIER LOW POWER FPGA-BASED IMPLEMENTATION OF DECIMATING FILTERS FOR MULTISTANDARD RECEIVER A LOW-POWER VITERBI DECODER DESIGN FOR WIRELESS COMMUNICATIONS APPLICATIONS

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