LAB 1 INTRODUCTION TO SIMULATION USING MODELSIM

Overview In this lab student will learn how to simulate, test and debug Verilog designs using the ModelSim simulator. The first task will be going through a basic tutorial on ModelSim so that student able to do simple simulation tasks. Students then will use ModelSim to simulate the simple design and analyze the results. If the results show that the design is in fact incorrect, so students will then have to modify the design to get it to compute the correct values. Objectives The objectives of this lab are: 1. Introduction to the facilities in this simulation. 2. To equip students with the basic skills necessary to design a simple Very Large Scale Integrated (VLSI) device using Verilog Hardware Description Language (HDL). 3. Learn how to create a test-bench verify the design Part 1: ModelSim Introduction The Verilog Hardware Description Language is designed for describing a hardware design or part of the design. Verilog models can be developed for several levels of abstraction including Behavioral level, Register Transfer level, and Structural level (Gate model/ Switch model). Specification High Level Design Low Level Design RTL Coding Functional Verification Logic Synthesis Place and Route Fabrication Post Si Validation Figure 1: Top-Down Design Approach Gate Level Simulation

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Ex 1.1 Starting ModelSim 1. Click the ModelSim icon to start the software.

2. To create / build new project, select File > New > Project. A Create Project Message box will pop out. Input Name and location of the project and in which library you want to compile into.

3. Add files into the project created. Right click at the Project in the workspace. Select Add to Project > New File (or Exist File). Please request a sample file and test-bench from your lab demonstrator. 4. To compile the project, right click anywhere in the project tab and select Compile > Compile All. 5. Now, students can view the designed unit in library. Click the Library tab in the workspace.

6. Load the design unit for simulation. Double click the test-bench. A waveform Viewer will be appeared as show.

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7. After add the selected path to the wave, Run the simulation. A complete simulation wave will be prompted as follow. Analyze the waveform to ensure the design is correct. If the output is incorrect, it means the design was incorrect.

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Part 2: Intoduction of Verilog HDL Ex 2.1 Verilog HDL (Half Adder) 1. Create the structural adder file below in the text editor and save the files as addbit.v

2. Students are required to draw the half adder logic circuit. Understand the circuit and the HDL coding given above. 3. Create a test-bench file below and save the files as add_tst.v using text editor.

4. Compile and simulate the Verilog HDL given according to the step in Part 1. 5. Select the suitable simulation running time. Analyze the waveform and re-simulate the hardware by adjusting the variable in the test-bench file. 6. Students are required to print-screen the waveform with the corresponding values for report purpose. E&E Engineering, SKTM, UMS 2014 Page 4

Report 1. Access to E-Report System (ERS) at http://www.els.bugs3.com to submit online lab report before end of the lab. Please ask instructions from your lab demonstrator. 2. Your report must include the output/ waveform and all related information that support your analysis. All the information MUST BE in SINGLE document. The extension file accept in the form is .doc / .docx / .pdf 3. All report submission must be on-time. Late submission will NOT BE accepted automatically.

References 1. ModelSim (v6.5b) Tutorial Chapter 3 to 6 2. Introduction to simulation of Verilog designs Using ModelSim Graphical Waveform Editor (Altera, 2010)

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