Phase Locked Loop Frequency Synthesizers

Phase locked loop frequency synthesizers
Analog Integrated Circuit Design A video course under the NPTEL Nagendra Krishnapura
Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, 600036, India
National Programme on Technology Enhanced Learning
Nagendra Krishnapura
Outline
Phase locked loop (PLL) requirements PLL frequency multiplier

Derivation Phase model
Type I PLL
Practical phase detectors Type I PLL limitations
Type II PLL
Feedback systems and stability Type II PLL
LC oscillator Programmable frequency divider
Phase locked loops
Frequency synthesizers in radios for local oscillators Frequency multiplication for reference clock generation Phase alignment
Local oscillator requirements

10kHz interchannel spacing Broadcast AM band
channel spacing 0.2MHz bandwidth 0.15MHz
Broadcast FM band
88MHz
88.2MHz
5kHz
channel spacing 0.2MHz
channel spacing
GSM uplink band
0.2MHz
GSM downlink band
890MHz
890.2MHz
935MHz
935.2MHz
915MHz
108MHz 960MHz
fc
1610kHz
530kHz
Tuned to the desired channel frequency plus an intermediate frequency (IF) Generate equally spaced frequencies from a reference frequency Waveform shape not very important Spurious output and noise must be sufciently low
Nagendra Krishnapura Phase locked loop frequency synthesizers
Frequency divider
Vref R(N-1) Vref/N R fref fref/N
N frequency divider
Digital frequency divider can generate multiple frequencies Frequencies not equally spaced Reference frequency higher than output frequencies
Voltage multiplier
voltage difference zero, at steady state Vref + Vout/N K2 dt + Vctl K1Vctl+Vo + R Vout
R(N-1) Vout/N = Vref at steady state

A controlled source to generate the output voltage Divided output voltage subtracted from the reference to generate error Output source controlled by the integral of the error
Frequency multiplier
frequency difference zero, at steady state cos(2freft) frequency measure fref + fout/N frequency measure N K2 dt Vctl KvcoVctl+fo cos(2foutt) fout fo Vctl slope = Kvco
cos(2fout/N t) fout/N = fref at steady state
A controlled source to generate the output frequency

A voltage controlled oscillator
Divided output frequency subtracted from the reference frequency to generate error Output source controlled by the integral of the frequency error
Phase and frequency
Sinusoid: cos((t )) Phase: (t )

d (t ) Instantaneous frequency: fi = 21 dt Typically expressed as fi = fo + fe (t )
fo : average frequency fe : instantaneous frequency error
Phase (t ) = 2 fo t + o + 2 fe (t )dt Phase (t ) = 2 fo t + o + (t )

o : phase offset-ideal ramp versus time (t ): instantaneous phase
Phase error
70 60 50 40 30 20 10 0 10 0 ideal phase error phase with error
4
10
Frequency multiplier
phase difference fref K2 dt + dt
cos(2freft)
frequency measure
Vctl
KvcoVctl+fo
cos(2foutt)
fout/N = fref at steady state
fout/N frequency measure N
K2
cos(2fout/N t)
Integration before subtraction Integral of the frequency is phase Integrator+subtractor measures phase difference between the reference input and the divided output (feedback)
Frequency multiplierPhase locked loop
Vctl = Kpd(ref-out/N) cos(2freft+ref) phase detector Vctl KvcoVctl+fo cos(2foutt)
N cos(2fout/N t + out/N) fout/N = fref at steady state
Use a phase detector to generate the control voltage
Voltage controlled oscillator

slope = Kvco fout Vctl fout=KvcoVctl+fo fo Vctl 2fot Vctl 2Kvco dt + + vco
fvco = fo + Kvco Vctl

fo : Free running frequency
vco = 2 fo t + 2 Kvco Vctl dt Kvco : VCO gain in Hz/V

Phase detector
1 2
phase detector
Kpd(1-2)
Kpd: phase detector gain

Kpd : Phase detector gain in V/radian Ideal phase detector: assumed to have an output Vpd = Kpd (1 2 )
Phase locked loop model

2fot 2freft+ref + Kpd Vctl 2Kvco dt + + 2fout t+out
2fout/N t+vco/N 1/N Vctl = 2(fref-fout/N)t + ref - out/N At steady state, fref=fout/N; Vctl = ref - out/N
Modelled in terms of phases of signals The loop locks with Vctl = Kpd (ref out /N ) = (Nfref fo )/Kvco This is the operating point of the circuit
At steady state (lock), Vctl is a constant fref = fout /N
Phase locked loop model
2fot 2freft+ref+ref + Vctl+vctl Kpd 2Kvco dt + + 2fout t+out+out
2fout/N t+out/N+out/N
1/N
An increment ref in the input phase causes increments out , vctl
Phase locked loop modelincremental picture

ref + out/N 1/N
An increment ref in the input phase causes increments out , vctl Type-I loopOne integrator in the loop Phase model of the PLL
vctl Kpd 2Kvco dt
out
Phase locked loop modelfrequency domain

ref(s) + Kpd vctl(s) 2Kvco s out(s)
out(s)/N 1/N
Loop gain L(s) = 2 Kpd Kvco /Ns Transfer function out (s)/ref (s) = N /(1 + Ns/(2 Kpd Kvco )) Type-I loopOne integrator in the loop Closed loop bandwidth (= unity loop gain frequency) = 2 Kpd K vco/N rad/s
Type-I PLLlimitations
Phase error when locked (fout = Nfref ):

ref out /N = (Nfref fo )/Kvco Kpd dc value of Kpd matters; We have a constant Kpd
|ref out /N | < 2 |fout fo | < 2 Kpd Kvco Lock range limited by periodicity of phase detector
Period of all phase detectors not necessarily 2 Commonly used three state phase detector periodic with 2
Kpd Kvco large for wide lock range
Phase detector
Frequency divider output has a varying duty cycle Phase detector should sensitive to duty cycle
XOR gate etc. are not preferable
Phase detector should be sensitive only to rising edges (or only to falling edges) of inputs
Tri state phase detector
A B
A
A ref
QA
RST
-1
+1
A
B div RST D Q QB
output=QA-QB
Output +1, 1, 0
+1 if reference leads divider output 1 if reference lags divider output 0 if reference coincides with divider output
Tri state phase detector-waveforms
Tref +1 +1
Tref
A B QA QB
-1 +1 -1 +1 +1
A B QA QB
-1 +1 -1 +1 +1
ref-div
div-ref
A leading B
A lagging B
Flip ops assumed to be reset instantaneously
Tri state phase detector-frequency difference between inputs

A B A
A ref 1 D Q QA
RST
-1
+1
A
B div RST D Q QB
output=QA-QB
fA > fB : Eventually get two consecutive edges of A Circulates between 0 and +1 states: Average output > 0 Similarly, average output > 0 for fA < fB This detector is a phase/frequency detector (PFD)
Tri state phase detector output

Tref +1 reference -1 reference divider o/p +1 -1 pdout +1 -1 = ref-div Tref divider o/p Tri-state phase detector pdout
Average value = / Output periodic at fref
Vout (f ) =
sinc 2 n=
n 2 n 2
(f nfref ) cos(2 nfref t )
+ Vout (t ) = 2
sinc
n =1
Tri state phase detector
Output average value = /2

Kpd = 1/2 Phase detector offset = 0 Loop locks with = ref out /N = 0 for Nfref = fo Input range = 2 PLL lock range = fo 2 Kpd Kvco < fout < fo + 2 Kpd Kvco
n
Output contains fref and its harmonics Output = 1/2 ( + Periodic signal in addition to Kpd
an cos(2 nfref t ))
All real phase detectors have a periodic error in addition to the dc term proportional to phase error
Phase detector-Output spectrum

=/2 0.6 0.4 0.2 0 0.2 0 2 4 =/8 0.5 6 8 10
0.5 0
f/fref
10
PLL with tri state phase detectorperiodic error

n ancos(2nfreft) ("error") ref + + + vctl Kpd 2Kvco dt out
vco/N 1/N
Error e(t ) added to the input of the phase detector Disturbances in the VCO output phase out (t ) even with a perfect reference (ref (t ) = 0) VCO output: cos(2 Nfref t + N ref + out (t )) VCO output not periodic at Nfref
Phase error
70 60 50 40 30 20 10 0 10 0 ideal phase error phase with error
4
10
PLL with tri-state phase detectorfrequency domain

E(s) ref(s) + + + E(j2f) = n an/2 (fnfref) vctl(s) Kpd 2Kvco s out(s)
vco(s)/N 1/N ref(s) = 0 for a perfectly periodic reference
Transfer function from the error to the output out (s)/E (s) = out (s)/ref (s) = N /(1 + Ns/(2 Kpd Kvco )) E (j 2 f ) =
n (an /2) (f
nfref )
Type-I PLL
out (s) E (s) out (s) ref (s) 2 Kpd Kvco /Ns = N 1 + 2 Kpd Kvco /Ns 1 = N 1 + sN /2 Kpd Kvco
Loop gain L(s) = Closed loop bandwidth (Hz) f3dB =

2 Kpd Kvco Ns Kpd Kvco N

Type I PLL
dB loop gain |L|
2KpdKvco/N
L/(1+L)
|out/ref| 20log(N)
dB
2KpdKvco/N (loop bandwidth)
Feedback system
In our system, out (s) E (s) = N 2 Kpd Kvco /Ns 1 + 2 Kpd Kvco /Ns
In general, in a feedback system with a loop gain L(s) Hclosedloop (s) = Hideal (s) L(s) 1 + L(s)
Where Hideal (s) is the ideal closed loop gain (with L = ). This can be approximated as Hclosedloop (s) = Hideal (s)L(s) = Hideal (s) |L | 1
|L | 1
PLL with tri state phase detectorOutput signal

Considering only the term at fref , and b1 1 Vout (t ) = cos(2 Nfref t + b1 sin(2 fref t )) = cos(2 Nfref t ) cos(b1 sin(2 fref t )) cos(2 Nfref t ) b1 sin(2 fref t ) sin(2 Nfref t ) b1 /2 cos(2 (N 1)fref t ) sin(2 Nfref t ) sin(b1 sin(2 fref t ))
= cos(2 Nfref t )
b1 /2 cos(2 (N + 1)fref t )
Spurious tones in the output at a spacing of fref from the desired frequencyReference feedthrough In general, spurious tones will be present at nfref from the desired PLL output
Reference feedthrough
b1 = a1 |H (j 2 fref )| Kpd Kvco /jNfref = a1 N 1 + Kpd Kvco /jNfref Kpd Kvco a1 N jNfref Nf3dB sinc = 2 fref 2 Maximum value of b1 = 4Kpd Kvco when =
Reference feedthroughexample
To generate 1 GHz from 1 MHz reference

b1 /2 = 102 (spurious tones at (N 1)fref 40 dB below the fundamental output at Nfref ) N = 103 = (locked with a phase shift of )
f3dB /fref = 5 106 f3dB = 5 Hz Lock range = 2 Nf3dB 10 kHz Lock range is too small; Cant switch to the next channel which is 1 MHz away! May not be able to lock for any value of N , unless the free running frequency happens to be Nfref for some N
Type I phase locked loop
input signal at fref = ref-out/N Kpd phase detector
In steady state, Vctl = (fout-ffree)/Kvco Kpd Vctl VCO N frequency divider
output signal at fout (fout=Nfref at steady state)
In steady state, = (fout-ffree)/KvcoKpd
= 0 if fout happens to be equal to fref . Zero spurs!
Changing the free running frequency of a VCO
Voff Vctl VCO VCO ffree = ffree+KvcoVoff (ffree+KvcoVoff)+KvcoVctl Vctl ffree+KvcoVctl
Add a bias to the input to change the free running frequency
Slowly change the bias until = 0

monitor and continuously adjust Voff until =0 input signal at fref = ref-out/N Kpd phase detector ffree N frequency divider
+ Voff Kpd VCO
output signal at fout (fout=Nfref at steady state)
Slowly change the bias Voff until = 0
Slowly change the bias until = 0

integral phase detector Kpd,I dt Kpd,I dt
In steady state, Voff = (fout-ffree)/KvcoKpd output signal at fout (fout=Nfref at steady state)
input signal at fref = ref-out/N Kpd phase detector
Voff Kpd ffree N frequency divider VCO
In steady state, = 0
Measure and integrate it to control Voff
Type II Phase locked loop

phase detector + loop filter integral phase detector Kpd,I dt Kpd,I dt proportional phase detector Kpd Kpd output signal at fout (fout=Nfref at steady state) VCO In steady state, = 0 N
input signal at fref = ref-out/N
Proportional + integral loop lter
Type II PLL with a tri state phase detector
Lock range is not limited by the phase detector Loop locks with zero phase difference between reference and feedback signals Tri state phase detector output is zero for zero input phase difference No reference feedthrough! Reference feedthrough does exist in reality due to mismatches
Type II PLLphase model
zero at steady state Kpd,I 2freft+ref + Kpd dt + Vctl + 2Kvco dt
2fot + + 2fout t+out
2fout/N t+out/N 1/N dVctl/dt 2(fref-fout/N)t + ref - out/N At steady state, fref=fout/N; ref - out/N = 0;
Type II PLLincremental model
zero at steady state Kpd,I 2freft+ref + Kpd dt + Vctl + 2fout t+out 2Kvco dt
Type II PLLincremental model
Kpd,I s ref(s) + Kpd + + vctl(s) 2Kvco s out(s)
out(s)/N 1/N
Type II PLLFrequency domain
Kpd,I s ref(s) + Kpd
p1 > 2KpdKvco/N more poles can be used + vctl(s) Vctl 1 1+s/p1 + 2Kvco s out(s)
out(s)/N 1/N
Type II PLLImplementation
Tref +1 reference -1 divider o/p +1 -1 reference pdout +Icp -Icp proportional +IcpR output -IcpR integral output slope=Icp/C divider o/p
tri-state phase detector
reference divider o/p = ref-div
iout + R1 proportional iout + C1 integral

output output
reference divider o/p
iout R1 +
proportional + integral output
C1 -
Phase detector with a current output (Icp )
Integral term Kpd ,I /s: Current owing into a capacitor C1 Proportional term Kpd : Current owing into a resistor R1 Series RC to obtain the sum Kpd = Icp R1 /2 ; Kpd ,I = Icp C1 /2
Tri state phase detector with charge pump

Vdd
Icp
1 A ref D Q QA (UP)
RST
iout + R1
QB (DN)
B div 1
RST D Q
proportional + integral output
C1 Icp -
QA and QB drive a charge pump Charge driven into the loop lter Icp Tref /2
Tri state phase detector implementation example
1 CLK
CLK
RST
D latch with reset and D="1"
CLK
S R
Q Q
Q Q
S R
RESET
(D input with "1" implicit) Realization using SR latches
RESET
Realization using NOR gates
D ip ops with reset implemented using SR latches
Tri state phase detector-reset path delay

Tref +1 +1 Tref
A B QA QB
-1 +1 -1 +1 +1
A B QA QB
= ref-div QA and QB simultaneously on
-1 +1 -1 +1 +1
A leading B
A lagging B
QA and QB simultaneously high for a short duration QA QB proportional to
Tri state phase detector-current source mismatch

Vdd
phase offset in steady state = ref-div +1
Icp+Icp/2
1 A ref D Q QA (UP)
A iout R1 C2 B
-1 Tref +1 -1
RST
B div 1
RST D Q QB (DN)
QA QB Itop Icp-Icp/2 C1
Icp-Icp/2 Trst Icp+Icp/2
Ibot iout
-Icp (zero average)
Ideally = 0 in a type-II loop no ref. feedthrough Mismatch between top and bottom current sources and switching transients causes a non zero and reference feedthrough Current pulse area Icp Trst much smaller than in a Type I PLL (area Icp Tref )
Type II PLL with a tri state phase detector

n ancos(2nfreft+n) ("error")
Kpd,I ref + + +
dt + vctl + Kpd out 2Kvco dt
out/N 1/N
Loop locks with a small phase offset (due to mismatch) between ref and vco /N for all frequencies Error E (t ) is periodic at fref : E (t ) = n=1 an cos(2 nfref t + n ) Amplitude of E (t ) related to mismatch; much smaller than in a type-I PLL
Type II PLL with a tri state phase detector-Frequency domain
E(j2f) = n an ejn (f-nfref) E(s) ref + + + Kpd out/N 1/N Kpd,I s + vctl + 2Kvco s out
Type II PLLAdditional attenation poles
zero at steady state Kpd,I 2freft+ref + Kpd dt + +
poles beyond 2KpdKvco/N Vctl filter 2Kvco dt
2fot + + 2fout t+out
Additional poles beyond the unity loop gain frequency to reduce reference feedthrough
Kpd,I s ref(s) + Kpd
p1 > 2KpdKvco/N more poles can be used + vctl(s) Vctl 1 1+s/p1 + 2Kvco s out(s)
out(s)/N 1/N
Additional poles beyond the unity loop gain frequency to reduce reference feedthrough

Vdd
Icp
1 A ref D Q QA (UP)
RST
iout R1
QB (DN)
for two extra poles R2
B div 1
RST D Q
C1 Icp
C2 C3
for one extra pole
Extra RC sections for additional poles Must be sufciently beyond the unity loop gain frequency to ensure sufcient phase margin
Noise sources in a PLL

Kpd,I s ref + Kpd + + 2Kvco s out vnc vco
out/N 1/N
Noise can be added as ref (reference phase noise, charge-pump noise, divider output phase noise) or vnc (loop lter noise) or vco (VCO phase noise) Need to compute transfer functions from each of these noise sources to out
Type-II PLL: transfer functions
L(s) = u ,loop = z1 = out (s) ref (s) out (s) Vnc (s) out (s) vco (s) = = =
u ,loop z1 s 1+ s s z1 2 Kpd Kvco Icp RKvco = N N Kpd ,I 1 = Kpd RC 1 + s/z1 N 1 + s/z1 + s2 /z1 u ,loop s/z1 N Kpd 1 + s/z1 + s2 /z1 u ,loop s2 /z1 u ,loop 1 + s/z1 + s2 /z1 u ,loop
L(s) 1 + L(s)
1 + s/z1 1 + s/z1 + s2 /z1 u ,loop
Two poles and a zero Zero z1 = Kpd ,I /Kpd Natural frequency n = Quality factor Q = 2 Kpd ,I Kvco /N NKpd ,I /2 Kvco /Kpd u ,loop /z1 z1 /u ,loop =
Damping factor = 1/2Q = 1/2
For well separated (real) poles (z1 u ,loop ), 2 / p1 z1 + z1 u ,loop z1 , p2 u ,loop z1 ,
Pole zero doublet {p1 , z1 }; p1 at a slightly higher frequency than z1


5 0
1/N|out/ref| [dB]
5 2 10 1 0 15 1 3 10 =4.08 =0.3162 =1 10
2 2 1 0
10
10
10
20
25 3 10
10 /
10
10
u,loop
out (s) ref (s)
= N
1 + s/z1 1 + s/z1 + s2 /z1 u ,loop
Peaking in |out /ref | because of the zero

Damping factor 1 to avoid peaking slow settling


PLL transfer functions 30 20 10 Magnitude response [dB] 0 10 20 30 40 50 60 70 2 10
1 0 1
10 10 f/f 10
out
/ /
ref
out nc out
/v *1V
vco
10
u,loop
(Example parameters: N = 10, z1 = 0.1u ,loop , N /Kpd = 2 Kvco /u ,loop = 25 V1 ) |out /ref |: Lowpass with a dc gain N |out /vnc |: Bandpass with peak gain N /Kpd = 25 V1 |out /vco |: Highpass with a high frequency gain of 1
Type-II PLL phase noise example

PLL phase noise components 20 40 60 80 dBc/Hz 100 120 140 160 180 2 10
reference ref. contribution to PLL VCO VCO contribution to PLL Total 10

1
10 f/f
10
10
u,loop
(Example parameters: N = 10, z1 = 0.1u ,loop , N /Kpd = 2 Kvco /u ,loop = 25 V1 ) Reference contribution dominant below 0.1u ,loop VCO contribution dominant above 0.1u ,loop VCO contribution reduced by the loop upto u ,loop Charge pump and loop lter noise ignored in the above
Type-II PLL: Reference input

20log(N) Kpd,I/Kpd |out/ref| dB, closed loop gain S(f) dBc/Hz 2KpdKvco/N
pole-zero doublet at Kpd,I/Kpd 2KpdKvco/N
reference oscillator phase noise
pll phase noise
out (s) ref (s)
= N
1 + sKpd /Kpd ,I K N + s pd + 1 s2 2 Kpd ,I Kvco Kpd ,I
Low pass response; Reference noise attenuated at high frequencies Low frequency gain of N , -3 dB bandwidth of 2 Kpd Kvco /N Pole zero doublet p1 z1 = Kpd ,I /Kpd ; p1 at a slightly higher frequency than z1
Type-II PLL: Noise added to control node

dB, loop gain
|out/Vctl|
dB(radians/V)
20log(N/Kpd)
zero at Kpd,I/Kpd 2KpdKvco/N +20dB/dec 2KpdKvco/N Kpd,I/Kpd
-20dB/dec
out (s) Vctl (s)
N Kpd
sKpd /Kpd ,I K N s2 + s pd + 1 2 Kpd ,I Kvco Kpd ,I
radians/Volt Bandpass response Mid band gain of N /Kpd Lower cutoff at Kpd ,I /Kpd , Upper cutoff at 2 Kpd Kvco /N
Type-II PLL: VCO noise

vco phase noise -30dB/dec.(1/f3) Kpd,I/Kpd |out/vco| dB 2KpdKvco/N S(f) dBc/Hz -20dB/dec.(1/f2) pll phase noise 2KpdKvco/N Kpd,I/Kpd
0dB
+20dB/dec +10dB/dec
out (s) vco (s)
s2 = s2
N 2 Kpd ,I Kvco
N 2 Kpd ,I Kvco
+s
Kpd +1 Kpd ,I
Second order highpass response Feedback loop effectively inactive beyond 2 Kpd Kvco /N
Type-II PLL phase noise example
S(f) dBc/Hz due to vco 2KpdKvco/N Kpd,I/Kpd
S(f) dBc/Hz
total phase noise
2KpdKvco/N Kpd,I/Kpd
due to reference oscillator
reference dominated vco dominated
LC oscillator
LC oscillator
L C RP (GP) L C GP -GN GN GP for sustained oscillation
Lossless LC resonator sustains a sinusoidal voltage indenitely LC resonator loss modeled using a parallel resistance Rp Compensate the loss of a lossy LC resonator using a parallel negative resistance Oscillation frequency fo = 1/2 LC
LC resonator losses
Rs,L
Rs,C L C
C RP=RP,L||RP,C
RP,L = (L)2/Rs,L QL2 Rs,L
RP,C = 1/(L)2Rs,C QC2 Rs,C
Capacitor and Inductor series resistances represented by equivalent parallel resistances Effective Rp is a parallel combination of losses from all components
Negative resistance-implementation
+ v -
GNv -GN GNv

Transconductor GN connected in positive feedback
Negative resistance-implementation
-gm/2 -gm/2 gmv/2 v/2 gm gm Itail Itail Itail gmv/2 -v/2
Cross coupled differential pair Negative conductance = gm /2 where gm is the transconductance of each MOS device
LC oscillator
Vdd L C -gm/2 GP
Itail
Parallel LC tank with cross coupled differential pair This and its variants are the most commonly used topologies of CMOS integrated oscillators
LC oscillator-amplitude
Vdd L C GP vp M1 Itail vn M2 M1 off M2 on vp-vn M1 on M2 off
Complete switching of MOS devices assumed Equivalent to a square wave current of amplitude I /2 driving the parallel LC tank
Vdd I L C GP I/2 I/2 "bias" point
2I/ I/2
Vdd I L C GP M1 off 0 M2 on I I
Vdd + L C GP M1 on I M2 off 0 vp-vn

2IRP/
sinusoid at fo
v(t)
L C GP vn
vp I/2 I/2 To
driving current
fundamental component
differential voltage
Equivalent to a square wave current of amplitude I /2 driving the parallel LC tank All components except the fundamental ltered out Amplitude of the differential sinusoidal voltage = 2IRP /
LC oscillator-tunability
a a n+ n- well pa b p+ n+ n- well pa n+ b
b b
Tunable using a varactor Reverse biased p-n junction MOS device in accumulationlarger tuning range; more popular in CMOS ICs
Accumulation MOS varactor

a b a n+ n- well pn+ n+ n+ n+ b
metal
metal
n+
n+
n+
n+
n+
Wfinger
n+
n+
n+
n+
n+
Wfinger
metal Lfinger Lfinger
nMOS in n-well Multi ngered structure to reduce gate, channel resistance W few microns; L > Lmin to reduce parasitics Quality factor: 20+
Gate contacts at both ends to further reduce resistance
MOS varactor with differential excitation

ap an b n+ n- well pap an b n+ n- well p0V due to symmetry n+ b n+ n+ n+ n+ n+ n+ n+ n+
ap
an
Interdigitated ngersalternate ones connected to ap and an Region between gates connected to ap and an at 0 V due to symmetry All n+ contacts except the ones at the end can be removed [7] Smaller structure, lower series resistance, and smaller parasitic capacitances
On chip inductors
via
Planar inductor on one of the metal layers Top level metal preferred
Farther from the substrate Smaller parasitic capacitance Lesser coupling to substrate, and hence, loss
Thicker top level metal ( 2 m) available in mixed signal processes Nagendra Phase loop frequency synthesizers on Inductor values up Krishnapura to a couple of locked tens of nH practical
Inductor loss mechanisms

C distributed model: more sections can be added
RS
2 C2
C1
R1 substrate
R2 substrate
Winding resistance
R2 L/W Effective R2 larger due to skin effect Copper: 2 m skin depth ( 1/ f ) at 1 GHz
Capacitive coupling to substrate and its resistance Inductive coupling to (resistive) substrate Quality factors upto 15 possible, typically 8-10 Use adequate thickness and number of vias during layout
Differential inductor
vias
via
via
Symmetrical differential inductor

More compact for a given differential inductance Larger potential difference between turns larger effect of interwinding parasitic capacitance
Symmetrically laid out single ended inductors

Greater area Interwinding parasitic capacitance not very signicant
Inductor simulation
Some processes have scalable inductor library and models Typically needs to be simulated from process parametersmetal thickness, resistivity, intermetal spacing etc. Inductance value
FastHenry, Asitic etc. Accurate estimation possible
Quality factor
FastHenry, Asitic etc. Harder to accurately estimate losses due to substrate coupling
Parasitic capacitance
First order parallel plate estimationOK for single ended inductors FastCap etc. Use distributed models for accuracy2 to 3 sections are sufcient
VCO design: bias current and transistor sizing

Bias current is a function of tank losses and desired amplitude
Maximize the inductance for a large amplitude from a small current
Transistors typically minimum length at high frequencieslonger to lower 1/f corner Bias source: longer than minimum length to lower 1/f noise Minimize all parasitics to maximize tuning range from the varactor Transistor W /L to get the desired gm for startup in the worst case
Large gm increased phase noise; So dont go crazy! Minimize gm variations over process and temperature; Less overdesign
5 GHz VCO in 0.18 m CMOS

1x Vdd 5x 4nH differential 200uA 100 Vdd 100 output 130fF vp Vc vn 130fF vp vn V-bias
L = 4 nH and C = 0.25 pF (differential) chosen 6 turn inductor on top metal layer, 140 m square From inductor simulations, Q 6 Minimum length transistors
Cascode buffer for measurement

5GHz VCO-inductor
5GHz VCO layout
5GHz VCO layout
VCO (higher freq. version)-measured f vs. V

frequency vs Vctl curve
6.3
6.2
6.1
fvco(in GHz)
5.9
5.8
5.7
5.6 0.5
0.5
1.5
Vctl (V)
VCO-simulated phase noise

Phase Noise
20
30 dB/decade
20
Phase Noise (dBc/Hz)
40
60
80
100
20 dB/decade
120
140 2 10
10
10
10
10
10
Frequency offset from carrier (Hz)
Programmable frequency divider
Programmable divider-Synchronous counter
D Q combinational logic N
D Q
D Q fin
All of the circuitry running at full speed Very high power dissipation Asynchronous operation preferred
Programmable divider-Pulse swallow architecture

M A
fin
P/P+1
M
reset
output fin/N N=MP+A
Dual modulus prescaler P /P + 1 Divide by P + 1 for A cycles Divide by P for M A cycles Full cycle = (P + 1)A + P (M A) = MP + A Only the dual modulus prescaler running at full speed Programmability using M and A
Programmable divider using divide-by-2/3 cells

fin 2/3 2/3 2/3 2/3 2/3 fout Vdd
p0
p1
p2 5
p3
p4
Each stage divides by 2 (if pk = 0) Each stage divides by 3 (if pk = 1) once in each output cycle With L stages, the division factor range from 2L to 2L+1 1 Modular approach
Programmable divider using divide-by-2/3 cells

fin 2/3 mod0 f1 2/3 mod1 fout=fin/7
Vdd
p0 fin mod0 f1 fout 3
p1
p0p1=11
Each stage divides by 2 (if pk = 0) Each stage divides by 3 (if pk = 1) once in each cycle With L stages, the division factor range from 2L to 2L+1 1 Modular approach
Divide-by-2/3 cell for the programmable divider
A1
Latch1 D clk Q
Latch2 D Q Fout clk Q
Fin modout A3 Q D Q D clk Latch3 Pi Q clk Latch4
A2 modin
References
Behzad Razavi, RF Microelectronics, Prentice Hall, 1998. Behzad Razavi (editor), Monolithic Phase Locked Loops and Clock Recovery Circuits-Theory and Design, IEEE Press, 1996. Behzad Razavi (editor), Phase Locking in High Performance Systems-From Devices to Architectures, IEEE Press, 2003. Nagendra Krishnapura, Introducing Negative Feedback with an Integrator as the Central Element, 2012 International Symposium on Circuits and Systems (ISCAS), Seoul, South Korea, 20-23 May 2012. Nagendra Krishnapura, Synthesis Based Introduction to Opamps and Phase Locked Loops, 2012 International Symposium on Circuits and Systems (ISCAS), Seoul, South Korea, 20-23 May 2012. Marc Tiebout, Low Power VCO Design in CMOS (Springer Series in Advanced Microelectronics) , Springer 2005. A. S. Porret et al., Design of high-Q varactors for low-power wireless applications using a standard CMOS process, IEEE Journal of Solid-State Circuits, pp. 337-345, Volume 35, Issue 3, March 2000. C. Vaucher et al., A family of low-power truly modular programmable dividers in standard 0.35- m CMOS technology, IEEE Journal of Solid-State Circuits, vol. 35, no. 7, pp. 1039-1045, July 2000.

Phase Locked Loop Frequency Synthesizers

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Phase locked loop frequency synthesizers

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