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  • Objective Key

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    This document contains an objective key for a VLSI Design course taken during the 2013-2014 academic year at Narayana Engineering College in Nellore/Gudur, India. It includes objective questions and answers across 8 units covering topics like CMOS fabrication, transistor operation, layout design, arithmetic circuits, programmable logic, simulation, and testing. The key was prepared by faculty members A. Surendra Reddy and Sk. Shaguftha for a class of I1 B.Tech II semester students in the department of Electronics and Communication Engineering.

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    for vlsi nec nle

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    This document contains an objective key for a VLSI Design course taken during the 2013-2014 academic year at Narayana Engineering College in Nellore/Gudur, India. It includes objective questions and answers across 8 units covering topics like CMOS fabrication, transistor operation, layout design, arithmetic circuits, programmable logic, simulation, and testing. The key was prepared by faculty members A. Surendra Reddy and Sk. Shaguftha for a class of I1 B.Tech II semester students in the department of Electronics and Communication Engineering.

    Copyright:

    Attribution Non-Commercial (BY-NC)
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    59 Ansichten3 Seiten

    Objective Key

    Hochgeladen von

    edurubirra
    This document contains an objective key for a VLSI Design course taken during the 2013-2014 academic year at Narayana Engineering College in Nellore/Gudur, India. It includes objective questions and answers across 8 units covering topics like CMOS fabrication, transistor operation, layout design, arithmetic circuits, programmable logic, simulation, and testing. The key was prepared by faculty members A. Surendra Reddy and Sk. Shaguftha for a class of I1 B.Tech II semester students in the department of Electronics and Communication Engineering.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Als DOC, PDF, TXT herunterladen oder online auf Scribd lesen
    Markieren Sie unangemessene Inhalte
    von 3

    NARAYANA ENGINEERING COLLEGE::NELLORE/GUDUR

    DEPARTMENT OF ECE
    ACADEMIC YEAR: 2013 2014
    OBECTIVE KEY
    Subject: VLSI Design (R09) ,Common to ECE &EIE
    : I11B.TECH. II SEM

    Class

    Faculty :A. SURENDRA REDDY/SK. SHAGUFTHA

    ------------------------------------------------------------------------------------------UNIT-1
    1

    11

    CHEMICAL VAPOUR
    DEPOSITION

    16

    low

    12

    ELECTRON

    17

    limited
    load
    driving
    capability

    13

    DEAL AND GROVER

    18

    ON

    14

    ZERO

    19

    FASTER

    10

    15

    20

    LOW

    11

    8:1

    16

    faster

    12

    BODY EFFECT

    17

    High,low

    13

    LESS

    18

    low

    14

    /2(

    19

    CMOS

    10

    15

    (vgs-vt )

    20

    LOW

    Vss, Vdd

    UNIT-2

    vgs-vt

    )2

    UNIT-3
    1

    11

    METAL 2

    16

    Diffusion

    12

    STICK DIAGRAM

    17

    local
    distribution,
    global
    distribution

    13

    BROWN

    18

    14

    POWER RAILS

    19

    reduces

    10

    15

    20

    black line

    UNIT-4
    1

    11

    Td= n2 rc( )

    16

    frequency

    12

    SILLICIDE

    17

    Polysilicon

    13

    2.5

    18

    large
    capacitive
    load

    14

    0.4

    19

    exponentially

    10

    15

    HIGH LOAD DRIVING


    CAPABILITY

    20

    reduced

    UNIT-5
    1

    11

    12

    13

    14

    10

    15

    ONE BIT PARITY


    CELL
    CONTENT
    ADDRESABLE
    MEMORY
    REFRESHMENT
    ZERO AND ONE
    ARITHEMETIC AND
    LOGICAL SHIFTER

    16

    EX-OR

    17

    previous
    counter
    stage

    18

    6 CMOS

    19

    3 times

    20

    Booth
    encoding

    UNIT-6
    1

    11

    12

    13

    14

    10

    15

    AND, OR ARRAY
    ROUTING
    CHANNEL
    STANDARD
    LIBRARY
    RARELY
    ABSENCE OF
    ROUTING
    CHANNEL

    16

    increased design
    complexity

    17

    number of inputs

    18

    FIXED,PROGRAMMABLE

    19

    PAL

    20

    UV erasable memories

    UNIT-7
    1

    11

    12

    13

    14

    10

    15

    CIRCUIT

    16

    QN+1=D

    SWITCH AND TIMING

    17

    DESIGN RULES

    18

    Floor plan
    Design
    rules
    Mixed
    mode
    simulators

    SWITCH

    19

    NETWORK
    ISOMORPHISM

    20

    Schematic
    editors

    UNIT-8
    1

    11

    SERIAL SCAN

    16

    Built In Self
    Test

    12

    17

    pseudorandom

    13

    18

    delay fault

    14

    SELF TEST
    LEVEL SENSITIVE
    SCAN DESIGN
    BRIDGING

    10

    15

    STUCK AT 0

    19
    20

    boundary scan
    testing
    TAP
    controller

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