Toshiba Satellite c660 La-6841p r01

A
PWWAA
Marseille LC
2
L-A6841P REV 0.1 Schematic

Intel Penryn/ Cantiga/ ICH9M
2010-07-22 Rev. 0.1
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2009/06/12
Issued Date
Deciphered Date
2010/06/12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Cover Page
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Monday, August 16, 2010
Sheet
E
of
44
Compal Confidential
Fan Control
Model Name : PWWAA

File Name : LA-6841P
APL5607
uPGA-478 Package
(Socket P) page
page 4
Clock Generator
EMC1402-1
SLG8SP556VTR
page 4
page 16
1
4,5,6
FSB
H_A#(3..35)
CRT
Thermal Sensor
Intel Penryn Processor
H_D#(0..63)
667/800/1066MHz
Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2
Intel Cantiga
Dual Channel
page 18
GM45/GL40
page 14,15
BANK 0, 1, 2, 3
1.5V DDR3 800/1066
LCD Conn.
page 17
uFCBGA-1329
page 7,8,9,10,11,12,13
PCIeMini Card
WiMax
USB port 7
page 25
USB
DMI x 4
C-Link
5V 480MHz
USB
5V 480MHz
PCIe 1x [2,4,5]
PCIeMini Card
WLAN
USB/B
Int. Camera
USB port 0,1
USB port 11
1.5V 2.5GHz(250MB/s)
PCIe port 4
page 25
SATA port 1
RJ45
page 26
PCIe port 3
PCIe 1x
page 26
USB port 10
1.5V 2.5GHz(250MB/s)
BGA-676
SATA port 4
USB
RTS5138E 2IN1
page 29
page 17
Intel ICH9-M
5V 1.5GHz(150MB/s)
RTL8105E 10/100M
page 23
5V 1.5GHz(150MB/s)
5V 480MHz
SATA HDD0
page 23
SATA ODD
page 23
page 19,20,21,22
Power/B
3.3V 33 MHz
LPC BUS
HD Audio
3.3V/1.5V 24.576MHz/48Mhz
HDA Codec
page 24
Debug Port
page 31
RTC CKT.
ALC259
ENE KB926 D2
page 29
page 30
page 20
Touch Pad
DC/DC Interface CKT.
page 24
page 33
Int.KBD
SPI ROM
page 24
Int.
MIC CONN
page 30
page 31
MIC CONN
page 30
HP CONN
page 30
SPK CONN
page 30
Power Circuit DC/DC

Compal Secret Data
page 34,35,36,37,38,39,40
2009/06/12
Issued Date
Deciphered Date
2010/06/12
A
Title
Block Diagrams
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
E
of
44
Voltage Rails
Power Plane
SIGNAL
STATE
Description
S1
S3
S5
Adapter power supply (19V)
ON
ON
ON
OFF
B+
AC or battery power rail for power circuit.
ON
ON
ON
ON
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
Full ON
HIGH
HIGH
HIGH
HIGH
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
S5 (Soft OFF)
LOW
LOW
LOW
LOW
G3
LOW
LOW
LOW
LOW
G3
VIN
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
OFF
+0.75VS
0.75V switched power rail for DDR terminator
ON
OFF
OFF
OFF
+1.05VS
1.05V switched power rail
ON
OFF
OFF
OFF
+1.5VS
ON
OFF
OFF
OFF
+1.5V
1.5 power rail for DDR
ON
ON
OFF
OFF
+1.8VS
1.8V power rail
ON
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON
OFF
+3VL
3.3V always on power rail
ON
ON
ON
ON
+3V_SB
3.3V power rail for SB
ON
ON
OFF
OFF
+3V_LAN
3.3V power rail for LAN
ON
ON
OFF
OFF
+3VS
ON
OFF
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON
OFF
+5V_SB
5V power rail for SB
ON
ON
OFF
OFF
+5VS
5V switched power rail
ON
OFF
OFF
OFF
+VSB
VSB always on power rail
ON
ON
ON
OFF
+RTCVCC
RTC power
ON
ON
ON
ON
BTO Option Table

Camera
WLAN
Energy Star
description
(X)
Always
Always
explain
Camera
WLAN
Energy Star
BTO
CAM@
Function
Card Reader
WLAN@
External PCI Devices

DEVICE
PCI DEVICE ID
IDSEL#
REQ/GNT#
EC SM Bus1 address
Power Device
+3VL
EC KB926 D2
+3VL
Smart Battery
PIRQ
EC SM Bus2 address
Address
0001 011X b
Power Device
+3VS
EC KB926 D2
+3VS
CPU THM Sen

SMSC SMC1402
Address
1001 101Xb
ICH9M SM Bus address

Power Device
Address
+3V_SB ICH9M
4
1101 001Xb
+3VS
Clock Generator
(SLG8SP556V)
DDR DIMM0
+3VS
DDR DIMM1
1001 010Xb
+3VS
1001 000Xb
Compal Secret Data
2009/06/12
Issued Date
Deciphered Date
2010/06/12
A
Title
Notes List
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
E
of
44
@
JCPUA
<7>
H_REQ#0
<7>
H_REQ#1
<7>
H_REQ#2
<7>
H_REQ#3
<7>
H_REQ#4
<7> H_A#[17..35]
A6
A5
C4
A20M#
FERR#
IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
D5
C6
B4
A3
STPCLK#
LINT0
LINT1
SMI#
M4
N5
T2
V3
B2
D2
D22
D3
F6
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
Reserve for
debug
close to South
Bridge
IERR#
INIT#
D20
B3
LOCK#
H4
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
C1
F3
F4
G3
G2
HIT#
HITM#
G6
E4
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
H_BR0#
H_IERR#
H_INIT#
R1 1
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
0.1U_0402_16V4Z
F1
<7>
2 56_0402_5%
H_INIT#
<20>
+1.05VS
C2
1
H_LOCK# <7>
H_RESET#
H_RESET# <7>
H_RS#0
<7>
H_RS#1
<7> if use XDP,these resistor are 51ohm
H_RS#2
<7>
+1.05VS
H_TRDY# <7>
H_HIT#
<7>
H_HITM# <7>
XDP_TDO
XDP_TMS
XDP_TDI
XDP_TCK
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
XDP_TRST#
PAD T13
+1.05VS
XDP_DBRESET# <21>
1
R14
1
R4
1
R5
2
54.9_0402_1%
2
54.9_0402_1%
2
54.9_0402_1%
1
R6
1
R7
2
54.9_0402_1%
2
54.9_0402_1%
1
R8
1
R9
2
@ 56_0402_5%
2
56_0402_5%
H_PROCHOT#
D21
A24
B25
H_PROCHOT#
H_THERMDA
H_THERMDC
C7
+3VS
R3
1
2
10K_0402_5%
VDD
DP
DN
THERM#
SMCLK
SMDATA
ALERT#
GND
EC_SMB_CK2 <30>
EC_SMB_DA2 <30>
1
R2
2
10K_0402_5%
@ Reserve
+3VS
for source control
FAN Control Circuit
1A
C3
10U_0805_10V4Z
OCP#
<21>
JFAN
+FAN1
1
2
U2
PROCHOT# PU: 68Ohm near CPU and MVP6.

56Ohm near CPU if no used.
1
2
3
4
+FAN1
10mil
CLK_CPU_BCLK <16>
CLK_CPU_BCLK# <16>
EMC1402-1-ACZL-TR_MSOP8
+5VS
H_THERMTRIP# <8,20>
A22
A21
U1
H_THERMDC
2
2200P_0402_50V7K
CPU_THERM#
<30> EN_DFAN1
BCLK[0]
BCLK[1]
C1
Address:0100_1100 EMC1402-1
Address:0100_1101 EMC1402-2
Q6
@ MMBT3904_SOT23
H CLK
H_THERMDA
H_STPCLK#
H_INTR
H_NMI
H_SMI#
H_A20M#
H_FERR#
H_IGNNE#
H_DEFER# <7>
H_DRDY# <7>
H_DBSY# <7>
THERMAL
ICH
<20> H_A20M#
<20> H_FERR#
<20> H_IGNNE#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
H5
F21
E1
<7>
<7>
<7>
<7> H_ADSTB#1
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
H_ADS#
H_BNR#
H_BPRI#
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
BR0#
ADDR GROUP_1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
DEFER#
DRDY#
DBSY#
H1
E2
G5
K3
H2
K2
J3
L1
ADS#
BNR#
BPRI#
CONTROL
<7> H_ADSTB#0
+3VS
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
XDP/ITP SIGNALS
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
ADDR GROUP_0
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_THERMDA, H_THERMDC routing together,

Trace width / Spacing = 10 / 10 mil
EN
VIN
VOUT
VSET
GND
GND
GND
GND
C4
@ 1000P_0402_25V8J
1
8
7
6
5
1
2
3
1
2
3
4
5
GND
GND
ACES_85204-0300N
@
APL5607KI-TRG_SO8
C5
10U_0805_10V4Z
R10
10K_0402_5%
1
+3VS
FAN_SPEED1 <30>
2
C6
0.01U_0402_16V7K
1 @
RESERVED
<7> H_A#[3..16]
<20>
<20>
<20>
<20>
Penryn
B
H_FERR#
2
C596
H_SMI#
H_INIT#
H_NMI
H_A20M#
H_INTR
H_IGNNE#
H_STPCLK#
2
C597
2
C598
2
C599
2
C600
2
C601
2
C602
2
C603
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
Reserve for
debug
close to CPU
A
Compal Secret Data
2009/06/12
Issued Date
Deciphered Date
2010/06/12
5
Title
Penryn(1/3)-AGTL+/THM/FAN
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
of
44
@
JCPUD
@
JCPUB
<7>
<7>
<7>
<7>
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#[16..31]
+1.05VS Close
<7> H_DSTBN#1
<7> H_DSTBP#1
<7> H_DINV#1
+CPU_GTLREF
+CPU_GTLREF
R11
1K_0402_1%
to
CPU pin
AD26
within
500mils.
R17
2K_0402_1%
<8,16> CPU_BSEL0
<8,16> CPU_BSEL1
<8,16> CPU_BSEL2
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]
DATA GRP 1
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#[32..47]
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
DATA GRP 0
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
MISC
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP[0]
COMP[1]
COMP[2]
COMP[3]
R26
U26
AA1
Y1
COMP0
COMP1
COMP2
COMP3
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
E5
B5
D24
D6
D7
AE6
H_DPRSTP#
H_DPSLP#
DATA GRP 2
H_D#[0..15]
DATA GRP 3
<7>
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
<7>
H_DSTBN#2 <7>
H_DSTBP#2 <7>
H_DINV#2 <7>
H_D#[48..63] <7>
Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 5 mils.
H_DSTBN#3 <7>
H_DSTBP#3 <7>
H_DINV#3 <7>
H_PW RGOOD
H_CPUSLP#
COMP0
1
R12
1
R13
COMP2
1
R15
COMP3
1
R18
COMP1
2
27.4_0402_1%
2
54.9_0402_1%
2
27.4_0402_1%
2
54.9_0402_1%
H_DPRSTP# <8,20,40>
H_DPSLP# <20>
H_DPW R# <7>
H_PW RGOOD <20>
H_CPUSLP# <7>
H_PSI#
<40>
layout note: Please use "Daisy Chain"

to layout and the signal (H_DPRSTP#)
is routed from ICH9 to power IC,
then to NB and CPU
Penryn
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
B
CPU_BSEL
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
H_CPUSLP#
166
200
266
2
C650
H_PW RGOOD
2
C651
H_DPRSTP#
2
C652
H_DPSLP#
2
C653
Reserve for
debug
close to CPU
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
1
@ 180P_0402_50V8J
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
Penryn
.
Compal Secret Data
2009/06/12
Issued Date
Deciphered Date
2010/06/12
5
Title
Penryn(2/3)-AGTL+/GND
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
of
44
Near CPU CORE regulator
+CPU_CORE
ESR <= 1.5m ohm

Capacitor > 1980uF
D
1
Place these capacitors on L8
(North side,Secondary Layer)
+CPU_CORE
C11
10U_0805_6.3V6M
C12
10U_0805_6.3V6M
C13
10U_0805_6.3V6M
C14
10U_0805_6.3V6M
C15
10U_0805_6.3V6M
C16
10U_0805_6.3V6M
C17
10U_0805_6.3V6M
C18
10U_0805_6.3V6M
+CPU_CORE
+CPU_CORE
@
JCPUC
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
330U_6.3V_M_R15
330U_6.3V_M_R15
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
VCCA[01]
VCCA[02]
B26
C26
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
AD6
AF5
AE5
AF4
AE3
AF3
AE2
VCCSENSE
AF7
VCCSENSE
VCCSENSE <40>
VSSSENSE
AE7
VSSSENSE
VSSSENSE <40>
C79
C80
2
330U_6.3V_M_R15
C81
1
(North side,Secondary Layer)
C19
10U_0805_6.3V6M
C20
10U_0805_6.3V6M
C21
10U_0805_6.3V6M
C22
10U_0805_6.3V6M
C23
10U_0805_6.3V6M
C24
10U_0805_6.3V6M
C25
10U_0805_6.3V6M
C26
10U_0805_6.3V6M
C82
need to change P/N
+CPU_CORE
330U_6.3V_M_R15
1
(Sorth side,Secondary Layer)
C27
10U_0805_6.3V6M
C28
10U_0805_6.3V6M
C29
10U_0805_6.3V6M
C30
10U_0805_6.3V6M
C31
10U_0805_6.3V6M
C32
10U_0805_6.3V6M
C33
10U_0805_6.3V6M
C34
10U_0805_6.3V6M
+CPU_CORE
1
(Sorth side,Secondary Layer)
C35
10U_0805_6.3V6M
C36
10U_0805_6.3V6M
C37
10U_0805_6.3V6M
C38
10U_0805_6.3V6M
C39
10U_0805_6.3V6M
C40
10U_0805_6.3V6M
C41
10U_0805_6.3V6M
C42
10U_0805_6.3V6M
Mid Frequence Decoupling

+1.05VS
4.5A
Place these inside socket cavity on L8
+1.05VS (North side Secondary)
+
C146
2 330U_6.3V_M_R15
C44
0.1U_0402_10V6K
C45
0.1U_0402_10V6K
C46
0.1U_0402_10V6K
C47
0.1U_0402_10V6K
C48
0.1U_0402_10V6K
C49
0.1U_0402_10V6K
Near pin B26
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
<40>
<40>
<40>
<40>
<40>
<40>
<40>
+1.5VS
C50
0.01U_0402_16V7K 10U_0805_6.3V6M
2
C51
Penryn
.
+CPU_CORE
VCCSENSE
100_0402_1% 2
R19
VSSSENSE
100_0402_1% 2
R20
Close to CPU pin

within 500mils.
Length match within 25 mils.

The trace width/space/other is
14/7/25.
5
Compal Secret Data
2009/06/12
Issued Date
Deciphered Date
2010/06/12
3
Title
Penryn(3/3)-PWR/Bypass
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
of
44
<5>
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
Layout Note:
H_RCOMP / +H_VREF / H_SWNG
trace width and spacing is 10/20
within 100 mils from NB
+1.05VS
R22
221_0402_1%
C52
0.1U_0402_16V4Z
@
H_SWING=0.3125*VCCP
H_SW NG
C5
E3
H_SWING
H_RCOMP
R24
24.9_0402_1%
R23
2K_0402_1%
H_SW NG
H_RCOMP
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_RCOMP
+H_VREF
R25
100_0402_1%
1 2
R21
1K_0402_1%
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
C53
0.1U_0402_16V4Z
<4>
H_RESET#
<5> H_CPUSLP#
Near B3 pin
+H_VREF
H_A#[3..35]
U3A
H_D#[0..63]
+1.05VS
HOST
C12
E11
H_CPURST#
H_CPUSLP#
A11
B11
H_AVREF
H_DVREF
<4>
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# <4>
H_BR0# <4>
H_DEFER# <4>
H_DBSY# <4>
CLK_MCH_BCLK <16>
CLK_MCH_BCLK# <16>
H_DPW R# <5>
H_DRDY# <4>
H_HIT#
<4>
H_HITM# <4>
H_LOCK# <4>
H_TRDY# <4>
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
J8
L3
Y13
Y1
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
L10
M7
AA5
AE6
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
<5>
<5>
<5>
<5>
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
L9
M8
AA6
AE5
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
<5>
<5>
<5>
<5>
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
B15
K13
F13
B13
B14
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
<4>
<4>
<4>
<4>
<4>
H_RS#_0
H_RS#_1
H_RS#_2
B6
F12
C8
H_RS#0
H_RS#1
H_RS#2
<4>
<4>
<4>
<5>
<5>
<5>
<5>
CANTIGA ES_FCBGA1329
GM45R3@
Compal Secret Data
2009/06/12
Issued Date
Deciphered Date
2010/06/12
5
Title
Cantiga GMCH(1/7)-GTL
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
of
44
Internal pull-up
0 = PCIe Loopback Enable

1 = Disable*(Default)
AY21
Internal pull-up
01
00
10
11
Internal pull-up
0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled *(Default)
CFG[13:12]
= All Z Mode Enabled

= Reserved
= XOR Mode Enabled
= Normal Operation*(Default)
BG23
BF23
BH18
BF18
CFG19 Internal pull-down
0 = Normal Operation
1 = DMI Lane Reversal Enable
CFG20
0 = Only PCIE or [SDVO/DP/HDMI] is operational.
Internal pull-down
RSVD22
RSVD23
RSVD24
RSVD25
*(Default)
* (Default)
1 = PCIE/[SDVO/DP/HDMI] are operating simu.
MCH_CFG_9
MCH_CFG_10
R46
R47
1
1
2@ 2.21K_0402_1%
2@ 2.21K_0402_1%
MCH_CFG_12
MCH_CFG_13
+3VS
R48
2@ 2.21K_0402_1%
MCH_CFG_16
1
1
T16 PAD MCH_CFG_19

2 4.02K_0402_1%
MCH_CFG_20
2@ 4.02K_0402_1%
R49
R50
B
2 PM_EXTTS#_R
10K_0402_5%
1
2 0_0402_5%
<5,20,40> H_DPRSTP#
<14,15> PM_EXTTS#
R53
<19,25,26,30,31> PLT_RST#
<4,20> H_THERMTRIP#
<21,40> PM_DPRSLPVR
R54
R55
R56
1
1
1
PM_SYNC#_R
PM_EXTTS#_R
GMCH_PWROK
2 100_0402_5% MCH_RSTIN#
NB_THERMTRIP#
2 0_0402_5%
DPRSLPVR
0_0402_5%
2
2 0_0402_5%
R29
B7
N33
P32
AT40
AT11
T20
R32
PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
PM
1
R52
R51
SMRCOMP
SMRCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
BF28
BH28
+SM_RCOMP_VOH
+SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
AV42
AR36
BF17
BC36
+SM_VREF
R29
R30
1
1
B38
A38
E41
F41
1
+1.5V
1
R33
DDR3_SM_PWROK <38>
2
499_0402_1%
CLK_DREF_96M
CLK_DREF_96M#
CLK_DREF_SSC
CLK_DREF_SSC#
1
C58
0.1U_0402_16V4Z
2 @
CLK_DREF_96M <16>
CLK_DREF_96M# <16>
CLK_DREF_SSC <16>
CLK_DREF_SSC# <16>
AE41
AE37
AE47
AH39
DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3
<19>
<19>
<19>
<19>
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
AE40
AE38
AE48
AH40
DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3
<19>
<19>
<19>
<19>
AE35
AE43
AE46
AH42
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
<19>
<19>
<19>
<19>
AD35
AE44
AF46
AH43
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
<19>
<19>
<19>
<19>
GFX_VR_EN
2
2
R31
1K_0402_1%
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
2.2U_0603_6.3V6K
C57
R28
1K_0402_1%
+1.5V
2 80.6_0402_1%
2 80.6_0402_1%
CLK_MCH_3GPLL <16>
CLK_MCH_3GPLL# <16>
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
80 Ohm
C56
0.01U_0402_16V7K
<14>
<14>
<15>
<15>
F43
E43
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
+SM_RCOMP_VOL
For Cantiga
20mil
SM_REXT
R34
1K_0402_1%
+1.05VS
+3VS
R38
1K_0402_5%
Lane reversal
R41
54.9_0402_1%
MCH_TSATN#
R42
1K_0402_5%
3
1
Q7
MMBT3904_SOT23-3
MCH_TSATN_EC# <30>
Strap Pin Table
B33
B32
G33
F33
E33
SDVO_CTRLDATA
(Internal pull-down)
0 = SDVO interface disabled *(Default)

1 = SDVO interface enabled
DDPC_CTRLDATA
0 = Digital display (iHDMI/DP) interface disabled

1 = Digital display (iHDMI/DP) interface enabled
*(Default)
C34
+1.05VS
2
+3VS
<21> PM_SYNC#
BG22
BH21
2.2U_0603_6.3V6K
C55
R27
3.01K_0402_1%
1
1
2@ 2.21K_0402_1%
2@ 2.21K_0402_1%
SM_RCOMP
SM_RCOMP#
R44
R45
R39
R40
R43
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
DDRA_ODT0
DDRA_ODT1
DDRB_ODT0
DDRB_ODT1
<14>
<14>
<15>
<15>
1
1
1
T14 PAD
T15 PAD MCH_CFG_5
2@ 2.21K_0402_1%
MCH_CFG_6
2@ 2.21K_0402_1%
MCH_CFG_7
2@ 2.21K_0402_1%
T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28
CFG
1 1K_0402_5% MCH_CLKSEL0
BD17
AY17
BF15
AY13
PEG_CLK
PEG_CLK#
DMI
<5,16> CPU_BSEL0
<5,16> CPU_BSEL1
<5,16> CPU_BSEL2
2
2
2
R35
R36
R37
SA_ODT_0
SA_ODT_1
SB_ODT_O
SB_ODT_1
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
GRAPHICS VID
DDRA_SCS0#
DDRA_SCS1#
DDRB_SCS0#
DDRB_SCS1#
SM_DRAMRST# <14,15>
CLK
(PCIE/SDVO select)
RSVD20
BA17
AY16
AV16
AR13
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SM_DRAMRST# would be
needed for DDR3 only
CFG10
RSVD15
RSVD16
RSVD17
C54
0.01U_0402_16V7K
<14>
<14>
<15>
<15>
Internal pull-up
B31
B2
M1
RSVD
CFG9
0 = Lane Reversal Enable

1 = Normal Operation *(Default)
DDRA_CKE0
DDRA_CKE1
DDRB_CKE0
DDRB_CKE1
+SM_RCOMP_VOH
T18
1 = Intel Management Engine Crypto TLS cipher suite with

confidentiality *(Default)
BC28
AY28
AY36
BB36
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
<14>
<14>
<15>
<15>
Internal pull-up
DDRA_CLK0#
DDRA_CLK1#
DDRB_CLK0#
DDRB_CLK1#
0 = Intel Management Engine Crypto Transport Layer Security

(TLS) cipher suite with no confidentiality
AR24
AR21
AU24
AV20
PAD
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
*(Default)
can support disble by SW.
R26
1K_0402_1%
0 = iTPM Host Interface is enabled
<14>
<14>
<15>
<15>
1 = iTPM Host Interface is Disabled
DDRA_CLK0
DDRA_CLK1
DDRB_CLK0
DDRB_CLK1
Internal pull-up
AP24
AT21
AV24
AU20
CFG6
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
0 = DMI x 2
1 = DMI x 4 *(Default)
CFG16
+1.5V
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
COMPENSATION
Internal pull-up
M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24
DDR CLK/ CONTROL/
CFG5
CFG7
U3B
011 = FSB667
010 = FSB800
000 = FSB1067
CFG[2:0]
Strap Pin Table
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
TSATN#
R57
1K_0402_1%
CL_CLK0 <21>
CL_DATA0 <21>
ICH_PWROK
Width:Spacing
12mil:12mil
CL_RST#0 <21>
+CL_VREF
+CL_VREF=0.355V
C59
0.1U_0402_16V4Z
N28
M28
G36
E36
K36
H36
SDVO_SCLK
T17 PAD
B12
MCH_TSATN#
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
R60
499_0402_1%
CLKREQ_3GPLL# <16>
MCH_ICH_SYNC# <21>
+3VS
Compal Secret Data

2010/06/12
Deciphered Date
3
1
2.2K_0402_5%
B28
B30
B29
C29
A28
2009/06/12
Issued Date
CL_VREF
should be
0.35 V
SDVO_SCLK 2
R61
GM45R3@
AH37
AH36
AN36
AJ35
AH34
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
ME
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
MISC
GMCH_PWROK
2
@ 0_0402_5%
2
0_0402_5%
HDA
<21,30,40> VGATE
<21,30> ICH_PWROK
1
R58
1
R59
NC
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47
Use VGATE for GMCH_PWROK
Title
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
of
44
<15> DDR_B_D[0..63]
DDR_A_BS0 <14>
DDR_A_BS1 <14>
DDR_A_BS2 <14>
SA_RAS#
SA_CAS#
SA_WE#
BB20
BD20
AY20
DDR_A_RAS# <14>
DDR_A_CAS# <14>
DDR_A_W E# <14>
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
SYSTEM
MEMORY
DDR_A_DM[0..7]
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
AJ43 DDR_A_DQS#0
AT43 DDR_A_DQS#1
BA44 DDR_A_DQS#2
BD37 DDR_A_DQS#3
AY12 DDR_A_DQS#4
BD8 DDR_A_DQS#5
AU9 DDR_A_DQS#6
AM8 DDR_A_DQS#7
DDR_A_DQS#[0..7]
DDR_A_MA[0..14]
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
<14>
DDR_A_DQS[0..7]
U3E
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
<14>
<14>
<14>
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
GM45R3@
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
SA_BS_0
SA_BS_1
SA_BS_2
BD21
BG18
AT25
SB_BS_0
SB_BS_1
SB_BS_2
BC16
BB17
BB33
DDR_B_BS0 <15>
DDR_B_BS1 <15>
DDR_B_BS2 <15>
SB_RAS#
SB_CAS#
SB_WE#
AU17
BG16
BF14
DDR_B_RAS# <15>
DDR_B_CAS# <15>
DDR_B_W E# <15>
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
MEMORY
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
DDR
AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SYSTEM
U3D
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
DDR
<14> DDR_A_D[0..63]
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
<15>
C
DDR_B_DQS#[0..7]
AL46 DDR_B_DQS#0
AV47 DDR_B_DQS#1
BH41 DDR_B_DQS#2
BH37 DDR_B_DQS#3
BG9 DDR_B_DQS#4
BC2 DDR_B_DQS#5
AT2 DDR_B_DQS#6
AN5 DDR_B_DQS#7
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
<15>
DDR_B_MA[0..14]
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
<15>
<15>
GM45R3@
Compal Secret Data
2009/06/12
Issued Date
Deciphered Date
2010/06/12
5
Title
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
of
44
L_DDC_DATA
0 = LFP Disable
*(Default)
1 = LFP Card Present; PCIE disable
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
<17> UMA_LCD_TXCLK<17> UMA_LCD_TXCLK+
C41
C40
B37
A37
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
<17> UMA_LCD_TXOUT0<17> UMA_LCD_TXOUT1<17> UMA_LCD_TXOUT2-
H47
E46
G40
A40
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
<17> UMA_LCD_TXOUT0+
H48
D45
F40
B40
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
A41
H38
G37
J37
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
B42
G38
F37
K37
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3
LVDS
R74
R75
1
1
1
2 TV_COMPS
75_0402_1%
2 TV_LUMA
75_0402_1%
2 TV_CRMA
75_0402_1%
UMA_CRT_B
2
150_0402_1%
UMA_CRT_G
2
150_0402_1%
UMA_CRT_R
2
150_0402_1%
TV_COMPS
TV_LUMA
TV_CRMA
<18> UMA_CRT_B
<18> UMA_CRT_G
F25
H25
K25
TVA_DAC
TVB_DAC
TVC_DAC
H24
TV_RTN
C31
E32
TV_DCONSEL_0
TV_DCONSEL_1
UMA_CRT_B
E28
CRT_BLUE
UMA_CRT_G
G28
CRT_GREEN
R76
1
R77
1
2.2K_0402_5%
UMA_CRT_CLK
2
2.2K_0402_5%
UMA_CRT_DATA
2
UMA_CRT_CLK
UMA_CRT_DATA
UMA_CRT_HSYNC
1UMA_CRT_IREF
1.02K_0402_1%
<18> UMA_CRT_CLK
<18> UMA_CRT_DATA
<18> UMA_CRT_HSYNC
2
R78
J28
CRT_RED
G29
CRT_IRTN
H32
J32
J29
E29
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
UMA_CRT_VSYNC L29
<18> UMA_CRT_VSYNC
PEG_COMPI
PEG_COMPO
T37
T36
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
VGA
UMA_CRT_R
<18> UMA_CRT_R
+3VS
TV
R73
within 500 mils

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
1
R70
1
R71
1
R72
U3C
Reserve
LCTLA_CLK
L32
2
<17> NB_PW M
10K_0402_5%
G32
<30> UMA_ENBKL
LCTLB_DATA
LCTLA_CLK
2
M32
10K_0402_5%
LCTLB_DATA
M33
UMA_LCD_EDID_CLK <17> UMA_LCD_EDID_CLK
UMA_LCD_EDID_CLK K33
2
2.2K_0402_5%
UMA_LCD_EDID_DATAJ33
<17> UMA_LCD_EDID_DATA
UMA_LCD_EDID_DATA
UMA_ENVDD
2
M29
<17> UMA_ENVDD
2.2K_0402_5%
R69 1
2 LVDS_IBG
C44
2.37K_0402_1% Spacing=20mil B43
R501 1
2 0_0402_5%
E37
R502 1
2 0_0402_5%
E38
1
R64
1
R66
1
R67
1
R68
GRAPHICS
+3VS
PCI-EXPRESS
CRT_VSYNC
PEG_COMP 1
R65
2
49.9_0402_1%
+1.05VS
10mils
GM45R3@
Compal Secret Data
2009/06/12
Issued Date
Deciphered Date
2010/06/12
5
Title
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
10
of
44
U3F
+1.05VS
DDR2,667MHz,2600mA
DDR2,800MHz,3000mA
0.1U_0402_16V4Z
BA36
BB24
BD16
BB21
AW16
AW13
AT13
VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC
8700mA
For layout placement un-mound C123 and mound C84
Int. Graphic
+1.05VS
+1.05VS
10U_0805_10V4Z
1
+
C225
330U_6.3V_M_R15 C85
2
1
C86
0.47U_0603_10V7K
1
C87
1
C88
2
2
2
10U_0805_10V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1
C89
2
1
C90
2
0.1U_0402_16V4Z
AJ14
AH14
VCC_AXG_SENSE
VSS_AXG_SENSE
0.22U_0402_10V4Z
1
+
C72
1
+
C73
C74
1
C75
C76
C77
2 330U_6.3V_M_R15
2 330U_6.3V_M_R15
2
2
2
10U_0805_10V4Z
0.22U_0402_10V4Z
U3G
0.1U_0402_16V4Z
Intel: VCC -- 220U*2, ESR 12mOhm
AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
T32
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
+1.05VS
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
GFX
PAD T3
PAD T4
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
NB Core,Intel Management Engine Link
VCC
Intel:AXG and AXG_NCTF -- 220U*2, ESR 15mOhm

For layout issue to separate 220u*1 to +1.05VS
B
Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14
+1.05VS
VCC CORE
SM
10U_0805_10V4Z
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
Extnal Graphic: 1210.34mA

integrated Graphic: 1930.4mA
Intel Management Engine Link:508.12mA
NCTF
VCC
1
C71
VCC_AXG_NTCF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC
1
C70
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
GFX NCTF
C69
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
VCC
10U_0805_10V4Z
VCC SM LF
1
C78 +
390U_2.5V_M_R10
DDR PWR
Int. Graphic
POWER
+1.5V
POWER
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
AV44 VCCSM_LF1
BA37 VCCSM_LF2
AM40 VCCSM_LF3
AV21 VCCSM_LF4
AY5 VCCSM_LF5
AM10 VCCSM_LF6
BB13 VCCSM_LF7
C91
0.1U_0402_16V4Z
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
GM45R3@
C93
1
0.22U_0603_10V7K
C92
2 0.1U_0402_16V4Z 2
C95
1
0.47U_0603_10V7K
C94
2 0.22U_0603_10V7K 2
1 C96
1U_0402_6.3V4Z
2
C97
1U_0402_6.3V4Z
2
A
GM45R3@
2009/06/12
Issued Date
Compal Secret Data
2010/06/12
Deciphered Date
5
Title
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
11
of
44
+3VS_TVCRT_DACBG
C101
R81,R82,PN change to SM01000DR00
,footprint no change
+1.05VS_DPLLA
+1.05VS_AHPLL
F47
+1.05VS
2
1
KC FBM-L11-160808-121LMT
0603 1
1
2 0.1U_0402_16V4Z
2
Pin AD1
+1.5VS_PEG_BG
PCIe&DMI
R87
1
2
0_0603_5%
B27
A26
+3VS_TVCRT_DAC
5mA
VCCA_DAC_BG
B25
VSSA_DAC_BG
+1.05VS_DPLLA
F47
VCCA_DPLLA64.8mA
+1.05VS_DPLLB
L48
VCCA_DPLLB64.8mA
AD1
VCCA_HPLL 24mA
+1.05VS_MPLL
AE1
VCCA_MPLL 139.2mA
+1.8V_TXLVDS
J48
VCCA_LVDS
J47
VSSA_LVDS
L48
+1.8V_TXLVDS
LVDS
13.2mA
1
C118
1000P_0402_50V7K
Pin J48
GND to J47
414uA
+1.5VS_PEG_BG
AD48
VCCA_PEG_BG
+1.05VS_PEGPLL
AA48
VCCA_PEG_PLL
50mA
+1.05VS_PEGPLL
Pin AD48
0.1U_0402_16V4Z
PCIe&DMI
Pin AA48
+1.05VS
R88
1
2
0_0805_5%
DDR3
AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16
+1.05VS_A_SM
4.7U_0805_10V4Z
1
1
C124
C125
C126
2
2
2
10U_0805_10V4Z
1U_0402_6.3V4Z
+1.05VS_A_SM_CK
0.1U_0402_16V4Z
1
1
C133
C134
2
2.2U_0603_6.3V4Z
Pin AP28
AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23
VCC_TX_LVDS
2
2
0.01U_0402_25V4Z
M25
+1.5VS_QDAC
L28
VCCD_TVDAC
AF1
+1.05VS_DHPLL
+1.05VS_DHPLL
R98
+1.05VS_PEGPLL
AA47
+1.8V_LVDS
M38
L37
VCCD_HPLL
50mA
VCCD_PEG_PLL
PEG
60.31mA
1
2
0_0402_5%
C150
0.1U_0402_16V4Z
VCCD_LVDS_1
VCCD_LVDS_2
Pin AF1
BF21
BH20
BG20
BF20
+1.05VS
+1.05VS_PEGPLL
PCIe&DMI
L1
2
1
BLM18PG121SN1D_0603
0.1U_0402_16V4Z
1
R100
1_0805_1%
C152
2
2
1 C154
10U_0805_10V4Z
Pin AA47
C128
10U_0805_10V4Z
2 @
+1.8V
R91
1
2
0_0603_5%
1
LVDS
1
+1.8V_TXLVDS
C130
1000P_0402_50V7K
C131
10U_0805_10V4Z
Pin K47
C35
B35
A35
+3VS
+3VS
1
V48
U48
V47
U47
U46
+1.05VS
AH48
AF48
AH47
AG47
+1.05VS
D3
2 R93
1
1
2
+1.05VS
10_0603_5%
CH751H-40PT_SOD323-2
C137
0.1U_0402_16V4Z
Pin C35
B
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4
+1.05VS
PCIe&DMI
10U_0805_10V4Z
1
C144
C145
2
10U_0805_10V4Z
Pin V48
VTTLF1
VTTLF2
VTTLF3
VTTLF1
A8
VTTLF2
L1
AB2 VTTLF3
1
PCIe&DMI
+1.05VS
C147
C148
C149
0.47U_0603_10V7K 0.47U_0603_10V7K 0.47U_0603_10V7K
2
2
2
C151
0.1U_0402_16V4Z
Pin AH48
+1.8V_LVDS
+1.8V
R99
2
1
0_0603_5%
LVDS
1
C153
1U_0402_6.3V4Z
2
Pin M38
Compal Secret Data
2009/06/12
Issued Date
Deciphered Date
2010/06/12
5
C129
1
105.3mA
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
R90
1_0805_1%
10U_0805_10V4Z
2
VCC_HV_1
VCC_HV_2
VCC_HV_3
C127
0.1U_0402_16V4Z
+1.8V_TXLVDS
K47
+1.5V
R89
1
2
0_0805_5%
1
+1.5V_SM_CK
GM45R3@
DDR2
Pin BF21
VCCD_QDAC500uA
157.2mA
+1.05VS
C120
10U_0805_10V4Z
2 @
TV
HDA
35mA
+1.5VS_TVDAC
456mA
VCC_HDA
C143
Pin
L282
2
2 330U_6.3V_M_R15
+1.05VS_AXF
1782mA
DMI
C142
0.1U_0402_16V4Z
A32
B22
B21
A21
118.8mA
50mA
R94
1
2
0_0402_5%
R96
TV
2
1 0.01U_0402_25V4Z
0_0603_5% 1
1
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
VTTLF
C141
Pin M25
+1.5VS_QDAC
+1.5VS
D TV/CRT
C140
TV
VCCA_TV_DAC_1
VCCA_TV_DAC_2
LVDS
C139
@ 10U_0805_10V4Z
+1.5VS_TVDAC
0.1U_0402_16V4Z
1
1
C119
1U_0402_6.3V4Z
DDR2,667MHz,119.85mA
DDR2,800MHz,124mA
Pin B24
+3VS_TVCRT_DAC
C103
+1.05VS
R86
1
2
1 0_0603_5%
+1.05VS_AXF
+1.5V_SM_CK
VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8
B24
A24
321.35mA
C136
Intel: VTT 270U*1 ESR 12mOhm
Host Interface I/O and HSIO
SM CK
DDR3
Pin B22
79mA
+1.5VS
R95
2
1
0_0603_5% 1
HV
TV
C104
C105
C106
C107
0.47U_0603_10V7K
2.2U_0603_6.3V6K 4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
2
2
2
POWER
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
667MTs,24mA
800MTs,26mA
0.01U_0402_25V4Z
1
1
A CK
+1.05VS
R92
2
11
0_0603_5% 1
C155
1U_0402_6.3V4Z
C132
2
10U_0805_10V4Z 2
C135
0.1U_0402_16V4Z
AGTL+
NB I/O
Pin AR20
+3VS_TVCRT_DAC
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
667MTs,480mA
800MTs,720mA
C121
2
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
A25
+3VS_TVCRT_DACBG
+1.05VS_AHPLL
+1.05VS
FSB=1067Mhz,852mA
73mA
C122
0.1U_0402_16V4Z
C
U3H
+1.05VS_MPLL
2
1
MBK2012121YZF_0805
1
C117
1
2
C114
R85 0.5_0805_1%
10U_0805_10V4Z
Pin AE12
0.1U_0402_16V4Z
C116
C98
10U_0805_10V4Z
+1.05VS_DPLLB
R84
C115
4.7U_0805_10V4Z
GNDtoB25
R82
10U_0805_10V4Z
2
1
10U_FLC-453232-100K_0.25A_10%
1
1
1
C109 +
220U_B2_2.5VM
C112
C113
@
Pin
2
2
2
0.1U_0402_16V4Z
R83
+1.5VS
+1.05VS
R81
10U_0805_10V4Z
2
1
10U_FLC-453232-100K_0.25A_10%
1
1
1
C108 +
220U_B2_2.5VM
C110
C111
@
Pin
2
2
2
0.1U_0402_16V4Z
+1.05VS
Pin A25
C102
2
0.1U_0402_16V4Z
CRT
Pin B27
VTT
+1.05VS
R79
2
1
BLM18PG181SN1D_0603 1
PLL
C100
2
0.1U_0402_16V4Z
+3VS_TVCRT_DACBG
+3VS
A PEG A LVDS
C99
TV
0.01U_0402_25V4Z
1
1
AXF
+3VS_TVCRT_DAC
CRT
R80 1
0.01U_0402_25V4Z
2
0_0603_5% 1
1
A SM
+3VS_TVCRT_DACBG
Title
Crestline GMCH (6/7)-VCC

Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
12
of
44
VSS
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6
BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
BA16
VSS_235
AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
GM45R3@
VSS
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
VSS_351
VSS_352
VSS_353
VSS_354
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS NCTF
U3J
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
VSS SCB
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
NC
U3I
AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
U24
U28
U25
U29
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
BH48
BH1
A48
C1
A3
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
GM45R3@
Compal Secret Data
2009/06/12
Issued Date
2010/06/12
Deciphered Date
5
Title
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
13
of
44
<9> DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
1
CD6
2
RD5
10K_0402_5%
2
1
CD5
2.2U_0603_6.3V4Z
+3VS
0.1U_0402_16V4Z
DDR_A_D58
DDR_A_D59
RD3 1
2
10K_0402_5%
+0.75VS
205
G1
G2
206
1
2
1
+1.5V
DDRA_CLK1 <8>
DDRA_CLK1# <8>
DDR_A_BS1 <9>
DDR_A_RAS# <9>
DDRA_SCS0# <8>
DDRA_ODT0 <8>
RD4
DDRA_ODT1 <8>
1
0_0402_5%
+V_DDR3_DIMM_REF
1
1
CD16
DDR_A_DM7
A
DDR_A_MA2
DDR_A_MA0
CD15
DDR_A_D56
DDR_A_D57
DDR_A_MA6
DDR_A_MA4
0.1U_0402_16V4Z
DDR_A_D50
DDR_A_D51
Layout Note: Place these 4 Caps near Command

and Control signals of DIMMA
CD14
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_MA11
DDR_A_MA7
+
CD45 @
330U_6.3V_M_R15
+DDR_VREF_CA_DIMMA
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
Layout Note:
Place near JDDRH.203 & JDDRH.204
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
+0.75VS
close to JDDRH.126
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
10U_0805_6.3V6M
DDR_A_D48
DDR_A_D49
Layout Note:
Place near JDDRH
0.1U_0402_16V4Z
DDR_A_D42
DDR_A_D43
+1.5V
CD13
DDR_A_DM5
2
@ 0_0402_5%
0.1U_0402_16V4Z
DDR_A_D40
DDR_A_D41
DDRA_CKE1 <8>
RD6 1
DDR_A_MA14
10U_0805_6.3V6M
DDR_A_D34
DDR_A_D35
<BOM Structure>
DDR_A_D30
DDR_A_D31
10U_0805_6.3V6M
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_DQS#3
DDR_A_DQS3
10U_0805_6.3V6M
DDR_A_D32
DDR_A_D33
1K_0402_1%
DDR_A_D28
DDR_A_D29
10U_0805_6.3V6M
DDR_A_MA13
<8> DDRA_SCS1#
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
+V_DDR3_DIMM_REF
RD2
10U_0805_6.3V6M
<9> DDR_A_W E#
<9> DDR_A_CAS#
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
DDR_A_D22
DDR_A_D23
10U_0805_6.3V6M
DDR_A_MA10
<9> DDR_A_BS0
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
RD1
1K_0402_1%
DDR_A_DM2
0.1U_0402_16V4Z
<8> DDRA_CLK0
<8> DDRA_CLK0#
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR_A_D20
DDR_A_D21
CD12
<8> DDRA_CKE0
+1.5V
+1.5V
1U_0402_6.3V4Z
CD22
SM_DRAMRST# <8,15>
DDR_A_D14
DDR_A_D15
CD21
DDR_A_D26
DDR_A_D27
1U_0402_6.3V4Z
DDR_A_DM3
<9>
DDR_A_DM1
CD20
DDR_A_D24
DDR_A_D25
<9>
DDR_A_D18
DDR_A_D19
DDR_A_DM[0..7]
DDR_A_D12
DDR_A_D13
CD11
DDR_A_DQS#2
DDR_A_DQS2
<9>
DDR_A_MA[0..14]
1U_0402_6.3V4Z
DDR_A_D16
DDR_A_D17
<9>
DDR_A_D[0..63]
DDR_A_D6
DDR_A_D7
CD19
DDR_A_D10
DDR_A_D11
DDR_A_DQS#0
DDR_A_DQS0
CD10
DDR_A_DQS#1
DDR_A_DQS1
close to JDDRH.1
<9>
DDR_A_DQS#[0..7]
1U_0402_6.3V4Z
DDR_A_DQS[0..7]
CD18
DDR_A_D8
DDR_A_D9
DDR_A_D4
DDR_A_D5
CD9
DDR_A_D2
DDR_A_D3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CD8
DDR_A_DM0
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
CD7
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
CD4
2.2U_0603_6.3V4Z
CD2
2.2U_0603_6.3V4Z
CD1
0.1U_0402_16V4Z
DDR_A_D0
DDR_A_D1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DDR3 SO-DIMM A
REVERSE TYPE
JDDRH
+V_DDR3_DIMM_REF
CD3
0.1U_0402_16V4Z
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
A
DDR_A_D62
DDR_A_D63
PM_EXTTS# <8,15>
PM_SMBDATA <15,16,21,25>
PM_SMBCLK <15,16,21,25>
+0.75VS
Compal Secret Data
2009/06/12
Issued Date
Deciphered Date
2010/06/12
LOTES_AAA-DDR-111-K01
CONN@
4
Title
DDRII-SODIMM0
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
14
of
44
<9> DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
4
DDR_B_D58
DDR_B_D59
RD8 1
2
10K_0402_5%
1
1
CD25
2
1 RD9
2
10K_0402_5% +0.75VS
0.1U_0402_16V4Z
CD26
2.2U_0603_6.3V4Z
+3VS
205
G2
206
G1
DDRB_SCS0# <8>
DDRB_ODT0 <8>
+V_DDR3_DIMM_REF
DDRB_ODT1 <8>
RD7
1
0_0402_5%
+DDR_VREF_CA_DIMMB
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
Layout Note:
Place near JDDRL.203 & JDDRL.204
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
+0.75VS
close to JDDRL.126
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55
@2
10U_0805_6.3V6M
DDR_B_D48
DDR_B_D49
DDR_B_BS1 <9>
DDR_B_RAS# <9>
CD35
DDR_B_D42
DDR_B_D43
+1.5V
DDRB_CLK1 <8>
DDRB_CLK1# <8>
CD36
DDR_B_DM5
DDR_B_MA2
DDR_B_MA0
0.1U_0402_16V4Z
DDR_B_D40
DDR_B_D41
DDR_B_MA6
DDR_B_MA4
CD37
DDR_B_D34
DDR_B_D35
Layout Note: Place these 4 Caps near Command

and Control signals of DIMMB
0.1U_0402_16V4Z
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_MA11
DDR_B_MA7
CD38
Layout Note:
Place near JDDRL
0.1U_0402_16V4Z
DDR_B_D32
DDR_B_D33
+1.5V
2
@ 0_0402_5%
10U_0805_6.3V6M
<8> DDRB_SCS1#
DDRB_CKE1 <8>
RD10 1
DDR_B_MA14
10U_0805_6.3V6M
DDR_B_MA13
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_B_D30
DDR_B_D31
10U_0805_6.3V6M
<9> DDR_B_W E#
<9> DDR_B_CAS#
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
DDR_B_DQS#3
DDR_B_DQS3
10U_0805_6.3V6M
DDR_B_MA10
<9> DDR_B_BS0
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
DDR_B_D28
DDR_B_D29
0.1U_0402_16V4Z
<8> DDRB_CLK0
<8> DDRB_CLK0#
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DDR_B_D22
DDR_B_D23
CD34
<8> DDRB_CKE0
+1.5V
DDR_B_DM2
CD33
DDR_B_D20
DDR_B_D21
22U_0805_6.3V6M
DDR_B_D26
DDR_B_D27
SM_DRAMRST# <8,14>
DDR_B_D14
DDR_B_D15
1U_0402_6.3V4Z
CD44
DDR_B_DM3
DDR_B_DM1
CD43
DDR_B_D24
DDR_B_D25
<9>
DDR_B_D12
DDR_B_D13
1U_0402_6.3V4Z
DDR_B_D18
DDR_B_D19
<9>
DDR_B_MA[0..14]
CD41
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_DM[0..7]
DDR_B_D6
DDR_B_D7
CD32
DDR_B_D16
DDR_B_D17
<9>
1U_0402_6.3V4Z
DDR_B_D10
DDR_B_D11
DDR_B_DQS#0
DDR_B_DQS0
<9>
DDR_B_D[0..63]
CD42
DDR_B_DQS#1
DDR_B_DQS1
close to JDDRL.1
<9>
DDR_B_DQS#[0..7]
CD31
DDR_B_DQS[0..7]
1U_0402_6.3V4Z
DDR_B_D8
DDR_B_D9
DDR_B_D4
DDR_B_D5
CD40
DDR_B_D2
DDR_B_D3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CD29
CD30
DDR_B_DM0
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
22U_0805_6.3V6M
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
CD28
2.2U_0603_6.3V4Z
CD24
2.2U_0603_6.3V4Z
CD23
0.1U_0402_16V4Z
DDR_B_D0
DDR_B_D1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DDR3 SO-DIMM B
REVERSE TYPE
JDDRL
+V_DDR3_DIMM_REF
CD27
0.1U_0402_16V4Z
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
4
DDR_B_D62
DDR_B_D63
PM_EXTTS# <8,14>
PM_SMBDATA <14,16,21,25>
PM_SMBCLK <14,16,21,25>
+0.75VS
Compal Secret Data
2009/06/12
Issued Date
Deciphered Date
2010/06/12
TYCO_2-2013289-1
CONN@
B
Title
DDRII-SODIMM0
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
E
15
of
44
FSC
FSB
FSA
CLKSEL2
CLKSEL1
CLKSEL0
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
DOT_96 USB
MHz
MHz
266
100
33.3
14.318
96.0
48.0
133
100
33.3
14.318
96.0
48.0
200
100
33.3
14.318
96.0
48.0
R108
80mA
0.1U_0402_16V4Z
1
2
0_0805_5% 1
1
C213
C214
+1.05VS
2
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
1
1
1
C216
C217
C218
C215
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
+3VS
+3VS_CK505
+1.05VS_CK505
C219
R107
1
2
0_0805_5% 1
2
0.1U_0402_16V4Z
250mA
0.1U_0402_16V4Z
1
C207
C206
2
10U_0805_10V4Z
0.1U_0402_16V4Z
1
C209
C208
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C211
C210
2
0.1U_0402_16V4Z
C212
0.1U_0402_16V4Z
+3VS_CK505
U4
SDA
PM_SMBDATA <14,15,21,25>
SCL
10
PM_SMBCLK <14,15,21,25>
VDD_PCI
CPU_0
71
CLK_CPU_BCLK <4>
VDD_CPU
CPU_0#
70
CLK_CPU_BCLK# <4>
166
100
33.3
14.318
96.0
48.0
333
100
33.3
14.318
96.0
48.0
100
100
33.3
14.318
96.0
48.0
400
100
33.3
14.318
96.0
48.0
+1.05VS_CK505
Reserved
CLK_XTAL_OUT
55
place 22ohm for damping resistor

when loading is two device,If one
device use 33ohm
Routing the
trace at
least 10mil
Y1
CLK_XTAL_IN
1
2
2
2
14.318MHZ_16PF_7A14300083
C221
C220
22P_0402_50V8J
22P_0402_50V8J
1
1
<29> CLK_48M_CR
<21> CLK_48M_ICH
2 R131
1 22_0402_5%
1 R117
2 22_0402_5% CLK_FSA
FSB
CPU_BSEL1
2
R116
<5,8> CPU_BSEL0
CLK_FSA
1
2.2K_0402_5%
R111 1
2 33_0402_5%
CLK_14ICH
2
R109
<5,8> CPU_BSEL2
<21> CK_PW RGD
CLK_FSC
1
10K_0402_5%
0
1
0
1
CLK_EC
=
=
=
=
C854
33P_0402_50V8J
@
<30>
CLK_PCI_EC
62
VDD_SRC_IO
52
VDD_SRC_IO
R113 1
CLK_MCH_BCLK <7>
67
CLK_MCH_BCLK# <7>
VDD_CPU_IO
SRC_0/DOT_96
24
CLK_DREF_96M <8>
VDD_PLL3_IO
SRC_0#/DOT_96#
25
CLK_DREF_96M# <8>
23
VDD_IO
38
VDD_SRC_IO
20
REF_0/FS_C/TEST_
REF_1
NC
XTAL_IN
CLK_XTAL_OUT
XTAL_OUT
2CLK_EC
33_0402_5%
<19> CLK_PCI_ICH
R112 1
2CLK_ICH
33_0402_5%
C856
33P_0402_50V8J
@
CLK_DREF_SSC
29
CLK_DREF_SSC#
SRC_2
32
CLK_PCIE_ICH
SRC_2#
33
CLK_PCIE_ICH#
NB (96MHz)
NB_SSC (100MHz)
<8>
<19>
ICH-DMI
<19>
SRC_3
35
CLK_PCIE_SATA <20>
SRC_3#
36
CLK_PCIE_SATA# <20>
SRC_4
39
CLK_W LAN <25>
SRC_4#
40
CLK_W LAN# <25>
SATA
WLAN
PCI_1
14
PCI_2
15
PCI_3
16
PCI_4/SEL_LCDCL
17
PCIF_5/ITP_EN
18
VSS_PCI
VSS_REF
SRC_6
57
SRC_6#
56
SRC_7
61
CLK_MCH_3GPLL <8>
SRC_7#
60
CLK_MCH_3GPLL# <8>
3G_PLL
SRC_8/CPU_ITP
64
SRC8_LAN
R513 1
SRC_8#/CPU_ITP#
63
SRC8_LAN#
R514 1
SRC_9
44
SRC9_LAN
R511 1
@ 2
SRC_9#
45
SRC9_LAN#
R512 1
@ 2
SRC_10
50
SRC_10#
51
SRC_11
48
SRC_11#
47
CLK_LAN <26>
0_0402_5%
LAN
CLK_LAN# <26>
0_0402_5%
0_0402_5%
0_0402_5%
Reserve (Check layout)
+3VS
22
VSS_48
CLKREQ_3#
37
CLKREQ_SATA#
26
VSS_IO
CLKREQ_4#
41
CLKREQ_W LAN#
69
VSS_CPU
CLKREQ_6#
58
CLKREQ_6#
30
VSS_PLL3
CLKREQ_7#
65
CLKREQ_3GPLL#
34
VSS_SRC
CLKREQ_9#
43
CLKREQ_LAN#
59
VSS_SRC
SLKREQ_10#
49
CLKREQ_10#
42
VSS_SRC
CLKREQ_11#
46
CLKREQ_11#
73
THERMAL_PAD
USB_1/CLKREQ_A#
21
CLKREQ_SATA# <21>
CLKREQ_W LAN# <25>
CLKREQ_SATA#
CLKREQ_W LAN#
CLKREQ_6#
CLKREQ_3GPLL# <8>
CLKREQ_3GPLL#
CLKREQ_LAN#
CLKREQ_LAN# <26>
CLKREQ_10#
Reserve
CLKREQ_11#
2
R125
2
R124
2
R119
2
R118
2
R123
2
R126
2
R120
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
SLG8SP556VTR_QFN72_10X10
CLK_EC
R128
10K_0402_5%
GM
Compal Secret Data
2009/06/12
Deciphered Date
2010/06/12
Title
Clock Generator
Issued Date
A
<8>
NB
CKPWRGD/PD#
CLK_XTAL_IN
CLK_DDR
28
FS_B/TEST_MODE
PCI_STOP#
2 33_0402_5%
LCDCLK/27M
LCDCLK#/27M_SS
USB_0/FS_A
54
R122
10K_0402_5%
@
68
<21> H_STP_PCI#
1
1
PM
CLK_ICH
R127
10K_0402_5%
31
CPU_1
CPU_STOP#
+3VS
R121
10K_0402_5%
@
66
CPU
CPU_1#
53
SRC8/SRC8# (100MHz)
ITP/ITP# (266MHz)
Enable DOT96 & SRC1(UMA)
Enable SRC0 & 27MHz(DIS)
+3VS
VDD_PLL3
13
CLK_ICH
VDD_48
27
<21> H_STP_CPU#
R115 1
<31> CLK_PCI_DDR
19
11
close to U4 befor R115

EMI request 6/25
72
CPU_BSEL1
<5,8> CPU_BSEL1
VDD_REF
12
CLK_FSC
<21> CLK_14M_ICH
VDD_SRC
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:

G
Sheet
16
of
H
44
LCD/PANEL BD. Conn.

+LCD_VDD
+3VS
W=60mils
2
47K_0402_5%
C671
0.01U_0402_25V7K
<10> UMA_ENVDD
+LCD_VDD
W=60mils
Q17B
2N7002DW -T/R7_SOT363-6
C672
4.7U_0805_10V4Z
@
C673
0.1U_0402_16V4Z
R626
100K_0402_5%
Inrush current = 0A
Q18
AO3413_SOT23
2
1
1
R623
C853
0.1U_0402_16V7K
Q17A
2N7002DW -T/R7_SOT363-6
+3VS
R622
100K_0402_5%
6 2
R621
150_0603_5%
1.5A
+LCDVDD_R
2 L16
1
0_0805_5%
1
+LCD_VDD
1
C674
0.1U_0402_16V4Z
C675
4.7U_0805_10V4Z
C
+3VS_LVDS_CAM
CAM@
0.1U_0402_16V4Z
1
2
C766
0_0402_5% R837
1
L85
2
<19> USB20_P11
<19> USB20_N11
Camera
2
3
1
4
USB20_P11_R
USB20_N11_R
W=20mils
4
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
@ W CM2012F2SF-900T04_0805
2
CAM@
+3VS
CAM@
0_0603_5%
R104 1
2
1
0_0402_5% R841
<30>
UMA_LCD_TXOUT0+
UMA_LCD_TXOUT0UMA_LCD_TXOUT1+
UMA_LCD_TXOUT1UMA_LCD_TXOUT2+
UMA_LCD_TXOUT2UMA_LCD_TXCLK+
UMA_LCD_TXCLKBKOFF#_R
1
2
33_0402_5%
R137
BKOFF#
To prevent EC pin from damage
CAM@
2
R627
10K_0402_5%
1
3
JLVDS @
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
32
GND1
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1 R217
1 R204
@
INT_MIC_CLK <27>
INT_MIC_DATA <27>
+LCDVDD_R
+LCD_INV
B+
B
Rated Current MAX:600mA
ACES_88242-3001
2 0_0402_5%
2 0_0402_5%
INT_MIC_CLK
+3VS
L3 2
1
FBMA-L11-201209-221LMA30T_0805
C391
68P_0402_50V8J
<30> INVT_PW M
<10> NB_PW M
PACDN042Y3R_SOT23-3
UMA_LCD_EDID_CLK <10>
UMA_LCD_EDID_DATA <10>
INT_MIC_DATA
INVT_PW M_R
BKOFF#_R
@ D84
2
C676
0.1U_0402_25V6
INVT_PW M_R
Compal Secret Data
2009/06/12
Issued Date
Deciphered Date
2010/06/12
5
Title

NB9M GDDR2A
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
17
of
44
CRT CONNECTOR
D55
+5VS
D56
D57
D58
2
3
+3VS
If=1A
C679
@ 0.1U_0402_16V4Z
DAN217_SC59
@
DAN217_SC59
@
DAN217_SC59
@
+CRT_VCC_R
+CRT_VCC
F3
30mil
1
1
2
RB491D_SOT23-3
1.1A_6V_MINISMDC110F-2 1
JCRT
C681
L19
1
2
NBQ100505T-800Y_0402
CRT_G_L
L20
1
2
NBQ100505T-800Y_0402
CRT_B_L
C682
1
C683
CRT_DDC_DAT
CRT_G_L
HSYNC
CRT_B_L
C684
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
CRT_R_L
C685
+CRT_VCC
2.2P_0402_50V8C
C680
CRT_R_L
2.2P_0402_50V8C
2.2P_0402_50V8C
R672
2
1
150_0402_1%
R671
2
1
150_0402_1%
R670
2
1
150_0402_1%
<10> UMA_CRT_B
2.2P_0402_50V8C
<10> UMA_CRT_G
L18
1
2
NBQ100505T-800Y_0402
2.2P_0402_50V8C
<10> UMA_CRT_R
2.2P_0402_50V8C
VSYNC
CRT_DDC_CLK
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
G
G
16
17
ALLTO_C10532-11505-L_15P-T
@
+CRT_VCC
+CRT_VCC
1
L21
2
10_0402_5%
HSYNC
D_CRT_VSYNC
1
L22
2
10_0402_5%
VSYNC
1
C687
@
5
1
P
OE#
1
C688
@
Q19A
<10> UMA_CRT_DATA
Q19B
<10> UMA_CRT_CLK
R678
2.2K_0402_5%
2
+CRT_VCC
<10> UMA_CRT_VSYNC
R677
2.2K_0402_5%
U39
SN74AHCT1G125GW _SOT353-5
U38
SN74AHCT1G125GW _SOT353-5
D_CRT_HSYNC
1
C850
33P_0402_50V8K
2
@
+3VS
10P_0402_50V8J
10P_0402_50V8J
1
10K_0402_5%
5
1
2
R673
<10> UMA_CRT_HSYNC
2
0.1U_0402_16V4Z
P
OE#
1
C686
CRT_DDC_DAT
2N7002DW -T/R7_SOT363-6
CRT_DDC_CLK
2N7002DW -T/R7_SOT363-6
C689
C849
470P_0402_50V8J
@
33P_0402_50V8K
2 @
C690
470P_0402_50V8J
2 @
Compal Secret Data
2009/06/12
Issued Date
Deciphered Date
2010/06/12
A
Title
CRT\TV\LVDS
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
E
18
of
44
+3VS
U9B
D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
PCI
PCI_REQ#0
F1
G4
B6
A7
F13
F12
E6
F6
C/BE0#
C/BE1#
C/BE2#
C/BE3#
D8
B4
D6
A5
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
D3
E3
R1
C6
E4
C2
J4
A4
F5
D7
PLTRST#
PCICLK
PME#
C14
D4
R2
PCI_GNT#0 <21>
PCI_REQ#1
PCI_REQ#2
RP15
PCI_PIRQB#
PCI_PERR#
PCI_TRDY#
PCI_REQ#3
1
2
3
4
PCI_REQ#3
8
7
6
5
8.2K_0804_8P4R_5%
RP16
1
8
2
7
3
6
4
5
STRAP_A16 <21>
PCI_STOP#
PCI_DEVSEL#
PCI_FRAME#
PCI_REQ#1
8.2K_0804_8P4R_5%
RP17
1
8
2
7
3
6
4
5
PCI_IRDY#
PCI_PLOCK#
PCI_IRDY#
PCI_PIRQD#
PCI_REQ#2
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
CLK_PCI_ICH
8.2K_0804_8P4R_5%
PLT_RST# <8,25,26,30,31>
CLK_PCI_ICH <16>
@ 10P_0402_50V8J
+3VS
+3VS
RP18
1
2
3
4
C257
R179
2
1
@ 10_0402_5%
CLK_PCI_ICH
PCI_PIRQA#
PCI_PIRQF#
PCI_PIRQH#
PCI_REQ#0
8
7
6
5
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
J5
E1
J6
C4
8.2K_0804_8P4R_5%
RP19
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
ICH9-M ES_FCBGA676
ICH9R3@
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
H4
K6
F2
G2
PCI_PIRQE#
PCI_SERR#
PCI_PIRQG#
PCI_PIRQC#
1
2
3
4
8
7
6
5
8.2K_0804_8P4R_5%
For WLAN
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PCIE_IRX_C_LANTX_N3
PCIE_IRX_C_LANTX_P3
PCIE_ITX_C_LANRX_N3
PCIE_ITX_C_LANRX_P3
C262 2
C263 2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
PCIE_ITX_LANRX_N3
PCIE_ITX_LANRX_P3
J29
J28
K27
K26
PCIE_IRX_C_W LANTX_N4
PCIE_IRX_C_W LANTX_P4
PCIE_ITX_C_W LANRX_N4
PCIE_ITX_C_W LANRX_P4
C264 2
C265 2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
PCIE_ITX_W LANRX_N4
PCIE_ITX_W LANRX_P4
G29
G28
H27
H26
PERN4
PERP4
PETN4
PETP4
E29
E28
F27
F26
PERN5
PERP5
PETN5
PETP5
<26>
<26>
<26>
<26>
<25>
<25>
<25>
<25>
L29
L28
M27
M26
+3VALW
RP21
4 USB_OC#4
3 USB_OC#6
2 USB_OC#11
1 USB_OC#10
10K_0804_8P4R_5%
5
6
7
8
<21>
<21> ICH_SPI_MOSI
RP22
5
6
7
8
1
R183
1
R184
1
R187
SPI_CS#1
USB_OC#5
4
USB_OC#0
3
USB_OC#8
2
USB_OC#2
1
10K_0804_8P4R_5%
<23,30> USB_OC#0
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11
2 USB_OC#9
10K_0402_5%
2 USB_OC#3
10K_0402_5%
2 USB_OC#7
10K_0402_5%
Within 500 mils
USBBIAS
1
2
R186
22.6_0402_1%
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
D23
D24
F23
SPI_CLK
SPI_CS0#
SPI_CS1#GPIO58/CLGPIO6
D25
E23
SPI_MOSI
SPI_MISO
AG2
AG1
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
V27
V26
U29
U28
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_ITX_MRX_N3
DMI_ITX_MRX_P3
<8>
<8>
<8>
<8>
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
Y27
Y26
W29
W28
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_ITX_MRX_N2
DMI_ITX_MRX_P2
<8>
<8>
<8>
<8>
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB27
AB26
AA29
AA28
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_ITX_MRX_N1
DMI_ITX_MRX_P1
<8>
<8>
<8>
<8>
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD27
AD26
AC29
AC28
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_ITX_MRX_N0
DMI_ITX_MRX_P0
<8>
<8>
<8>
<8>
T26
T25
CLK_PCIE_ICH# <16>
CLK_PCIE_ICH <16>
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
C29
C28
D27
D26
N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3
Direct Media Interface
For LAN
PERN1
PERP1
PETN1
PETP1
PCI - Express
U9D
N29
N28
P27
P26
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#/GPIO44
OC9#/GPIO45
OC10#/GPIO46
OC11#/GPIO47
SPI
USB
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
AF29
AF28
AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2
DMI_IRCOMP
1
R180
2
24.9_0402_1%
USB20_N0
USB20_P0
USB20_N1
USB20_P1
<23>
<23>
<23>
<23>
USB20_N7 <25>
USB20_P7 <25>
USB20_N10
USB20_P10
USB20_N11
USB20_P11
+1.5VS
USB/B-Left
USB/B-Left
WiMax(WLAN)
<29>
<29> Card reader(3
<17>
<17> Int. Camera
IN 1)
USBRBIAS
USBRBIAS#
Compal Secret Data

2009/06/12
Issued Date
Deciphered Date
2010/06/12
4
Within 500 mils
ICH9-M ES_FCBGA676
ICH9R3@
Lane reversal
Title
ICH9M(1/4)-PCI
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
19
of
44
2
2
1
SHORT PADS
C274 1
1U_0402_6.3V6K
E25
GLAN_CLK
C13
LAN_RSTSYNC
F14
G13
D14
2
2
2 SM_INTRUDER#
<27> AZ_RST_HD#
C855
33P_0402_50V8J
@
R212 1
<21>
AZ_SDOUT
GLAN_COMPI
GLAN_COMPO
AZ_SYNC
AF6
AH4
HDA_BIT_CLK
HDA_SYNC
AZ_RST#
AE7
HDA_RST#
AF4
AG4
AH3
AE5
AZ_SDOUT
AZ_SDOUT
<23> SATA_IRX_C_DTX_N1
<23> SATA_IRX_C_DTX_P1
<23> SATA_ITX_DRX_N1
<23> SATA_ITX_DRX_P1
N7
AJ27
DPRSTP#
DPSLP#
AJ25
AE23
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
AG8
SATALED#
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
GATEA20 <30>
H_A20M# <4>
H_DPRSTP# <5,8,40>
H_DPSLP# <5>
FERR#
R195 1
H_FERR#
2 56_0402_5%H_FERR#
AJ26
CPUPWRGD
H_PW RGOOD <5>
IGNNE#
AF25
H_IGNNE#
INIT#
INTR
RCIN#
AE22
AG25
L3
H_INIT#
<4>
H_INTR
<4>
KB_RST# <30>
NMI
SMI#
AF23
AF24
KB_RST#
AH27
+3VS
+1.05VS
<4>
KB_RST#
R197 2 @
1 10K_0402_5%
2
<4>
<4>
1
2
R201
56_0402_5%
H_THERMTRIP#
H_STPCLK# <4>
AG26 THRMTRIP_ICH# 1
R208
TP12
AG27
PAD
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
AH11
AJ11
AG12
AF12
SATA_IRX_C_DTX_N4 <23>
SATA_IRX_C_DTX_P4 <23>
SATA_ITX_DRX_N4 <23> SATA
SATA_ITX_DRX_P4 <23>
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
AH9
AJ9
AE10
AF10
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
AH18
AJ18
AJ7
AH7
H_THERMTRIP#
2
54.9_0402_1%
+3VS
1
+1.05VS
R199
330_0402_5%
@
Q10
1 2SC2411K_SOT23
@
H_THERMTRIP# <4,8>
T5
D50
DAN202UT106_SC70-3
@
ODD
ENTRIP1_HW
<37>
ENTRIP2_HW
<37>
CLK_PCIE_SATA# <16>
CLK_PCIE_SATA <16>
SATARBIAS
R216
24.9_0402_1%
10mils width
less than
500mils
ICH9-M ES_FCBGA676
ICH9R3@
2
@ 10K_0402_5%
1
@ 56_0402_5%
1
56_0402_5%
H_FERR# <4>
+1.05VS
H_NMI
H_SMI#
1
R191
2
R192
2
R193
H_DPRSTP#
AD22
TP12
HDA_SDOUT
GATEA20
GATEA20
FERR#
STPCLK#
AG7
AE8
AH13
AJ13
AG14
AF14
A20GATE
A20M#
THRMTRIP#
AG5
AJ16
AH16
AF17
AG17
1ST HDD
B28
B27
2 33_0402_5%
SATA_LED#
SATA_LED#
2
10K_0402_5%
1
R215
+3VS
GPIO56
AZ_BITCLK
2 33_0402_5%
<27> AZ_SDIN0_HD
2 33_0402_5%
B10
LPC_FRAME# <30,31>
J3
J1
R209 1
GLAN_COMP
LAN_TXD_0
LAN_TXD_1
LAN_TXD_2
K3
LDRQ0#
LDRQ1#/GPIO23
<27> AZ_SYNC_HD
1 R198
2
24.9_0402_1%
LAN_RXD0
LAN_RXD1
LAN_RXD2
D13
D12
E13
FWH4/LFRAME#
FBMA-10-100505-301T
R200
R205 1
<27> AZ_BITCLK_HD
<27> AZ_SDOUT_HD
INTVRMEN
LAN100_SLP
J2
+1.5VS
close to U9A
befor R200
B22
A22
<21> ICH_INTVRMEN
<21> LAN100_SLP
<30,31>
<30,31>
<30,31>
<30,31>
1
SHORT PADS
C273 1
1U_0402_6.3V6K
2ICH_SRTCRST#
R196 1
1M_0402_5%
RTCRST#
SRTCRST#
INTRUDER#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
ICH_RTCRST#
A25
F20
C22
J1
ITPM Setting, near DDR Door

R194 1
20K_0402_5%
ICH_RTCRST#
ICH_SRTCRST#
SM_INTRUDER#
K5
K4
L6
K2
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
RTCX1
RTCX2
R190 1
20K_0402_5%
+RTCVCC
C23
C24
C272
15P_0402_50V8J
CMOS Setting, near DDR Door
U9A
ICH_RTCX1
ICH_RTCX2
LPC
CPU
32.768KHZ_12.5PF_Q13MC14610002
RTC
OSC
LAN / GLAN
OSC
NC
IHDA
NC
SATA
X1
R189
10M_0402_5%
2
1
C270
15P_0402_50V8J
2
1
+RTCBATT
D10
2
1
1
1
R16
2
1K_0402_5%
CHN202UPT SC-70
C271
0.1U_0402_16V4Z
+3VL
R16 locate around

RTC battery
+RTCVCC
@ JRTC
LOTES_AAA-BAT-054-K01
A
Compal Secret Data
2009/06/12
Issued Date
Deciphered Date
2010/06/12
5
Title
ICH9M(2/4)-LAN,IDELPC,RTC
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
20
of
44
+3VS
+3VS
2 4.7K_0402_5%
2 4.7K_0402_5%
+3VALW
R242 1
+3VS
R244 1
R245 1
10K_0402_5%
2
2 @ 8.2K_0402_5%
R246 1
+3VS
ACIN
R250 1
R251 1
+3VALW
1 R807
+3VS
SB_W AKE#
<16> H_STP_PCI#
<16> H_STP_CPU#
SERIRQ
EC_THERM#
10K_0402_5%
PM_CLKRUN#
THRM# not
used, 8.2K to <26> SB_W AKE#
<30,31> SERIRQ
10K PU to
<30> EC_THERM#
+3VS.
OCP#
ICH_ACIN
1
2
R248 330K_0402_5%
1
D12
+3VS
<30,36>
1K_0402_5%
2
2
2
8.2K_0402_5%
10K_0402_5%
EC_SMI#
EC_SCI#
100K_0402_5%
2HDD_DET#
T6
<4>
<30>
<30>
R253 1
R255 2
R257 2
+3VALW
8.2K_0402_5%
VGATE
<8,30,40> VGATE
+3VS
SB_W AKE#
SERIRQ
EC_THERM#
TP11
PAD
OCP#
ICH_ACIN
OCP#
EC_SMI#
EC_SCI#
HDMI_HPD
EC_SMI#
EC_SCI#
BT_DET#
2HDD_DET#
BT_DET#
1 @ 10K_0402_5%
100K_0402_5%
1
GPIO57
<16> CLKREQ_SATA#
+3VS
R809 2 100K_0402_5%
R744
CIR_EN#
CIR_EN#
HDMI_HPD
100K_0402_5%
GPIO57
Assert = iTPM Physical Presence Enable

De-assert = iTPM disable
**Only used in iAMT w/ME Firmware
Desktop Platform used only
CLGPIO5
Mobil Platform
GPIO57
ICH9M Strap Pin

+3VS
1
R258 @
2
1K_0402_5%
SB_SPKR
<27> SB_SPKR
<8> MCH_ICH_SYNC#
iTPM Physical Presence
ICH_SPI_MOSI
T7
T8
T9
PAD
PAD
PAD
ICH_TP3
TP8
TP9
TP10
SMBALERT#/GPIO11
A14
E19
STP_PCI#
STP_CPU#
L4
E20
M5
AJ23
CLKRUN#
WAKE#
SERIRQ
THRM#
D21
VRMPWRGD
A20
TP11
AG19
AH21
AG21
A21
C12
C21
AE18
K1
AF8
AJ22
A9
D19
L1
AE19
AG22
AF21
AH24
A8
M7
AJ24
B21
AH20
AJ20
AJ21
PM_SLP_S3# <30>
PM_SLP_S4# <30>
PM_SLP_S5# <30>
S4_STATE#/GPIO26
C10
S4_STATE#
PWROK
G20
ICH_PW ROK
PMSYNC#/GPIO0
A17
GPIO1
GPIO6
GPIO7
GPIO8
GPIO12
GPIO13
GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5
SPKR
MCH_SYNC#
TP3
TP8
TP9
TP10
DPRSLPVR/GPIO16
BATLOW#
SPI_MOSI
PWRBTN#
R3
D20
RSMRST#
CK_PWRGD
CLPWROK
1
R261
SB_SPKR
2
1K_0402_5%
SB_SPKR
2
@ 1K_0402_5%
PCI_GNT#0 <19>
2
@ 1K_0402_5%
SPI_CS#1 <19>
1
R267
2
@ 1K_0402_5%
0
0
1
1
CL_DATA0
CL_DATA1
F22
C19
CL_DATA0 <8>
CL_VREF0
CL_VREF1
C25 +CL_VREF0_ICH
A19
CL_RST0#
CL_RST1#
F21
D18
MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9
A16
C18
C11
C20
PCI_GNT#3
Low= A16 swap override Enable

High= Default* (Internal pull-up)
2
10K_0402_5%
2
C278
0.1U_0402_16V4Z
Mobile Platform used only

Desktop Platform used only
Low = Internal VR Disabled

High = Internal VR Enabled(Default)
Flash Descriptor Security Override Strap

GPIO33
Low= Descriptor Security override

High= Default* (Internal pull-up)
ICH8M LAN100 SLP Strap

(Internal VR for VccLAN1.05 and VccCL1.05)
DMI Termination Voltage

GPIO49 Low= Desktop used
High= Mobile* (Internal pull-up)
XOR Chain Entrance Strap

ICH_TP3
(Internal pull-up)
0
+3VS
R266
@ 1K_0402_5%
R268
ICH_TP3
@ 1K_0402_5%
AZ_SDOUT <20>
HDA_SDOUT
0
Description
RSVD
Enter XOR Chain
Normal Operation
Set PCIE port config bit 1
Deciphered Date
2010/06/12
3
(Default)
Compal Secret Data

2009/06/12
Issued Date
D68
POK
+3VALW
Low = Internal VR Disabled

ICH_LAN100_SLP High = Internal VR Enabled(Default)
R254
453_0402_1%
CL_RST#0 <8>
SUS_PW R_ACK 1
R256
SB_RSMRST#
<20>
LAN100_SLP <20>
RESERVED
SPI
PCI
LPC* (Default)
A16 Swap Override Strap
D66
R252
3.24K_0402_1%
Width:Spacing
12mil:12mil
SUS_PWR_ACK
ICH_INTVRMEN
RSMRST# circuit
<35,37>
ICH_INTVRMEN
+RTCVCC
+3VALW
EC_RSMRST# <30>
1
2
+3VALW
R243
4.7K_0402_5%
D11A
@
BAV99DW -7_SOT363
@
ICH_PW ROK
GPIO10
2
330K_0402_5%
2
@ 0_0402_5%
1 R275 @2
1K_0402_5%
+3VS
<8>
Internal VR Enable Strap

(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
1
R259
1
R260
+3VALW
<8,30>
CL_CLK0
Low= Disable
High= iTPM enable by MCH strap*
Low= *Default
High= "No Reboot"
ICH_PW ROK
B16
ICH9-M ES_FCBGA676
ICH9R3@
0
1
0
1
STRAP_A16 <19>
R6
2
@ 10K_0402_5%
1
8.2K_0402_5%
MMBT3906_SOT23-3
2
1
R249
@
2.2K_0402_5%
CK_PW RGD <16>

ICH_PW ROK
F24
B19
Boot BIOS Strap (Internal pull-up)
1
R265
R5
SLP_M#
PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction

1
R263
PBTN_OUT# <30>
D22
D11B
BAV99DW -7_SOT363
@
1
2
R247 0_0402_5%
SB_RSMRST#
CL_CLK0
CL_CLK1
No Reboot Strap (Internal pull-up)

+3VS
B13 ICH_LOW _BAT#
1
R235
2
R237
2 R239
1
0_0402_5%
1 Q11 3
SB_RSMRST#
1
2
R241
10K_0402_5%
PM_DPRSLPVR <8,40>
LAN_RST#
Internal TPM Strap(Internal pull-down)

<19>
M2
ICH_LOW _BAT#
<30> EC_LID_OUT#
+3VALW
SLP_S3#
SLP_S4#
SLP_S5#
C16
E16
G17
S4_STATE#
<30>
EC_LID_OUT#
EC_CLK
2
B
M6
<8> PM_SYNC#
P1
PM_CLKRUN#
SUSCLK
clocks
10K_0402_5%
SUS_STAT#/LPCPD#
SYS_RESET#
2
1
2
C276
@ 4.7P_0402_50V8C
2
1
2
C277
@ 4.7P_0402_50V8C
R4
G19
R240 1
<4> XDP_DBRESET#
RI#
XDP_DBRESET#
CLK_14M_ICH <16>
CLK_48M_ICH <16>
CLK14
CLK48
EC_LID_OUT#
F19
10K_0402_5%
ICH_RI#
BT_PW R# <25>
H1 CLK_14M_ICH
AF3 CLK_48M_ICH
1
R228
@ 10_0402_5%
CLK_48M_ICH
1
R229
@ 10_0402_5%
R238 1
CLK_14M_ICH
AH23
AF19
AE21
AD20
10K_0402_5%
LINKALERT#
10K_0402_5%
ME_EC_CLK1
10K_0402_5%
ME_EC_DATA1
10K_0402_5%
ICH_RI#
10K_0402_5% XDP_DBRESET#
SMB
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37
SATA
GPIO
2
2
2
2
2
SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1
+3VALW
1
1
1
1
1
2N7002DW -T/R7_SOT363-6
G16
A13
E17
C17
B18
Power MGT
R230
R232
R233
R234
R236
ICH_SMBCLK
3
Q4B
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ME_EC_CLK1
ME_EC_DATA1
SYS / GPIO
<14,15,16,25> PM_SMBCLK
+3VALW
U9C
Q4A
2N7002DW -T/R7_SOT363-64
for EMI request
R971
100K_0402_5%
BT@
ICH_SMBDATA
6
5
<14,15,16,25> PM_SMBDATA
R221 1
R224 1
MISC
GPIO
Controller Link
1 R223
1
R226
1
4.7K_0402_5% 2
4.7K_0402_5% 2
Title
ICH9M(3/4)-USB,GPIO,PCIE
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
21
of
44
U9F
1
C281
0.1U_0402_16V4Z
+3VS
+5VS
+ICH_V5REF
+ICH_V5REF_SUS
+ICH_V5REF
1
R269 1
100_0402_5%
+5VALW
C284
1U_0402_6.3V4Z
D14
1
+ICH_V5REF_SUS
2
1
R270
2
100_0402_5%
C289
1U_0402_6.3V4Z
1
+1.5VS_PCIE_ICH
L14
2
1
KC FBM-L11-201209-221LMAT_0805
+1.5VS
2.2U_0603_6.3V6K
1
1
C293
220U_6.3V_M
10U_0805_10V4Z
C294
2
For power consumption measurement

+1.5VS
C295
C296
2 10U_0805_10V4Z
2
+1.5VS_SATAPLL_ICH
L15 1
2
MBK1608121YZF_0603
C304
10U_0805_10V4Z
1
C305
1U_0402_6.3V4Z
2
6uA at G3 state
VCCRTC
V5REF
V5REF_SUS
2mA
VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]
1634mA
646mA
23mA VCCDMIPLL
48mA
2mA
VCC3_3[07]
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]
11mA
close to AE15
Symbol
S0
S3
close to AF11
VCCLAN1_05
VCC_1_05
VCCLAN3_3
VCCLAN3_3
VCCCL1_5
VCC_1_5_A
VCCCL3_3
VCCCL3_3
VCCCL1_05
VCC_1_05
VCCCL3_3
VCCCL3_3
close to AC9
+1.5VS
AC9
C314
VCCSUS1_5
VCCSUS1_05
VCC_1_5_A
VCCSUS3_3
VCC_1_05
VCCSUS3_3
VCCSUS3_3
C315
AC18
AC19
0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z
VCCSUS3_3
Internal voltage regulators power these wells inside the ICH9

and current for this rail is accounted for in the sourcing voltage
rail current requirements.
close to AC7
AC21
G10
G9
close to AC14
close to AJ5
AJ5
+1.5VS
1
C316
0.1U_0402_16V4Z
C317
0.1U_0402_16V4Z
VCCLAN1_05_INT_ICH
1
+1.5VS
A27
1
D28
D29
E26
E27
C323
0.1U_0402_16V4Z
2
+1.5VS
A26
1
C324
0.1U_0402_16V4Z
+3VS
VCCSUS1_5[2]
VCC1_5_A[09]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]
+1.5VS_DMIPLL_ICH
1
C285
2
+1.5VS
L13 1
2
MBK1608121YZF_0603
0.01U_0402_16V7K
C286
10U_0805_10V4Z
+1.05VS
R29
C287
4.7U_0805_10V4Z
W23
Y23
+1.05VS
AB23
AC23
1
C290
0.1U_0402_16V4Z
AG29
AJ6
AC10
AD19
AF20
AG24
AC20
C291
0.1U_0402_16V4Z
C297
B9
F9
G3
G6
J2
J7
K7
0.1U_0402_16V4Z
1
C298
0.1U_0402_16V4Z
2
close to AG24
0.1U_0402_16V4Z
1
C299
C300
0.1U_0402_16V4Z
2
close to AD19
close to AJ6
AJ4
1
AC8 TP_VCCSUS1_05_ICH_1
F17 TP_VCCSUS1_05_ICH_2
@
@
PAD
PAD
T10
T11
C306
0.1U_0402_16V4Z
AD8
F18
VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
VCC1_5_A[20]
VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]
VCCUSBPLL 11mA
VCC1_5_A[26]
VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]
VCCLAN1_05[1]
VCCLAN1_05[2]
VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCCL1_05
VCCCL1_5
C310
2
0.1U_0402_16V4Z
23mA
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
80mA
1mA
ICH9-M ES_FCBGA676
ICH9R3@
C309
0.1U_0402_16V4Z
AF1
+3VALW
1
1
C313
0.1U_0402_16V4Z
close to AF1 2
close to T1
T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7
VCCCL1_05_INT_ICH
VCCCL1_5_INT_ICH
1
G22
G23
78mA
VCCCL3_3[1]
VCCCL3_3[2]
+VCCSUS1_5_ICH_INT
1
A18
D16
D17
E22
A24
B24
+3VS
2
1
1
C320
1U_0402_6.3V4Z
C321
0.1U_0402_16V4Z
C319
0.1U_0402_16V4Z
2009/06/12
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]
H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25
A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29
ICH9-M ES_FCBGA676
ICH9R3@
Compal Secret Data
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
close to G22
close to G23
2010/06/12
Deciphered Date
5
C303
0.1U_0402_16V4Z
2
AJ3
VCC1_5_A[18]
VCC1_5_A[19]
VCCGLAN3_3
0.1U_0402_16V4Z
1
close to B9, G6, K7
C311
C312
0.022U_0402_16V7K 0.022U_0402_16V7K
2
2
VCCGLANPLL
C301
C302
0.1U_0402_16V4Z
2
2
+3VS
VCCLAN3_3[1]
VCCLAN3_3[2]
C292
4.7U_0805_10V4Z
+3VS
close to AG29
Issued Date
C283
0.1U_0402_16V4Z
VCC1_5_A[17]
GLAN POWER
C322
0.1U_0402_16V4Z
2
A10
A11
A12
B12
+3VS
1
AA7
AB6
AB7
AC6
AC7
AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29
1
C282
0.1U_0402_16V4Z
212mA
USB CORE
C318
0.1U_0402_16V4Z
AC12
AC13
AC14
U9E
+1.05VS
1
+3VALW
VCCSUS1_5[1]
ATX
AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10
S4/S5
VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCCPSUS
C308
1U_0402_6.3V4Z
VCCSUS1_05[1]
VCCSUS1_05[2]
ARX
1
C307
1U_0402_6.3V4Z
VCCHDA
VCCSUSHDA
A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
VCCSATAPLL
VCCPUSB
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
11mA
1342mA
AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15
+1.5VS
VCC_DMI[1]
VCC_DMI[2]
V_CPU_IO[1]
V_CPU_IO[2]
308mAVCC3_3[01]
VCC3_3[02]
47mA
AJ19
VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
2mA
VCCA3GP
+3VALW
AE1
AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25
D13
1
A6
CORE
1
C280
0.1U_0402_16V4Z
VCCP_CORE
1
C279
1U_0402_6.3V4Z
PCI
A23
+RTCVCC
Title
ICH9M(4/4)-POWER&GND
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
22
of
44
SATA HDD Conn.

+5VS
1.2A
1
C698
0.1U_0402_16V4Z
SATA ODD Conn

+5VS
Place closely JHDD SATA CONN.
C697
10U_0805_10V4Z
C699
0.1U_0402_16V4Z
Place components close to ODD CONN.
1.1A
1
C700
0.1U_0402_16V4Z
C721
C723
@
10U_0805_10V4Z 1U_0402_6.3V4Z
2
2
10U_0805_10V4Z
C722
1
C724
0.1U_0402_16V4Z
C725
0.1U_0402_16V4Z
JODD
JHDD
GND
A+
AGND
BB+
GND
24
23
GND
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
1
2
3
4
5
6
7
SATA_ITX_C_DRX_P1 C713 1
SATA_ITX_C_DRX_N1 C715 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_IRX_DTX_N1
SATA_IRX_DTX_P1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
C717 1
C719 1
SATA_ITX_DRX_N1 <20>
15
14
GND
GND
GND
A+
AGND
BB+
GND
1
2
3
4
5
6
7
DP
+5V
+5V
MD
GND
GND
8
9
10
11
12
13
SATA_ITX_C_DRX_P4_ODD
SATA_ITX_C_DRX_N4_ODD
SATA_IRX_DTX_N4_ODD
SATA_IRX_DTX_P4_ODD
+5VS
SANTA_206401-1_RV
CONN@
+3VS
+5VS
SATA_ITX_C_DRX_P4_ODD C733 1
SATA_ITX_C_DRX_N4_ODDC734 1
2
2
0.01U_0402_25V7K
0.01U_0402_25V7K
SATA_IRX_DTX_N4_ODD
SATA_IRX_DTX_P4_ODD
2
2
0.01U_0402_25V7K
0.01U_0402_25V7K
C735 1
C736 1
SATA_ITX_DRX_N4 <20>
<30>
W=60mils
1.4A
U42
+5VALW
1
2
3
4
USB_EN#
GND
IN
IN
EN#
OUT
OUT
OUT
FLG
+USB_VCCA
8
7
6
5
For EMI request

1
1000P_0402_50V7K
2
C693
USB_OC#0 <19,30>
G528_SO8
SANTA_191201-1
CONN@
this is temp. footprint
C752
4.7U_0805_10V4Z
2 @
USB Conn
+USB_VCCA
C84
+USB_VCCA
1
+
220U_6.3V_M
B
C63
C60
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
<BOM
0_0402_5%
2R843Structure>
1
C64
2
L87
VCC
DD+
GND
GND
GND
GND
GND
5
6
7
8
3
<19>
<19>
USB20_N1
USB20_P1
3
2
L86
2
PJDLC05_SOT23-3
JUSB2
USB20_N1_R
USB20_P1_R
D62 @
1
2
3
4
VCC
DD+
GND
GND
GND
GND
GND
5
6
7
8
ALLTOP C107L8-10405-L
PJDLC05_SOT23-3
<BOM
R838Structure>
0_0402_5%
<BOM
R839Structure>
0_0402_5%
W=60mils
@ W CM2012F2SF-900T04_0805
ALLTOP C107L8-10405-L
D65 @
USB20_N0_R
USB20_P0_R
USB20_N0
USB20_P0
JUSB1
1
2
3
4
<19>
<19>
1000P_0402_50V7K
W=60mils
@ W CM2012F2SF-900T04_0805
3 3
4 4
C61
<BOM
Structure>
0_0402_5%
2
1
R842
1000P_0402_50V7K
Compal Secret Data
2009/06/12
Issued Date
Deciphered Date
2010/06/12
5
Title
SATA-HDD/ODD/USB
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
23
of
44
POWER/B Connector
Check footprint and pin define
<30,32> ON/OFFBTN#
JPOW ER
1 1
2 2
3 3
4 4
5 G1
6 G2
ON/OFFBTN#
D79
PACDN042Y3R_SOT23-3
@
ACES_85201-0405N
CONN@
1
2
R755 300_0402_5%
+3VS
KSO17
KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
JKB4
2
1
CAPS_LED# R762 300_0402_5%
NUM_LED#
+3VS
CAPS_LED# <30>
NUM_LED# <30>
ACES_88170-3400
@
SMT1-05-A_4P
6
5
Check signal to TP module through FFC

JTouch
TP_SW L
TP_SW R
TP_SW L
SMT1-05-A_4P
D22
PACDN042Y3R_SOT23-3
@
1
2
3
4
5
6
G7
G8
7
8
P-TW O_161021-06021_6P-T
@
Compal Secret Data

2009/06/12
Issued Date
Deciphered Date
2010/06/12
4
TP_CLK
TP_DATA
SW 3
Left Switch
D21
PACDN042Y3R_SOT23-3
@
1
2
3
4
5
6
+5VS
<30>
<30>
JKB34
KSO16
JKB
TP_SW R
SW 2
KSO[0..17] <30>
Right Switch
6
5
<30>
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
KSO[0..17]
KSI[0..7]
1
C821
KSO17
1
C818
KSO2
1
C789
KSO1
1
C790
KSO0
1
C791
KSO4
1
C792
KSO3
1
C795
KSO5
1
C796
KSO14
1
C797
KSO6
1
C798
KSO7
1
C799
KSO13
1
C800
KSO8
1
C801
KSO9
1
C802
KSO10
1
C803
KSO11
1
C804
KSO12
1
C805
KSO15
1
C807
KSI7
1
C808
KSI2
1
C810
KSI3
1
C811
KSI4
1
C812
KSI0
1
C813
KSI5
1
C814
KSI6
1
C815
KSI1
1
C816
CAPS_LED#
1
C817
NUM_LED#
1
C819
KSO16
KSI[0..7]
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Touch/B Connector
please close to JKB1
KEYBOARD CONN
Title
USB/BT/FP/Int. Cam
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
24
of
44
+3V_W LAN
PCIe Mini Card-WLAN/WiMax
+3V_W LAN
Default
PJ18
2 2
1 1
+3VS
@ JUMP_43X79
+3V_W LAN
+1.5VS
<16> CLK_W LAN#

<16> CLK_W LAN
<19> PCIE_IRX_C_W LANTX_N4

<19> PCIE_IRX_C_W LANTX_P4
<19> PCIE_ITX_C_W LANRX_N4
<19> PCIE_ITX_C_W LANRX_P4
WLAN/ WiFi
+3V_W LAN
Debug card using
53
GND1
+3VALW
0.1U_0402_16V4Z
1
CM20
2
4.7U_0805_10V4Z
CM21
2
0.01U_0402_25V4Z
R959
100K_0402_5%
1
CM22
2
4.7U_0805_10V4Z
@ JUMP_43X79
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
54
XMIT_OFF# <30>
WLAN&BT Combo module circuits
PLT_RST# <8,19,26,30,31>
BT
on module
BT
on module
Enable
Disable
BT_CRTL
BT_PWR#
PM_SMBCLK <14,15,16,21>
PM_SMBDATA <14,15,16,21>
USB20_N7 <19>
USB20_P7 <19>
WiMax
**If +3V_WLAN is +3VS, please

remove D77
E51_TXD
E51_RXD
2 0_0402_5% E51_TXD_R
2 0_0402_5% E51_RXD_R
CM19
SUSP#
<30,33,39> SUSP#
FOX_AS0B226-S40N-7F
@
D77 @
2
BT_CTRL
<21>
<30>
<30>
R110 1
R106 1
BT_PW R#
BT_CTRL
<16> CLKREQ_W LAN#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
0.01U_0402_25V4Z
PJ19
CM18
JW LAN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
CM17
+1.5VS
0.1U_0402_16V4Z
1
Q47
BT@
S 2N7002_SOT23-3
2
G
Add BT_CTRL for WLAN & BT

Combo module at DVT
Issued Date
Compal Secret Data
2009/06/12
Deciphered Date
2010/06/12
Title
PCIe-WLAN/HDDVD/NAND/NEW
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
25
of
44
UL1
<19> PCIE_IRX_C_LANTX_P3
CL1
2 0.1U_0402_16V7K PCIE_IRX_LANTX_P3
22
<19> PCIE_IRX_C_LANTX_N3
CL2
2 0.1U_0402_16V7K
PCIE_IRX_LANTX_N3
23
HSON
17
18
<19> PCIE_ITX_C_LANRX_P3
<19> PCIE_ITX_C_LANRX_N3
1
RL19
<16> CLKREQ_LAN#
<8,19,25,30,31>
+3V_LAN
1
RL3
2 SB_W AKE#
10K_0402_5%
HSIP
HSIN
EECS/SCL
EEDI/SDA
30
32
CLKREQB
MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3
1
2
4
5
7
8
10
11
DVDD10
DVDD10
DVDD10
13
29
41
PERSTB
19
20
REFCLK_P
REFCLK_N
LAN_X1
43
CKXTAL1
LAN_X2
44
CKXTAL2
28
LANWAKEB
26
ISOLATEB
DVDD33
DVDD33
27
39
14
15
38
NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT
AVDD33
AVDD33
AVDD33
AVDD33
12
42
47
48
33
ENSWREG
34
35
VDDREG
VDDREG
SB_W AKE#
<21> SB_W AKE#

+3VS
31
37
40
25
CLK_LAN
CLK_LAN#
1 CLKREQ_LAN#
10K_0402_5%
0_0402_5% 16
PLT_RST#
<16>
<16>
2
RL8
LED3/EEDO
LED1/EESK
LED0
HSOP
ISOLATEB
+3V_LAN
RL6
1K_0402_1%
1 RL22
RL22 need always pull-high
for RTL8105E Efuse mode
ISOLATEB
2 1K_0402_5%
ENSW REG
+LAN_VDDREG
RL7
15K_0402_5%
2
1
RL5
2
2.49K_0402_1%
46
RSET
24
49
GND
PGND
LL1,CL13 will be changed to

2.2uH&4.7uF after EVT test
RL2
RL1
1 10K_0402_5%
1 10K_0402_5%
2
2
21
AVDD10
AVDD10
AVDD10
AVDD10
3
6
9
45
REGOUT
36
Layout Note: LL1 must be

8105E_VB@
within 200mil to Pin36,
CL13
CL13,CL9 must be within 4.7U_0603_6.3V6K
200mil to LL1
+LAN_REGOUT: Width =60mil
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-
+LAN_VDD10
+LAN_VDD10
+3V_LAN
<30> W OL_EN
0_0402_5%
RL12
0_0402_5%
CL9
0.1U_0402_16V4Z
1
8105E_VB@
+3V_LAN
CL17
0.1U_0402_16V4Z
1
+LAN_VDD10
0.1U_0402_16V4Z
Close to Pin 21
0.1U_0402_16V4Z
+LAN_EVDD10
0.1U_0402_16V4Z
+LAN_VDD10
0.1U_0402_16V4Z
+3V_LAN
LAN_X2
CL28
4.7U_0603_6.3V6K
8105E_VB@
CL29
0.1U_0402_16V4Z
1 8105E_VB@
CL26
27P_0402_50V8J
1
1
LAN Conn.
JLAN
8105E_VB@
7
6
8105E_VC@
5
4
1
CL27
27P_0402_50V8J
Need to change to non-LED type
25MHZ_20PF_7A25000012
2
CL19
2
CL20
2
CL21
2
CL22
2
2
1
0_0603_5%
LL3
8105E_VB@
+LAN_REGOUT
RJ45_MIDI1-
+LAN_VDDREG
LAN_X1
CL19,CL20,CL21,CL22 close to
Pin 3,13,29,45
ENSW REG
RL23
0_0402_5%
0.1U_0402_16V4Z
+3V_LAN
YL1
2
CL4
2
CL5
2
CL6
2
CL7
0.1U_0402_16V4Z
8105E_VC@
RL4
0_0402_5%
0.1U_0402_16V4Z
+LAN_EVDD10
1
LL2
CL18
1U_0402_6.3V4Z
UL1
ISOLATEB
@
RL11
0.1U_0402_16V4Z
RTL8105E-GR QFN _6X6

8105E_VB@
<30,33> W OL_EN#
+3V_LAN
+LAN_REGOUT
8105E_VB@
1
2
2.2UH +-5% NLC252018T-2R2J-N
2
0_0603_5%
EVDD10
CL4,CL5,CL6,CL7 close to
Pin 27,39,47,48
+LAN_VDD10
LL1
RJ45_MIDI1+
RJ45_MIDI0-
RJ45_MIDI0+
PR4PR4+
PR2PR3PR3+
3
PR2+
PR1PR1+
SHLD1
SHLD2
9
10
SANTA_130452-C
@
UL3
LAN_MDI1+
LAN_MDI1-
Place these components

colsed to LAN chip
1
CL35
0.1U_0402_25V4K
16
15
14
13
12
11
10
9
RJ45_MIDI0+
RJ45_MIDI0-
RJ45_MIDI1+
RJ45_MIDI1-
CL42
2
1000P_0402_50V7K
1
CL41
2
1000P_0402_50V7K
1
RJ45_GND
1
RL15
2
75_0402_1%
LANGND
2
D69
1
RL13
2
75_0402_1%
PJDLC05_SOT23-3
1
CL37
120P_0402_50V8J
CL38 @
4.7U_0603_6.3V6K
CL34
0.1U_0402_25V4K
place near pin 3 and pin 6
Compal Secret Data

2009/01/23
Issued Date
2010/01/23
Deciphered Date
A
RJ45_GND
CL35 and CL34 for EMI request
1000P_1808_3KV7K
1
CL36
LFE8456E-R
TX+
TXCT
NC
NC
CT
RX+
RX-
TD+
TDCT
NC
NC
CT
RD+
RD-
1
2
3
4
5
6
7
8
LAN_MDI0+
LAN_MDI0-
Title

RTL8105E 10/100 LAN
Size
Document Number
Custom
Date:
Rev
0.1
PWWAA LA6841P M/B
Sheet
E
26
of
44
Codec
600 mA
+PVDD1
2
0.1U_0402_16V4Z
CA2
+1.5VS
D
@
2
RA20 0_0603_5%
CA1
+DVDD_IO
RA1
2
1
0_0603_1%
CA8
2
10U_0805_10V4Z
EC Beep
RA7
1
2
47K_0402_5%
<30> EC_BEEP#
RA11
+PVDD2
1
CA61
0.1U_0402_16V4Z
35 mA
0.1U_0402_16V4Z
2
+AVDD
CA7
10U_0805_10V4Z
2
2
68 mA
place close to chip
+3VS_DVDD
10U_0805_10V4Z
2
2
place close to chip

+3VS
Beep sound
+5VS
1
2
0_0603_5%
@
CA63
0.1U_0402_16V4Z
1
1
CA62
2
10U_0805_10V4Z
+5VS
PCI Beep
CA58
@
2
10U_0805_10V4Z
RA3
10U_0805_10V4Z 0.1U_0402_16V4Z 1
2
@
0_0603_5%
CA13
1
2
RA8
1
2
47K_0402_5%
<21> SB_SPKR
MONO_IN
0.1U_0402_16V4Z
+5VS
2
RA19 0_0603_5%
CA43
CA56
2
10U_0805_10V4Z
JA1
JUMP_43X39
0.1U_0402_16V4Z
1
1
CA44
+3VS
RA2
1
2
0_0603_5%
0.1U_0402_16V4Z
1
1
CA57
CA23
1
2
4.7U_0805_10V4Z
<28> MIC1_R_R
1
CA29
Int. Mic
<17> INT_MIC_DATA
<17> INT_MIC_CLK
INT_MIC_DATA
INT_MIC_CLK
1
CA83
27P_0402_50V8J
RA46
FBMA-10-100505-301T
<30> EC_MUTE#
EC_MUTE#
1
RA45
1
CA12
MIC1_L
MIC1_R
16
17
MIC2_L
MIC2_R
MONO_IN
2
100P_0402_50V8J
EC control EC_MUTE# behavior:

High-state / low-state
1
2
CA15
2.2U_0603_6.3V4Z
CA51 1
+MIC1_VREFO_L
2 0.1U_0603_50V7K
CA47 1
2 0.1U_0603_50V7K
CA48 1
2 0.1U_0603_50V7K
CA49 1
2 0.1U_0603_50V7K
CA50 1
2 0.1U_0603_50V7K
1
RA18
Sense Pin
GPIO1/DMIC_CLK
SENSE A
18
SENSE B
RA4
RA5
SPKL+
SPKL-
<28>
<28>
SPKR+
SPKR-
<28>
<28>
75_0402_1%
75_0402_1%
HP_L
HP_R
place close to chip
<28>
<28>
CA18
0.1U_0402_16V4Z
place close to chip
AZ_SYNC_HD
<20>
BCLK
AZ_BITCLK_HD
<20>
SDATA_IN
EAPD
47
SPDIFO
48
MONO_OUT
20
MIC2_VREFO
29
MIC1_VREFO_R
LDO_CAP
30
28
AZ_SDOUT_HD <20>
AZ_SDIN0_HD_R
2
RA6
1
33_0402_5%
AZ_SDIN0_HD
@
1
2
1
R746 10_0402_5%
CA80
+3VS
close to Audio Codec(UA1) for EMI

R222
4.7K_0402_5%
2
22P_0402_50V8J
@
AZ_SYNC_HD
CA81
22P_0402_50V8J
@
<20>
AZ_RST_HD#
CA82
22P_0402_50V8J
place close to chip

+MIC1_VREFO_R CA28 10U_0805_10V4Z
1
2
CBP
35
CBN
VREF
27
AC_VREF
31
MIC1_VREFO_L
JDREF
19
AC_JDREF2 RA9
PVSS2
PVSS1
DVSS2
DVSS1
CPVEE
34
AVSS1
AVSS2
26
37
+MIC1_VREFO_R
1
CA14
+MIC1_VREFO_L
1 20K_0402_1%
1
2
2.2U_0603_6.3V4Z
CA17
CA16
10U_0805_10V4Z
2
2 @
0.1U_0402_16V4Z
ALC259-GR_QFN48_7X7
@
CA37
1U_0402_6.3V4Z
@
CA36
1U_0402_6.3V4Z
place close to chip
DGND
AGND
2
0_0603_5%
Impedance
Codec Signals
Function
39.2K
PORT-I (PIN 32, 33)
Headphone out
20K
PORT-B (PIN 21, 22)
Ext. MIC
10K
PORT-C (PIN 23, 24)
place close to chip

<28> MIC_SENSE
SENSE A
RA12
10K_0402_5%
10
36
43
42
49
7
CA6
SYNC
SDATA_OUT
RESET#
13
38
HP_OUT_L
HP_OUT_R
32
33
GPIO0/DMIC_DATA
PCBEEP
AVDD2
25
AVDD1
39
46
PVDD2
SPK_OUT_R+
SPK_OUT_R-
45
44
12
SENSE_A
40
41
11
CA5
AZ_BITCLK_HD
EC_MUTE#
4 PD#
<20> AZ_RST_HD#
4.7K_0402_5%
LINE2_L
LINE2_R
21
22
CA4
4.7U_0805_10V4Z
2
<28> MIC1_R_L
2
2
2
2
10U_0805_10V4Z 0.1U_0402_16V4Z
SPK_OUT_L+
SPK_OUT_L-
LINE1_L
LINE1_R
CA3
Ext. Mic
14
15
PVDD1
1
DVDD
23
24
DVDD_IO
1
UA1
<28>
5.1K
NBA_PLUG
2
RA10
1
20K_0402_1%
RA21
39.2K_0402_1%
SENSE_A
(PIN 48)
39.2K
SENSE B
PORT-E (PIN 14, 15)
20K
PORT-F (PIN 16, 17)
10K
PORT-H (PIN 20)
Int. MIC
Compal Secret Data
2009/01/23
Issued Date
Deciphered Date
2010/01/23
5
Title
HD CODEC ALC272
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
27
of
44
Speaker Connector
Ext. Mic
RA31
1K_0402_5%
2
1
<27> MIC1_R_L
placement near Audio Codec UA1
<27>
SPKR+
SPKR+
RA30
2
1
0_0603_5%
2
1
1K_0402_5%
RA22
<27> MIC1_R_R
2
RA32
1
2.2K_0402_5%
MIC1_L
2
RA33
1
2.2K_0402_5%
+MIC1_VREFO_L
MIC1_R
+MIC1_VREFO_R
SPK_R1
CA25
@ 10U_0805_10V4Z
2
1
CA26
@ 10U_0805_10V4Z
2
1
0_0603_5%
CA27
1U_0402_6.3V4Z
@
RA34
RA35
2
1
0_0603_5%
SPK_L1
CA19
@ 10U_0805_10V4Z
2
1
CA20
@ 10U_0805_10V4Z
RA36
2
2
1
0_0603_5%
SPK_L2
HeadPhone/LINE Out JACK

JLINE
@ DA4
PJDLC05_SOT23-3
3
2
JSPK
SPK_L1
SPK_L2
SPK_R1
SPK_R2
1
2
3
4
@ DA5
PJDLC05_SOT23-3
3
<27> NBA_PLUG
<27>
HP_R
<27>
HP_L
LA6 1
2 HP_R_L
KC FBM-L11-160808-121LMT 0603
LA7 1
2 HP_L_L
KC FBM-L11-160808-121LMT 0603
1
2
3
4
3
6
2
1
CA45
100P_0402_50V8J
CA46
100P_0402_50V8J
CA11 @
2
0.1U_0402_16V4Z
DA6 @
PJDLC05_SOT23-3
1
2
10
9
8
7
FOX_JA63331-B39S4-7F
CONN@
1
3
1
ACES_85204-0400N
@
For EMI
Ext.MIC/LINE IN JACK
JEXMIC
5
4
<27> MIC_SENSE
MIC1_R
MIC1_L
LA8 1
2 MIC1_L_R
KC FBM-L11-160808-121LMT 0603
LA9 1
2 MIC1_L_L
KC FBM-L11-160808-121LMT 0603
3
6
2
1
3
1
2
CA41
100P_0402_50V8J
CA42
100P_0402_50V8J
10
9
8
7
FOX_JA63331-B39S4-7F
CONN@
DA7 @
PJDLC05_SOT23-3
1
2
6
3
SPKL-
SPKL-
CA24
1U_0402_6.3V4Z
@
<27>
7
8
GND
GND
SPKL+
SPK_R2
1
2
6
3
SPKL+
<27>
SPKR-
SPKR-
7
8
GND
GND
<27>
CA21
2
0.1U_0402_16V4Z
For EMI
Issued Date
Compal Secret Data
2009/06/12
Deciphered Date
2010/06/12
Title
AUDIO AMP/MIC/SPK/VR
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
28
of
44
@
CC2
100P_0402_50V8J
2
1
D
RC1
6.19K_0402_1%
2
1
2
0_0603_5%
1
1
2 0_0402_5%
2 0_0402_5%
+VCC_3IN1
CC1
4.7U_0805_10V4Z
CC3
0.1U_0402_16V4Z
+V1_8
CC4
1U_0402_6.3V4Z
SDW P_MSCLK_R
1
RC24
SDW P_MSCLK
2
0_0402_5%
CC10
10P_0402_50V8J
@
DM
DP
4
5
6
3V3_IN
CARD_3V3
V18
XD_CD#
8
9
10
11
12
SD_DATA1
SD_DATA0
REFE
2
3
SP1
SP2
SP3
SP4
SP5
EPAD
1
RC4
R63
R62
<19> USB20_N10
<19> USB20_P10
+3VS_CR
+3VS
UC1
RTS5138@
25
GPIO0
17
CLK_IN
24
XD_D7
23
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6
22
21
20
19
18
16
15
14
13
CLK_48M_CR
CLK_48M_CR <16><
48MHz >
SD_DATA2_MS_DATA5
MS_DATA1_SD_DATA3
SDCMD
MS_DATA2_SDCLK
1
RC22
2
0_0402_5%
SDCD#
MS_DATA2_SDCLK_R
1 CC9
10P_0402_50V8J
@
RTS5138-GR_QFN24_4X4
2
UC1
For EMI request

For EMI request
RTS5137@
for EMI request

< 2 in 1 Card Reader >
1
CLK_48M_CR
JREAD
MS_DATA1_SD_DATA3
SDCMD
D0
D1
D2
WP
CD
7
8
9
10
11
SD_DATA0
SD_DATA1
SD_DATA2_MS_DATA5
SDW P_MSCLK_R
SDCD#
GND1
GND2
GND3
GND4
12
13
14
15
R748
@ 10_0402_5%
1
2
3
4
5
6
D3
CMD
VSS1
VDD
CLK
VSS2
+VCC_3IN1
MS_DATA2_SDCLK_R
CC6
0.1U_0402_16V4Z
C785
@ 22P_0402_50V8J
CC5
1U_0402_6.3V4Z
TAITW _PSDAT3-09GLAS1N14N @
Compal Secret Data
2009/10/01
Issued Date
Deciphered Date
2010/10/01
5
Title

RTS5138 Card Reader
Size
Document Number
Custom
Date:
Rev
0.1
PWWAA LA6841P M/B
Sheet
1
29
of
44
+3VL
+3VL
C774
C775
1000P_0402_50V7K1000P_0402_50V7K
1
for EMI request
EC_SMI#
VCC
VCC
VCC
VCC
VCC
VCC
U43
CLK_PCI_EC
D
R738
@ 10_0402_5%
2
1
C778
@ 22P_0402_50V8J
1
2
3
4
5
7
8
10
<20> GATEA20
<20> KB_RST#
<21,31> SERIRQ
<20,31> LPC_FRAME#
<20,31> LPC_AD3
<20,31> LPC_AD2
<20,31> LPC_AD1
<20,31> LPC_AD0
CLK_PCI_EC 12
13
ECRST#
37
20
38
<16> CLK_PCI_EC
<8,19,25,26,31> PLT_RST#
2
C780
<21>
R739
47K_0402_5%
2
1
ECRST#
EC_SCI#
RN3
100K_0402_5%
1
0.1U_0402_16V4Z
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
77
78
79
80
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
+3VL
1
R595
1
R596
2
47K_0402_5%
2
47K_0402_5%
KSO1
KSO2
to avoid EC entry ENE test mode
<24>
<24>
KSI[0..7]
KSI[0..7]
KSO[0..17]
KSO[0..17]
RP23
1
2
3
4
+3VL
+3VS
8
7
6
5
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
<35>
<35>
<4>
<4>
2.2K_8P4R_5%
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
<21> PM_SLP_S3#
<21> PM_SLP_S5#
<21> EC_SMI#
<26>
W OL_EN
<8> MCH_TSATN_EC#
<17> INVT_PW M
<4> FAN_SPEED1
<25> E51_TXD
<25> E51_RXD
<24,32> ON/OFFBTN#
<32> PW R_LED#
<24> NUM_LED#
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
68
70
71
72
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
83
84
85
86
87
88
AD Input
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
PS2 Interface
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
97
98
99
109
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
119
120
126
128
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
73
74
89
90
91
92
93
95
121
127
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
100
101
102
103
104
105
106
107
108
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
110
112
114
115
116
117
118
V18R
124
SPI Flash ROM
GPIO
SM Bus
GPI
@ 10M_0402_5%
2
100P_0402_50V8J
AGND
BATT_TEMPA <35>
ADP_I
ADP_V
<36>
<36>
+5VS
TP_CLK
1
4.7K_0402_5%
TP_DATA
1
4.7K_0402_5%
EN_DFAN1 <4>
IREF
<36>
CHGVADJ <36>
TP_CLK
TP_DATA
1
R749
2
R743
2
R262
D64
ACIN_D
ACIN
<21,36>
<31>
ENBKL
EC_SI_SPI_SO <31>
EC_SO_SPI_SI <31>
SPI_CS#
1
R766
1
2
R742 330K_0402_5%
VGATE
<8,21,40>
W OL_EN# <26,33>
2
0_0402_5%
LID_SW #
2
47K_0402_5%
+3VL
TP_CLK <24>
TP_DATA <24>
LID_SW #
+3VALW
2
R740
2
R741
SYSON
1
4.7K_0402_5%
VR_ON
1
10K_0402_5%
EC_MUTE# <27>
USB_EN# <23>
VGATE
2
100P_0402_50V8J
2
100P_0402_50V8J
<31>
1
R745
SPI_CLK
1
R747
C857
33P_0402_50V8J
@
2
0_0402_5%
UMA_ENBKL <10>
<31>
2
100K_0402_5%
FSTCHG <36>
BATT_FULL_LED# <32>
CAPS_LED# <24>
BATT_CHG_LOW _LED# <32>
SYSON
VR_ON
ACIN_D
SYSON
VR_ON
<38,39>
<40>
EC_RSMRST# <21>
EC_LID_OUT# <21>
EC_ON
<32,37>
PM_PW ROK
BKOFF#
<17>
XMIT_OFF# <25>
ENBKL
PM_SLP_S4# <21>
EC_THERM# <21>
SUSP#
<25,33,39>
PBTN_OUT# <21>
USB_OC#0 <19,23>
ICH_PW ROK
1
R231
1
R264
PM_PW ROK
+3VS
+EC_V18R
C782
4.7U_0805_10V4Z
KB926QFE0_LQFP128_14X14
1
C777
VGATE
PM_PW ROK
1
R752@
2
10K_0402_5%
2
10K_0402_5%
2
0.1U_0402_16V4Z
ICH_PW ROK
<8,21>
U5
NC7SZ08P5X_NL_SC70-5
2
0_0402_5%
To reduce CMOS dischage fail rate
Compal Secret Data
2009/06/12
Issued Date
Deciphered Date
2010/06/12
32.768KHZ_12.5PF_Q13MC14610002
5
2
100P_0402_50V8J
C450
Y4
18P_0402_50V8J
OSC
NC
OSC
NC
18P_0402_50V8J
C449
<34,36>
1
1
1
A
2CRY2
ACOFF
BATT_TEMPA
R389
CRY1
C451
18P_0402_50V8J
R624
100K_0402_5%
XCLK1
XCLK0
69
122
123
GND
GND
GND
GND
GND
R97
<21> EC_CLK
R101 1
2 0_0402_5%
2 0_0402_5%
@
2 0_0402_5%
1
11
24
35
94
113
R102 1
BATT_TEMPA
1
C776
ACIN_D
1
C779
EC_BEEP# <27>
SPI Device Interface
@
CRY1
CRY2
21
23
26
27
63
64
65
66
75
76
DA Output
1
C783
2
100P_0402_50V8J
@
PWM Output
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
1
C781
KB_RST#
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
+3VL
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
1
C784
0.1U_0402_16V4Z
C773
2
2
0.1U_0402_16V4Z
PLT_RST#
67
C772
2
2
0.1U_0402_16V4Z
Reserve for EMI test

C769
1
2
0.1U_0402_16V4Z
1
2
AVCC
0.1U_0402_16V4Z
1 C771
1
C770
9
22
33
96
111
125
Title
ENE-KB926 RevD2
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
30
of
44
Lid SW
SPI Flash (16Mb*1)
LPC Debug Port

Please place the PAD under DDR DIMM.
+3VALW
20mils
U47
8
2
<30> SPI_CLK
<30> EC_SO_SPI_SI
VSS
4
2
HOLD
<30> SPI_CS#
VCC
VOUT
C822
0.1U_0402_16V4Z
H1
+3VS
LID_SW #
<30>
PLT_RST# <8,19,25,26,30>
<20,30> LPC_AD3
LPC_AD2 <20,30>
<20,30> LPC_AD1
LPC_AD0 <20,30>
10
CLK_PCI_DDR
1
C823
10P_0402_50V8J
<21,30> SERIRQ
1
2
R761 0_0402_5%
<20,30> LPC_FRAME#
EC_SI_SPI_SO <30>
<16>
0.1U_0402_16V4Z
VDD
C786
GND
U48
APX9132ATI-TRL_SOT23-3
+3VL
@ DEBUG_PAD
R764
22_0402_5%
MX25L1605DM2I-12G_SO8-200mil
SPI_CLK
R953 1
2
33_0402_5%
2
1
C852
2
33P_0402_50V8J
1
reserve for EMI, close to U46
C820
22P_0402_50V8J
for EMI
close to the H9 boss
+3VALW
+5VS
B+
+5VALW
1
1
1
C62
C68
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
Compal Secret Data
Issued Date
C66
C65
2009/06/12
Deciphered Date
2010/06/12
Title
SPI ROM/TP/KB/Debug
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
31
of
44
ISPD
Power Button
DC-IN
PJP1
ZZZ
+3VL
PCB
2
PJP1
45@
R765
DAZ0HE00100
100K_0402_5%
SW 5 @
TJG-533-V-T/R_6P
ON/OFFBTN#
3
U3
SW 6@
TJG-533-V-T/R_6P
1
3
<34>
Q28A
2N7002DW -T/R7_SOT363-6
EC_ON
For EMI request
R767
10K_0402_5%
NB_GL40_R1
CANTIGA GL40
GL40R3@
CANTIGA GL40
GL40R1@
U3
U9
another at page36
2
2
<30,37>
51_ON#
NB_GL40_R3
C646
0.1U_0402_16V4Z
@
NB_GM45_R1
SB_R1
6
5
BTM side
ON/OFFBTN# <24,30>
U3
2
6
5
TOP side
debug phase using
CANTIGA GM45
GM45R1@
ICH9-M ES
ICH9R1@
Screw Hole
C
H2
BATT CHARGE/FULL LED
R773
510_0402_5%
R774
1
2
BATT_CHG_LOW _LED# <30>
H13
H_3P0
@
H14
H_3P0
@
H_3P0
@
H12
H_3P0
@
H11
H_3P0
@
H_2P7N
@
footprint is SC510UDG000
BATT_FULL_LED# <30>
H36
H33
H34
H35
CPU
1
HT-210UD/UYG_AMB/GRN
B
H_3P7
@
H_3P7
@
H_3P7
@
H10
H_3P0
@
D70
H9
H_3P0
@
H26
H_2P7x3P2N
@
Vf=1.9V(typ),2.4V(max) for amber

Vf=2.0V(typ),2.4V(max) for green
If=30mA(max)
510_0402_5%
H8
H_3P0
@
HT-110UYG-CT_YEL/GRN
+5VALW
H6
H_3P0
@
H5
PW R_LED# <30>
D67
2 510_0402_5%
2
footprint is SC510UYG000
R768
+5VALW
Vf=2.0V(typ),2.4V(max)
If=30mA(max)
DC-IN LED
H_3P7
@
SB
H15
H16
H19
H_3P3
@
H_3P3
@
H_5P0N
@
H18
H_5P0N
@
MINI CARD
PCB Fedical Mark PAD

1
FD3
@
2009/06/12
Issued Date
Deciphered Date

2010/06/12
4
Compal Secret Data
FD4
@
FD2
@
FD1
@
Title
Comm. SW/ Sub Conn./LEDS

Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
32
of
44
+1.5V to +1.5VS
+5VALW TO +5VS
+5VALW
+5VS
+1.5V
4.7U_0805_10V4Z
C833
R788
200K_0402_5%
@
Q36B
FDS6676AS
C834
1
2
C829
R783
1U_0402_6.3V4Z
FDS6676AS_SO8
Q36A
SUSP 5
2
2N7002DW -T/R7_SOT363-6
2N7002DW -T/R7_SOT363-6
1
2
3
4
1
1 R786
2
+VSB
220K_0402_5%
R789
820K_0402_5%
470_0805_5%
C828
S
S
S
G
3 1
C832
+VSB
3 1
1 R785
2
47K_0402_5%
D
D
D
D
2
1U_0402_6.3V4Z
Q34
8
7
6
5
Q37A
Q37B
SUSP 5
2
2N7002DW -T/R7_SOT363-6
2N7002DW -T/R7_SOT363-6
Q35B
R782
470_0805_5%
SI4800BDY_SO8
Q35A
SUSP
2
5
2N7002DW -T/R7_SOT363-6
2N7002DW -T/R7_SOT363-6
1
2
3
4
Vgs=10V,Id=14.5A,Rds=6mohm
4.7U_0805_10V4Z
S
S
S
G
R787
330K_0402_5%
+VSB
D
D
D
D
C831
0.022U_0402_25V7K
4.7U_0805_10V4Z
C830
1 R784
2
47K_0402_5%
8
7
6
5
1U_0402_6.3V4Z
SI4800BDY_SO8
R781
C827
C826
0.01U_0402_25V7K
1
2
3
4
S
S
S
G
+1.5VS
4.7U_0805_10V4Z
Q33
3 1
D
D
D
D
C825
8
7
6
5
C824
Inrush current = 0A
1
4.7U_0805_10V4Z
4.7U_0805_10V4Z
Q32
470_0805_5%
Inrush current = 0A
Vgs=10V,Id=9A,Rds=18.5mohm
+3VS
+3VALW
0.1U_0402_25V6
+3VALW TO +3VS
C835
+3VALW TO +3V_LAN
+3VALW TO +3V_SB
+3VALW
+3VALW
1
1
3
1
PJ35
JUMP_43X39
@
+3V_LAN
Q41
AO3413_SOT23
G
<26,30> W OL_EN#
C839
0.1U_0402_16V7K
@
1
1
2
R795@ 47K_0402_5% 2
C837
0.01U_0402_25V7K
@
1
Vgs=-4.5V,Id=3A,Rds<97mohm
2
R793
100K_0402_5%
@
Inrush current = 0A
1
C840
4.7U_0805_10V4Z
@
1
C841
C43
C67
1U_0402_6.3V4Z
10U_0805_6.3V6M
10U_0805_6.3V6M
+5VALW
+0.75VS
R802
470_0805_5%
SUSP
SUSP
<38>
R796
100K_0402_5%
Q28B
2N7002DW -T/R7_SOT363-6
another at page35
another at page35
R799
10K_0402_5%
SUSP
2
G
Q30
2N7002_SOT23-3
<25,30,39> SUSP#
Compal Secret Data
2009/06/12
Issued Date
Deciphered Date
2010/06/12
A
Title
DC-DC INTERFACE
Size
Document Number
Rev
0.1
PSWAA LA6511P M/B

Date:
Sheet
E
33
of
44
PreCHG
2
B+
1
2
1K_1206_5%
PR6
PR4
PR3
100K_0402_5%
100K_0402_5%
PR5
1
2
1
2
RLS4148_LL34-2
PR2
1
2
1K_1206_5%
PC4
100P_0402_50V8J
SINGA_2DW -0005-B03
1K_1206_5%
VIN
PC3
1000P_0402_50V7K
PC2
100P_0402_50V8J
PC1
1000P_0402_50V7K
DC_IN_S2
7A_24VDC_429007.W RML
DC_IN_S1 1
@ PJP1
PQ1
TP0610K-T1-E3_SOT23-3
PD1
PR1
PF1
DC301001M80
VIN
PL1
SMB3025500YA_2P
1
2
1K_1206_5%
1
PR12
PR7
100K_0402_5%
2
1
1 2
1K_1206_5%
VIN
PD2
<37>
2
3
PD3
RB715F_SOT323-3
PQ3
PR8
68_1206_5%
PD4
N1
VS
RLS4148_LL34-2
BATT+
PR9
68_1206_5%
2
TP0610K-T1-E3_SOT23-3
PQ4
DTC115EUA_SC70-3
RLS4148_LL34-2
PQ2
DTC115EUA_SC70-3
ACOFF
+5VALW P
<30,36>
PR10
100K_0402_1%
PC5
0.1U_0603_25V7K
PC6
0.22U_0603_25V7K
PR11
<32>
51_ON#
22K_0402_1%
PJ3
2
+3VLP
+3VL
@ JUMP_43X39
(100mA,40mils ,Via NO.= 2)

PJ332
2
+3VALW P
PJ76
1
+3VALW
+0.75VSP
@ JUMP_43X118
+0.75VS
@ JUMP_43X79
(5A,200mils ,Via NO.= 10)

OCP=7.7A
(0.98A,40mils ,Via NO.= 2)
PJ352
2
+5VALW P
+5VALW
PJ153
@ JUMP_43X118
(5A,200mils ,Via NO.= 10)

OCP=7.9A
@ JUMP_43X118
PJ152
PJ182
2
+1.8VP
+1.5VP
1
@ JUMP_43X39
+1.5V
@ JUMP_43X118
+1.8V
(1.46A,60mils ,Via NO.= 3)
(7.5A,300mils ,Via NO.= 15)

OCP=8.87A
ACIN
PJ402
2
PJ2
2
+VSBP
Precharge detector
Min.
typ.
Max.
H-->L 14.42V 14.74V 15.23V
L-->H 15.39V 15.88V 16.39V
@ JUMP_43X118
+VSB
@ JUMP_43X39
(120mA,40mils ,Via NO.= 1)
PJ403
+1.05VSP
+1.05VS
@ JUMP_43X118
(7.5A,300mils ,Via NO.=15)

OCP=8.41A
Issued Date
Compal Secret Data
2009/06/12
Deciphered Date
2010/06/12
A
Title
DCIN & DETECTOR

Size
Document Number
Rev
0.1
KSWAA
Date:
Sheet
D
34
of
44
VMB
PF2
10A_125V_451010MRL
1
2
@ PJP2
BATT_P3
BATT_P4
BATT_P5
EC_SMDA
EC_SMCA
PL2
SMB3025500YA_2P
1
2
BATT+
PH1 under CPU botten side :

CPU thermal protection at 90 degree C
Recovery at 56 degree C
PR14
1K_0402_1%
+3VLP
PC8
0.01U_0402_25V7K
PC7
1000P_0402_50V7K
GND
GND
GND
GND
BATT_S1
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
4
5
6
7
8
9
SUYIN_200045MR009G171ZR
PD6
VL
1
2
1
2
2
PR16
6.49K_0402_1%
2
1
PC9
0.1U_0402_16V4Z
PJSOT24C_SOT23-3
SE070104Z80
+3VLP
<37>
OT1 TMSNS2
OT2 RHYST2
4
PR21
100_0402_1%
PH1
100K_0402_1%_NCP15W F104F03RC
BATT_TEMPA <30>
G718TM1U_SOT23-8
GND RHYST1
VCC TMSNS1
2
3
VS_ON
PR19
1K_0402_1%
PR20
100_0402_1%
PR18
10.7K_0402_1%
PU1
PD5
PJSOT24C_SOT23-3
PR15
23.2K_0402_1%
EC_SMB_DA1 <30>
EC_SMB_CK1 <30>
Rset = 3 * Rtmh
Rhyst = (Rset* Rtml) / (3*Rtml - Rset)
Rtmh at 90C = 7.79K, Rtml at 56C = 26.1K
Rset = 3 * 7.79K = 23.37K ==> 23.2K
Rhyst = (23.2K * 26.1K) / (3 * 26.1K - 23.2K) = 10.99K ==> 10.7K
PQ5
TP0610K-T1-E3_SOT23-3
3
2
1
PR25
100K_0402_1%
PR24
+VSBP
VL
PC10
0.22U_0603_25V7K
1
PR23
100K_0402_1%
B+
PC11 @
0.1U_0603_25V7K
22K_0402_1%
PR26
<21,37>
POK
PQ6
SSM3K7002FU_SC70-3
2
G
@ PC12
.1U_0402_16V7K
0_0402_5%
Issued Date
Compal Secret Data
2008/10/09
Deciphered Date
2009/10/09
A
Title
BATTERY CONN / OTP

Size
Document Number
Rev
0.1
KSWAA
Date:
Sheet
D
35
of
44
1
2
VCOMP
CSIP
19
ICM
PHASE
18
LX_CHG
VREF
UGATE
17
DH_CHG
6251VDDP
LGATE
14
DL_CHG
PGND
13
GND
2
2
VADJ
12
0.1U_0603_25V7K
PD202
RB751V-40_SOD323-2
1
2 6251VDD
PR233
PC221
4.7U_0603_6.3V6M
PR235
BATT+
2
PR206
4.7_1206_5%
3
0.02_1206_1%
AO4466L_SO8
15
VDDP
BST_CHG 1
2
0_0603_5%
PC205
BST_CHGA 2
1
ACLIM
16
1
2
5
6
7
8
10
11
PR223
20K_0402_1%
PL202
10UH_MSCDRI-104A-100M-E_4.6A_20%
CHG
1
2
3
2
1
6251aclim
BOOT
75K_0402_1%
6251VREF
1
2
2_0402_5%
PQ202
1
PR221
120K_0402_1%
CHLIM
PC220
0.1U_0603_25V7K
1
PR232
PR205
PR222
PQ216
SSM3K7002FU_SC70-3
1 20_0402_5%
2
G
PC206
680P_0603_50V7K
PC204
10U_1206_25V6M
2
1
ACPRN
PQ201
AO4466L_SO8
20
BATT_ON
CSIN
PC222
2200P_0402_25V7K
ICOMP
CSOP
PC216
PQ213
DTC115EUA_SC70-3
ACOFF
2
6251VREF
IREF
CSOP
PR2312
CELLS
21
.1U_0402_16V7K
ACOFF
PR219
1
2
47K_0402_1%
PC215
1
2
PR220
154K_0402_1%
2
1
1
<30,34>
10K_0402_1%
CSON
22
<37>
PC219
0.047U_0402_16V7K
1
2
PR230
20_0402_5%
CSON
6800P_0402_25V7K
2
ADP_I
<30>
PR218
1
ACPRN
PR229 20_0402_5%
1
2
3
2
1
EN
23
0.01U_0402_25V7K
<30>
4
PR211
47K_0402_5%
1
2
0.01U_0402_25V7K
5
G
PACIN
PC214
1
2
PR238
100K_0402_1%
5
6
7
8
ACSET ACPRN
PC213
1
2
PQ212B
DMN66D0LDW -7_SOT363-6
6251_EN
DCIN 2
100K_0402_1%
PQ212A
PQ215
DTC115EUA_SC70-3
PC203
10U_1206_25V6M
2
1
24
DCIN
VIN
1.26V
PR228
14.3K_0402_1%
0.1U_0603_25V7K
2
G
S
ACSETIN
PC218
VDD
PC202
10U_1206_25V6M
2
1
PR236
PR237
10K_0402_1%
1 1
PU200
PC217
1000P_0402_25V8J
2
1
PR227
10_1206_5%
47K_0402_1%
1 1
6251VDD
1
PC212
2.2U_0603_6.3V6K
PD201
RB751V-40_SOD323-2
PR217
PR213
150K_0402_1%
PQ211
DTC115EUA_SC70-3
PR226
191K_0402_1%
FSTCHG
1
BATT_ON
PR216
10K_0402_1%
2
1
LDO 5.075V
ACSETIN
<30>
PreCHG
8
7
6
5
2
2
PR212
200K_0402_1%
PQ210
DTA144EUA_SC70-3
CSIN
CSIP
VIN
PC211
5600P_0402_25V7K
PQ207
AO4435_SO8
1
2
3
PC235
10U_1206_25V6M
2
1
PL201
2
1
HCB2012KF-121T50_0805
PC234
10U_1206_25V6M
2
1
CHG_B+
PC236
10U_1206_25V6M
PC233
4.7U_0805_25V6-K
2
1
0.02_1206_1%
4
PC232
4.7U_0805_25V6-K
2
1
B+
PR210
200K_0402_1%
PC210
0.1U_0603_25V7K
2
1
1
1
PC231
4.7U_0805_25V6-K
2
1
8
7
6
5
4
VIN
1
2
3
PR215
P3
PQ204
AO4407A_SO8
1
2
3
P2
PQ203
AO4435_SO8
8
7
6
5
4.7_0603_5%
G5209S31U_SSOP24
PR224
<30> CHGVADJ
2
2
15.4K_0402_1%
PR225
31.6K_0402_1%
1
VIN
1
PR240
47K_0402_1%
PR241
10K_0402_1%
1
2
ACIN
<21,30>
@ PR246
309K_0402_1%
@
PR247
10K_0402_1%
1
2
PACIN
ADP_V
<30>
@ PR248
PC223
High 18.089V
Low 17.44V
.1U_0402_16V7K
47K_0402_1%
PQ214
DTC115EUA_SC70-3
Iada=0~3.421A(65W) CP= 92%*Iada; CP=3.15A

Vaclim=0.6221V(65W)
PR243
14.3K_0402_1%
CHGVADJ=(Vcell-4)*9.445
CP mode
Vin Detector
1
ACPRN
PR242
10K_0402_1%
6251VDD
PR222=75K, PR223=20K
1.26 / 14.3 * 205.3 = 18.089V

CC=0.25A~3.6A
4
IREF=0.9133*Icharge
Vcell
IREF=0.228V~3.29V
4V
VCHLIM need over 95mV
4.2V
1.889V
4.35V
3.30575V
CHGVADJ
0V
Issued Date
Compal Secret Data
2010/01/25
Deciphered Date
2009/04/28
A
Title
CHARGER
Size Document Number
Custom
Date:
Rev
0.1
Huron river

D
Sheet
36
of
44
PC363
1U_0603_10V6K
2VREF_6182
PR365
19.1K_0402_1%
1
2
5
6
7
8
2
LX_5V
LG_3V
12
DRVL1
19
LG_5V
PL352
4.7UH_SIL1045R-4R7PF_6.3A_30%
1
2
AO4712L_SO8
+
PC356
680P_0603_50V7K
15mohm
VL
UP6182_B+
PC364
4.7U_0805_10V6K
Ipeak=5A
Imax=3.5A
F=245KHz
Total Capacitor 220uF
ESR 15mohm
PR361
<20>
ENTRIP2_HW
PC352
330U_6.3V_M
1
PQ352
TPS51125ARGER_QFN24_4X4
<20>
@ PR375
0_0402_5%
1
2
+5VALWP
VIN
AO4466L_SO8
PR356
4.7_1206_5%
VCLK
18
17
16
14
13
VREG5
DRVL2
PC355
2 0.1U_0603_25V7K
3
2
1
20
<21,35>
5
6
7
8
21
LL1
5
G
PC365
0.1U_0603_25V7K
PQ360B
S
1
DRVH1
LL2
1
3
DRVH2
11
2VREF_6182
G
ENTRIP1
10
LX_3V
2
ENTRIP2
PQ360A
UG_3V
PR355
BST_5V 1
2
0_0603_5%
UG_5V
1
ENTRIP1_HW
VFB1
22
PC362
1U_0402_6.3V6K
@ PR374
0_0402_5%
ENTRIP11
2
VREF
VFB2
23
VBST1
SF000002O00
Ipeak=5A
Imax=3.5A
F=305KHz
Total Capacitor 220uF
ESR 15mohm
TONSEL
PGOOD
VBST2
EN0
B+
VREG3
100K_0402_5%
AO4712L_SO8
1
2
3
PC336
680P_0603_50V7K
POK
PR360
499K_0402_1%
1
2
330U_6.3V_M
24
4
VO1
PR336
PQ351
3
2
1
VO2
GND
PQ332
4.7_1206_5%
15mohm
PC366
10U_1206_25V6M
BST_3V
PR335
1
2
0_0603_5%
8
7
6
5
PL332
4.7UH_SIL1045R-4R7PF_6.3A_30%
1
2
+3VALWP
P PAD
SKIPSEL
1
2
3
PC335
0.1U_0603_25V7K
1
25
15
PU330
ENTRIP2
4.7U_0805_10V6K
PC361
2
1
8
7
6
5
PQ331
AO4466L_SO8
PC332
PR357
150K_0402_1%
1
2
PR337
150K_0402_1%
1
2
UP6182_B+
1
PC360
10U_1206_25V6M
PC367
10U_1206_25V6M
PC368
2200P_0402_50V7K
2
1
+3VLP
PR363
20K_0402_1%
1
2
ENTRIP1
B+
PL331
HCB2012KF-121T50_0805
1
2
PR364
30K_0402_1%
1
2
ENTRIP2
UP6182_B+
PR362
13K_0402_1%
1
2
PR370
VL
1
1
100K_0402_1%
VS_ON
2
G
1
PQ362
PC370
2
1
PR372
PR373
2.2U_0603_10V6K
200K_0402_1%
ACPRN
1
<36>
A
2
42.2K_0402_1%
1
2
100K_0402_1%
VS
<35>
PR371
PQ361
DTC115EUA_SC70-3
SSM3K7002FU_SC70-3
EC_ON
2009/11/13
Issued Date
DTC115EUA_SC70-3
Compal Secret Data
PQ363
<30,32>
Deciphered Date
2009/04/28
4
Title
3VALWP/5VALWP
Size
Document Number
Rev
0.1
Huron river
Date:
Sheet
1
37
of
44
PL151
HCB2012KF-121T50_0805
1
2
5
6
7
8
PR164
255K_0402_1%
1
2
PQ151
PC164
4.7U_0805_25V6-K
2
1
PC163
4.7U_0805_25V6-K
2
1
1.5_B+
4
1
OUT
VCC
FB
PGOOD
VFB=0.75V
DH_1.5V
LX
12
LX_1.5V
ILIM
11
VDD
DL
PR157
1
2
15.4K_0402_1%
10
+1.5VP
0.1U_0603_25V7K
PQ152
+5VALW
PR156
4.7_1206_5%
+ PC152
330U_6.3V_M
AO4712L_SO8
DL_1.5V
Ipeak=7.5A
Imax=5.25A
F=315KHz
Total Capacitor 880uF,
ESR 5mohm
PGND
G5603RU1U_TQFN14_3P5X3P5
PC162
4.7U_0805_10V6K
PC156
680P_0603_50V7K
AGND
7
PC161
4.7U_0603_6.3V6K
3
2
1
14
13
DH
5
6
7
8
BST
TP
TON
100_0603_5%
PL152
1.8UH_SIL104R-1R8PF_9.5A_30%
PC155
1
2
BST_1.5V-1
EN_SKIP
PU150
AO4466L_SO8
PR161
PC160 @
.1U_0402_16V7K
15
1
2
1
2.2_0603_1%
0_0402_5%
+5VALW
PR155
BST_1.5V
3
2
1
PR160
<30,39> SYSON
B+
PC166
2200P_0402_50V7K
2
1
PR162
10K_0402_1%
PR163
10K_0402_1%
PR165
100K_0402_5%
1
2
<8>
DDR3_SM_PW ROK
+1.5V
@ PC165 .1U_0402_16V7K
+1.5V
B
PJ75
JUMP_43X79
@
PU75
VIN
VCNTL
GND
NC
VREF
NC
VOUT
NC
TP
+3VALW
PC264
2
PR262
1K_0402_1%
2
PC261
4.7U_0805_6.3V6K
1U_0603_10V6K
+0.75VSP
PC263
.1U_0402_16V7K
2
1
1
2
PR263
1K_0402_1%
PQ260
SSM3K7002FU_SC70-3
@ PC260
.1U_0402_16V7K
A
2
G
1
<33> SUSP
G2992F1U_SO8
PR260
0_0402_5%
1
2
PC262
10U_0603_6.3V6M
For shortage changed
2009/06/12
Issued Date
Compal Secret Data
2010/06/12
Deciphered Date
Title
1.8V / 1.5V / 0.75V

Size
Document Number
Rev
0.1
KSWAA
Date:
Sheet

1
38
of
44
PL401
HCB2012KF-121T50_0805
1
2
@ PC416
100U_25V_M
+
2
BST
VDD
10
DL
+1.05VSP
ILIM
LX_1.05VS
PR407
1
2
15.4K_0402_1%
PC412
4.7U_0805_10V6K
PR406
4.7_1206_5%
PQ402
+5VALW
DL_1.05VS
G5603RU1U_TQFN14_3P5X3P5
PC402
330U_6.3V_M
2
PC406
680P_0603_50V7K
AO4712L_SO8
Ipeak=7.5A
Imax=5.25A
F=315KHz
ESR 2.5mohm
12
11
PGND
PGOOD
LX
3
2
1
14
15
TP
FB
VFB=0.75V
VCC
DH_1.05VS
AO4466L_SO8
PL402
1.8UH_SIL104R-1R8PF_9.5A_30%
1 2
OUT
13
DH
B+
PR405
PC405
0_0603_5% 0.1U_0603_25V7K
1
2
1
2
5
6
7
8
TON
BST_1.05VS
3
2
1
EN_SKIP
PU400
AGND
PC410
@
.1U_0402_16V7K
PR411
100_0603_1%
1
2
PC411
4.7U_0603_6.3V6K
<25,30,33> SUSP#
PC414
4.7U_0805_25V6-K
2
1
PQ401
PR410
0_0402_5%
1
2
+5VALW
5
6
7
8
PR414
255K_0402_1%
1
2
PC413
4.7U_0805_25V6-K
2
1
1.05VS_B+
PC418
2200P_0402_50V7K
2
1
PC417
10U_1206_25V6M
2
1
PR412
4.02K_0402_1%
1
2
2
PR413
10K_0402_1%
+3VALW
PJ181
JUMP_43X39
@
1
2
PR182
2.4K_0402_1%
PC185
22U_0805_6.3V6M
2
APL5930KAI-TRG_SO8
PR181
3K_0402_1%
PC184
0.01U_0402_25V7K
FB
VOUT
VOUT
+1.8VP
EN
POK
1
2
@ PC183
0.01U_0402_25V7K
8
7
3
4
PR183
0_0402_5%
1
2
VCNTL
VIN
VIN
SYSON
<30,38>
PU180
6
5
9
GND
PC182
4.7U_0805_6.3V6K
3
PC181
1U_0603_6.3V6M
+5VALW
Issued Date
Compal Secret Data
2009/06/12
Deciphered Date
2010/06/12
A
Title
1.05V / 1.8V
Size
Document Number
Rev
0.1
KSWAA
Date:
Sheet
D
39
of
44
1
PR523
2
147K_0402_1%
<6>
+
2
@ PC550
100U_25V_M
@ PC549
100U_25V_M
PC545
100U_25V_M
PC544
100U_25V_M
PC543
4.7U_0805_25V6-K
2
1
PC542
4.7U_0805_25V6-K
2
1
+
2
B+
1
+
2
4
PL503
0.36UH_PCMC104T-R36MN1R17_30A_20%
PMON
PHASE1
34
RBIAS
PGND1
33
LGATE1
32
PVCC
31
LGATE2
30
+CPU_CORE
1
PR557
1_0402_5%
2
PR555
10K_0402_1%
2
1
PC506
680P_0603_50V7K
PHASE_CPU1
3.65K_0805_1%
UGATE_CPU1
PR554
35
36
PR506
4.7_1206_5%
1 2
BOOT1
UGATE1
1
1
3
2
1
37
TPCA8030-H_SOP-ADV8-5
PQ502
MDU2653RH_POW ERDFN56-8-5
VID0
38
VID1
39
VID2
40
VID3
PC541
4.7U_0805_25V6-K
2
1
PC539
0.022U_0402_16V7K
2
1
PR542
PR543
PR544
PC538
2.2U_0603_6.3V6K
2
1
<6>
<6>
<6>
CPU_VID2
<6>
CPU_VID1
<6>
CPU_VID0
<6>
<30>
CPU_VID3
CPU_VID4
PR545
PR546
41
VID4
42
VID5
44
43
VID6
46
45
47
@ PR556
1
VSUM
3
2
1
PSI#
DPRSLPVR
PGOOD
DPRSTP#
48
PL502
FBMA-L18-453215-900LMA90T_1812
1
2
0_0603_5%
2
2
VCC_PRM
ISEN1 PC552
0.22U_0603_10V7K
LGATE_CPU1
VR_TT#
NTC
SOFT
OCSET
PGND2
29
VW
PHASE2
28
PHASE_CPU2
10
COMP
UGATE2
27
UGATE_CPU2
11
FB
BOOT2
26
12
FB2
NC
25
BOOT_CPU2 1
PR515
2.2_0603_1%
TP
49
+CPU_B+
2
2
PC531
330P_0603_50V8
VCC_PRM
PC535
0.22U_0603_10V7K
PR535 4.53K_0402_1%
PC533 .1U_0402_16V7K
1
2
2
3
2
1
PC548
4.7U_0805_25V6-K
2
1
PC547
4.7U_0805_25V6-K
2
1
1
PR559
10K_0402_1%
2
1
PR561
1_0402_5%
2
1
PR558
3.65K_0805_1%
2
3
2
1
1 2
ISEN1
24
ISEN2
@ PR560 0_0603_5%
1
2
1
PC555
0.22U_0603_10V7K
VCC_PRM
ISEN2
+CPU_B+
Rfset = (Fsw/2232)^(-1.1202)
Fsw = 339KHz
Rfset = 8.25K
PR537
PR536 1K_0402_1%
PR532
20_0402_5%
1
2
PR531 0_0402_5%
PC532 180P_0402_50V8J
1
2
<6> VSSSENSE
PC516
680P_0603_50V7K
VSUM
VSUM
PC529
0.01U_0603_50V7K
11K_0402_1%
PR538
2 2
1
2
20_0402_5%
PR516
4.7_1206_5%
+5VALW
PC536
0.1U_0603_25V7K
PR534
+CPU_CORE
0_0402_5%
PR533
PC530 330P_0603_50V8
1
2
PC515
0.22U_0603_10V7K
PQ504
MDU2653RH_POW ERDFN56-8-5
<6> VCCSENSE
4
ISEN1
ISEN2
2
PR539
10_0603_5%
1
2
PR530 1K_0402_1%
PL504
0.36UH_PCMC104T-R36MN1R17_30A_20%
TPCA8030-H_SOP-ADV8-5
2.61K_0402_1%
PR529 1
Ipeak=38A
Imax=26.6A
Iocp=60A
F=339KHz
ESR 3.75mohm
PH501
10K_0402_5%_ERTJ0ER103J
1K_0402_5%
PC528 2200P_0402_50V7K
1
2
PQ503
LGATE_CPU2
PR540 1_0603_5%
PC537
1U_0402_6.3V6K
220P_0402_50V8J
100_0402_1%
1
PC527
23
PR528
1
VDD
22
GND
21
VIN
20
VSUM
19
DFB
DROOP
VO
18
17
13
1
PR527 97.6K_0402_1% PC526 270P_0402_50V7K

1
2
2
1
16
PC525 1000P_0402_50V7K
RTN
VDIFF
1
2
1000P_0402_50V7K PC524
PR526 8.25K_0402_1%
1
2
15
13K_0402_1%
1
2
VSEN
PR525
14
0.022U_0603_25V7K PC523
1
2
ISL6266AHRZ-T_QFN48_7X7
PC546
4.7U_0805_25V6-K
2
1
VR_TT#
PR547
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
3V3
H_PSI#
CLK_EN#
2
1
<5>
PQ501
BOOT_CPU1
PU500
<8,21,30> VGATE
+CPU_B+
2.2_0603_1%
0.22U_0603_10V7K
PR505
PC505
1
2
1
2
1
PR520
1.91K_0402_1%
+3VS
PR521
499_0402_1%
0_0402_5%
2
PC540
1U_0603_6.3V6M
PR553
1
+3VS
0_0402_5%
2
VR_ON
<5,8,20> H_DPRSTP#
PR541
1_0603_5%
0_0402_5%
2
PR548
1
PR551
1
PR549
PR550
<8,21> PM_DPRSLPVR
CPU_VID5
CPU_VID6
VR_ON
+5VALW
PC534 0.22U_0402_6.3V6K
2
1
2007/11/12
Issued Date
Compal Secret Data
2008/11/12
Deciphered Date
+CPU_CORE
5
Title
Size Document Number

Custom
Date:
Rev
0.1
KSWAA
Sheet
1
40
of
44
PIR (Product Improve Record)
REVISION CHANGE: 0.1 TO 0.2 PVT

NO DATE
PAGE MODIFICATION LIST
PURPOSE
--------------------------------------------------------------------------------------------------------------------------------------------------1. 07/23
32
Change R768,R773 from 120 ohm to 510 ohm
for changed 5mA LED
2. 07/23
32
Chage LED power rail from +3valw to +5valw
for changed 5mA LED
3. 07/23
23
del. L86,L87 EMI component
for EMI request
4. 07/23
31
Add 1PCS(C62) 0.1uF_0402 on +3Valw-->GND
for EMI request
5. 07/23
31
Add 1PCS(C65) 0.1uF_0402 on +5Vs-->GND
for EMI request
6. 07/23
31
Add 0.1uF_0402(C66) on B+-->GND close to H8
for EMI request
7. 07/23
28
JLINE and JEXMIC change from DC2300006300 to DC230004L00
for SMT DFx request
8. 07/27
30
change R742 from +3VALW to +3VL
for LED no function issue
9. 07/27
8
add test pad ON U3.E36,U3.AK34
for ATE request
10. 07/27
33
change part number of Q30 (SB770020010)
for Reduce BOM part type
11. 07/27
32
Change D67(power on LED) from SC510UYG000 to SC500009D00
for changed 5mA LED
12. 07/27
32
Change D70(DC in LED) from SC510UDG000 to SC500009800
for changed 5mA LED
13. 07/29
14
un-mount CD7,CD8,CD9,CD10,CD11,CD12,CD30,CD31,CD32,CD34,and mount(22uF) CD29,CD33
for design change
14. 07/29
11
For +1.5V ,C78 from 330uF to 390u (SF000002O00)
for design change
15. 07/29
12
Change R82 and R81 from inductor to Bead
for design change
16. 07/29
15
+0.75VS filter un-mount CD22 and CD44
for design change
17. 08/03
25
un-mount D77
for If +3V_WLAN is +3VS, please un-mount D77
2009/06/12
Issued Date
Compal Secret Data
2010/06/12
Deciphered Date
5
Title
PIR
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
41
of
44
REVISION CHANGE: 0.2 TO 0.3 Pre-MP

NO DATE
PURPOSE
--------------------------------------------------------------------------------------------------------------------------------------------------1. 08/09
29
Change net V1_8 to +v1_8
for power trace
2. 08/09
32
add R774
for LED control
3. 08/12
32
un-mount SW5 and SW6
for Pre-MP do need power SW
4. 08/12
20
add R16 (for RTC battery)
for design change
5. 08/13
26
add D69 and un-mount CL38
for EMI request
6. 08/13
26
CL37 from 0.1uF to 120pF
for EMI request
7. 08/13
26
add CL35
for EMI request
8. 08/13
27
add CA51
for EMI request
9. 08/13
33
add C67 and C43
for EMI request
2009/06/12
Issued Date
Compal Secret Data
2010/06/12
Deciphered Date
5
Title
PIR
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
42
of
44

REVISION CHANGE: 0.1 TO 1.0
NO DATE
PURPOSE
---------------------------------------------------------------------------------------------------------------------------------------------------
2009/06/12
Issued Date
Compal Secret Data
2010/06/12
Deciphered Date
5
Title
PIR
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
1
43
of
44
Version Change List ( P. I. R. List ) for Power Circuit

Page#
Item Title
Solution Description
PVT : modification from EVT

P35
mount ESD diode
mount PD5, PD6
P36
EMI request
add PC236 10uF
P37
EMI request
add PC367 10uF, PC368 2200pF
P37
change 3/5V IC main source
change PU330 to UP6182
P38
EMI request
add PC166 2200pF
P39
EMI request
add PC417 10uF, PC418 2200pF
P40
adjust loadine
change PR535 to 3.09K
P34
unify source
change PD1 to SC11N414880
P36
unify source
change PQ216 to SB000009610
P37
unify source
change PQ362 to SB000009610
P40
unify source
change PL502 to SM010020720
P40
turn on speed too quick
change PQ502, PQ504 to MDU2653RH
P37
change cap to 330uF with same price
change PC332, PC352 to SF000002000
P38
change PC152 to SF000002000
P39
change PC402 to SF000002000
P36
EMI request to mount snubber circuit, ISN caps
add PR206, PC206; PC234, PC235
P37
EMI request to mount snubber circuit
add PR336, PC336; PR356, PC356
P38
EMI request to mount snubber circuit & boost resistor
add PR156, PC156; change PR155 to 2.2ohm
P39
add PR406, PC406
P40
add PR506, PC506; PR516, PC516
PreMP : modification from PVT

P34
increase precharge design margin
add PR12 1K
P35
change OTP setting
change PR15 to 23.2K, PR18 to 10.7K
P35
change source
chagne PC9 to SE070104Z80
P37
change 3/5V IC main source
change PU330 to TPS51125A
P38
change 0.75V IC main source
change PU75 to G2992
P40
adjust loadine
change PR535 to 4.53K
P40
adjust transient stability
change PR527 to 220pF
Issued Date
Compal Secret Data
2009/06/12
Deciphered Date
2010/06/12
Title
PIR
Size
Document Number
Rev
0.1
PWWAA LA6841P M/B

Date:
Sheet
44
of
44

Toshiba Satellite c660 La-6841p r01

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A

L-A6841P REV 0.1 Schematic

Compal Electronics, Inc.

Compal Secret Data

PWWAA LA6841P M/B

Monday, August 16, 2010

Model Name : PWWAA

Intel Penryn Processor

Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2

1.5V DDR3 800/1066

USB port 0,1

DC/DC Interface CKT.

Power Circuit DC/DC

Compal Secret Data

PWWAA LA6841P M/B

Monday, August 16, 2010

Adapter power supply (19V)

AC or battery power rail for power circuit.

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Core voltage for CPU

0.75V switched power rail for DDR terminator

1.05V switched power rail

1.5V switched power rail

1.5 power rail for DDR

1.8V power rail

3.3V always on power rail

3.3V always on power rail

3.3V power rail for SB

3.3V power rail for LAN

3.3V switched power rail

5V always on power rail

5V power rail for SB

5V switched power rail

VSB always on power rail

BTO Option Table

External PCI Devices

CPU THM Sen

ICH9M SM Bus address

Compal Electronics, Inc.

Compal Secret Data

PWWAA LA6841P M/B

Monday, August 16, 2010

for source control

FAN Control Circuit

PROCHOT# PU: 68Ohm near CPU and MVP6.

H_THERMDA, H_THERMDC routing together,

Compal Electronics, Inc.

Compal Secret Data

PWWAA LA6841P M/B

Monday, August 16, 2010

Resistor placed within

layout note: Please use "Daisy Chain"

Compal Electronics, Inc.

Compal Secret Data

PWWAA LA6841P M/B

Monday, August 16, 2010

Near CPU CORE regulator

ESR <= 1.5m ohm

need to change P/N

Mid Frequence Decoupling

+1.05VS (North side Secondary)

Near pin B26

Close to CPU pin