module dds(CLK,WCLK,OUT,DIN,EN,SQR,TRI); input CLK; input WCLK; output SQR; input TRI; output [9:0] OUT; input DIN;

input EN; reg [9:0] OUT; reg [31:0] PhaseAccum; reg [31:0] Freq=32'h10000000; reg [4:0] addr; wire c; wire w; and a(c,CLK,EN); and a1(c2,c,EN); nand b(w,WCLK,!EN); wire [9:0] PhasetoAmp; reg SQR; sin amp(.THETA(PhaseAccum[31:22]),.SINE(PhasetoAmp),.CLK(c2)); always@(negedge c) begin PhaseAccum<=PhaseAccum+Freq; end always@(posedge c) if(TRI==1'b1) begin OUT<=PhasetoAmp; addr<=0; end else begin OUT<=PhaseAccum[9:0]; SQR<=PhaseAccum[31]; end always@(negedge w) begin addr<=addr+1; Freq[addr]<=DIN; end endmodule