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J-K FLIP FLOP VHDL CODE USING BEHAVIOURAL MODELING

Library ieee declaration.

library IEEE; In ieee library std_logic_1164 package is declared for std_logic data types (predefined data types). use IEEE.STD_LOGIC_1164.ALL; -------------------------------------------------------------entity j_kff is Entity describes circuit external ports. Port (j, k, clk, rst: in STD_LOGIC; J, k , clk, rst: - input port to J-K flip flop. q, qbar: - output port to J-K flip flop. q, qbar : inout STD_LOGIC); q:- present state, qbar: - next state. end j_kff; -------------------------------------------------------------architecture Behavioral_jkff of j_kff is begin Architecture begins. -------------------------------------------------------------process(clk, rst, j,k) variable temp: std_logic:=0; begin if (clk'event and clk='1') then if (rst='0') then if (j='0' and k='0') then temp:= q; elsif (j='0' and k='1') then temp:='0'; elsif (j='1' and k='0') then temp:= '1'; elsif (j='1' and k='1') then temp:= not q; else temp:= q; end if; end if; end if; q<= temp; qbar<= not temp; end process; ------------------------------------------------------------End of architecture. end Behavioral_srff;

In a process all the statements will be executed sequentially. In process, a variable (temp) is declared to hold the output value. Its life is bounded till process end. If clock rising edge is +ve and reset is 0 then flip flop will work otherwise its output will be previous state. Truth table of J-K flip flops. J 0 0 1 1 K 0 1 0 1 Q Previous state 1 0 toggle QBAR Previous sate 0 1 toggle

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