ONLINE PLATFORM FOR PROGRAMMING AND RESEARCH (OP2R) EX-OR GATE VHDL CODE USING BEHAVIOURAL MODELING

library IEEE; use IEEE.STD_LOGIC_1164.ALL; ----------------------------------------------entity xor_1 is Port ( o, p : in STD_LOGIC; q : out STD_LOGIC); end xor_1; ----------------------------------------------architecture Behavioral_xor of xor_1 is begin ----------------process(o, p) begin if(p='0') then q<= o; else q<= not o; end if; end process; ----------------end Behavioral_xor; TRUTH TABLE: -

*\\ o and p are the input port to the and gate. *\\ q is output port to the and gate.

*\\ architecture of xor_1 entity begins. *\\ process (sensitivity list). After this statement all statement will be *\\ if (condition is true) then output (q) equal to o.

*\\ otherwise output (q) equal to not o.

*\\ end the architecture.

OUTPUT WAVEFORM: -

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