INFOOP2R.WIX.

COM/OP2R

HALF SUBTRACTOR VHDL CODE USING BEHAVIOURAL MODELING

Library declaration library IEEE; use IEEE.STD_LOGIC_1164.ALL; --------------------------------------------

Std_logic_1164; package for std_logic (predefined data type).

entity half_subtractor is Port ( a, b: in STD_LOGIC; diff ,borrow: out STD_LOGIC); end half_subtractor; --------------------------------------------architecture Behavioral_HS of half_subtractor is begin ------------------------------process (a,b) begin if(a='0') then diff<=b; borrow <= b; else diff<= not b; borrow<= '0'; end if; end process; --------------------------------end Behavioral_HS;

Entity declaration. a, b :- input port bits (bits to be added) Sum, carry:- output port bits

Process statements (sensitivity list) Behavioral representation of half adder... Truth table:-

A 0 0 1 1

B 0 1 0 1

Sum 0 1 1 0

Borrow 0 1 0 0

RTL VIEW:-

OUT PUT WAVEFORMS:-

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