INFOOP2R.WIX.

COM/OP2R

HALF SUBTRACTOR VHDL CODE USING STRUCTURAL MODELING

Library declaration library IEEE; use IEEE.STD_LOGIC_1164.ALL; --------------------------------------------

Std_logic_1164; package for std_logic (predefined data types).

entity half_subtractor is Port ( a, b: in STD_LOGIC; diff ,borrow: out STD_LOGIC); end half_subtractor; --------------------------------------------architecture Behavioral of half_subtractor is ---------------------------------------------Signal s1: in std_logic; component xor_1 is Port ( o,p : in STD_LOGIC; q : out STD_LOGIC); end component; component and_1 is Port ( x,y : in STD_LOGIC; z : out STD_LOGIC); end component; component not_1 is port (u: in std_logic; v: out std_logic); end component; ----------------------------------------------begin X1: xor_1 port map (a, b, diff); X2: not_1 port map (a, s1); x2: and_1 port map (s1, b, borrow); ----------------------------------------------end Behavioral;

Entity declaration. a, b: - input port bits (bits to be added) diff, borrow: - output port bits.

Signal declaration. Signal s1 will act as inout port. Component (Ex-or, And, Not) declaration These components are describing the structure view of half adder.

Architecture statements part (Architecture body). Components are port mapped to perform the circuit (subtract) operation.

INFOOP2R.WIX.COM/OP2R

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INFOOP2R.WIX.COM/OP2R