PowerBookG415High Res

8
1
CK
APPD
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
REV
ZONE
ECN
ENG
APPD
DESCRIPTION OF CHANGE
DATE
399027
PRODUCTION RELEASED
DATE
09/09/05 ?
D
PDF
TABLE_TABLEOFCONTENTS_HEAD
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TABLE_TABLEOFCONTENTS_ITEM
CSA
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CONTENTS
SYNC MASTER
Table Of Contents
Board Information
System Block Diagram
Power Block Diagram
Revision History
Q16C Pin Swaps
Functional Test Points
I2C Connections
JTAG Connections
Power Synonyms
Signal Synonyms
Power Inputs
Battery Charger
12.8V PBUS/PMU Supplies
5V/3.3V Supplies
1.8V/1.5V Supplies
2.5V Supply
Vesta Power & Misc
I2 Power
I2 Power Supplies
I2 Supplemental
I2 Miscellaneous
PCI Clock Buffer
LEDs/Reset/Debug
Power Management Unit (PMU05)
Power Sequencing
Fan Controller
ALS Support
Sudden Motion Sensor
Q16C Internal I/O I
Q16C Internal I/O II
I2 Processor Interface
A8 MaxBus (CPU0)
A8 Configuration Straps
A8 Power (CPU0)
CPU VCore Supply
CPU AVDD Supply
I2 Memory Interface
Memory Series Termination
DDR2 SO-DIMM Slot A
DATE
PDF
TABLE_TABLEOFCONTENTS_HEAD
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MULLET
08/02/2005
MULLET
08/02/2005
MULLET
08/02/2005
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CSA
CONTENTS
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110
111
112
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114
115
DDR2 SO-DIMM Slot B

M11 Frame Buffer Constraints
I2 AGP Interface
GPU (M11) AGP Interface
GPU VCore Supply
GPU (M11) Core Power
GPU (M11) I/O Power
GPU (M11) Frame Buffer I/F
GPU Frame Buffer A
GPU Frame Buffer B
GPU (M11) GPIOs/Straps
GPU (M11) Clocks/Misc
GPU (M11) DVI/DAC Outputs
Lower TMDS Transmitter
Upper TMDS Transmitter
Internal Display Conns
External Display Conns
BootROM
I2 PCI Interface
Q85 Airport/BT Connector
Cardbus
NEC USB2
I2 UATA Interface
HDD/ODD Connectors
I2 Ethernet Interface
Vesta Ethernet PHY
Ethernet Connector
I2 FireWire Interface
Vesta FireWire PHY
FireWire Ports
FireWire Series Term
I2 USB Interface
NEC USB2 Interface
Audio Board Connector
Spacing & Physical Constraints
Spacing & Physical Constraints 2
Cross Reference Page
SYNC MASTER
DATE
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DIMENSIONS ARE IN MILLIMETERS
Apple Computer Inc.
METRIC
XX
X.XX
DRAFTER
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ENG APPD
MFG APPD
QA APPD
DESIGNER
RELEASE
SCALE
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
ANGLES
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
REFERENCE DESIGNATOR(S)
CRITICAL
NOTICE OF PROPRIETARY PROPERTY
DESIGN CK
X.XXX
TITLE
BOM OPTION
DO NOT SCALE DRAWING
TABLE_5_ITEM
051-6929
SCHEM,MARIAS-STD,Q16C
SCH1
820-1875
PCBF,MLB,Q16C
PCB1
826-4393
LBL,P/N LABEL,PCB,28MM X 6MM
[EEE:SYU]
Q16C_BST_VRAM_S
826-4393
LBL,P/N LABEL,PCB,28MM X 6MM
[EEE:TMK]
Q16C_BST_VRAM_H
SCHEM,MARIAS-STD,Q16C
TABLE_5_ITEM
CRITICAL
NONE
TABLE_5_ITEM
SIZE
TABLE_5_ITEM
THIRD ANGLE PROJECTION
MATERIAL/FINISH
NOTED AS
APPLICABLE
DRAWING NUMBER
REV.
051-6929
SHT
C
OF
115
Design-Specific Rules
BOARD HOLES
CHASSIS GND CONNECTIONS
TABLE_SPACING_RULE
TABLE_SPACING_RULE
STANDARD
=DEFAULT
=DEFAULT
=DEFAULT
=DEFAULT
=DEFAULT
=DEFAULT
GND_CHASSIS_UPPER_DVI
TABLE_SPACING_RULE
BGA_P1MM
10
0.10 MM
1.25 MM
0.1 MM
12.5 MM
15.0 MM
20
0.20 MM
1.25 MM
0.1 MM
12.5 MM
15.0 MM
TABLE_SPACING_RULE
BGA_P2MM
TABLE_SPACING_RULE
GND_CHASSIS_FW_LOWER_DVI
DEFAULT
0.1 MM
2.5 MM
0.15 MM
10.0 MM
15.0 MM
"1MM" area defined around BGAs to

reduce DRCs caused by fan-out.
TABLE_SPACING_ASSIGNMENT
1MM
BGA_P1MM
AGP_STB
1MM
BGA_P2MM
1MM
BGA_P2MM
"BGA_P2MM" rule ensures these critical

signals do not fan-out routed next
to any other signals.
CLOCK
RAM_DIFF
1MM
BGA_P2MM
GND_CHASSIS_LCD
TABLE_PHYSICAL_RULE
STANDARD
=DEFAULT
=DEFAULT
=DEFAULT
=DEFAULT
0.100 MM
0.100 mm
1.25 MM
GND_CHASSIS_INVERTER
TABLE_PHYSICAL_RULE
DEFAULT
GND_CHASSIS_BATT_CHGR
TABLE_SPACING_RULE
90_OHM_DIFF
TOP,BOTTOM
2.5 MM
0.200 MM
2.5 MM
1.0 MM
2.5 MM
0.200 MM
2.5 MM
1.0 MM
ZT0200
HOLE-VIA-P5RP25
57
57
ZT0201
70
HOLE-VIA-P5RP25
70
HOLE-VIA-P5RP25
56
LWR CPU
56
ZT0203
0.118 MM
0.1 MM
0.125 MM
0.1 MM
ZT0212
HOLE-VIA-P5RP25
56
2
=GND_CHASSIS_BATTCHGR_HOLE
=GND_CHASSIS_INV_GND_CLIP
MECH. HOLES
INVERTER
ZT0221
Layer-specific rules for 60-ohm single-ended impedance
TABLE_SPACING_RULE
TABLE_PHYSICAL_RULE
SHLD-SM-LF
ZT0223
HOLE-VIA-P5RP25
TP_OPTICAL_DRIVE_SCREW
TABLE_SPACING_RULE
SH0200
OG-503040
TP_RT_KYBRD_SCREW
5 MM
ZT0222
HOLE-VIA-P5RP25
5 MM
Layer-specific rules for 100-ohm differential impedance
TABLE_PHYSICAL_RULE
100_OHM_DIFF
TOP,BOTTOM
2.5 MM
0.200 MM
2.5 MM
1.0 MM
2.5 MM
0.200 MM
2.5 MM
1.0 MM
60_OHM_SE
HOLE-VIA-P5RP25 1394
LWR RT GPU
TABLE_PHYSICAL_RULE
90_OHM_DIFF
=GND_CHASSIS_FW_HOLE
DVI
BATT. CHGR
HOLE-VIA-P5RP25
56
TP_LEFT_KYBRD_SCREW
56
HOLE-VIA-P5RP25
TOP,BOTTOM
=GND_CHASSIS_DVI_HOLE
ZT0211
ZT0202
56
UPPER RT GPU
70
TABLE_PHYSICAL_RULE
HOLE-VIA-P5RP25
67
TABLE_PHYSICAL_RULE
90_OHM_DIFF
ZT0210
LEFT CPU
57
TABLE_SPACING_RULE
90_OHM_DIFF
CHASSIS MOUNTS
=GND_CHASSIS_BATTCHGR_HOLE 2
=GND_CHASSIS_SLEEP_LED
30
MAKE_BASE=TRUE
VOLTAGE=0V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
TABLE_SPACING_RULE
HEATSINK MOUNTS
57
=GND_CHASSIS_INV_GND_CLIP
=GND_CHASSIS_INVERTER1
MAKE_BASE=TRUE
VOLTAGE=0V
57
=GND_CHASSIS_LCD1
=GND_CHASSIS_LCD2
=GND_CHASSIS_LCD3
=GND_CHASSIS_LCD4
MAKE_BASE=TRUE
VOLTAGE=0V
TABLE_PHYSICAL_RULE
=GND_CHASSIS_FW_HOLE
=GND_CHASSIS_DVI1
=GND_CHASSIS_DVI3
=GND_CHASSIS_TV
=GND_CHASSIS_ENET
=GND_CHASSIS_FW_PORT1
=GND_CHASSIS_FW_EMI
MAKE_BASE=TRUE
VOLTAGE=0V
=GND_CHASSIS_DVI_HOLE
=GND_CHASSIS_DVI2
=GND_CHASSIS_DVI4
MAKE_BASE=TRUE
VOLTAGE=0V
0.076 MM
=50_OHM_SE
=50_OHM_SE
TABLE_SPACING_RULE
100_OHM_DIFF
Layer-specific rules for 50-ohm single-ended impedance

TABLE_SPACING_RULE
BOARD STACK-UP AND CONSTRUCTION
TABLE_PHYSICAL_RULE
TABLE_SPACING_RULE
TABLE_PHYSICAL_RULE
100_OHM_DIFF
TOP,BOTTOM
0.092 MM
0.1 MM
5 MM
0.100 MM
0.1 MM
5 MM
50_OHM_SE
TABLE_PHYSICAL_RULE
2.5 MM
0.125 MM
2.5 MM
1.0 MM
SEE BOARD FILE FOR DETAILED INFORMATION

CONVENTIONAL CONSTRUCTION WITH Pxx TH VIA
TABLE_PHYSICAL_RULE
100_OHM_DIFF
TABLE_PHYSICAL_RULE
50_OHM_SE
0.100 MM
0.100 MM
1.25 MM
TABLE_SPACING_RULE
110_OHM_DIFF
TOP,BOTTOM
2.5 MM
0.330 MM
2.5 MM
1.0 MM
2.5 MM
0.300 MM
2.5 MM
1.0 MM
TABLE_SPACING_RULE
110_OHM_DIFF
TABLE_PHYSICAL_RULE
NO_TEST Properties
TABLE_PHYSICAL_RULE
110_OHM_DIFF
TOP,BOTTOM
0.080 MM
0.1 MM
5 MM
0.085 MM
0.1 MM
5 MM
TABLE_PHYSICAL_RULE
I256
110_OHM_DIFF
I257
I258
Portable-specific Override Rules
I259
TABLE_SPACING_RULE
I260
TABLE_SPACING_RULE
I261
AGP
201
0.2 MM
I262
TABLE_SPACING_RULE
I277
AGP_STB
251
0.25 MM
I263
TABLE_SPACING_RULE
I264
VGA
151
0.15 MM
=DEFAULT
=DEFAULT
=DEFAULT
=DEFAULT
I265
1778_ITH_RC
1778_VRNG
GPU_DVOD_R<18>
LTC3412_RUNSS
TMDS_CONN_CLKP
TP_NEC_SMC
TP_NEC_SMI_L
TP_NEC_SRCLK
TP_USB2_PWREN<0>
TP_USB2_PWREN<2>
TP_USB2_PWREN<3>
45
45
6 53
17
57
62
62
62
73
73
73
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
I266
I267
I268
I269
I270
I271
I272
I273
I274
I275
I276
TABLE_SPACING_RULE
TV
151
0.15 MM
=DEFAULT
=DEFAULT
=DEFAULT
I249
=DEFAULT
I244
I245
TABLE_PHYSICAL_RULE
I246
TABLE_PHYSICAL_RULE
VGA
I247
=60_OHM_SE
=60_OHM_SE
=60_OHM_SE
=60_OHM_SE
I248
UATA_DD_R<0>
UATA_DD_R<8>
UATA_DD_R<10>
UATA_DA_R<0>
UATA_DA_R<1>
6 63
6 63
6 63
6 63
6 63
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
TABLE_PHYSICAL_RULE
TV
I250
I251
I252
I253
I254
I255
=60_OHM_SE
=60_OHM_SE
=60_OHM_SE
TP_VESTA_DNC_E9
TP_VESTA_F1000
TP_VESTA_PHYA<0>
TP_VESTA_REGSEN2
TP_VESTA_SPD0
USB_NEC_BT_N
USB_NEC_N<1>
USB_NEC_N<2>
USB_NEC_N<3>
USB_NEC_P<0>
USB_NEC_P<1>
SI_TMDS_DN<5>
SI_TMDS_DN<4>
SI_TMDS_DP<3>
SI_TMDS_DN<2>
SI_TMDS_DN<1>
SI_TMDS_DN<0>
SI_TMDS_CLKP
18
66
66
18
66
6 11
73
73
73
73
73
55
55
55
54
54
54
54
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
SIGNAL (1/2 OZ + COPPER PLATING)
1
2
3
4
5
6
7
8
9
10
11
12
TABLE_SPACING_RULE
PREPREG
GROUND (1/2 OZ)
CORE
SIGNAL (1/2 OZ)
PREPREG
SIGNAL (1/2 OZ)
CORE
GROUND (1/2 OZ)
PREPREG
CUT POWER PLANE (1 OZ)
CORE
CUT POWER PLANE (1 OZ)
PREPREG
GROUND (1/2 OZ)
CORE
SIGNAL (1/2 OZ)
PREPREG
SIGNAL (1/2 OZ)
CORE
GROUND (1/2 OZ)
PREPREG
SIGNAL (1/2 OZ + COPPER PLATING)
TABLE_BOARD_INFO
=60_OHM_SE
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
BOM OPTIONS
NO_TYPE,1MM
MM
Module Components
TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
343S0383
IC,ASIC,I2,REV1.2,NB/SB,974 BGA
U2100
CRITICAL
BOM OPTION
337S3135
IC,PMU05,BLANK,QFP
U2700
CRITICAL
341S1772
IC,PMU05,V1,QFP
U2700
CRITICAL
PMU_PROG
337S3162
IC,A7PM,R1.5,1.67GHZ,LGA,1.28V,23W,85C
U3600
CRITICAL
A7PM_1P67_LGA
337S3163
IC,A7PM,R1.5,1.5GHZ,LGA,1.28V,23W,85C
U3600
CRITICAL
A7PM_1P5_LGA
337S3077
IC,A8,xxxGHZ
U3600
CRITICAL
CPU_A8
338S0252
IC,GPU,M11P
U5700
CRITICAL
335S0088
BOOTROM,BLANK
U7100
CRITICAL
BOOTROM_BLANK
341S1736
IC,BOOTROM,B,Q16C
U7100
CRITICAL
BOOTROM_PROG
343S0356
IC,ASIC,VESTA,V1.3,LF
U8500
CRITICAL
TABLE_BOMGROUP_ITEM
630-7016
PCBA,MLB,BESTMHZ,MARIAS,VRAM_S,Q16C
COMMON,ALTERNATE,gQ16C,gQ16C_BST,Q16C_BST_VRAM_S,VRAM_SAMSUNG,gCommon
TABLE_BOMGROUP_ITEM
630-7185
PCBA,MLB,BESTMHZ,MARIAS,VRAM_H,Q16C
COMMON,ALTERNATE,gQ16C,gQ16C_BST,Q16C_BST_VRAM_H,VRAM_HYNIX,gCommon
PMU_BLANK
Board Information
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
gCommon
5V_HD_LOGIC,BACKUP_BATT,CPU_A7PM,I2_FW_BETA,I2_MAXBUS_50OHM,MAXBUS_1V8,gCommon1
gCommon1
MMM_ACCEL_KIONIX,GPU_PWRPLAY,GPU_SS,GPU_LVDDR_2V8,GPU_MEMIO_1V8,gCommon2
gCommon2
I2_REV1_NOT,I2_MAXBUS_FBCLK_MATCHED,I2_AGP_FBCLK_MATCHED,I2_PCI_FBCLK_MATCHED,gCommon3
TABLE_BOMGROUP_ITEM
SYNC_MASTER=N/A
SYNC_DATE=N/A
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM
gCommon3
CPU_VCORE_2STATES,I2_MAXBUS_166MHZ,I2VCORE_1V5,I2VCORE_BURST,gCommon4
gCommon4
VESTA_PORT2_DISABLE,DVO_1V8,TMDS_DUAL,VCORE_OFFSET,VCORE_OFFSET_SW,gUSB

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM
gUSB
USB2_NEC,USB1P1_NEC,TPAD_SEQ_PMU
gQ16C
Q16C_PARTS,BOOTROM_PROG,PMU_PROG,MAXBUS_TBEN_SYNC
333S0317
IC,GDDR SDRAM,2MX32X4,300MHZ, LF FBGA144
U6200,U6250,U6300,U6350
CRITICAL
VRAM_SAMSUNG
333S0314
IC,GDDR SDRAM,2MX32X4,300MHZ, LF FBGA144
U6200,U6250,U6300,U6350
CRITICAL
VRAM_HYNIX
SIZE
TABLE_BOMGROUP_ITEM
IS
PART NUMBER
ALTERNATE FOR
PART NUMBER
343S0388
343S0356
TABLE_ALT_HEAD
BOM OPTION
REF DES
COMMENTS:
U8500
v1.4 is alt to v1.3
APPLE COMPUTER INC.
SCALE
TABLE_BOMGROUP_ITEM
gQ16C_BST
A7PM_1P67_LGA,CPU0_BUSRATIO_10.0X,CPU0_VCORE_1V28,CPU0_AVDD_1V28,Q16BST
TABLE_ALT_ITEM
DRAWING NUMBER
REV.
C
051-6929
2
115
SHT
OF
NONE
8
J8600
Ethernet
7
J9020
FW - A
Connector
Connector
Connector
P.67
P.70
P.70
2 DATA PAIRS
@ 200MHz
4 DATA PAIRS
J9010
FW - B
J3320
2 DATA PAIRS
@ 400MHZ
JA000
Audio
Connector
SW MODEM
Connector
P.30
J3400
J1250
Battery
Power Supply
& Charger
Connector
P.74
P.12
DC-In
Connector
P.13-17
P.31
U8500
Vesta
Ethernet Combo FireWire
P.66
PHY
P.69
U1250
BATTERY
CURRENT
SENSOR
J8200/J8250
G/MII
3.3V
10/100/1000
8BIT TX
8BIT RX
125MHZ
1394 OHCI
3.3V
8BIT TX/RX
100MHZ
P.12
HDD/ODD
Connectors
ALS Sensors
U3000
P.64
Fan
I2S
I2C
Circuit
P.27
UATA
SLEEP
LED
P.24
SMBUS
3.3V
U2700
ETHERNET
FIREWIRE
800 Mb/S
P.68
10/100/1000
P.65
C
UNUSABLE
PMU
I2S I2C
x2 x2
UATA 100
P.63
J2690
P.21 P.21
USB2.0
PORTS A-F
P.21
U3220
SMS Sensor
P.24
P.73
U7100
P.21
I2
J7300
BOOT ROM
1M X 8
P.58
BOOTROM
P.21
P.61
33MHZ
16/32 BITS
3.3V/5V
AIRPORT
Connector
P.60
TI PCI1510
CardBus
Controller
P.61
PCI
PCI BUS
32BITS
33MHZ
P.59
MAXBUS
P.32
DDR2 MEMORY
1.5V/3.3V
32BITS
66MHZ
ATI
M11P
P.43
P.47
MEMORY BUS
1.8V
MAXBUS
1.8V
167MHZ
32BIT ADDR
64BIT DATA
J5000/J5200
P.44-53
167MHZ
64BITS
J6950
J6900
J7060
U7500
(x2 Channels)
NEC USB2.0
EHCI HC
P.62
MEMORY CH A
U6200/U6250
MEMORY CH B
U6300/U6350
LEFT USB2
CONN
BlueTooth (1.1)
RIGHT USB2
CONN
Trackpad (1.1)
P.60
P.30
DDC
P.50
RGB
TMDS
LVDS
(MPC7448)
P.33-35
COMPOSITE
CPU
EDID (I2C)
P.40/41
S-VIDEO
DDR2 SDRAM DIMM 1

SO-DIMM Connector
A7PM
240MHZ
64BITS
P.49
DDR2 SDRAM DIMM 0
U3600
32BITS
33MHZ
3.3V
MEMORY BUS
1.8V
U5700
(VIA SIL1178)
AGP BUS
4X AGP
U7400
P.29
VIA/PMU
U2100
CARDBUS
Connector
P.25
Serial Debug
Connector
SCCA
J7400
128MB
System Block Diagram

SYNC_MASTER=N/A
SYNC_DATE=N/A

J7000
Inverter
Connector
CPU PLL
Config
P.7
P.56
LCD Panel
Connector
P.56
S-Video
Connector
P.57
DVI-I
Connector
P.57

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
3
115
SHT
OF
NONE
POWER SYSTEM ARCHITECTURE

5V_PWRON
BACKLIGHT
>~13.44V TURNS-ON
+
<~13.44V SHUTS-OFF
INVERTER
RUN/SS
AC
INRUSH
LIMITER
ADAPTER
+24V_PBUS
IN
BUCK
REGULATOR
VCC
(LTC1625)
14V_PBUS
VCC
MAIN 1.8V/1.5V
DC/DC
(MAX1715)
+PBUS
NO AC: BATTERY VOLTAGE

1625 NOT RUNNING
3V3_ALL
LDO
5V_PWRON
VCC
DC/DC
(MAX1717)
5V_PWRON
PMU
3V3_ALL
RUN/SS
- 5V
TURNS ON AT >1V
5V_PWRON
<100UA ALLOWED
INTERNAL ZENER CLAMP TO 6V
MAIN 3V/5V
PGOOD
DC/DC
(LTC3707)
VCC
STBYMD
14V_PBUS
BACKUP
AGP I/O
ON1/ON2
RC AT 1M*0.047UF @ 24V
4V6_ALL
1V5_PWRON
TURNS ON OUTPUT @ 2.4V
SHUTDOWN: RUNNING
SLEEP: RUNNING
RUN: RUNNING
+BATT
1V8_1V5_OK
SHUTDOWN: STOPPED
SLEEP: RUNNING
RUN: RUNNING
AC: 12.8V
5V_PWRON
1V8_PWRON
PGOOD
+PBUS
MAXBUS
VRAM CORE
VRAM I/O
DDR2 POWER
1V20_REF -
+PBUS
3V_5V_OK
TURNS CONTROL TO RUN/SS

WHEN ITS OPEN
GPU_VCORE
+1.3V
CPU_VCORE
(+1.3V)
RUN/SS
3V3_PWRON
INTERNAL ZENER CLAMP TO 6V

<100UA ALLOWED
TURNS ON AT >1V
BATTERY
DC/DC
(LTC1778)
TURNS ON AS LOW AS 0.8V/TYP 1.5V
INTERNAL 1.2UA CURRENT SOURCE
SHUTDOWN: STOPPED
SLEEP: RUNNING
RUN: RUNNING
14V CHARGES BACKUP BATTERY
VCC
SHUTDOWN: STOPPED
SLEEP: STOPPED
RUN: RUNNING
HOLDS BOTH RUN/SS AT GND

WHEN ITS CONNECTED TO GND
SHUTDOWN: STOPPED
SLEEP: STOPPED
RUN: RUNNING
EXT_VCC
RUN/SS - 3V
POWER SEQUENCE
24V IS OUTPUT ONLY FROM
BACKUP BATTERY
(CONTROLLED BY PMU)
RC AT 1M*0.1UF @ 24V
CHARGER INPUT
NO INRUSH PROTECTION
& BOOST OUTPUT
WHEN ONLY BATTERY IS CONNECTED
+24V_PBUS
BACKUP BATTERY CIRCUIT CHARGES OFF +PBUS
SHUT-DOWN
DC/DC
(LTC3412)
RUN
SLEEP
RUN
SHUT-DOWN
SLEEP
2V5_PWRON
SHUTDOWN: STOPPED
SLEEP: RUNNING
RUN: RUNNING
AND PREVENTS +PBUS AND +24V_PBUS FROM DROPPING BELOW 6V
5V_PWRON
5V_RUN
(UNTIL DRAINED)
BATTERY
CHARGER
(MAX1772)
DC/DC
(LTC3412)
I2
CORE
+1.5V
SHUTDOWN: STOPPED
SLEEP: RUNNING
RUN: RUNNING
+BATT
NO INRUSH PROTECTION
3S 2P 18650 CELLS
WHEN ONLY BATTERY IS CONNECTED
BATTERY VOLTAGE
+PBUS
FEED-IN PATH
~2.23MS
~7.36MS
3V3_PWRON
3V3_RUN
3V_5V_OK
2V5_PWRON
2V5_RUN
1V8_PWRON
1V8_RUN
INCORRECT
2.4V - ??? MS
??? MS
??? MS
1V5_PWRON
Power Block Diagram
1V5_RUN
SYNC_MASTER=N/A
CPU_VCORE
SYNC_DATE=N/A
~8.2MS

GPU_VCORE

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
4
115
SHT
OF
NONE
REVISION HISTORY
EVT
04/04/2005 - Beginning revision history

- Made DDR2 and FB pin swaps as requested by CM
04/06/2005 - Modem connector moved to non-shared page
- Chassis grounds partitioned as in previous products
- CPU0 Vcore A/B select line hooked to I2 GPIO1
04/06/2005 - Made additional FB pin swaps
- Changed DDR2 CS/CKE RPAKs to RPAK2P (added RP4871, RP4876)
04/11/2005 - Implemented more DDR2 pin swaps
- Implemented FireWire pin swaps
- Added remaining spacing and physical rule tables
- Added upper LVDS channel to functional test page
- Changed battery sense resistor to 0.006 ohm (R1250)
- Stuffed R2903 to disable FW port power when off on AC
- Changed audio caps to X5R (CA033, CA050, CA051)
04/12/2005 - Corrected MIN_LINE_WIDTH properties on PP3V3_PWRON
- Corrected TMDS DIFFERENTIAL_PAIR properties at DVI connector
- Reduced MIN_NECK_WIDTH property on GND to 0.2 mm for TMDS parts
- Corrected line and neck width properties
- Added RAM_DQS_N pulldowns
- Added high/low swing BOMOPTIONs for DVO on SI TMDS parts
- Added 1.5V DVO option to GPU
04/13/2005 - Removed series R isolating VG from digital ground on FW ports (per design guide)
04/14/2005 - Changed GPU to M11
04/15/2005 - Moved FB series R to page 61
- Updated straps, VREF inputs and decoupling on GPU
04/18/2005 - Corrected synonym problems on PMU port usage
- Added CPU0 VCore VID mux
04/19/2005 - Added NO_TEST properties to buses between JTAG enabled devices
04/20/2005 - Corrected ENET power rail to PWRON from RUN (for Wake-on-LAN)
- Fixed ENET_LOWPWR and VESTA_RESET circuits per Vesta design guide
- Changed R5880 to 6.34K to take GPU Vcore to 1.3V/1.05V
- Added page 6 and modified pages 11,35,81 for design specific pin swaps
04/21/2005 - Corrected STOP_AGP_L net name (hooked to I2 now) and removed redundant pullup
04/22/2005 - Added external pullups to replace missing internal I2 pullups
- Added ADC caps at PMU
- Corrected load capacitance for Vesta FireWire crystal (to 18pF)
- Disconnected FW_POWERDOWN from Vesta LPWR_1394 pin
- Corrected pulldown resistor value for 0.006 ohm battery current sense
05/03/2005 - Changed 220uF CPU VCore caps to 330 uF LF caps
- Changed GPU FB MVREFs into separate dividers
- Pinswapped UATA I/F, DVO I/F, USB pulldowns
- Added extra cap at input to I2 USBAVDD
05/04/2005 - Added pulldowns to unused serial debug signals (DTR/RTS)
05/05/2005 - Added pulldown to Vesta LPWR_1394
- Added PDIAG signal between HDD and ODD connectors
05/10/2005 - Various Pb-free component replacements
- Pinswaps for I2 RPAKs to match up with Q41C style layout
- Added Hynix VRAM option and PCBAs
- Added TBEN sync circuit
- Added DASP signal between HDD and ODD connectors
05/21/2005 - Corrected AGP_INT_L connection between I2 and GPU
- Corrected VGA sync connections at GPU
05/23/2005 - Release as REV 01 for Pre-EVT/EVT
05/24/2005 - Added NEC USB2 controller
05/25/2005 - Added ZDB clock buffer for PCI clocks
- Various Pb-free component replacements
05/26/2005 - Removed SMS PIC microcontroller
05/31/2005 - Added 2 0.1uF caps to GPU Vcore regulator output
- Corrected USB2 diff pair and spacing/physical rules on port connections
06/01/2005 - Corrected FireWire VP caps to 50V
- Various Pb-free component replacements
06/02/2005 - Released as REV 02 for EVT
06/03/2005 - Changed PCI clock series Rs to 0 ohms
- Changed CPU clock series Rs to 10 ohms
- Released as REV 03 for EVT
06/07/2005 - Updated BOM options on CPU Vcore and AVDD for 1.22,1.30, and 1.33V
- Corrected alternate errors and a leaded table item
- Released as REV 04 for EVT
DVT
06/28/2005 07/06/2005 07/08/2005 07/09/2005 07/14/2005 07/18/2005 07/19/2005 07/22/2005 07/25/2005 07/26/2005 07/29/2005 -
Added 10K pullup to VIA_REQ_L

Changed Q2941 to level shift/pass FET to correct GPU VCore and CPU Vcore power sequencing
Moved R2943 to SYS_PWRSEQ_1_L to correct trackpad power state in sleep
Moved =PP3V3_I2C_SB to RUN rail to correct pumpup problem in sleep
Changed to USB1P1_NEC BOMOPTION
Various Pb-free replacements
Changed TMDS drive strength resistors to 301 ohm, which was built at EVT
Added FET to allow PMU control of trackpad power sequencing
Added resistor mux for I2s MAXBUS I/O rail (PWRON vs RUN)
Changed CPU Vcore to 2-states only (no MUX)
Removed I2s connection to TBEN (leakage path)
Removed 1.5GHz config
Changed 32.768kHz crystal to new APN specifing 1uW drive parts
Added line width constraints to LTC1625 and CPU Vcore gate nodes
Added external 1K pullups in parallel with all I2 internal pullups
Changed NEC USB2 series R value to 39.2 ohm
Added 150 ohm pulldowns to FW_CTL lines at Vesta
Changed TMDS transmitter ferrites to part with higher current rating (1.5A)
Added BOMOPTIONs for and stuffed CPU Vcore at 1.28V and 1.30V
Added audio mute sequencing FETs
Moved UATA_DSTROBE cap to other side of series resistor
Released as REV 06 for DVT
Changed all external I2 GPIO pullups to 10K
Stuffed R2452, R2462, R2463 to correct I2 2.5V pullup problem
Replaced 371S0299 with 371S0300
Swapped I2_MAXBUS_33OHM and I2_MAXBUS_50OHM BOMOPTIONs
Changed to Vesta v1.4 as primary U8500, Vesta v1.3 as alternate
Changed PCI ZDB output series term to 22 ohms
Swapped locations (i.e values) of C2500 and C2501
Released as REV 07 for DVT
Pre-PVT
08/02/2005
08/03/2005
08/05/2005
08/16/2005
08/17/2005
08/18/2005
08/22/2005
08/24/2005
Added R0985 10K pull down on JTAG_CPU0_TCK

Added R3772 10K pull down on CPU0_EXT_QUAL on Mullet and syncd
Changed R2949 to NO STUFF for BOM.
Changed C1721 and C2205 to 2200pF
Changed C1730 to 5.6pF
Changed C1700 and C1701 and C2215 andC2216 to 47uF
Changed R1720 and R2205 to 7.5K
Changed C3940-C3947 to 1206 ceramic caps
Changed power supply jumpers to shorts
Added five ceramic caps to Vcore supply
Changed D1460,D1461 to 60V schottky to reduce reverse leakage
Changed R2958 to 10K for improved power sequencing timing
Added FETs to prevent leakage onto Vesta rails
Changed C8600-C8603 to 1uF due to insertion of FET
Changed R5822 to 100K for power sequence improvement
NO STUFFed R2969 for power sequence improvement
Released as REV 08 for Pre-PVT
PVT
08/29/2005 - Released as REV A for PVT
08/31/2005 - Stuffed R8420 with 10K, 5% to ensure MDIO logic levels
09/02/2005 - Stuffed R2464 to correct unused GPIO logic level
- Changed MLB to 820-1940, which corrects tolerance on DIMM conn holes
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
115
5
SHT
OF
NONE
I2S Series Rs
D
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
22
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
22
22
22
22
22
22
22
I2S0_SB_TO_DEV_DTO_R
I2S0_BITCLK_R
I2S0_MCLK_R
I2S0_SYNC_R
=RP1150P1
=RP1150P2
=RP1150P3
=RP1150P4
I2S1_SYNC_R
I2S1_MCLK_R
I2S1_BITCLK_R
=RP1151P1
=RP1151P2
=RP1151P3
=RP1151P4
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
63
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
63
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
63
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
63
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
63
63
63
63
63
63
63
63
63
63 2
63 2
63 2
63
63 2
63
63 2
UATA_DD_R<12>
UATA_CS0_L_R
UATA_DD_R<14>
UATA_DD_R<11>
=RP8150P1
=RP8150P2
=RP8150P3
=RP8150P4
UATA_DD_R<7>
UATA_DD_R<2>
UATA_DD_R<3>
UATA_DD_R<15>
=RP8151P1
=RP8151P2
=RP8151P3
=RP8151P4
UATA_DD_R<9>
UATA_DD_R<4>
UATA_DD_R<6>
UATA_DD_R<5>
=RP8152P1
=RP8152P2
=RP8152P3
=RP8152P4
UATA_DA_R<2>
UATA_DD_R<8>
UATA_DD_R<10>
UATA_DA_R<0>
=RP8153P1
=RP8153P2
=RP8153P3
=RP8153P4
UATA_DD_R<13>
UATA_DD_R<0>
UATA_DD_R<1>
UATA_DA_R<1>
=RP8154P1
=RP8154P2
=RP8154P3
=RP8154P4
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
63
=RP1150P8
=RP1150P7
=RP1150P6
=RP1150P5
I2S0_SB_TO_DEV_DTO
I2S0_BITCLK
I2S0_MCLK
I2S0_SYNC
=RP1151P8
=RP1151P7
=RP1151P6
=RP1151P5
I2S1_SB_TO_DEV_DTO
I2S1_SYNC
I2S1_MCLK
I2S1_BITCLK
=RP8150P8
=RP8150P7
=RP8150P6
=RP8150P5
UATA_DD<12>
UATA_CS0_L
UATA_DD<14>
UATA_DD<11>
=RP8151P8
=RP8151P7
=RP8151P6
=RP8151P5
UATA_DD<7>
UATA_DD<2>
UATA_DD<3>
UATA_DD<15>
=RP8152P8
=RP8152P7
=RP8152P6
=RP8152P5
UATA_DD<9>
UATA_DD<4>
UATA_DD<6>
UATA_DD<5>
=RP8153P8
=RP8153P7
=RP8153P6
=RP8153P5
UATA_DA<2>
UATA_DD<8>
UATA_DD<10>
UATA_DA<0>
=RP8154P8
=RP8154P7
=RP8154P6
=RP8154P5
UATA_DD<13>
UATA_DD<0>
UATA_DD<1>
UATA_DA<1>
MAXBUS Pullups
MAKE_BASE=TRUE 33
MAKE_BASE=TRUE
MAKE_BASE=TRUE 33
MAKE_BASE=TRUE
32
32
32
MAKE_BASE=TRUE 33
MAKE_BASE=TRUE
MAKE_BASE=TRUE 33
MAKE_BASE=TRUE 33
32
MAKE_BASE=TRUE
MAKE_BASE=TRUE 33
MAKE_BASE=TRUE 34
MAKE_BASE=TRUE
32
32
32
32
32
32
32
MAKE_BASE=TRUE 33
MAKE_BASE=TRUE
MAKE_BASE=TRUE 33
32
MAKE_BASE=TRUE 33
MAKE_BASE=TRUE
MAKE_BASE=TRUE 33
32
32
32
32
32
MAXBUS_TS_L
MAXBUS_CPU1_BG_L
MAXBUS_CPU0_DBG_L
NC_MAXBUS_I2_TBEN
NO_TEST=YES
MAXBUS_CPU0_BG_L
MAXBUS_CPU1_HIT_L
MAXBUS_CPU0_HIT_L
MAXBUS_CPU0_BR_L
=RP3510P1
=RP3510P2
=RP3510P3
=RP3510P4
7 74
7 74
7 74
7 74
30
30
30
30
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
53
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
53
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
53
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
53
MAXBUS_CPU1_BR_L
MAXBUS_TA_L
MAXBUS_CPU0_INT_L
MAXBUS_CPU1_INT_L
=RP3512P1
=RP3512P2
=RP3512P3
=RP3512P4
=RP3511P1
=RP3511P2
=RP3511P3
=RP3511P4
MAXBUS_CPU0_DRDY_L
MAXBUS_CPU1_DRDY_L
MAXBUS_AACK_L
=RP3513P2
=RP3513P3
=RP3513P4
MAXBUS_ARTRY_L
MAXBUS_CPU1_DBG_L
MAXBUS_TEA_L
=RP3514P1
=RP3514P2
=RP3514P3
7 63 64
7 63 64
7 63 64
7 63 64
7 63 64
7 63 64
7 63 64
7 63 64
7 63 64
7 63 64
7 63 64
7 63 64
7 63 64
7 63 64
7 63 64
7 63 64
7 63 64
7 63 64
7 63 64
7 63 64
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
(IDE_CS1FX_L)
53
53
53
53
53
53
53
53
53
53
53
53
GPU_DVOD_R<16>
GPU_DVOD_R<4>
GPU_DVOD_R<7>
GPU_DVOD_R<6>
=RP6720P1
=RP6720P2
=RP6720P3
=RP6720P4
GPU_DVOD_R<11>
GPU_DVOD_R<9>
GPU_DVOD_R<10>
GPU_DVO_HSYNC_R
=RP6721P1
=RP6721P2
=RP6721P3
=RP6721P4
GPU_DVOD_R<3>
GPU_DVOD_R<5>
GPU_DVOD_R<13>
GPU_DVOD_R<12>
=RP6722P1
=RP6722P2
=RP6722P3
=RP6722P4
GPU_DVOD_R<2>
GPU_DVOD_R<1>
GPU_DVOD_R<0>
GPU_DVOD_R<14>
=RP6723P1
=RP6723P2
=RP6723P3
=RP6723P4
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
32
32
32
32
32
32
32
MAKE_BASE=TRUE 44
MAKE_BASE=TRUE 44
MAKE_BASE=TRUE 44
MAKE_BASE=TRUE 44
43
MAKE_BASE=TRUE 44
MAKE_BASE=TRUE 44
MAKE_BASE=TRUE 44
MAKE_BASE=TRUE 44
43
43
43
43
43
43
43
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
53
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
53
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
53
53
53
53
53
53
53
53
53
53 2
GPU_DVO_DE_R
GPU_DVO_VSYNC_R
GPU_DVO_CLKP_R
GPU_DVOD_R<8>
=RP6821P1
=RP6821P2
=RP6821P3
=RP6821P4
GPU_DVOD_R<21>
GPU_DVOD_R<19>
GPU_DVOD_R<17>
GPU_DVOD_R<15>
=RP6822P1
=RP6822P2
=RP6822P3
=RP6822P4
GPU_DVOD_R<20>
GPU_DVOD_R<22>
GPU_DVOD_R<23>
GPU_DVOD_R<18>
=RP6823P1
=RP6823P2
=RP6823P3
=RP6823P4
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
AGP_TRDY_L
AGP_IRDY_L
AGP_REQ_L
AGP_RBF_L
=RP5610P1
=RP5610P2
=RP5610P3
=RP5610P4
AGP_FRAME_L
AGP_DEVSEL_L
AGP_STOP_L
AGP_GNT_L
=RP5611P1
=RP5611P2
=RP5611P3
=RP5611P4
43
72
43
72
43
72
43
72
43
72
43
72
43
72
43
72
72
PCI Pullups
32
32
MAKE_BASE=TRUE
MAKE_BASE=TRUE 60
62
MAKE_BASE=TRUE 60
62
MAKE_BASE=TRUE 60
32
32
11
59
61
59
61
59
62 61
32
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE 60
32
32
32
11
11
11
59
62 61
GPU_DVOD<16>
GPU_DVOD<4>
GPU_DVOD<7>
GPU_DVOD<6>
=RP6721P8
=RP6721P7
=RP6721P6
=RP6721P5
GPU_DVOD<11>
GPU_DVOD<9>
GPU_DVOD<10>
GPU_DVO_HSYNC
=RP6722P8
=RP6722P7
=RP6722P6
=RP6722P5
GPU_DVOD<3>
GPU_DVOD<5>
GPU_DVOD<13>
GPU_DVOD<12>
=RP6723P8
=RP6723P7
=RP6723P6
=RP6723P5
GPU_DVOD<2>
GPU_DVOD<1>
GPU_DVOD<0>
GPU_DVOD<14>
55
54
54
54
54
54
54
54 55
54
54
55
55
54
54
54
55
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=RP6821P8
=RP6821P7
=RP6821P6
=RP6821P5
GPU_DVO_DE
GPU_DVO_VSYNC
GPU_DVO_CLKP
GPU_DVOD<8>
=RP6822P8
=RP6822P7
=RP6822P6
=RP6822P5
GPU_DVOD<21>
GPU_DVOD<19>
GPU_DVOD<17>
GPU_DVOD<15>
=RP6823P8
=RP6823P7
=RP6823P6
=RP6823P5
GPU_DVOD<20>
GPU_DVOD<22>
GPU_DVOD<23>
GPU_DVOD<18>
54 55
54 55
54 55
54
55
55
55
55
55
55
55
55
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
USB Pulldowns
32
32
=RP6720P8
=RP6720P7
=RP6720P6
=RP6720P5
Upper DVO Series Rs
AGP Pullups
32
Lower DVO Series Rs
UATA Series Rs
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
72
72
PCI_AIRPORT_GNT_L
PCI_TRDY_L
PCI_IRDY_L
PCI_STOP_L
=RP7250P1
=RP7250P2
=RP7250P3
=RP7250P4
PCI_CBUS_REQ_L
PCI_AIRPORT_REQ_L
PCI_CBUS_GNT_L
PCI_FRAME_L
=RP7251P1
=RP7251P2
=RP7251P3
=RP7251P4
72
=RP9210P8
=RP9210P7
=RP9210P6
=RP9210P5
USB_I2_BT_P
USB_I2_BT_N
USB2_I2_RIGHT_PORT_N
USB2_I2_RIGHT_PORT_P
=RP9211P8
=RP9211P7
=RP9211P6
=RP9211P5
USB2_I2_P<1>
USB2_I2_N<1>
USB2_I2_N<3>
USB2_I2_P<3>
=RP9212P8
=RP9212P7
=RP9212P6
=RP9212P5
USB_I2_TPAD_N
USB_I2_TPAD_P
USB2_I2_LEFT_PORT_P
USB2_I2_LEFT_PORT_N
=RP9300P8
=RP9300P7
=RP9300P6
=RP9300P5
USB2_NEC_LEFT_PORT_P
USB2_NEC_LEFT_PORT_N
USB2_NEC_RIGHT_PORT_N
USB2_NEC_RIGHT_PORT_P
=RP9301P8
=RP9301P7
=RP9301P6
=RP9301P5
USB_NEC_BT_P
USB_NEC_BT_N
USB_NEC_TPAD_N
USB_NEC_TPAD_P
11
11
11
11
72
72
72
72
11
11
11
11
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
59
59
73
59
73
59
73
73
11
11
11
11
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
59
59
73
59
73
59
73
73
11
2 11
11
11
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
FW Series Rs
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
68 9
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
68 9
68 9
68 9
68 9
68 9
68 9
68 9
FW_D_R<7>
FW_D_R<3>
FW_D_R<4>
FW_D_R<2>
=RP9100P1
=RP9100P2
=RP9100P3
=RP9100P4
FW_D_R<0>
FW_D_R<6>
FW_D_R<1>
FW_D_R<5>
=RP9101P1
=RP9101P2
=RP9101P3
=RP9101P4
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
71
=RP9100P8
=RP9100P7
=RP9100P6
=RP9100P5
FW_D<7>
FW_D<3>
FW_D<4>
FW_D<2>
=RP9101P8
=RP9101P7
=RP9101P6
=RP9101P5
FW_D<0>
FW_D<6>
FW_D<1>
FW_D<5>
9 69
9 69
9 69
9 69
9 69
9 69
9 69
9 69
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
Q16C Pin Swaps
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
6
115
SHT
OF
NONE
Enhanced MAC-1 Test Coverage

D
Functional test points use a P6 pad placed on bottom side.
I1
I2
I4
POWER
I3
I6
I5
I7
I8
I9
I10
I62
PP24V_ADAPTER
PP24V_ALL_PBUSA
PP12V8_ALL_PBUSB
PPVCORE_RUN_GPU
PPVCORE_RUN_CPU
PP1V8_PWRON
PP2V5_PWRON
PP5V_PWRON
PP3V3_PWRON
PP5V_RUN
PP3V3_ALL
=FTP_GND
10
10
10
10
10
10
10
10
10
10
10
7 10
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
Place 2 TPs @ connector
I76
I77
I78
I88
I89
Place within 50 mm
of power supply.
SYSTEM
I121
I43
I45
I30
I29
I31
I87
Place 5-10 GND TPs.
I90
I91
I105
LVDS
I86
I11
I12
I13
I14
I16
I15
I17
I18
I19
I20
I21
INVERTER
I63
I22
I23
I25
I24
I96
I117
I118
I32
I33
UATA
I35
I34
I36
I38
I37
I40
I39
I41
I42
I75
I60
I59
I61
I44
I46
I48
I47
I50
AUDIO
I49
I51
I53
I52
I56
I55
I57
I58
I107
I108
I109
I110
I111
I112
I113
PPBUS_INVERTER
PP5V_INV_SW
BRIGHT_PWM
GND_INVERTER
=PP5V_RUN_ODD
=PP5V_RUN_HDD
PP3V3R5V_RUN_HDD_LOGIC
UATA_DD<15..0>
UATA_DMARQ
UATA_DSTROBE
UATA_DMACK_L
UATA_DA<2..0>
UATA_CS0_L
UATA_CS1_L
UATA_RESET_L
UATA_HSTROBE
UATA_STOP
UATA_INTRQ
PP5V_PWRON_AUDIO_PVDD
PP5V_PWRON_AUDIO_AVDD
PP3V3_PWRON_AUDIO_AVDD
=PP3V3_RUN_AUDIO
=I2C_AUDIO_SCL
=I2C_AUDIO_SDA
I2S0_MCLK
I2S0_BITCLK
I2S0_SYNC
I2S0_SB_TO_DEV_DTO
I2S0_DEV_TO_SB_DTI
AUDIO_LO_MUTE_L
AUDIO_SPKR_MUTE_L
AUDIO_CODEC_RESET_L
AUDIO_SPDIFRX_RESET_L
AUDIO_LO_DET_L
AUDIO_LI_DET_L
AUDIO_LO_OPTICAL_PLUG_L
AUDIO_LI_OPTICAL_PLUG_L
AUDIO_I2S_DTIB_SEL
AUDIO_EXT_MCLK_SEL
AUDIO_GPIO_11
GND_AUDIO_AGND
GND_AUDIO_PGND
53 56
53 56
53 56
53 56
53 56
53 56
53 56
53 56
53 56
53 56
53 56
51 56
51 56
10 56
56
56
56
56
56
10 64
10 64
64
6 63 64
63 64
63 64
63 64
6 63 64
6 63 64
63 64
63 64
63 64
63 64
63 64
74
74
74
10 74
8 74
8 74
6 74
6 74
6 74
6 74
22 74
22 74
22 74
22 74
22 74
22 74
22 74
22 74
22 74
22 74
22 74
22 74
74
74
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
CPU FAN
53 56
Place within 25 mm
of LVDS connector.
GPU FAN
I85
53 56
ALS
I84
53 56
SCCA
I83
I106
Place within 25 mm
of inverter connector.
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
Place within 50 mm
of ODD/HDD connector.
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
Place within 25 mm
of audio connector.
BATT
I82
53 56
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
BACKUP
I81
53 56
RT USB
I80
LVDS_U0_P
LVDS_U0_N
LVDS_U1_P
LVDS_U1_N
LVDS_U2_P
LVDS_U2_N
CLKLVDS_U_P
CLKLVDS_U_N
LVDS_L0_P
LVDS_L0_N
LVDS_L1_P
LVDS_L1_N
LVDS_L2_P
LVDS_L2_N
CLKLVDS_L_P
CLKLVDS_L_N
LVDS_DDC_CLK
LVDS_DDC_DATA
=PP3V3_DDC_LCD
PP3V3_LCD_CONN
LT USB
I79
I100
I98
I97
I119
I102
I101
I104
I120
I70
I68
I69
I72
I71
I73
I74
I64
I65
I66
I114
I116
I115
PP5V_TPAD_F
USB_TPAD_P
USB_TPAD_N
PP3V3_PWRON_DS1775_R
SYS_OVERTEMP_L
PP3V3_ALL_HALL_EFFECT_R
SYS_LID_OPEN_F
SYS_POWER_BUTTON_L_F
=FTP_SLEEP_LED
SYS_CHARGE_LED_L
SYS_ADAPTER_ANALOG_AC_DET
KBDLED_ANODE
KBDLED_RETURN
=I2C_DS1775_SDA
=I2C_DS1775_SCL
=PP5V_FAN1_PWR
FAN1_TACH
FAN1_PWM
=FTP_GND
=PP5V_FAN2_PWR
FAN2_TACH
FAN2_PWM
=FTP_GND
=PP3V3_PWRON_LEFT_ALS
ALS_0_OUT
ALS_GAIN_BOOST
SCCA_RXD
SCCA_TXD_L
=PPVIO_BU_BATT
=PPVOUT_BU_BATT
=PP5V_PWRON_RIGHT_USB
USB2_RIGHT_PORT_P
USB2_RIGHT_PORT_N
=PP5V_PWRON_LEFT_USB
USB2_LEFT_PORT_P
USB2_LEFT_PORT_N
30
11 30
11 30
30
11 25 30
30
30
30
30
24 74
12 74
28 30
28 30
8 30
8 30
10 31
27 31
27 31
7 10
10 31
27 31
27 31
7 10
10 31
25 31
25 28 31
22 24
22 24
10 31
10 31
10 31
11 31
11 31
10 74
11 74
11 74
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
Place within 25 mm
of TPAD connector.
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
Place within 25 mm
of fan connector.
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
Place within 25 mm
of fan connector.
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
Place within 25 mm
of ALS connector.
FUNC_TEST=YES
FUNC_TEST=YES
Place within 25 mm
of debug connector.
FUNC_TEST=YES
FUNC_TEST=YES
Place within 25 mm
of battery connector.
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
Place within 25 mm
of right USB connector.
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
Place within 25 mm
of left USB connector.
Functional Test Points

SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
7
115
SHT
OF
NONE
8
ELECTRICAL_CONSTRAINT_SET
I2C_NB
I2C_NB
7
NET_TYPE
SPACING PHYSICAL
DIFFERENTIAL_PAIR
I2C
I2C
I2C
I2C
I2C_PMU_SMB_SCL
I2C_PMU_SMB_SDA
I2C
I2C
I2C
I2C
I2C_PMU_SCL
I2C_PMU_SDA
I2C
I2C
I2C
I2C
I2C_I2_NB_SCL
I2C_I2_NB_SDA
I2C
I2C
I2C
I2C
I2C_I2_SB_SCL
I2C_I2_SB_SDA
I2C
I2C
I2C
I2C
I2C_GPU_TMDS_SCL
I2C_GPU_TMDS_SDA
SouthBridge I2C Bus
8
8
8
8
10
=PPI2C_I2_SB
8
8
R08401
I2
1K
U2100
(MASTER)
5%
1/16W
MF-LF
402 2
8
8
22
=I2C_I2_SB_SCL
22
=I2C_I2_SB_SDA
Audio Board
R0841
1K
JA000
(Write: 0x8C Read: 0x8D)
(Write: 0x22 Read: 0x23)
=I2C_AUDIO_SCL
7 74
5%
1/16W
MF-LF Codec
2 402
SPDIF
I2C_I2_SB_SCL
MAKE_BASE=TRUE
I2C_I2_SB_SDA
MAKE_BASE=TRUE
=I2C_AUDIO_SDA
7 74
Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:

- GOV_I2C / GOV_I2C_BYPASS
Allows bypassing Governator I2C bus.
Most devices are connected directly to
PMU unstead. One ADT7467 connects to NB
I2C bus 1 to resolve address conflict.
- MMM_PWR_ALL / MMM_PWR_PWRON
Selects whether MMM MCU is powered all
the time or only when the system is on.
ALL moves the MCU to the PMU I2C bus so
it can be monitored by in shutdown.
NOTE: Neither option is necessary when
MMM_MCU_PMU BOM option is selected.
NorthBridge I2C Bus
PMU I2C Bus

10
=PPI2C_SYS1
10
R08201
PMU
1K
U1300
(MASTER)
5%
1/16W
MF-LF
402 2
25
=I2C_PMU_SCL
25
=I2C_PMU_SDA
=PPI2C_I2_NB
R08301
I2
R0821
1K
2.0K
U2100
(MASTER)
5%
1/16W
MF-LF
2 402
I2C_PMU_SCL
MAKE_BASE=TRUE
I2C_PMU_SDA
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402 2
22
=I2C_I2_NB_SCL
22
=I2C_I2_NB_SDA
DIMMs
R0831
2.0K
J5000A / J5000B
(Write: 0xA0 / 0xA2,
Read: 0xA1 / 0xA3)
=I2C_SODIMM_SCL
40 41
5%
1/16W
MF-LF
2 402
I2C_I2_NB_SCL
MAKE_BASE=TRUE
I2C_I2_NB_SDA
MAKE_BASE=TRUE
=I2C_SODIMM_SDA
40 41
ADT7467
U3000
(Write: 0x5C Read: 0x5D)
PMU SMBus
10
=PPI2C_SYS0
PMU
R0850
7.15K
U1300
(MASTER)
1%
1/16W
MF-LF
402 2
25
=I2C_PMU_SMB_SCL
25
=I2C_PMU_SMB_SDA
R0851
7.15K
1%
1/16W
MF-LF
2 402
=I2C_ADT7467_SCL
27
=I2C_ADT7467_SDA
27
Battery Conn
DS1775
J790
I2C_PMU_SMB_SCL
MAKE_BASE=TRUE
I2C_PMU_SMB_SDA
MAKE_BASE=TRUE
=I2C_BATT_SCL
12
=I2C_BATT_SDA
12
On Trackpad Flex
=I2C_DS1775_SCL
7 30
=I2C_DS1775_SDA
7 30
GPU I2C Bus

10
=PPI2C_GPU
R08421
GPU
1K
U5700
(MASTER)
5%
1/16W
MF-LF
402 2
51
=I2C_GPU_TMDS_SCL
51
=I2C_GPU_TMDS_SDA
R0843
1K
5%
1/16W
MF-LF
2 402
EXT TMDS/M
U6700
I2C_GPU_TMDS_SCL
MAKE_BASE=TRUE
I2C_GPU_TMDS_SDA
MAKE_BASE=TRUE
=I2C_SI_M_SCL
54
=I2C_SI_M_SDA
54
EXT TMDS/S
U6800
=I2C_SI_S_SCL
55
=I2C_SI_S_SDA
55
I2C Connections
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
8
115
SHT
OF
NONE
7
10
=PPJTAG_CPU
NO STUFF
R09801
R09811
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
10K
10K
JTAG_CPU_TDI
MAKE_BASE=TRUE
D
1
R0982
PMU (BOOTBANGER)
25
=JTAG_BBANGER_TDI
25
=JTAG_BBANGER_TMS
25
=JTAG_BBANGER_TRST_L
25
=JTAG_BBANGER_TCK
CPU0
=JTAG_CPU0_TDI
34
=JTAG_CPU0_TDO
34
TP_JTAG_CPU_TDO
MAKE_BASE=TRUE
R0983
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
=JTAG_CPU0_TMS
=JTAG_CPU0_TRST_L
=JTAG_CPU0_TCK
34
34
34
Nets not requiring TPs due to JTAG
JTAG_CPU_TMS
MAKE_BASE=TRUE
JTAG_CPU_TRST_L
MAKE_BASE=TRUE
JTAG_CPU_TCK
MAKE_BASE=TRUE
NO STUFF
R09841
200
R0985
10K
5%
1/16W
MF-LF
2 402
I76
I77
MAXBUS
5%
1/16W
MF-LF
402 2
I78
I79
I80
I81
I82
I83
I85
10
MAXBUS_DATA<63..0>
MAXBUS_ADDR<31..0>
MAXBUS_CI_L
MAXBUS_GBL_L
MAXBUS_TBST_L
MAXBUS_TSIZ<2..0>
MAXBUS_TT<4..0>
MAXBUS_WT_L
MAXBUS_DTI<2..0>
21 32 33
32 33
32 33
32 33
32 33
32 33
32 33
32 33
32 33
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
=PP3V3_PWRON_JTAG_ASIC
RP0990
10K
5%
1/16W
SM-LF
3
I2
JTAG_I2_TDI
MAKE_BASE=TRUE
=JTAG_I2_TDI
22
RP0990
22
=JTAG_I2_TMS
=JTAG_I2_TRST_L
=JTAG_I2_TCK
10K
5%
1/16W
SM-LF
TP_JTAG_I2_TDO
MAKE_BASE=TRUE
=JTAG_I2_TDO
22
22
22
JTAG_ASIC_TMS
MAKE_BASE=TRUE
JTAG_ASIC_TRST_L
MAKE_BASE=TRUE
JTAG_ASIC_TCK
MAKE_BASE=TRUE
2
1K
5%
1/16W
MF-LF
402 2
RP0990
I86
10K
I87
5%
1/16W
SM-LF
I88
ENET
R09901
I89
I90
I92
I91
I93
I94
FIREWIRE
I95
I96
I97
I98
I99
I100
I101
I103
I102
ENET_MDC
ENET_MDIO
ENET_TXD<7..0>
ENET_TX_EN
ENET_TX_ER
ENET_RXD<7..0>
ENET_RX_DV
ENET_RX_ER
ENET_COL
ENET_CRS
11 65
11 65
11
11
11
11 65
11 65
11 65
11 65
11 65
FW_D_R<7..0>
FW_D<7..0>
FW_CTL_R<1..0>
FW_CTL<1..0>
FW_LPS_R
FW_LPS
FW_LREQ_R
FW_LREQ
6 68
6 69
68 71
69 71
68 71
69 71
68 71
69 71
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
VESTA
TP_JTAG_VESTA_TDI
MAKE_BASE=TRUE
=JTAG_VESTA_TDI
18
18
=JTAG_VESTA_TDO
=JTAG_VESTA_TMS
=JTAG_VESTA_TRST_L
=JTAG_VESTA_TCK
TP_JTAG_VESTA_TDO
MAKE_BASE=TRUE
18
18
18
TP_JTAG_VESTA_TMS
MAKE_BASE=TRUE
JTAG_VESTA_TRST_L
MAKE_BASE=TRUE
TP_JTAG_VESTA_TCK
MAKE_BASE=TRUE
JTAG Connections
SYNC_MASTER=N/A
SYNC_DATE=N/A
R0950
10K

5%
1/16W
MF-LF
402 2

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
9
115
SHT
OF
NONE
13
=PP14VR24V_ALL_PBUS_A
13
=PPVBATT_BATT_PBUSA
31 7
=PPVIN_ALL_LTC1625
=PPVIN_ALL_BATT_CHGR
=PPVIN_ALL_LTC3707
PP24V_ALL_PBUSA
MAKE_BASE=TRUE
VOLTAGE=24V
=PPVOUT_BU_BATT
14
18
=PP12V8_LTC1625_VREG
13
=PPVBATT_BATT_PBUSB
31 7
=PP12V8_PBUS_PMU_SUPPLY
=PPVIN_ALL_MAX1715
16
PP12V8_ALL_PBUSB
MAKE_BASE=TRUE
VOLTAGE=12.8V
=PPVIO_BU_BATT
PP3V3_VESTA
MAKE_BASE=TRUE
VOLTAGE=3.3V
15
=PP24V_PBUSA_HOLDUP_CAPS
14
=PP3V3_VESTA_REG
13
31
=PP12V8_PBUSB_HOLDUP_CAPS
=PPVIN_LTC1778_GPU
45
=PPBUS_FWPWRSW
18
=PPVIN_CPUVCORE_MAX1717 36
=PPBUS_INVERTER
56
12
31
12
14
=PPVBATT_ISNS_N
=PP24V_ADAPTER_CONN
=PPVBATT_BATT_VSNS
=PP4V85_ALL_VREG
18
=PP2V5_VESTA_LDO
18
=PP1V2_VESTA_REG
18
=PPBUS_FW_FET
31
PPBUS_DVI_PWRSW
MAKE_BASE=TRUE
VOLTAGE=12.8V
=PPBUS_DVI_PWRSW
57
36
PPVBATT_BATT
MAKE_BASE=TRUE
VOLTAGE=12.8V
PP24V_ADAPTER
MAKE_BASE=TRUE
VOLTAGE=24V
=PPVBATT_BATT
13
=PPVBATT_BATTERY_PMU_SUPPLY
PPVBATT_BATT_CHRG_VSNS
MAKE_BASE=TRUE
VOLTAGE=12.8V
PP4V85_ALL
MAKE_BASE=TRUE
VOLTAGE=4.85V
=PPVIN_BATT_CHRG_VSNS
=PP3V3_ALL_VREG
PP3V3_ALL
MAKE_BASE=TRUE
VOLTAGE=3.3V
PP2V5_VESTA
MAKE_BASE=TRUE
VOLTAGE=2.5V
PP1V2_VESTA
MAKE_BASE=TRUE
VOLTAGE=1.2V
=PP2V5_VESTA
=PP2V5_ENETFW
PPFW_CABLE_POWER
=PPFW_PHY_CPS
=PPFW_PORT1
=PPFW_PORT2
=PPFW_P3V3VESTA
=PPVCORE_CPU_REG
PPVCORE_RUN_CPU
MAKE_BASE=TRUE
VOLTAGE=1.3V
=PPVCORE_CPU0
18
18 65 66 67
69 70
69
18
66 69
18
66 69
69
70
70
18
14
20
=PP1V5_PWRON_I2PLL_LDO
PP1V5_PWRON_I2PLL
MAKE_BASE=TRUE
VOLTAGE=1.5V
=PP1V5_PWRON_I2_PLL
19
=PP1V5_PWRON_I2_USBPLL 72
37
=PPVOUT_CPU0_AVDD
PPAVDD_CPU0
MAKE_BASE=TRUE
VOLTAGE=1.22V
=PPAVDD_CPU0
35
15
=PP5V_RUN_HDDFET
=PP5V_RUN_HDD
7 64
15
=PP5V_RUN_RUNFET
PP5V_RUN_HDD
MAKE_BASE=TRUE
VOLTAGE=5V
PP5V_RUN
MAKE_BASE=TRUE
VOLTAGE=5V
35
PPVCORE_CPU_ADT7467
MAKE_BASE=TRUE
VOLTAGE=1.3V
=PPVCORE_CPU_ADT7467 27
13
XW1050
SM
=PP4V85_ALL_A29_DET
=FTP_GND
18
XW1013
SM
1
=PP24V_ADAPTER_RAW
12
=PP24V_ADAPTER_PMU_SUPPLY
=PP1V2_VESTA
=PP1V2_ENETFW
MAKE_BASE=TRUE
VOLTAGE=33V
14
12
15
C
14
GND
MAKE_BASE=TRUE
VOLTAGE=0V
14
XW1019
SM
1
=PP3V3_VESTA_1V2REG
=PP3V3_VESTA_2V5REG
=PP3V3_VESTA
=PP3V3_FW
=PP3V3_ENETFW
=PP5V_PWRON_REG
PP5V_PWRON_REG
MAKE_BASE=TRUE
VOLTAGE=5V
PP5V_PWRON
MAKE_BASE=TRUE
VOLTAGE=5V
=PP3V3_ALL_AC_DETECT 12
=PP3V3_ALL_A29_DET
12
=PP3V3_ALL_BATT_CHGR 13
=PP3V3_ALL_LTC1625_SW 14
=PPI2C_SYS0
8
=PP3V3_ALL_PBUS_ILIM 13
=PP3V3_ALL_HALL_EFFECT 30
=PP3V3_ALL_PMU
24 25
=PP3V3_ALL_PWRSEQ
26
=PP3V3_ALL_BATT0_DET 12
=PP3V3_ALL_DEBUG
24
=PP5V_PWRON_LTC1625_EXTVCC 14
=PP5V_PWRON_PMU_SUPPLY 14
=PP5V_PWRON_LTC3707_EXTVCC 15
=PP5V_PWRON_RUNFET
15
=PP5V_PWRON_PWRSEQ
26
=PP5V_PWRON_MAX1715_VDD 16
=PP5V_PWRON_TPS2211
61
=PP5V_PWRON_LTC1778_GPU_EXTVCC
=PP5V_PWRON_GPUVCORE_PWRPLAY 45
=PP5V_PWRON_CPUVCORE_PWRSEQ 36
=PP5V_PWRON_CPUVCORE_VDD 36
=PP5V_PWRON_LEFT_USB 7 74
=PP5V_PWRON_AUDIO_AVDD 74
=PP5V_PWRON_AUDIO_PVDD 74
=PP5V_PWRON_RIGHT_USB 7 31
=PP5V_PWRON_SLEEPLED 24
=PP5V_PWRON_TRACKPAD 15
=PP5V_PWRON_INVERTER 56
45
=PP5V_RUN_ODD
=PPBU_RUN_FW
=PP5V_RUN_FANPWM
=PP5V_RUN_KEYBRD_LED
=PP5V_RUN_DVI_DDC
=PP5V_FAN1_PWR
=PP5V_FAN2_PWR
=PP5V_RUN_PWRSEQ
26
30
7 64
18
27
28
57
7 31
7 31
15
=PP5V_TPAD_FET
PP5V_TPAD
MAKE_BASE=TRUE
VOLTAGE=5V
=PP5V_TPAD
15
=PP3V3_RUN_RUNFET
PP3V3_RUN
MAKE_BASE=TRUE
VOLTAGE=3.3V
=PP3V3_RUN_SI
54 55
=PP3V3_RUN_KEYBRD_LED 28
=PP3V3_PCI_AIRPORT
60
=PP3V3_RUN_PCI1510_R 61
=PP3V3_RUN_HDD
64
=PP3V3_GPU_CLOCKS
52
=PP3V3_RUN_FWPORTPWRSW 18
=PP3V3_RUN_FANTACH
27
=PP3V3_GPU
10
=PPI2C_GPU
8
=PP3V3_DDC_DVI
57
=PP3V3_DDC_LCD
7 56
=PP3V3_PCI
59
XW1033
SM
PP3V3_ALL_PMU_AVCC
MAKE_BASE=TRUE
25
=PPVREF_PMU
=PP3V3_BATT_IMON
25
15
12
22
R1033
10
=PP3V3_GPU
PP3V3_GPU
MAKE_BASE=TRUE
VOLTAGE=3.3V
5%
1/8W
MF-LF
805
=PP3V3_PWRON_REG
PP3V3_PWRON_REG
MAKE_BASE=TRUE
VOLTAGE=3.3V
=PP3V3_AGP
=PP3V3_GPU_VDDR3
=PP3V3_GPU_GPIOS
=PP3V3_GPU_PWRSEQ
=PPVIN_GPU_LVDDR_LDO
43 44
47
51 53
22
52
28
52
41 40
47
65
58
52
=PP2V8_GPU_LVDDR_LDO
R1025
10
=PP2V5_GPU
5%
1/8W
MF-LF
805
PP2V8_GPU_LVDDR
MAKE_BASE=TRUE
VOLTAGE=2.8V
=PP2V8_GPU_LVDS_IO
PP2V5_GPU
MAKE_BASE=TRUE
VOLTAGE=2.5V
=PP2V5_GPU_LVDS_IO
=PP2V5_GPU_PVDD
=PP2V5_GPU_PWRSEQ
=PP2V5_GPU_A2VDD
R1015
10
=PP1V5_GPU
PP1V5_GPU
MAKE_BASE=TRUE
VOLTAGE=1.5V
5%
1/8W
MF-LF
805
R1018
10
=PP1V8_GPU
PP1V8_GPU
MAKE_BASE=TRUE
VOLTAGE=1.8V
5%
1/8W
MF-LF
805
53
53
=PP1V8_GPU_AVDD
=PP1V8_GPU_TPVDD
XW1012
SM
45
=PPVCORE_GPU_REG
PPVCORE_GPU_REG
MAKE_BASE=TRUE
VOLTAGE=1.3V
PPVCORE_RUN_GPU
MAKE_BASE=TRUE
VOLTAGE=1.3V
22
19
=PP1V5_AGP
=PP1V5_GPU_VDD15
=PP1V5_GPU_PWRSEQ
=PP1V5_GPU_DVO
=PP1V8_GPU_PANEL_IO
=PP1V8_GPU_DVO
=PP1V8R2V5_GPU_FB_VIO
=PP1V8_FB_VDD
=PP1V8_FB_VDDQ
=PP1V8_GPU_PWRSEQ
=PP1V8_GPU_MEMVMODE
=PP1V05R1V3_GPU_VCORE
19
47
19
51
26
52
66
PP3V3_PWRON
MAKE_BASE=TRUE
VOLTAGE=3.3V
=PP3V3_AUDIO_MUTESEQ
=PPI2C_I2_NB
=PPI2C_SYS1
=PP3V3_PWRON_JTAG_ASIC
=PP3V3_PWRON_I2_MISC
=PP3V3_PWRON_RT_ALS
=PP3V3_PWRON_VDDSPD
=PP3V3_PCI_ROM
=PP2V5R3V3_PWRON_I2_ENET
=PP3V3_I2_PCISLOTEGPIOS
=PP3V3_PWRON_I2_AGPPCI
=PP3V3_PWRON_I2_IO1
=PP3V3_PWRON_I2_IO2
=PP3V3_PWRON_PWRSEQ
=PP3V3_ENET
XW1025
SM
53
43 44 47
17
46
52
47
=PP2V5_PWRON_REG
PP2V5_PWRON_REG
MAKE_BASE=TRUE
VOLTAGE=2.5V
=PP3V3_PWRON_MMM
29
=PP3V3_PWRON_RUNFET
15
=PP3V3_PWRON_LTC3412 17
=PP3V3_PWRON_TPS2211 61
=PP3V3_ADT7467
27
=PP3V3_PWRON_CPUVCORE_VID 36
=PP3V3_PWRON_CPUVCORE_OFFSET
=PP3V3_PWRON_BT
60
=PP3V3_PWRON_AUDIO_AVDD 74
=PP3V3_PWRON_PMU
25
=PP3V3_PWRON_MODEM
30
=PP3V3_PWRON_LEFT_ALS 7 31
=PP3V3_PWRON_DS1775
30
=PP3V3_PWRON_VGASYNC 57
=PP3V3_PWRON_LCD
56
=PP3V3_PWRON_INVERTER 56
=PP2V7R5V5_PWRON_I2VCORE 20
=PP3V3_PWRON_I2_MAXBUS 19
=PP3V3_PWRON_USB2
73
37
26
36
61
74 7
62
62
23
8
17
16
PP2V5_PWRON
MAKE_BASE=TRUE
VOLTAGE=2.5V
=PP2V5_PWRON_RUNFET
=PP2V5_ENET
=PPVIN_PWRON_I2PLLVDD
PP1V8_PWRON
=PP1V8_PWRON_RUNFET
=PP2V5_RUN_RUNFET
=PP1V8_RUN_RUNFET
17
=PPVIN_CPU0_AVDD
=PP3V3_RUN_PWRSEQ
=TPS2211_SHDN_L
=PP3V3_RUN_AUDIO
=PPVIO_PCI_USB2
=PP3V3_PCI_USB2
=PP3V3_PCI_ZDB
=PPI2C_I2_SB
PP2V5_RUN
MAKE_BASE=TRUE
VOLTAGE=2.5V
=PP2V5_RUN_PCI1510
=PP2V5_GPU
PP1V8_RUN
MAKE_BASE=TRUE
VOLTAGE=1.8V
=PP1V8_GPU
10
=PP1V5R1V8_MAXBUS
21 32 33
=PP1V5R1V8_RUN_I2_MAXBUS 32
=PPJTAG_CPU
9
=PP1V8_RAM_I2_VREF
38
=PP1V8_RUN_TBEN_SYNC 21
PP1V5_RUN
MAKE_BASE=TRUE
VOLTAGE=1.5V
=PP1V5_GPU
67
20
XW1018
SM
47
16
47
47 48
49 50
=PP1V8_PWRON_REG
PP1V8_PWRON_REG
MAKE_BASE=TRUE
VOLTAGE=1.8V
46
MAKE_BASE=TRUE
VOLTAGE=1.8V
=PP1V8_PWRON_DDR2
=PP1V8_PWRON_I2_RAM
16
16
=PP1V5_RUN_RUNFET
40 41
38
=PP1V5R1V8_PWRON_I2_MAXBUS
16
=PP1V5_PWRON_REG
PP1V5_PWRON_REG
MAKE_BASE=TRUE
VOLTAGE=1.5V
PP1V5_PWRON
MAKE_BASE=TRUE
VOLTAGE=1.5V
=PP1V5_PWRON_RUNFET
=PP1V5_I2_AGP
=PPVCORE_PWRON_I2_REG
PPVCORE_PWRON_I2_REG
MAKE_BASE=TRUE
VOLTAGE=1.5V
10
34
10
Power Synonyms
16
43
SYNC_MASTER=N/A
SYNC_DATE=N/A

XW1017
SM
20
61
32
XW1015
SM
49 50
52
48
PPVCORE_PWRON_I2
MAKE_BASE=TRUE
VOLTAGE=1.5V
=PPVCORE_PWRON_I2

19

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
10
115
SHT
OF
NONE
7
I2S0 Series Rs
CPU Clocks
33
32
6
6
6
6
=RP1150P1
=RP1150P2
=RP1150P3
=RP1150P4
=RP1150P8
=RP1150P7
=RP1150P6
=RP1150P5
R1120
MAXBUS_CLK_CPU0
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
6
6
=MAXBUS_CPU0_CLK
33
59
TP_PCI_CLK33M_SLOTA_R
PCI_CLK33M_ZDB_R
MAKE_BASE=TRUE
R1111
6
32
TP_MAXBUS_CLK_CPU1_R
MAXBUS_CLK_CPU1_R
MAKE_BASE=TRUE
One resistor for each of:

- I2S0_SB_TO_DEV_DTO(_R)
- I2S0_MCLK(_R)
- I2S0_BITCLK(_R)
- I2S0_SYNC(_R)
10
5%
1/16W
MF-LF
402
=SYSCLK_TBEN_SYNC
59
TP_PCI_CLK33M_SLOTD_R
PCI_CLK33M_TBEN_SYNC_R
MAKE_BASE=TRUE
R1160
74 7
USB2_LEFT_PORT_P
6
6
6
6
=RP1151P1
=RP1151P2
=RP1151P3
=RP1151P4
=RP1151P8
=RP1151P7
=RP1151P6
=RP1151P5
5%
1/16W
MF-LF
402
6
6
74 7
USB2_LEFT_PORT_N
22
51
USB2_NEC
R1163
0
NET_SPACING_TYPE=USB2
NET_PHYSICAL_TYPE=USB2
DIFFERENTIAL_PAIR=USB2_LT_PORT
31 7
AGP_CLK66M_GPU
USB2_RIGHT_PORT_P
5%
1/16W
MF-LF
402
44
=AGP_GPU_RESET_L
AGP_VREF
MAKE_BASE=TRUE
VOLTAGE=0.75V
=I2_AGP_VREF
=AGP_VREF
=GPU_AGP_VREF
USB2_NEC
R1165
1
DIFFERENTIAL_PAIR=USB2_RT_PORT
PCI_RESET_L
MAKE_BASE=TRUE
44
TP_EXTTMDS_RESET_L
SI_TMDS_RESET_L
MAKE_BASE=TRUE
31 7
USB2_RIGHT_PORT_N
44
5%
1/16W
MF-LF
402
44
=SI_TMDS_RESET_L
USB2_I2
USB2_NEC
R1167
1
DIFFERENTIAL_PAIR=USB2_RT_PORT
54 55
6 11
USB2_I2
5%
1/16W
MF-LF
402
USB_BT_P
DIFFERENTIAL_PAIR=USB_BT
USB1P1_NEC
USB_NEC_BT_P
R1171
0
=PCI_CLK33M_ZDBOUT_R<0>
PCI_CLK33M_AIRPORT_R
MAKE_BASE=TRUE
6 11
60
USB_BT_N
5%
1/16W
MF-LF
402
6 11
DIFFERENTIAL_PAIR=USB_BT
30 7
USB_TPAD_P
DIFFERENTIAL_PAIR=USB_TPAD
30 7
USB_TPAD_N
59 22
PCI_SLOTA_INT_L
PCI_CLK33M_TBEN_SYNC
MAKE_BASE=TRUE
=CLK33M_TBEN_SYNC
21
PCI_CLK33M_AIRPORT
MAKE_BASE=TRUE
=PCI_CLK33M_AIRPORT
60
PCI_AIRPORT_REQ_L
MAKE_BASE=TRUE
PCI_AIRPORT_GNT_L
MAKE_BASE=TRUE
PCI_AIRPORT_INT_L
MAKE_BASE=TRUE
PCI_AD<17>
MAKE_BASE=TRUE
PCI_RESET_L
MAKE_BASE=TRUE
=PCI_AIRPORT_REQ_L
60
=PCI_AIRPORT_GNT_L
60
=PCI_AIRPORT_INT_L
60
=PCI_AIRPORT_IDSEL
60
=PCI_AIRPORT_RESET_L
60
PCI_CLK33M_CBUS
MAKE_BASE=TRUE
=PCI_CLK33M_CBUS
61
PCI_CBUS_REQ_L
MAKE_BASE=TRUE
PCI_CBUS_GNT_L
MAKE_BASE=TRUE
PCI_CBUS_INT_L
MAKE_BASE=TRUE
PCI_AD<20>
MAKE_BASE=TRUE
PCI_RESET_L
MAKE_BASE=TRUE
=PCI_CBUS_REQ_L
61
=PCI_CBUS_GNT_L
61
=PCI_CBUS_INT_L
61
=PCI_CBUS_IDSEL
61
=PCI_CBUS_RESET_L
61
PCI_CLK33M_USB2
MAKE_BASE=TRUE
=PCI_CLK33M_USB2
62
PCI_USB2_REQ_L
MAKE_BASE=TRUE
PCI_USB2_GNT_L
MAKE_BASE=TRUE
PCI_USB2_INT_L
MAKE_BASE=TRUE
PCI_AD<21>
MAKE_BASE=TRUE
PCI_RESET_L
MAKE_BASE=TRUE
=PCI_USB2_REQ_L
62
=PCI_USB2_GNT_L
62
=PCI_USB2_INT_L
62
=PCI_USB2_IDSEL
62
=PCI_USB2_RESET_L
62
R1136
2 6 11
23
USB1P1_I2
USB_I2_BT_N
PCI_CLK33M_CBUS_R
MAKE_BASE=TRUE
R1175
0
DIFFERENTIAL_PAIR=USB_TPAD
PCI_SLOTD_REQ_L
59
PCI_SLOTD_GNT_L
59 22
PCI_SLOTD_INT_L
62 61 60 59 58
6 11
25 11
R1177
0
R1137
USB1P1_NEC
USB_NEC_TPAD_N
59
6 11
USB1P1_I2
USB_I2_TPAD_P
22
5%
1/16W
MF-LF
402
6 11
USB1P1_NEC
USB_NEC_TPAD_P
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
6 11
6 11
USB1P1_NEC
USB_NEC_BT_N
R1176
6 11
PCI_SLOTA_GNT_L
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
6 11
PCI_SLOTA_REQ_L
59
25 11
R1173
1
59
6 11
USB1P1_I2
USB_I2_BT_P
22
62 61 60 59 58
R1174
6 11
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R1172
5%
1/16W
MF-LF
402
R1166
43
USB2_I2
USB2_I2_LEFT_PORT_N
60
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R1164
5%
1/16W
MF-LF
402
25 11
5%
1/16W
MF-LF
402
R1140
USB2_I2
USB2_I2_LEFT_PORT_P
R1170
6 11
5%
1/16W
MF-LF
402
R1162
GPU
1
R1161

- I2S1_SB_TO_DEV_DTO(_R)
- I2S1_MCLK(_R)
- I2S1_BITCLK(_R)
- I2S1_SYNC(_R)
AGP_CLK66M_GPU_R
USB2_NEC
1
DIFFERENTIAL_PAIR=USB2_LT_PORT
1/16W
SM-LF
43
22
5%
1/16W
MF-LF
402
I2S1 Series Rs
5%
23
R1135
23
33
=PCI_CLK33M_ZDB_IN
R1130
21
USB Controller Mux

RP1151
PCI_CLK33M_ZDB
MAKE_BASE=TRUE
MAXBUS_TBEN_SYNC
MAXBUS_CLK_TBEN_SYNC
MAKE_BASE=TRUE
22
5%
1/16W
MF-LF
402
MAXBUS_TBEN_SYNC
1/16W
SM-LF
10
MAXBUS_CLK_CPU0_R
5%
PCI
R1110
RP1150
1
6 11
USB1P1_I2
USB_I2_TPAD_N
23
6 11
5%
1/16W
MF-LF
402
PCI_CLK33M_USB2_R
MAKE_BASE=TRUE
22
PCI_SLOTE_REQ_L
22
PCI_SLOTE_GNT_L
22
PCI_SLOTE_INT_L
22
5%
1/16W
MF-LF
402
62 61 60 59
25 11
23
TP_PCI_CLK33M_ZDBOUT3
MAKE_BASE=TRUE
USB Port Assignments

11 6
11 6
11 6
11 6
11 6
11 6
USB2_I2_LEFT_PORT_P
MAKE_BASE=TRUE
USB2_I2_LEFT_PORT_N
MAKE_BASE=TRUE
USB2_I2_P<0>
72
11 6
USB2_I2_N<0>
72
11 6
MAKE_BASE=TRUE
MAKE_BASE=TRUE
USB2_I2_P<2>
72
11 6
USB2_I2_N<2>
72
11 6
USB_I2_BT_P
MAKE_BASE=TRUE
USB_I2_BT_N
MAKE_BASE=TRUE
USB2_I2_P<4>
72
11 6
USB2_I2_N<4>
72
11 6 2
MAKE_BASE=TRUE
MAKE_BASE=TRUE
USB2_NEC_P<0>
73
USB2_NEC_N<0>
73
MAKE_BASE=TRUE
MAKE_BASE=TRUE
USB2_NEC_P<1>
73
30 25 7
USB2_NEC_N<1>
73
13
USB_NEC_BT_P
MAKE_BASE=TRUE
USB_NEC_BT_N
MAKE_BASE=TRUE
USB2_NEC_P<2>
73
USB2_NEC_N<2>
PMU Connections
25
12
73
25
11 6
11 6
USB_I2_TPAD_P
MAKE_BASE=TRUE
USB_I2_TPAD_N
MAKE_BASE=TRUE
USB2_I2_P<5>
72
USB2_I2_N<5>
72
11 6
11 6
USB2_NEC_P<3>
USB_NEC_TPAD_P
MAKE_BASE=TRUE
USB_NEC_TPAD_N
MAKE_BASE=TRUE
73
25
USB2_NEC_N<3>
73
25
SYS_OVERTEMP_L
MAKE_BASE=TRUE
PMU_CHARGE_V
MAKE_BASE=TRUE
PMU_CPU_HRESET_L
MAKE_BASE=TRUE
SYS_PMU_ANALOG_AC_DET
MAKE_BASE=TRUE
GOV_RESET_L
PMU_CPU_CLK_EN
MAKE_BASE=TRUE
PMU_SYS_CLK_EN
MAKE_BASE=TRUE
=ADT7467_THERM_L
27
26
TP_PMU_P7_5
25
26
=CPU_HRESET_L
34
26
TP_PMU_AN_P10_6
25
26
TP_GOV_RESET_L
MAKE_BASE=TRUE
=I2_STOPCPU_L
22
26
=I2_STOPXTAL_L
22
26
26
26
I105
Vesta Ethernet
I106
I107
ENET_TX_EN_R
65
ENET_TX_ER_R
65
65
ENET_TXD_R<7..0>
65
ENET_RESET_L
65 9
65 9
R11851
100K
5%
1/16W
MF-LF
402 2
65 9
65 9
65 9
65
65
65
65 9
65 9
ENET_TX_EN
MAKE_BASE=TRUE
ENET_TX_ER
MAKE_BASE=TRUE
ENET_TXD<7..0>
MAKE_BASE=TRUE
ENET_RXD<7..0>
MAKE_BASE=TRUE
ENET_RX_DV
MAKE_BASE=TRUE
ENET_RX_ER
MAKE_BASE=TRUE
ENET_COL
MAKE_BASE=TRUE
ENET_CRS
MAKE_BASE=TRUE
ENET_CLK125M_GBE_REF
MAKE_BASE=TRUE
ENET_CLK125M_RX
MAKE_BASE=TRUE
ENET_CLK25M_TX
MAKE_BASE=TRUE
ENET_MDC
MAKE_BASE=TRUE
ENET_MDIO
MAKE_BASE=TRUE
TP_ENET_ENERGYDET
MAKE_BASE=TRUE
=ENET_TX_EN
66
=ENET_TX_ER
66
=ENET_TXD<7..0>
66
=ENET_RXD_R<7..0>
66
=ENET_RX_DV_R
66
=ENET_RX_ER_R
66
=ENET_COL_R
66
=ENET_CRS_R
=VESTA_CLK125M_GBE_REF
TP_PMU_AN_P0_0
25
TP_PMU_AN_P0_1
25
TP_PMU_AN_P0_2
25
TP_PMU_AN_P0_3
25
TP_PMU_AN_P0_4
25
TP_PMU_AN_P0_5
25
TP_PMU_P7_4
25
TP_PMU_AN_P10_5
25
32
PCI_RESET_L
MAKE_BASE=TRUE
TP_MAXBUS_CPU1_QACK_L
66
25
25
25
25
=ROM_PWD_L
Signal Synonyms
58
SYNC_MASTER=N/A
NC_MAXBUS_CPU1_QACK_L
MAKE_BASE=TRUE
NO_TEST=YES
SYNC_DATE=N/A
66
66
=VESTA_CLK25M_TX
66
22
I2_GPIO_EXT_02
22
=SPI_I2_REQ
CPU0_VID_AB_SEL
MAKE_BASE=TRUE
CPU0_MAX1717_AB_SEL
MAKE_BASE=TRUE

=CPU0_VID_AB_SEL
36
=CPU0_MAX1717_AB_SEL
36

66
24
=VESTA_MDIO
66
=VESTA_ENERGYDET
66
=SLEEP_LED_IOUT
SLEEP_LED_IOUT
MAKE_BASE=TRUE
=SLEEP_LED_CONN
30
SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
11
115
SHT
OF
NONE
MISC
25 11
=VESTA_CLK125M_RX
=VESTA_MDC
I108
TP_PMU_P3_0
MAKE_BASE=TRUE
TP_PMU_P3_1
MAKE_BASE=TRUE
TP_PMU_P3_2
MAKE_BASE=TRUE
TP_PMU_P3_3
MAKE_BASE=TRUE
SYS_PWRSEQ_TPAD_L
MAKE_BASE=TRUE
SYS_PWRSEQ_1
MAKE_BASE=TRUE
SYS_PWRSEQ_2
MAKE_BASE=TRUE
SYS_PWRSEQ_3_L
MAKE_BASE=TRUE
SYS_PWRSEQ_4
MAKE_BASE=TRUE
SYS_PWRSEQ_5
MAKE_BASE=TRUE
SYS_PWRSEQ_6_L
MAKE_BASE=TRUE
SYS_PWRSEQ_FINAL
MAKE_BASE=TRUE
8
THERM
THERM
I317
I318
7
NET_TYPE
SPACING PHYSICAL
DIFFERENTIAL_PAIR
THERM
THERM
PPVBATT_ISNS_VINP
PPVBATT_ISNS_VINN
BATTERY_ISNS
BATTERY_ISNS
12
12
ADAPTER INPUT/INRUSH LIMITER

D
A29 ADAPTER DETECTION

Q1210
Adapter Connector Side

(Connector is on separate page
to facilitate design reuse)
IRF7416BF
System Side
=PP24V_ADAPTER_RAW
R12102
R1201
10
S1
0.1uF
330K
5%
1/16W
MF-LF
402
C1210
D4
D3
D2
D1
S3
S2
PP24V_ADAPTER_SW
VOLTAGE=24V
=PP4V85_ALL_A29_DET
10
=PP3V3_ALL_A29_DET
R1221
13
100K
1%
1/16W
MF-LF
1 402
GATE
20%
50V
CERM
805
74 7
100K
1%
1/16W
MF-LF
2 402
R1209
1%
1/16W
MF-LF
470K
1 402
2
R1202
97.6K
C1200
R1204
1V20_REF
AC_DET_DIV
10K
1%
1/16W
MF-LF
402 1
SYS_AC_DET 25
25 18 13
R12052
1M
SYS_ACIN_L
D
SOT23-LF
R1227
1
4.7M 2
5%
1/16W
MF-LF
402
R1226
127K
1%
1/16W
MF-LF
2 402
13
2N7002DW-X-F
2
5
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402 1
Q1208
A29_DET_L
1%
1/16W
MF-LF
2 402
V5
402K
SOT-363
R1206
1
57.6K
11
A29_DET_REF
R1223
2N7002DW-X-F
V-
SYS_PMU_ANALOG_AC_DET
Q1215
SYS_ACIN
5%
1/16W
MF-LF
402
24
SM-LF
R12032
AC_ENABLE_L
10K
2N7002
SM-LF
1
Q1220
LMC7211
R1224
1
5%
1/16W
MF-LF
402 2
U1220
V+
10K
5%
1/16W
MF-LF
2 402
SYS_AC_DET_L
LMC7211
V+
10K
5%
1/16W
MF-LF
2 402
U1200
R1216
A29_DETECT 13
3
ANALOG_AC_DET
5%
1/16W
MF-LF
1 402
R1215
10K
20%
16V
CERM 2
402
1%
1/16W
MF-LF
402 2
14
R1208
0.01uF
100K
1%
1/16W
MF-LF
402 1
5%
1/16W
MF-LF
2 402
20%
10V
2 CERM
402
1%
1/16W
MF-LF
2 402
R1222
100K
C1220
0.1uF
52.3K
AC_ENABLE_GATE
R1228
R1225
=PP3V3_ALL_AC_DETECT
1
1
20.0K
10
SOI
8
10
2N7002DW-X-F
2
2N7002DW-X-F
2
Q1215
Q1208
470K
5%
1/16W
MF-LF
402 1
6
D
R12072
SOT-363
ADAPTER IDs
SOT-363
SOT-363
SYS_AC_DET indicates adapter presence. SYS_ACIN is code-controlled

signal to enable use of AC in system. Q1208 ensures SYS_ACIN
goes low as soon as SYS_AC_DET goes low. Therefore, hardware
immediately disables the AC upon removal but only software can
enable AC after detection by the PMU.
GREATER THAN 13.1V DETECT
ADAPTER
ID RANGE
Q11 (65W)
1.65-2.31V
PIN VOLTAGE
2.007-2.066V
A29 (45W)
2.31-2.97V
2.558-2.661V
AIRLINE
0.33-0.99V
0.589-0.663V
BATTERY INPUT/CURRENT SENSE

=PPVBATT_BATT_VSNS
10
10
=PP3V3_ALL_BATT0_DET
2
R1256
L1252
470K
FERR-EMI-100-OHM
SM
L1250
SM-LF
87438-0832
M-RT-SM
0.0062
PPVBATT_BATT_RAW
VOLTAGE=12.8V
L1253
(BATT_IN_PD) MIN_LINE_WIDTH=0.5 mm
BATT_CLK
=I2C_BATT_SCL
VOLTAGE=10.8V
XW1252
XW1251
SM
SM
SM
2
BATT_DATA
BATT0_DET_L
GND_BATT_CONN
L1254
12
FERR-EMI-100-OHM
VOLTAGE=0V
=I2C_BATT_SDA
10
1%
1W
MF-LF
2512
FERR-EMI-100-OHM
PPVBATT_BATTPOS_CONN
=PPVBATT_ISNS_N
J1250
1
2
3
4
5
6
7
8
R1250
FERR-50-OHM
CRITICAL
5%
1/16W
MF-LF
2 402
PPVBATT_ISNS_VINP
VOLTAGE=12.8V
PPVBATT_ISNS_VINN
VOLTAGE=12.8V
12
8
SM
3
4
VIN+ VIN-
R1255
1
1K
SYS_BATT0_DET_L
5%
1/16W
MF-LF
402
U1250
24 25
10
5 V+
=PP3V3_BATT_IMON
INA138
SOT23-5-LF
CRITICAL
R1252
OUT 1
BATT_ISNS_R
L1251
C1250
FERR-50-OHM
1
0.1UF
20%
10V
CERM 2
402
SM-LF
R1251
GND
2
249K
1%
1/16W
MF-LF
2 402
49.9K2
1%
1/16W
MF-LF
402
BATT_ISNS
25
MAKE_BASE=TRUE
1
Power Inputs
C1252
SYNC_MASTER=N/A
10UF
SYNC_DATE=N/A
20%
2 4V
X5R
603
SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
12
115
SHT
OF
NONE
1K
C1370
0.01uF
6
5
D4
D3
D2
D1
S3
S2
S1
PP24V_ADAPTER_ILIM_P
VOLTAGE=24V
C1380
U1370
=PP14VR24V_ALL_PBUS_A
MAX4172
1
R1360
47K
5%
1/16W
MF-LF
402 2
3
4
NC
NC
RS-
PG
NC1
OUT
NC2
GND
5
R13611
C1361
1 C1371
7 NC
20%
50V
CERM
603
5%
1/16W
MF-LF
402
10K
2 50V
X7R
603-1
CRITICAL
2.21k
0.1%
1/16W
MF-LF
2 603
A29_DETECT 2
SOT-363
PP24V_ADAPTER_SW
RES,20K,1%,1/16W,MF-LF,402
R1345
Q16C_PARTS
114S0382
RES,48.7K,1%,1/16W,MF-LF,402
R1345
Q41C_PARTS
R1301
D13034.7
SWITCHER VOLTAGE CONTROL
=PP3V3_ALL_BATT_CHGR
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
C1301
C1303
1uF 0.47UF
1%
1/16W
MF-LF
2 402
OD OUTPUT LOW - WHEN AC GREATER THAN 18V

13
R1342
4.12K
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
1
R1323
1K
1%
1/16W
MF-LF
402 2
R1343
Q1340
5.23K
2N7002DW-X-F
SOT-363
SOT-363
2N7002DW-X-F
SOT-363
0.1uF
20%
10V
CERM 2
603
Q1347
2N7002DW-X-F
PMU_BATT0_CHARGE
C1350
0.1uF
U1350
SOT-363
R1353
100K
1%
1/16W
MF-LF
402 2
SM-LF
1
5
= CELLS X (4.096 + (0.4096 * V
BATT
VCTL
/ V
1772_DLOV
1772_BST
24
1772_DHI
23
21
20
1772_LX
1772_DLO
CHG
= (0.2048/R
_62
) * (V
SOT-363
WHEN AC IS IN, P-CHANNEL FETS ARE QUICKLY (DIODE) TURNED OFF
5%
1/4W
MF-LF
1206
SOT23
C1319
0.1uF
RC TIME IS 480K*10UF @ +3V_PMU
1772_BST_ESR
20%
25V
CERM 2
603
1
C1320
0.1uF
1
5
6 7
20%
50V
CERM 2
805
C1312 1 C1313 1 C1314 1 C1315 1 C1316

2.2UF
Q1300
SO8
L1300
10uH
20%
25V
CERM 2
603
20%
10V
2 CERM
603
C1323
0.1uF
Q1301
20%
2 25V
CERM
4
NO STUFF
XW1300
SM
R1318
100K
5%
1/16W
D1300
SMB
CRITICAL
603
10%
2 50V
X7R
1206
C1321
0.0022UF 1 2 3
10%
2 50V
CERM
402
SO-8-LF
C1305
4.7uF
R13041 R13051
1
5%
1/10W
MF-LF
603 2
C1307
4.7uF
20%
25V
2 CERM
1206
5%
1/10W
MF-LF
603 2
4.7uF
4.7uF
20%
25V
CERM 2
1206
20%
25V
CERM 2
1206
C1310
20%
2 25V
ELEC
SM1-LF
4.7uF
20%
25V
CERM 2
1206
MF-LF
402 2
IS
1%
1/16W
MF-LF
402 2
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
126S0084
126S0079
BOM OPTION
REF DES
COMMENTS:
C1311
Primary is 260C/Alt is 250C part
TABLE_ALT_ITEM
R1354
Battery Charger
MF-LF
R1352 1 C1352
1%
1/16W
MF-LF
2 402
SYNC_MASTER=N/A
100K
10
A29_CLS_ADJ
Q1330
402 2
2N7002DW-X-F
A29_DETECT 5
SOT-363

0.047uF
10%
2 16V
CERM
402
SYNC_DATE=N/A

ICTL
/ V
REFIN
SIZE
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
13
115
SHT
OF
NONE
C1311
33uF
20%
25V
2 CERM
1206
C1308
CRITICAL
C1309
4.7uF
20%
25V
2 CERM
1206
C1306
APPLE COMPUTER INC.
13
MAKE_BASE=TRUE
0.05 2
MBRS140XXG
IRF7811W
PPVBATT_BATT_PBUSA_FUSE
=PPVOUT_BATT_CHRG
1%
1W
MF-LF
2512
5 6 7 8
1
2.2UF
10%
2 50V
X7R
1206
R1303
SM1-LF
2.2UF
10%
2 50V
X7R
1206
PPVOUT_BATT_CHRG_R
VOLTAGE=14V
CRITICAL
1 2
C1322
C1317
0.1uF
1uF
2.2UF
10%
2 50V
X7R
1206
RLA130N03
1772_CLS
2.2UF
10%
2 50V
X7R
1206
CRITICAL
1772_CSIP
1772_CSIN
10
5%
1/10W
MF-LF
2 603
1%
1/16W
MF-LF
402 2
=PPVIN_ALL_BATT_CHGR
R1320
4.7
For 4.20V cells, VCTL = 0.245 REFIN
Q1392
2N7002DW-X-F
C1392
10uF
(GND)
BATT 17
1/16W
For 4.15V cells, VCTL = 0.123 REFIN
SYS_ACIN_L_RC
1%
1/16W
MF-LF
402 2
BATT_DIV
1V65_REF
100K
1%
))
REFIN
BATT_14PBUS_EN
1
R1330
6.34K
1%
1/16W
MF-LF
2 402
V+
V-
R1351
499K
LMC7211
BATT_LOW
20%
10V
CERM 2
603
1772_GND
20%
10V
2 CERM
402
1%
1/16W
MF-LF
2 402
BATT_24PBUS_EN 5
D1319
MMBD914XXG
R1319
33
=PPVIN_BATT_CHRG_VSNS
SOT-363
10
13
SOT-363
SOT-363
1
R1329
4.12K
VOLTAGE=0V
Q1347
2N7002DW-X-F
CHARGE_DISABLE 2
25
5%
1/16W
MF-LF
402 2
1772_CELLS
22
25
R1328
10K
1
SYS_ACIN_L
DP1390 1R1392
BAS16TW-X-F 158K
1uF
20%
2 10V
CERM
402
16
2
GND
8 9
1772_REF
R1347
100K
5%
1/16W
MF-LF
402 2
20%
2 16V
CERM
402
1%
1/16W
MF-LF
2 402
CSIP 19
CSIN 18
C1326
0.01uF
R1324
1K
C1324 C1327
4
13 10
20%
16V
CERM 2
402
12
5%
1/16W
402 2
DP1390 MF-LF
BAS16TW-X-F
WHEN AC IS NOT PLUGGED, P-CHANNEL FETS ARE ON
26
REF CLS
4
3
SOT-363
1%
1/16W
MF-LF
402 2
1772_CCV_RC
Q1340
2N7002DW-X-F
Q1348
2N7002DW-X-F
R1325
1KC1325
0.01uF
Q1348
1%
1/16W
MF-LF
2 402
R1396
10K
5%
1/16W
MF-LF
402 2
20%
2 6.3V
X5R
603
10%
2 50V
CERM
1206
7 CCV
6 CCI
5 CCS
1772_CCV
1772_CCI
1772_CCS
1%
1/16W
MF-LF
402 2
1
R1348
1K
BATTV_LOW2
1772_ICHG
1772_IINP
BATT_LOW_L
5%
1/16W
MF-LF
402 2
PMU_CHARGE_V
R1345
20.0K
BATTV_HIGH
R1340
100K
11
OMIT
BATT_14V_GATE
1
1772_LDO
C1302
0.47UF
R1317
100K
U1300
1772_ACIN
1772_ACOK_L
(+3V_PMU)
1772_VCTL
1772_ICTL
1
5%
1/16W
MF-LF
402 2
R1391
10K
1
C1384
Q1384
1uF
2N7002DW-X-F
R1395
47K
BATT_24V_GATE
SOT-363
SOT-363
402 2
1/16W
MF-LF
CSSP
CSSN
1 DCIN
CRITICAL CELLS
LDO
11 ACIN
12 ACOK MAX1772
DLOV
QSOP-LF
BST
13 RFIN
15 VCTL
DHI
14 ICTL
LX
10 ICHG
DLO
28 IINP
PGND
1772_DCIN
2 402
27
Q1384
5%
1/16W
MF-LF
51.1K
10 13
4.7
5%
10%
50V
CERM 2
1206
20%
2 50V
CERM
1210
1772_ACOK_L 2
R1302
1772_CSSP
1772_CSSN
402 2
1%
1/16W
MF-LF
402 2
R1346
10K
SOT23
12.7K
CHARGE THROTTLED BY LOW BATTERY VOLTAGE
R1341
R1344
27.4K
10K
1/16W
MMBD914XXG
MF-LF
R13221
CHARGE DISABLED BY PMU OR INPUT VOLTAGE <18V
S1
R1390
47K
2N7002DW-X-F
5%
1%
1/16W
MF-LF
402 2
SWITCHER CURRENT CONTROL
PMU SELECTS BETWEEN TWO VOLTAGES
100K
TABLE_5_ITEM
10
13
1%
1W
MF
2512-1
R13211
13
5
AC_GTR_18V
0.0252
TABLE_5_HEAD
114S0343
Q1330
2N7002DW-X-F
R1300
TABLE_5_ITEM
D4
D3
D2
D1
S3
S2
OVER_18V_ADJ
5%
1/16W
MF-LF
2 402
CRITICAL
BOM OPTION
14
0.1%
1/16W
MF-LF
2 603
100K
1625_COMP
GATE
DESCRIPTION
150
TO-252-LF
CRITICAL
R1384
Q1395
SUD45P03
SOI
R1383
13 12
QTY
CRITICAL
Q1390
1%
1/16W
MF-LF
402
=PP3V3_ALL_PBUS_ILIM
VOLTAGE=14V
CRITICAL
82.5K
SOT-363
PART#
R1382
A29_CURRENT_ADJ
13 12
0.1%
1/16W
MF-LF
603 2
PPVBATT_BATT_PBUSB_FUSE
VOLTAGE=14V
42.2K
=PPVBATT_BATT_PBUSB
IRF7416BF
CURRENT_THRESHOLD
CRITICAL
R13811
SM-LF
10
PPVBATT_BATT_PBUSA_FUSE
ADAPTER_I_REG
2N7002DW-X-F
13
R1387
BAS16TW-X-F
SOT23-5-LF
SOT-363
1
CRITICAL
Q1392
DP1390
U1380
LMC7111
MAX4172_OUT
SYS_ACIN
IAC_FB
0.1%
1/16W
MF-LF
603 2
SM-LF
LTC1625_ITH
1%
1/16W
MF-LF
402
BKFD_PROT_EN_L
25 18 12
0.1%
1/16W
MF-LF
2 603
R1385
0.1UF
10%
R13701
68K
0.01UF
42.2K
Place close to RS-
PLACE R383 CLOSE TO LTC1625

ROUTE LTC1625_ITH CAREFULLY
10V
CERM 2
402
R1380
BKFD_PROT_GATE
1
=PPVBATT_BATT_PBUSA
0.1uF
CRITICAL
20%
10
TSSOP-LF
RS+
10
F1395
5AMP-125V
2
V+
GATE
4
CRITICAL
=PP3V3_ALL_PBUS_ILIM
10
13
F1390
5AMP-125V
20%
2 50V
CERM
603
20%
10V
CERM
402
SOI
IAC_RC_COMP
1%
1/16W
MF-LF
402
IRF7416BF
8
PP24V_ADAPTER_SW
=PPVBATT_BATT
0.1uF
10
C1386
R1386
2
Q1360
13 12
BATTERY SWITCH-OVER CIRCUIT
+PBUS CURRENT LIMIT

PLACE U1370 NEXT TO R1300
BACKFEED
PROTECTION
D 4
CRITICAL
Q1430
FDG6324L
SC70-6-LF
3
10
D2
4 S2
=PP5V_PWRON_LTC1625_EXTVCC
PP5V_LTC1625_EXTVCC_SW
VOLTAGE=5V
R1430
G2
470K
5%
1/16W
MF-LF
402 2
1625_ENABLE_L
6
Q1430
1625_ENABLE 5
12.8V PBUS SUPPLY
CRITICAL
D1
FDG6324L
G1
SC70-6-LF
C1400
0.1uF
S1
20%
2 10V
CERM
402
10
CONNECT LTC1625 TK PIN AT TOP-SIDE FET

KEEP VIN/TK LOOP SHORT
C1420 1
1%
1/16W
MF-LF
402 2
20%
10V
CERM 2
402
0.1uF
97.6K
2
12
1V20_REF
1625_DIV
R1421
1%
1/16W
MF-LF
402 2
MMBD914XXG
SOT23
R1422
1
10K
V-
1M
16
15
2
3
5
1625_FCB 4
NC 8
D1420
5
1
U1420
SM-LF
13
1625_RUNSS
1625_COMP
2
R1425
1%
1/16W
MF-LF
402
C1427
0.1uF
20%
50V
CERM 2
805
4.99K
C1426
VINSSOP-LF BG
TK CRITICAL TG
SYNC VOSENSE
RUN/SS INTVCC
ITH
FCB
BOOST
VPROG
SW
SGND
4700pF
5%
25V
CERM 2
603
10
13
7
11
C1405
2.2UF
10%
2 50V
X7R
1206
2 50V
X7R
1206
SO8
C1404
2.2UF
1625_BST_ESR
2.2UF
10%
2 50V
X7R
10%
2 50V
X7R
1206
1206
C1406
10%
2 50V
CERM
603
R14101 C1410
2.2
12
14
CRITICAL
0.22uF
5%
1/10W
MF-LF
603
20%
25V
CERM
805
L1400
10
1625_VSW
SM1
PGND
5 6 7 8
C1401
4.7uF
1625_BG
1
4700pF
C1411
4.7uF
NO STUFF
1
C1412
SO-8-LF
D1400
SMB
MBRS140XXG
1 2 3
C1402
4.7uF
0.0047uF
1%
1/16W
MF-LF
2 402
1206
IRF7811W
20%
2 10V
CERM
1206
XW1400
SM
1
R1401
158K
2 25V
CERM
CRITICAL
Q1401
VOLTAGE=0V
=PP12V8_LTC1625_VREG
8.0uH-6.8A
1/16W
MF-LF
2 402
1625_SGND
2.2UF
1625_BST
0
5%
5%
25V
CERM 2
603
C1408
10%
2 50V
X7R
1206
20%
470pF
2.2UF
10%
2 50V
X7R
1206
MBR0540XXG
R1416
C1425
C1407
RLA130N03
C1403
2.2UF
10%
Q1400
D1410
SOD-123
U1400
LTC1625
CRITICAL
1625_TG
EXTVCC
C1421 1
1%
1/16W
MF-LF
402 1
COMP_RC
WHEN +24V_PBUS IS BELOW ~13.1V,
1625 IS SHUT-OFF
R1415
0
5%
1/16W
MF-LF
2 402
1625_VIN
LMC7211
V+
5%
1/10W
MF-LF
603 1
6 7
VOLTAGE=5V
NO STUFF
R1427
R14201
1625_INTVCC
=PP3V3_ALL_LTC1625_SW
10
=PPVIN_ALL_LTC1625
10%
25V
CERM
402
R1402
16.2K
1
1
1%
1/16W
MF-LF
20%
25V
CERM 2
1206
2 402
1625_VFB
PMU SUPPLY
10
B
BACKUP_BATT
=PP5V_PWRON_PMU_SUPPLY
D1460
SOD-123
NC
BOOTSTRAP SYSTEM FROM ADAPTER,

MAIN BATTERY OR BACKUP BATTERY
=PP24V_ADAPTER_PMU_SUPPLY 1
390
5%
1/4W
MF-LF
1206
MBR0540XXG
PPVIN_ALL_ADAPT_OR_BATT
VOLTAGE=18V
NC
NC
8
2
3
D1451
LP2951
SOI-LF
IN
OUT
SENSE ERR
SHUT FDBK
GND
MMBD914XXG
10
=PPVBATT_BATTERY_PMU_SUPPLY
C1450
0.1uF
20%
2 50V
CERM
805
D1452
SOD-123
=PP12V8_PBUS_PMU_SUPPLY
NC
BACKUP_BATT
1
R1451
294K
C1451 1
0.1uF
1%
1/16W
MF-LF
402 2
C1452
470pF
10%
50V
2 CERM
603
U1460
1
5%
8
2
RB160M-60
NC
=PP5V_SUPERCAP
LP2951
IN
OUT
SENSE ERR
SHUT FDBK
GND
SOI-3.3V-LF1
SUPERCAP HOOKS IN HERE
PP4V85_ALL_ESR
VOLTAGE=4.6V
R1452
C1460
20%
10V
2 CERM
402
2.2uF
MBR0540XXG
5
7
=PP3V3_ALL_VREG
10
NC
1
R1461
1
5%
1/10W
MF-LF
2 603
PP3V3_ALL_ESR
VOLTAGE=3.3V
1
C1461
10UF
20%
6.3V
2 X5R
20%
2 10V
CERM
805
0.1uF
C1453
1%
1/16W
MF-LF
402
BACKUP_BATT
1
100K
R1453
1/10W
MF-LF
2 603
FB_4_85V_BU
20%
10V
CERM 2
402
VTAP
D1461
SOD-123
10
BACKUP_BATT
1
3V_PMU_VTAP
SOT23
10
=PP4V85_ALL_VREG
1
5
7
PP4V6_ALL_RAW
MAKE_BASE=TRUE
VOLTAGE=4.6V
RB160M-60
U1450
SOD-123
PP24V_ADAPT_PMU_ILIM
VOLTAGE=24V
IF SUPERCAP BOM OPTION IS CHOSEN:

OUTPUT AT U23.1 IS 5.65V
OUTPUT AT U22.8 IS 5.4V
PLUS5VTAP
D1450
R1450
10
603
12.8V PBUS/PMU Supplies
SYNC_MASTER=N/A
SYNC_DATE=N/A

TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION
SUPERCAP

TABLE_5_ITEM
114S0465
RES,MF-LF,1/16W,357K OHM,1%,0402,SMD
R1451

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
14
115
SHT
OF
NONE
3.3V/5V SWITCHER
10
C1520
2.2UF
C1521
C1522
2.2UF
10%
2 50V
X7R
1206
2.2UF
C1523
1
8
2.2UF
10%
CRITICAL
50V
10%
2 50V
X7R
1206
10%
2 50V
X7R
1206
2 X7R
1206
6 5
Q1501
4
SO8
D
10
R1501
=PP5V_PWRON_REG
C1501
C1503
330uF
C1502
22uF
R1502
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402 2
8 7
10
1%
1/16W
MF-LF
2 402
CRITICAL
C1511
Q1502
R1503
SO-8-LF
10
NO STUFF
5%
1/16W
MF-LF
2 402
2 1
C1515
0.0022UF
26 SW1
23 BG1
C1514
2
NO STUFF
1
113K
C1504
180pF
1%
1/16W
MF-LF
402 2
C1512
C1510
0.0022uF
5%
50V
2 CERM
402
SNS2+ 14
SNS2- 13
3707_FSET
3707_FCB
R15051
15.0K
1%
1/16W
MF-LF
402 2
3707_STBYMD
R15121
21.5K
SGND
C1513
100pF
1%
1/16W
MF-LF
402 2
VOSNS2 12
ITH2 11
RUN/ 15
SS2
3707_SGND
VOLTAGE=0V
1%
1/4W
MF-LF
1206
CRITICAL
1
SO-8-LF
C1565
R15531
R15521
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
10
2 3
C1553
330uF
20%
10V
2 CERM
1210
NO STUFF
C1551
22uF
CRITICAL MBRS140XXG
10%
50V
2 CERM
402
20%
2 6.3V
TANT
CASE-D4-LF
C1552 1
10
22uF
20%
10V
CERM 2
1210
C1564
0.001uF
1
0.0022uF
C1560
10%
50V
2 CERM
402
0.1uF
20%
10V
2 CERM
402
PGND
20
NO STUFF
C1554 1
180pF
5%
50V
CERM 2
402
R1554
63.4K
1%
1/16W
MF-LF
2 402
3V_ITH_RC
1
R1562
C1563 1
R1555
12.7K
100pF
1%
1/16W
MF-LF
2 402
20%
50V
CERM
402
C1562
PGOOD 28
100K
20%
16V
CERM 2
402
0.0052
IRF7811W
0.0022UF 1
3V_RUNSS
R1531
0.01uF
5%
2 50V
CERM
402
6 7
Q1552
3V_VOSNS
3V_ITH
C1531 1
D
=PP3V3_PWRON_REG
10
3V_SNSP
3V_SNSM
6 STBYMD
10%
16V
CERM 2
402
5V_ITH_RC
7 FCB
5 FREQSET
2.2UF
R1551
2
D1551
SMB
3V_BOOST
3V_SW
3V_BG
SW2 17
BG2 19
3 SNS1-
1 RUN/
0.047uF
10%
50V
CERM 2
402
20.0K
1%
1/16W
MF-LF
2 402
5%
50V
CERM 2
402
1%
1/16W
MF-LF
2 402
=5V3V3PWRON_EN_L
1M
5%
1/16W
MF-LF
402
D1533
3
MMBD914XXG
SOT23
=5V3VPWRON_PGOOD
Q1533
R1533
26
CRITICAL
SS1
20%
50V
CERM
402
0.22uF
20%
25V
2 CERM
805
C1573
10%
2 50V
X7R
1206
10%
2 50V
X7R
1206
CRITICAL
4.7uH
C1561
2.2
2.2UF
3V_RSNS
IHLP-5050
5%
1/10W
MF-LF
603 2
C1572
10%
2 50V
X7R
1206
L1551
2 3
MBR0540XXG
R1561
2 SNS1+
4 VOSNS1
8 ITH1
5V_VOSNS
5V_ITH
5V_RUNSS
0.001uF
LTC3707
C1571
2.2UF
10%
2 50V
X7R
1206
CRITICAL
D1561
SOD-123
24 10
27 TG1 SSOP-LF TG2 16

25 BOOST1
BOOST2 18
5V_TG
5V_BOOST
5V_SW
5V_BG
2.2UF
SO8
3V_BOOST_ESR
U1500
5%
1/10W
MF-LF
2 603
5V_SNSP
5V_SNSM
R15041
5%
1/16W
MF-LF
2 402
EXT INT VIN 3.3

VOUT
VCC VCC
2.2
10%
50V
CERM 2
402
1M
NC
R1511
20%
25V
CERM 2
805
R1560
=PP5V_PWRON_LTC3707_EXTVCC
0.22uF
C1570
RLA130N03
3V_TG
20%
2 10V
CERM
1206
5V_BOOST_ESR
IRF7811W
C1530
4.7uF
100K
22 21
MBRS140XXG
10
20%
2 10V
CERM
1210
1M
R1530
5%
1/16W
MF-LF
402 2
R15101
MBR0540XXG
1
1
D1511
SOD-123
D1501
SMB
20%
10V
CERM 2
1210
20%
6.3V 2
TANT
CASE-D4-LF
22uF
CRITICAL
3 2
IHLP-5050
1%
1/4W
MF-LF
1206
Q1551
1
4.7uH
0.0052
CRITICAL
R15321
CRITICAL
L1501
6 7
3707_INTVCC
VOLTAGE=5V
RLA130N03
5V_RSNS
CRITICAL
=PPVIN_ALL_LTC3707
5V3VPWRON_EN_L_RC
XW1500
SM
SOT23-LF
220pF
C1533
C1532
5%
25V
2 CERM
402
1
1
26
2N7002
0.01uF
20%
2 16V
CERM
402
5V START TO TURN ON ~12.5MS =5V3V3PWRON_EN_L goes low
3V START TO TURN ON ~25MS AFTER =5V3V3PWRON_EN_L goes low
DIODE WILL ENSURE REGULATOR TURNS ON QUICKLY
POWERDOWN DELAY IS AROUND 4MS-15.6MS, VIA RC NETWORK
10
=PP3V3_PWRON_RUNFET
4
26
3V3RUN_EN_L
=PP3V3_RUN_RUNFET
10
6
5
10
=PP5V_PWRON_RUNFET
C1585
C1592
0.01uF
10
=PP5V_PWRON_TRACKPAD
TPAD_SEQ_PMU
R1535
100K
5%
1/16W
MF-LF
402 2
26
=5VPWRONTPAD_EN_L
=PP5V_TPAD_FET
5VRUNHD_EN_L
2
TSOP-LF
Q1535
C1591
100UF
20%
2 6.3V
POLY
B2
C1590
10
0.0022uF
2
TSOP-LF
10%
50V
CERM
402
C1587
20%
6.3V
X5R 2
603
C1536
Q1590
10UF
TSOP-LF
SI3443DV
C1586 1
SI3443DV
=PP5V_RUN_HDDFET
10
2
1
20%
6.3V
X5R 2
603
20%
16V
CERM
402
26
10UF
100UF
20%
6.3V
POLY
B2
SI3443DV
Q1585
10UF
20%
6.3V
2 X5R
603
C1580
0.1uF
1
20%
10V
CERM
402
4
26
5VRUN_EN_L
=PP5V_RUN_RUNFET
3
1
5V/3.3V Supplies
C1581
1
2
10UF
20%
2 6.3V
X5R
603
10
TSOP-LF
SI3443DV
Q1580
C1582
SYNC_MASTER=N/A
100UF
20%
2 6.3V
POLY
B2
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
15
115
SHT
OF
NONE
1.5V/1.8V SWITCHER
10
=PP5V_PWRON_MAX1715_VDD
16 10
=PPVIN_ALL_MAX1715
D
R1630
1
2
100K
5%
1/16W
MF-LF
402 2
DP1620
BAS16TW-X-F
MAX1715_EN_L_RC
2.2uF
5%
1/16W
MF-LF
2 402
Q1640
MF-LF
402
DIODE PROVIDE PROVIDE QUICK TURN-ON
POWER DOWN DELAY 1.5MS TO 3.5MS
DP1620
C1640
1_8V_ILIM 1_5V_ILIM
0.01uF
BAS16TW-X-F
SOT-363
20%
16V
2 CERM
402
R16211
158K
1%
1/16W
MF-LF
402 2
R1671
158K
1%
1/16W
MF-LF
2 402
MAX1715_GND
16 10
5%
1/16W
MF-LF
2 402
MAX1715_TON
SOT23-LF
NO STUFF
R1633
0
5%
1/16W
16 10
21
11
ILIM1
ILIM2
ON1
ON2
25
BST1
26
DH1
27
LX1
10
CRITICAL
C1652 1
R1670
4.7uF
20%
25V
CERM 2
1206
20%
25V
CERM 2
1206
1_5V_BOOST
8 7
6 5
1
Q1651
4
SO8
L1651
4.7
1_5V_BST
5%
1/10W
MF-LF
603
20%
2 25V
CERM
603
RLA130N03
CRITICAL
C1670
0.1uF
CRITICAL
2 1
26
NO STUFF
R1651
C1655
10UF
20%
6.3V
2 X5R
603
5.11K
1%
1/16W
MF-LF
2 402
C1653 1
10K
Rb
SO-8
D1651
SMB
TON
OUT1
PGOOD
REF
OUT2 14
FB1
AGND
FB2 13
THRML
1_5V_DL
C1671 1
3 2
0.0022UF
10%
50V
CERM 2
402
MAX1715_GND
CRITICAL
1_8V_DH
Q1601
RLA130N03
SO8
1_8V_LX
Ra
5
6 7
CRITICAL
Q1602
1_8V_DL
R1634 R1602
0
2
SM4-LF
1%
1/16W
MF-LF
402 2
Rb
SO-8
B130LBT01XF
C1621
C1603
10UF
D1601
SMB
IRF7805ZPBF
NO STUFF
10K
5%
1/16W
MF-LF
2 402
=PP1V8_PWRON_REG
L1601
4.7uH
8.06K
1%
1/16W
MF-LF
402 2
10
CRITICAL
2 3
1_8V_FB
16
4.7uF
R16011
29
C1632
6 7
20%
10V
2 CERM
603
C1620
1uF
XW1600
SM
1
20%
25V
2 CERM
603
C1602
20%
25V
2 CERM
1206
1_8V_BOOST
0.1uF
22
SKIP
5%
1/10W
MF-LF
603
16
19
4.7
1_8V_BST
DH2 17
LX2
CRITICAL
1
R1620
18
MAX1715_REF
NO STUFF
B130LBT01XF
1%
1/16W
MF-LF
2 402
28
20%
25V
2 CERM
1206
NC
NC
NC
CRITICAL
R1652
23
5%
1/16W
MF-LF
2 402
IRF7805ZPBF
2
20%
2.5V-ESR9V 2
POLY
CASE-D2E-LF
R1632
Q1652
1_5V_FB
330UF
7 6
15
DL2
1_5V_LX
CRITICAL
C1601
4.7uF
PGND
SM4-LF
BST2
DL1
=1V8_1V5PWRON_PGOOD
V+
NC_15
NC_23
NC_28
24
1_5V_DH
4.7uH
Ra
CRITICAL
QSOP-LF
4.7uF
10
MAX1715_SKIP
MAX1715
3
CRITICAL
=PP1V5_PWRON_REG
VDD
U1600
12
C1651
=PPVIN_ALL_MAX1715
20
VCC
16
=PPVIN_ALL_MAX1715
20%
2 10V
CERM
805
C1630
20%
2 10V
CERM
805
2N7002
330K 2
R1631
3
D
R1640
1
PP5V_MAX1715_VCC
VOLTAGE=5V
MAX1715_ON
SOT-363
6
1
=1V8_1V5PWRON_EN_L
5%
1/16W
MF-LF
402
NO STUFF
SOT-363
BAS16TW-X-F
26
20
DP1620
C1631
2.2uF
R1641
C1604
C1605
330UF
20%
2 6.3V
POLY
CASE-D2-LF
0.0022UF
150uF
20%
2 6.3V
X5R
603
20%
2 2.5V-ESR9V
POLY
CASE-D2E-LF
2 3
10%
2 CERM
402
50V
MAX1715_GND
VOLTAGE=0V
Vout = 1.0V * (1 + Ra/Rb)
10
=PP1V8_PWRON_RUNFET
=PP1V8_RUN_RUNFET
C1680
R1680
10UF
20%
6.3V
X5R 2
603
100K
=PP1V5_PWRON_RUNFET
SI3446DV
1
=PP1V5_RUN_RUNFET
10
26
2 3 6 7
5%
1/16W
MF-LF
2 402
Q1685
10
10
CRITICAL
Q1680
SI6467BDQ-E3
1V8RUN_EN_L
TSSOP
TSOP-LF
1 5 8
5
6
1V5RUN_EN
26
C1686 1
10UF
1.8V/1.5V Supplies
C1685
C1681
1000pF
10%
2 25V
X7R
402
20%
6.3V 2
X5R
603
SYNC_MASTER=N/A
2200pF
1
NO STUFF
C1682 1
1000PF
SYNC_DATE=N/A
5%
50V
CERM
603

10%
25V 2
X7R
402

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
16
115
SHT
OF
NONE
2.5V SWITCHER
=PP3V3_PWRON_LTC3412
5%
1/16W
MF-LF
402 2
R1723
C1710
22UF
5%
1/16W
MF-LF
2 402
C1711
22UF
20%
6.3V
2 CERM
1206
20%
6.3V
2 CERM
1206
LTC3412_RT
LTC3412_RUNSS
SVIN PVIN
LTC3412
RT TSSOP-LF
PGOOD 2
RUN/SS
=2V5PWRON_EN_L
R1720
7.5K
C1720
1%
1/16W
MF-LF
2 402
R1724
C1722 1
470PF
10%
50V
CERM 2
402
100PF
5%
50V
CERM 2
402
LTC3412_VFB
VFB
CRITICAL
R1731
5%
1/16W
MF-LF
2 402
110K
1%
1/16W
MF-LF
2 402
1.0uH-3.48A
1
LTC3412_SW
11
14
15
47uF
20%
2 6.3V
X5R
1206-1
309K
1%
1/16W
MF-LF
2 402
R1732
C1701 1
47uF
75K
1%
1/16W
MF-LF
2 402
5%
50V
CERM 2
603
C1700
R1733
2200pF
2
SM-LF
LTC3412_VFB_DIV
10
L1700
26
THERM
SGND PGND PAD
LTC3412_ITH_RC
C1721
10
SW
BURST MODE
NO STUFF
SOT-363
ITH
SYNC/MODE
1%
1/16W
MF-LF
2 402
=PP2V5_PWRON_REG
=2V5PWRON_PGOOD
17
26
2N7002DW-X-F
12
13
Q1740
LTC3412_ITH
LTC3412_SYNC
402K
+/-0.25pF
50V
CERM 2
402
CRITICAL
3
R1730
5.6pF
U1700
2
C1730 1
16
4.7M
CONTINUOUS MODE
R17221
10
XW1700
SM
1
LTC3412_GND
VOLTAGE=0V
20%
6.3V
X5R 2
1206-1
B
Q1780
TSSOP
SI6467BDQ-E3
=PP2V5_PWRON_RUNFET
=PP2V5_RUN_RUNFET
10
C1781 1
1 5
6 7
10
10UF
20%
6.3V 2
X5R
603
C1780
1000pF
26
2V5RUN_EN_L
2
10%
25V
X7R
402
2.5V Supply
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
17
115
SHT
OF
NONE
Page Notes
3.3V Regulator

- =PPBUS_FW (system supply for bus power)
- =PPBU_RUN_FW (backup PHY power)
- =PP3V3_RUN_FWPORTPWRSW
10
D1975
=PPFW_P3V3VESTA
CRITICAL
SC-59
CRITICAL
U1970
L1970
LM2594
3
10
PPVIN_VESTA3V3
=PPBU_RUN_FW

(NONE)
SM-LF
VIN
FB
VOUT
GND ON/OFF
VOLTAGE=33V
=PP3V3_VESTA_REG
2.5V LDO
10
Vout = 3.3V @ 500mA
PLC
CRITICAL
U1980
VESTA3V3_SW
SMD20E40C-X-F

- VESTA1V2_BURST / VESTA1V2_PULSE
Controls operating mode of Vesta 1.2V
regulator. If both options are off the
regulator will be in continuous mode.
100uH-0.8A
C1970
D1970
10uF
N20P20%
50V
CERM
2320
SOT-25A-LF
C1971
10
=PP3V3_VESTA_2V5REG
=PP2V5_VESTA_LDO
100UF
SMD
1 VIN
20%
2 6.3V
POLY
B2
MMBRM140XXG
2
MM1572FN
CRITICAL
GND
C1980
C1981
1uF
10%
6.3V
CERM
402
CRITICAL
Q1965
CRITICAL
NDS9407
F1965
10
=PPBUS_FWPWRSW
D1965
SOI-LF
8
2
MINISMDC
VOLTAGE=25V
VOLTAGE=25V
PPBUS_FW_FET_D
PPBUS_FWPWRSW_F
=PPBUS_FW_FET
SMB
1.5A-24V
2
Vout = 2.5V @ 150 mA
VESTA2V5_NOISE
3 CONT NOISE 4
Port Power Switch
10
VOUT 5
0.01uF
20%
16V
CERM
402
C1982
10UF
20%
6.3V
X5R
603
10
B340XF
1
5
C1965
R1965
1
4
0.01uF
470K
20%
16V
CERM
402
5%
1/16W
MF-LF
2 402
10
1.2V Regulator
=PP3V3_VESTA_1V2REG
R1990
FWPWR_EN_L_DIV
1
10
Burst Mode
VESTA1V2_BURST
5%
1/16W
MF-LF
2 402
=PP3V3_RUN_FWPORTPWRSW
R1992
5%
1/16W
MF-LF
402 2
DP1960
10%
6.3V
CERM
402
5%
1/16W
MF-LF
402 2
2N7002
FWPWR_EN
SOT23-LF
DP1960
5%
1/16W
MF-LF
402
SOT-363
5
VESTA1V2_RT
VESTA1V2_MODE
2
8
25 13 12
SYS_ACIN
R1963
C1992
VESTA1V2_ITH
R1996
CRITICAL
5%
50V
CERM
402
1M
2
1
5%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
Enables port power when machine is

running or on AC and not shut down.
4.99K
2
2
Vout = 1.199V @ 1.2 A
1%
1/16W
MF-LF
402
<R1>
R1998
C1994
10K
5%
50V
CERM
402
1%
1/16W
MF-LF
2 402
0.0033uF
2
C
Vout = 0.8V * (1 + (R2 / R1))
C1993
100pF
R1995
324K
10
4.99K
VESTA1V2_ITH_RC
R1994 1
<R2>
1
R1997
22pF
1
1%
1/16W
MF-LF
402 2
470K
5%
1/16W
MF-LF
402
=PP1V2_VESTA_REG
2
VESTA1V2_VFB
10
ITH
SGND
PGOOD
PGND
Continuous
Mode
If =FWPWR_PWRON is low when off:
5%
1/16W
MF-LF
402
2.2uH
1
VESTA1V2_SW
SYNC/MODE VFB 9
Enables port power when machine is

running or on AC.
SOT-363
FWPWR_ACIN
SW 4
SHDN/RT
If =FWPWR_PWRON is NC:
DP1960
10K
MSOP-LF
BAS16TW-X-F
R1961
CRITICAL
L1990
LTC3411
R1993 1
BAS16TW-X-F
=FWPWR_PWRON
10K
26
20%
6.3V
X5R
603
SVIN PVIN
U1990
1uF
Pulse Mode
VESTA1V2_PULSE
Q1960
SOT-363
3
SM1-LF
BAS16TW-X-F
FWPWR_RUN
C1991
1M
5%
1/16W
MF-LF
402 2
100K
R1991
C1990
10UF
VOLTAGE=3.3V
10K
FWPWR_EN_L
R1960 1
PPVOUT_VESTA1V2
5%
1/16W
MF-LF
402
R1966
330K
10
10%
50V
CERM
402
XW1990
VESTA1V2_SGND
C1995
22uF
20%
6.3V
X5R
805
SM
2
VOLTAGE=0V
=PP2V5_VESTA
10
L1900
FERR-EMI-600-OHM
1
C1920
PP1V2_VESTA_AVDDL
0.1uF
20%
10V
CERM
402
C1903
0.1uF
0.1uF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
0.1uF
2
20%
10V
CERM
402
0.1uF
2
20%
10V
CERM
402
DVDD
AVDDL
AVDD
65 18 10
67 66
R1951 1
20K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
C1950
VESTA_RESET 66
10%
6.3V
CERM
402
SOT-363
5%
1/16W
MF-LF
402
2N7002DW-X-F
TP_VESTA_DNC_B9
TP_VESTA_DNC_C9
TP_VESTA_DNC_E9
9
9
D7
E10
E7
E8
D8
B9
C9
E9
SOT-363
TDI
TDO
TCK
TMS
TRST*
0.1uF
2
20%
10V
CERM
402
C1930
NC
NC
C1931
0.1uF
0.1uF
20%
10V
CERM
402
20%
10V
CERM
402
=PP3V3_VESTA
10 18 65 66 67
C3
M13
C1940
A7
F15
C1941
C1942
C1943
0.1uF
0.1uF
0.1uF
0.1uF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
K1
OMIT
U8500
2.5V_EN M3
TP_VESTA_2_5V_EN
REGSUP1 E1
REGSEN1 F1
REGCTL1 G5
TP_VESTA_REGSUP1
TP_VESTA_REGSEN1
NC? TP_VESTA_REGCTL1
BCM5462
FBGA-200
1 OF 3
DNC
DNC
DNC
Vesta Power & Misc

SYNC_MASTER=N/A
SYNC_DATE=N/A

REGSUP2 E2
REGSEN2 F2
REGCTL2 G4
R1952 to enable wirespeed feature

1
C1925
20%
10V
CERM
402
OVDD
VESTA MISC
RESET*
Q1950
D
2
1uF
10K
2N7002DW-X-F
=JTAG_VESTA_TDI
=JTAG_VESTA_TDO
=JTAG_VESTA_TCK
=JTAG_VESTA_TMS
=JTAG_VESTA_TRST_L
R1952 1
Q1950
D
5
=PP3V3_VESTA
VESTA_RESET_L_RC
H4
Schmitt trigger
R1950 1
0.1uF
PVDD
(Int PU)
VESTA_RESET_L
C1924
20%
10V
CERM
402
A1
=PP3V3_VESTA
0.1uF
20%
10V
CERM
402
Reset circuit per Vesta design guide

67 66 65 18 10
C1923
0.1uF
N4
A15
R12
R3
P11
P10
P5
P4
C1913
N10
C1922
20%
10V
CERM
402
N9
C1912
0.1uF
N9/N10
N6
N5/N6
N5
L9/M9
C1921
20%
10V
CERM
402
1
M9
0.1uF
2
C1902
20%
10V
CERM
402
C1911
0.1uF
L6/M6
C1910
C1901
20%
10V
CERM
402
M6
0.1uF
L9
20%
6.3V
X5R
603
J1
C1900
10UF
L6
C1908
C15
0.1uF
VOLTAGE=1.2V
SM
B15
=PP1V2_VESTA
B1
10
NC
NC
TP_VESTA_REGSUP2
TP_VESTA_REGSEN2
NC? TP_VESTA_REGCTL2


K2
J2
F14
C14
B7
B2
A2
P9
P8
P7
P6
GND
N8
N7
M8
M7
L8
L7
J12
J11
H12
H11
AGND

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
19
115
SHT
OF
NONE
8
Page Notes
10
VCore Bypassing
=PPVCORE_PWRON_I2
C2146
C2147
C2120
C2121
C2122
C2123
C2124
(25 Balls on I2)
C2125
C2126
C2127
C2128
4 X 10uF (0603)
25 X 1uF (0402)
1
C2129
C2130
10UF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
1uF
20%
6.3V
X5R
603
20%
6.3V
X5R
603
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C2135
C2136
C2137
C2138
C2140
C2141
C2142
C2143
C2148
C2149
C2133
C2134
C2139
Y17
VDD15_24
VDD15_23
VDD15_22
VDD15_21
VDD15_20
VDD15_19
VDD15_18
VDD15_17
VDD15_16
VDD15_15
VDD15_14
VDD15_13
VDD15_12
VDD15_11
VDD15_10
VDD15_9
VDD15_8
VDD15_7
VDD15_6
VDD15_5
VDD15_4
VDD15_3
VDD15_2
VDD15_1
VDD15_0

(NONE)
10%
6.3V
CERM
402
Y15

(NONE)
1uF
2
W22
R16
W20
P20
W18
AB21
V22
C2144
V19
10%
6.3V
CERM
402
V17
1uF
10%
6.3V
CERM
402
U22
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
U20
1uF
10%
6.3V
CERM
402
U18
1uF
10%
6.3V
CERM
402
C2132
1uF
U15
1uF
10%
6.3V
CERM
402
T19
1uF
10%
6.3V
CERM
402
T15
1uF
10%
6.3V
CERM
402
R21
1uF
10%
6.3V
CERM
402
R18
1uF
10%
6.3V
CERM
402
P16
1uF
10%
6.3V
CERM
402
N17
1uF
20%
6.3V
X5R
603
AC19
10UF
20%
6.3V
X5R
603
AC16
10UF
C2131
10UF
T22

- =PPVCORE_PWRON_I2
- =PP1V5_PWRON_I2_PLL
- =PP3V3_PWRON_I2_IO1
- =PP3V3_PWRON_I2_IO2
- =PP3V3_PWRON_I2_AGPPCI
- =PP3V3_PWRON_I2_MAXBUS
NOTE: The four 3.3V rails are meant to be
aliased together. They are called
out separately for test purposes.
NOTE: When these four rails are not
aliased together, make sure there
is at least one 10uF cap per rail.
AA22
OMIT
OMIT
U2100
U2100
I2
I2
BGA
CORE POWER
& GND
BGA
PLL POWER
10
R2101
=PP1V5_PWRON_I2_PLL
PP1V5_PWRON_I2_PLL1AVDD
C2101
AA20
(1 of 14)
(3 of 14)
PLL1_AVDD
VOLTAGE=1.5V
5%
1/16W
MF-LF
402
1uF
2
4.7
AA13
AA15
10%
6.3V
CERM
402
PLL1
AA17
32/48 MHZ
AA21
AA25
AA29
Y20
R2102
3.3V I/O DECOUPLING
=PP3V3_PWRON_I2_IO1
10
C2150
C2151
C2152
C2153
C2154
C2155
1uF
1uF
1uF
1uF
1uF
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C2102
C2159
C2160
C2161
1uF
1uF
1uF
1uF
1uF
1uF
3.3V I/O POWER
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
VDD33_IO_1 (14)
VDD33_IO_2 (12)
For USB, FireWire,

I2S and some GPIOs
(2 of 14)
VDD33_0
VDD33_AGP
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
VDD33_6
VDD33_7
VDD33_8
VDD33_9
VDD33_10
VDD33_11
VDD33_12
VDD33_13
VDD33_14
VDD33_15
VDD33_16
VDD33_17
VDD33_18
VDD33_19
VDD33_20
VDD33_21
VDD33_22
VDD33_23
VDD33_24
VDD33_25
VDD33_26
VDD33_27
VDD33_
VDD33_28
MAXBUS
VDD33_29
VDD33_30
VDD33_31
VDD33_32
VDD33_33
VDD33_34
VDD33_35
VDD33_36
VDD33_37
VDD33_38
VDD33_39
VDD33_40
VDD33_41
VDD33_42
VDD33_43
VDD33_44
VDD33_45
VDD33_46
VDD33_47
VDD33_PCI (18)
C2158
BGA
For GPIOs, Pwr Mgt
VOLTAGE=1.5V
AB22
AB24
PLL2
AC2
Y19
PLL2_VSSA
R2103
AK19
PLL3_AVDD
VOLTAGE=1.5V
AC5
10%
6.3V
CERM
402
PLL3
AD16
49.15 MHZ
AD21
AD29
AE14
E3
L10
PLL3_VSSA
R2104
F5
J8
C2162
C2163
1uF
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
4.7
1uF
=PP3V3_PWRON_I2_IO2
10
H9
PLL4_AVDD
VOLTAGE=1.5V
5%
1/16W
MF-LF
402
C2104
AE25
SYSCLK
PCI(SS)
AGP(SS)
10%
6.3V
CERM
402
C2164
C2165
1uF
10%
6.3V
CERM
402
1uF
10%
6.3V
CERM
402
C2166
1uF
2
10%
6.3V
CERM
402
C2167
1uF
2
10%
6.3V
CERM
402
C2168
1uF
2
C2169
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
4.7
1
AB13
AC6
AF11
C2170
C2171
C2172
C2173
C2174
C2175
1uF
1uF
1uF
1uF
1uF
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C2105
AF9
10
C2106
1uF
AJ6
AM3
1uF
Y13
M16
10%
6.3V
CERM
402
1uF
10%
6.3V
CERM
402
C2179
1uF
2
10%
6.3V
CERM
402
1uF
10%
6.3V
CERM
402
C2199
AH20
AH23
C2180
C2181
1uF
10%
6.3V
CERM
402
C2182
10%
6.3V
CERM
402
1uF
10%
6.3V
CERM
402
C2183
10%
6.3V
CERM
402
1uF
C2184
10%
6.3V
CERM
402
1uF
C2185
10%
6.3V
CERM
402
1uF
20%
6.3V
X5R
603
M24
PLL6_AVDD
VOLTAGE=1.5V
AH14
AJ14
AJ17
AJ2
PLL6
AJ20
AJ23
4.7
PLL6_VSSA
1uF
AJ26
AJ27
AH22
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
E8
AJ8
H11
AM11
H12
AM14
H14
AM17
H15
AM2
H17
AM20
H18
AM23
H2
AM26
H20
AM29
H23
AM32
H24
AM35
H26
AM5
H27
AM7
H29
AM8
H32
AR11
H35
AR14
H5
AR17
H8
AR2
K10
AR20
K11
AR23
K14
AR26
K17
AR29
K20
AR32
K23
AR35
K25
AR5
K26
AR8
K29
B11
L2
B14
L20
B17
L27
B2
L29
B20
L32
B23
L35
L5
B26
B29
L8
B32
M13
B35
M15
B5
M17
B8
M19
E11
M21
E14
M23
E17
M26
E2
N14
E20
N16
E23
N18
E26
N23
E29
N25
C2186
C2187
10%
6.3V
CERM
402
1uF
10%
6.3V
CERM
402
C2188
1uF
2
10%
6.3V
CERM
402
C2189
1uF
2
10%
6.3V
CERM
402
C2190
1uF
2
C2191
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C2109
1uF
2
2
4.7
AH21
PLL7_VSSA
AK10
PLL9_AVDD
C2193
1uF
10%
6.3V
CERM
402
C2194
10%
6.3V
CERM
402
1uF
10%
6.3V
CERM
402
C2195
10%
6.3V
CERM
402
1uF
C2196
10%
6.3V
CERM
402
1uF
C2197
10%
6.3V
CERM
402
1uF
PLL9
P24
P27
P29
P32
P35
P8
R13
R15
R17
R19
R20
R22
R25
R29
T16
T18
T20
U13
U16
U2
U21
U25
U28
U32
U35
U5
U8
V12
V16
V20
V28
W15
W19
W21
W25
W26
Y11
Y16
Y18
Y2
Y22
Y29
Y32
Y35
Y5
Y8
10%
6.3V
CERM
402
AGP TRACK

PLL9_VSSA
SIZE
2
APPLE COMPUTER INC.
P5

1uF
P21
SYNC_DATE=N/A
DRAWING NUMBER
REV.
C
051-6929
21
115
SHT
OF
NONE
P2
SCALE
P17
I2 Power
SYNC_MASTER=N/A
VOLTAGE=1.5V
5%
1/16W
MF-LF
402
AL10
C2192
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
PCI TRACK
AL30
AP32
AJ5
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
PLL7_AVDD
AL29
AP29
E5
PLL7
10%
6.3V
CERM
402
AL27
AP26
E35
AJ35
R2109
1uF
AP23
E32
AJ32
VOLTAGE=1.5V
5%
1/16W
MF-LF
402
C2107
1uF
AH27
AL26
R2107
AH26
AL24
PLL5_VSSA
AJ24
AH24
AL23
AG14
AJ11
N24
AF8
AG11
10UF
AC21
1
AF5
SYS TRACK
M22
AD22
4.7
PLL5
10%
6.3V
CERM
402
M18
AD20
AF32
AF35
INT REF
PCI
AGP
ATA
5%
1/16W
MF-LF
402
10
AJ3
C2178
PLL5_AVDD
R2106
AF6
AD9
VOLTAGE=1.5V
AE9
=PP3V3_PWRON_I2_MAXBUS
=PP3V3_PWRON_I2_AGPPCI
C2177
AF27
AG29
10%
6.3V
CERM
402
AF3
C2176
2
5%
1/16W
MF-LF
402
1uF
T13
AC3
AF18
AF29
2
1
PLL4_VSSA
R2105
R14
AC15
AF10
AF2
H10
N13
P6
AE19
AE20
PLL4
L6
P3
AE15
AE17
L3
P12
AC32
AC35
AJ19
H6
AC26
AC29
5%
1/16W
MF-LF
402
C2103
1uF
4.7
AH17
H3
AB16
AC25
C2157
PLL2_AVDD
AC20
U2100
1
AA19
45.16 MHZ
C2156
10%
6.3V
CERM
402
OMIT
I2
2
5%
1/16W
MF-LF
402
1uF
2
AB12
AB15
4.7
1 X 10uF (0603)
48 X 1uF (0402)
(48 Balls on I2)
PLL1_VSSA
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
AJ29
8
Page Notes

- =PP2V7R5V5_PWRON_I2VCORE
- =PPVCORE_PWRON_I2_REG
- =PPVIN_PWRON_I2PLLVDD
- =PP1V5_PWRON_I2PLLVDD_LDO
- =I2VCORE_PGOOD
I2 VCore Regulator

- I2VCORE_CONT / I2VCORE_BURST
Selects between forced continuous and
burst mode for LTC3412 regulator.
- I2VCORE_xVx
Selects appropriate resistor for the
indicated LTC3412 output voltage.
D
10
=PP2V7R5V5_PWRON_I2VCORE
One for each PVIN pin
Vout = 0.8V * (1 + (Ra / (Rb1 + Rb2)))

C2200
I2VCORE_CONT
0
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
I2VCORE_RT
5
I2VCORE_RUNSS
I2VCORE_ITH
309K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
VFB
I2VCORE_VFB
2
C2206
I2VCORE_1V6
114S0442
RES,210K,1%,MF-LF,0402
R2210
I2VCORE_1V7
114S0446
RES,232K,1%,MF-LF,0402
R2210
I2VCORE_1V8
=PPVCORE_PWRON_I2_REG
I2VCORE_1V5
R2210 1
15
BOM OPTION
10
1%
1/16W
MF-LF
402
C2210
2
22pF
2
2
C2215
47uF
162K
5%
50V
CERM
402
20%
6.3V
X5R
1206-1
C2216
47uF
<Ra>
C2205
100pF
14
I2VCORE_ITH_RC
1
CRITICAL
R2210
SM-LF
THERM
SGND PGND PAD
470pF
10%
50V
CERM
402
SWITCH_NODE=TRUE
11
SW
RES,185K,1%,MF-LF,0402
CRITICAL
I2VCORE_SW
10
I2VCORE_MODE
REFERENCE DES
L2200
17
R2204
7.5K
ITH
SYNC/MODE
C2207
R2205
QTY
1.0uH-3.48A
CRITICAL
DESCRIPTION
114S0437
26
Open-Collector
TSSOP-LF
RT
PGOOD 2
RUN/SS
20%
6.3V
CERM
1206
=I2VCORE_PGOOD
LTC3412
SVIN PVIN
U2200
13
PART NUMBER
22uF
20%
6.3V
CERM
1206
C2201
16
4.7M
R2208
12
R2207
22uF
20%
6.3V
X5R
1206-1
2200pF
5%
50V
CERM
603
5%
50V
CERM
402
XW2200
SM
GND_I2VCORE
VOLTAGE=0V
I2VCORE_BURST
R2209 1
R2211 1
0
5%
1/16W
MF-LF
402
110K
1%
1/16W
MF-LF
402
<Rb1>
I2VCORE_MODE_VDIV
If I2VCORE_BURST is selected:
R2212
Iburst = (Vburst - 0.2V) * (3.75A / 0.8V)
75K
1%
1/16W
MF-LF
402
Vburst = 0.8V * (Rb2 / (Rb1 + Rb2))
<Rb2>
I2 PLL LDO
=PP1V5_PWRON_I2PLL_LDO
CRITICAL
U2250
10
C2254
LT1962-ADJ
=PPVIN_PWRON_I2PLLVDD
C2250
1uF
20%
10V
CERM
603
IN
NC
NC
NC
NC
2
5
SHDN
OUT
10%
16V
CERM
402
ADJ 2
R2255
Iadj = 30nA at 25 C
15.8K
0.01uF
MSOP-LF
8
10
Vout = 1.22V * (1 + Ra/Rb) + (Iadj * Ra)
2
2
1%
1/16W
MF-LF
402
<Ra>
I2PLLVDD_ADJ
10uF
2
BYP 3
GND 4
I2PLLVDD_BYP
R2256
C2259
20%
6.3V
X5R
603
68.1K
1%
1/16W
MF-LF
402
<Rb>
I2 Power Supplies
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
22
115
SHT
OF
NONE
NET_TYPE
SPACING
PHYSICAL
I2_FBCLK
I2_FBCLK
I2_FBCLK
I2_FBCLK
I2_FBCLK
I2_FBCLK
I2_FBCLK
I2_FBCLK
I2_FBCLK
I2_FBCLK
I104
I2_FBCLK
I2_FBCLK
I119
CLOCK
CLOCK
I120
CLOCK
CLOCK
I105
MaxBus Feedback Clock Network
DIFFERENTIAL_PAIR
I2_MAXBUS_FBCLK_IN
I2_MAXBUS_FBCLK_MATCHED
21
21
I2_AGP_FBCLK_IN
I2_AGP_FBCLK_MATCHED
21
21
21
I2_PCI_FBCLK_IN
I2_PCI_FBCLK_MATCHED
21
21
=CLK33M_TBEN_SYNC
=SYSCLK_TBEN_SYNC
R2350 1
11 21
11 21
5%
1/16W
MF-LF
402
32
IN
R2352
I2_MAXBUS_FBCLK_SHORTEST
R2340
Keep short
I2_MAXBUS_FBCLK_OUT
5%
1/16W
MF-LF
402
Keep short
21
I2_MAXBUS_FBCLK_IN
=I2_MAXBUS_FBCLK_IN
OUT
MAKE_BASE=TRUE
32
5%
1/16W
MF-LF
402
AGP Feedback Clock Ladder

R2365
43
IN
I2_AGP_FBCLK_OUT
I2_AGP_FBCLK_SHORTEST
R2360
21
5%
1/16W
MF-LF
402
0
5%
1/16W
MF-LF
402
43
OUT =I2_AGP_FBCLK_IN
21
2
R2367
0
I2_AGP_FBCLK_IN
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
I2 Configuration Straps
34 33 32 10
PCI Feedback Clock Ladder
=PP1V5R1V8_MAXBUS
I2_MAXBUS_33OHM
1
33 32 9
33 32 9
33 32 9
33 32 9
33 32 9
33 32 9
MAXBUS_D41_PU
1
R2306
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
MAXBUS_D44_PU
R2304
R2385
R2310
10K
I2_FW_BETA
R2300
MAXBUS_D43_PU
1
R2302
59
IN
I2_PCI_FBCLK_OUT
I2_PCI_FBCLK_SHORTEST
R2380
R2308
10K
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
OUT =I2_PCI_FBCLK_IN
59
21
R2387
1
5%
1/16W
MF-LF
402
MAXBUS_TBEN_SYNC
MAXBUS_TBEN_SYNC
C2390
0.1uF
MAXBUS_D43_PD
1
R2303
R2307
R2311
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
MAXBUS_D44_PD
R2301 1
10
R2305 1
A2
VCC
R2309 1
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
B2
B1
C2
21 11
Description
HIGH
1394b Support (Beta Mode)
LOW
C2392
0.1uF
20%
2 10V
CERM
402
=CLK33M_TBEN_SYNC
A1
MAXBUS_TBEN_SYNC
CRITICAL
20%
2 10V
CERM
402
A2
VCC
74AUC1G74
MAXBUS_TBEN_SYNC
CRITICAL
A2
VCC
74AUC1G74
U2390
U2391
U2392
BGA-YZP
BGA-YZP
BGA-YZP
PRE
Q
D
CLR
Q*
CLK
GND
B2
D2
TBEN_SYNC_F1
C1
NC
B1
C2
A1
D1
Tied
=PP1V8_RUN_TBEN_SYNC
MAXBUS_D42_PD
10K
MAXBUS_TBEN_SYNC
C2391
0.1uF
20%
2 10V
CERM
402
MAXBUS_D41_PD
10K
I2_FW_LEGACY
MAXBUS_DATA<54>
21
MAKE_BASE=TRUE
I2_MAXBUS_50OHM
MAXBUS_DATA<62>
2
I2_PCI_FBCLK_IN
MAXBUS_DATA<62>
MAXBUS_DATA<54>
MAXBUS_DATA<44>
MAXBUS_DATA<43>
MAXBUS_DATA<42>
MAXBUS_DATA<41>
Signal
0
5%
1/16W
MF-LF
402
MAXBUS_D42_PU
0
5%
1/16W
MF-LF
402
PRE
Q
D
CLR
Q*
CLK
GND
B2
D2
TBEN_SYNC_F2
C1
B1
C2
NC
A1
D1
PRE
Q
D
CLR
Q*
CLK
GND
MAXBUS_TBEN_SYNC
CRITICAL
74AUC1G74
MAXBUS_TBEN_SYNC
R2392
D2
C1
MAXBUS_TBEN_SYNC 1
MAXBUS_TBEN 33
5%
1/16W
MF-LF
402
D1
1394a Support (Legacy Mode)
HIGH
50-Ohm MaxBus Drivers
LOW
33-Ohm MaxBus Drivers
TBEN_SYNC_CLR_L
MAXBUS_DATA<44:41>
See Table Below
21 11
=SYSCLK_TBEN_SYNC
TABLE_BOMGROUP_HEAD
BOM GROUP
Tied
Description
I2_MAXBUS_133MHZ
0000
133.12MHz CPU / 266.24MHz DDR
MAXBUS_D44_PD,MAXBUS_D43_PD,MAXBUS_D42_PD,MAXBUS_D41_PD
I2_MAXBUS_150MHZ
1000
MAXBUS_D44_PU,MAXBUS_D43_PD,MAXBUS_D42_PD,MAXBUS_D41_PD
I2_MAXBUS_166MHZ
0100
MAXBUS_D44_PD,MAXBUS_D43_PU,MAXBUS_D42_PD,MAXBUS_D41_PD
I2_MAXBUS_172MHZ
1100
MAXBUS_D44_PU,MAXBUS_D43_PU,MAXBUS_D42_PD,MAXBUS_D41_PD
I2_MAXBUS_177MHZ
0010
MAXBUS_D44_PD,MAXBUS_D43_PD,MAXBUS_D42_PU,MAXBUS_D41_PD
I2 Supplemental
BOM OPTIONS
TABLE_BOMGROUP_ITEM
SYNC_MASTER=N/A
SYNC_DATE=N/A
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM
I2_MAXBUS_183MHZ
1010
MAXBUS_D44_PU,MAXBUS_D43_PD,MAXBUS_D42_PU,MAXBUS_D41_PD
I2_MAXBUS_189MHZ
0110
MAXBUS_D44_PD,MAXBUS_D43_PU,MAXBUS_D42_PU,MAXBUS_D41_PD
I2_MAXBUS_194MHZ
1110
MAXBUS_D44_PU,MAXBUS_D43_PU,MAXBUS_D42_PU,MAXBUS_D41_PD
I2_MAXBUS_200MHZ
0001
MAXBUS_D44_PD,MAXBUS_D43_PD,MAXBUS_D42_PD,MAXBUS_D41_PU
SIZE
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
APPLE COMPUTER INC.
D
SCALE
TABLE_BOMGROUP_ITEM
DRAWING NUMBER
REV.
C
051-6929
23
115
SHT
OF
NONE
NET_TYPE
PHYSICAL
I2S0_DTI
I2S
I2S
I2S0_DTO
I2S
I2S
I2S0_MCLK
I2S
I2S
I2S0_BITCLK
I2S
I2S
I2S0_SYNC
I2S
I2S
I2S1_DTI
I2S
I2S
I2S1_DTO
I2S
I2S
I2S1_MCLK
I2S
I2S
I2S1_BITCLK
I2S
I2S
I2S1_SYNC
I2S
I2S
I2_XTAL
XTAL
XTAL
(I2_XTAL)
XTAL
XTAL
(I2_XTAL)
XTAL
XTAL
DIFFERENTIAL_PAIR
I2S0_DEV_TO_SB_DTI
I2S0_MCLK_R
I2S0_BITCLK_R
I2S0_SYNC_R
7 22 74
6 22
6 22
6 22
6 22
I2S1_DEV_TO_SB_DTI
I2S1_MCLK_R
I2S1_BITCLK_R
I2S1_SYNC_R
22 30
6 22
6 22
6 22
6 22
30 25 22
I2_CLK18M_XOUT_R
I2_CLK18M_XOUT
I2_CLK18M_XIN
22
25 22
22
44 43
22
74 7
74 7
Page Notes
Audio Mute Sequencing
59 11
Prevents mute glitch from reaching audio circuit

- =PP3V3_PWRON_I2_GPIO
- =PP3V3_I2_PCISLOTEGPIOS (PWRON or PCI)
Should be same as =PP3V3_PCI if slot E
is used, or else =PP3V3_PWRON_I2_GPIO.
59 11
22 10
25 22
R2470
R2471
100K
5%
1/16W
MF-LF
2 402

(NONE)
74 7
10K
25 22
5%
1/16W
MF-LF
2 402
25 22
AUDIO_LO_MUTE_L
- I2_REV1_NOT
Use for I2 revisions > 1.0
7 74
74 7
74 7
Q2470
74 7
2N7002DW-X-F
AUDIO_LO_MUTE
5
SOT-363
22 11
22 11
22
I2_AUDIO_LO_MUTE_L
30
22
Q2470
2N7002DW-X-F
22
SOT-363
22
74 7
R24721
22
74 7
100K
MUTE_CONTROL
5%
1/16W
MF-LF
402 2
74 7
22
OMIT
U2100
Pin Direction
SPACING
Signal Direction
I2
BGA
MISCELLANEOUS
(4 OF 14)
AH1
MODEM_RING2SYS_L
PMU_INT_L
AGP_INT_L
AUDIO_LI_DET_L
AK4
AT19
AH2
J2
AR33
PCI_SLOTA_INT_L
PCI_SLOTD_INT_L
I2_EXT_08
PMU_SB_NMI_L
MMM_FFIRQ_L
MMM_SIRQ_L
I2_EXT_13
I2_EXT_14
AUDIO_LO_DET_L
AUDIO_GPIO_11
AN33
AG4
AK1
AG1
AG3
AG2
AF1
AE4
H1
G4
AK2
AUDIO_CODEC_RESET_L
=SPI_I2_REQ
I2_GPIO_EXT_02
MODEM_RESET_L
FW_POWERDOWN
I2_AUDIO_LO_MUTE_L
I2_AUDIO_SPKR_MUTE_L
AUDIO_I2S_DTIB_SEL
I2_GPIO_11
AUDIO_EXT_MCLK_SEL
AJ1
AH4
AH3
M1
G3
G1
AG8
G2
AG7
AG6
Address
MPIC Int
Int PU?
Alt Func
EXT_00
EXT_01
EXT_02
EXT_03
EXT_04
EXT_05
EXT_06
EXT_07
EXT_08
EXT_09
EXT_10
EXT_11
EXT_12
EXT_13
EXT_14
EXT_15
EXT_16
0x0_0058
0x0_0059
0x0_005A
0x0_005B
0x0_005C
0x0_005D
0x0_005E
0x0_005F
0x0_0060
0x0_0061
0x0_0062
0x0_0063
0x0_0064
0x0_0065
0x0_0066
0x0_0067
0x0_0068
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
(0x2E)
(0x2F)
(0x30)
(0x31)
(0x32)
(0x33)
(0x34)
(0x35)
(0x36)
(0x37)
(0x38)
(0x39)
(0x3A)
(0x3B)
(0x3C)
(0x3D)
(0x3F)
Yes
Yes
No
No
No
No
No
No
Yes
Yes
No
Yes
Yes
No
No
No
Yes
PCI_REQ_2_L (When PCI1_Slot2En = 10)
GPIO_EXT_00_H
GPIO_EXT_01_H
GPIO_EXT_02_H (Int PU)
GPIO_EXT_03_H (Int PU)
GPIO_04_H
GPIO_05_H
GPIO_06_H
GPIO_09_H
GPIO_11_H (Int PU)
GPIO_12_H (Int PU - rev 1)
GPIO_15_H
GPIO_16_H - See Ethernet Sym
GPIO_00
GPIO_01
GPIO_02
GPIO_03
GPIO_04
GPIO_05
GPIO_06
GPIO_09
GPIO_11
GPIO_12
GPIO_15
GPIO_16
0x0_006A
0x0_006B
0x0_006C
0x0_006D
0x0_006E
0x0_006F
0x0_0070
0x0_0073
0x0_0075
0x0_0076
0x0_0079
0x0_007A
14 (0x0E)
15 (0x0F)
16 (0x10)
17 (0x11)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
No
No
Yes
Yes
No
No
No
No
Yes
Yes
No
No
Alternate GPIO Functions
GPIO Pull-ups / Pull-downs
22 11
22 11
=PP3V3_I2_PCISLOTEGPIOS
1
Internal pull-up to 3.3V PWRON
10K Pull-up to 3.3V on I2 AGP page.
Pull-up/down to be provided by audio page.
10K Pull-up to Enet OVdd on I2 Enet page.
10K Pull-up to 3.3V on I2 PCI page.
10K Pull-up to 3.3V on I2 PCI page.
10K
EXT_08
10K
R2461
5%
1/16W
MF-LF
402
10K
MODEM_RING2SYS_L 22
PMU_INT_L
22 25
25 30
I2S1_DEV_TO_SB_DTI
30 22
EXT_13
24 7
10K
PMU_SB_NMI_L
AG5
SCCA_RXD
VIA_PMU_TO_SB
VIA_ACK_L
VIA_CLK
25
MMM_FFIRQ_L
25
I2_TST_TEI
I2_TST_PLLEN
=SPI_I2_MOSI
=JTAG_I2_TDI
=JTAG_I2_TMS
=JTAG_I2_TCK
=JTAG_I2_TRST_L
=SPI_I2_CLK
R2463
10K
MMM_SIRQ_L
22 25
11 22
R2400 1
10K
5%
1/16W
MF-LF
402
11 22
R2401
10K
5%
1/16W
MF-LF
402
9
9
=SPI_I2_REQ
11 22
R2451
10K
22 10
6 22
G6
FW_POWERDOWN
Pull-up/down to be provided by
22
AL6
I2_CLK18M_XOUT
10K
5%
1/16W
MF-LF
2 402
6 22
6 22
5%
1/16W
MF-LF
2 402
6 22
AE5
AUDIO_SPKR_MUTE_L
7 74
SCCA_TXD_L
SCC_TXDB_L
AL2
SCC_RTSB_L
AL4
VIA_SB_TO_PMU
VIA_REQ_L
SCC_TXDA_L
7 24
AL5
AN6
AN2
AN3
AP1
2N7002DW-X-F
SOT-363
25
Q2480
2N7002DW-X-F
TST_TEI_H
TST_PLLEN_H
JTG_TDI_H
JTG_TMS_H
JTG_TCK_H
JTG_TRSTN_L
Q2480
AUDIO_SPKR_MUTE
25
22
JTG_TDO_H
AN4
=SPI_I2_MISO
=JTAG_I2_TDO
I2_AUDIO_SPKR_MUTE_L 2
SOT-363
S
1
R24821
100K
MUTE_CONTROL
5%
1/16W
MF-LF
402 2
22
POWER MGMT/CLOCK
AH5
PWR_SPDREQ_L
AC12
REF_CLK_OUT
REF_CLK_IN
AH7
AH6
REF_PURESET_L
PWR_STPXTL_L
PWR_STPCPU_L
PWR_PCI_PME_L
PWR_INTRWD_H
AK7
AL7
SYS_PME_L
Q2481
D
25 62
2N7002DW-X-F
62 25 22
SYS_WATCHDOG
25
NB_SUSPENDACK_L
25
SYS_WARM_RESET_L
AC13
PWR_SPDACK_L
PWR_PENDINT_H
AK5
AK6
SOT-363
TP_I2_PENDINT
10M
I2 Miscellaneous
5%
1/16W
MF-LF
402
SYNC_MASTER=N/A
SYNC_DATE=N/A
CRITICAL
Y2410

18.432M
2
8X4.5MM-SM1
C2411
R2464
1
audio page. (*) - See above

audio page.
design.
R2481
100K
6 22
SCC_TRXCB_H
NB_SUSPENDREQ_L
audio page.
audio page.
audio page.
R2480
I2S1_MCLK_R
I2S1_BITCLK_R
I2S1_SYNC_R
0
5%
1/16W
MF-LF
402 2
22
AL1
SCC_GPIOB_L
25
R2411 1
5%
1/16W
SM-LF
GPIO_05
GPIO_06
GPIO_09
GPIO_11
GPIO_12
GPIO_15
GPIO_16
AM1
SCC_RXDB_H
11
10K
4
6 22
R2410
(*) - Rev 1.0: Missing internal pull-up to 3.3V PWRON

I2_GPIO_EXT_02 11 22
5%
1/16W
MF-LF
402
RP2450
GPIO_04
Prevents mute glitch from reaching audio circuit
6 22
NO STUFF
GPIO_EXT_02
GPIO_EXT_03
AL3
AK3
Put crystal circuit close to I2

22 I2_CLK18M_XOUT_R
22 I2_CLK18M_XIN
NO STUFF
10K
8
SCC_RXDA_H
SYS_WARM_RESET_L
=I2_STOPXTAL_L
=I2_STOPCPU_L
11
RP2450
5%
1/16W
SM-LF
Audio Mute Sequencing

6 22
TEST/JTAG
62 25 22
MOD_BITCLK_B_H
MOD_SYNC_B_H
J7
(Slave)
G5
J6
I2S0_MCLK_R
I2S0_BITCLK_R
I2S0_SYNC_R
D2
MOD_CLKOUT_B_H
(Slave)
F2
(Master)
MOD_DTO_B_H
=I2C_I2_SB_SCL
=I2C_I2_SB_SDA
22 25

Pull-up/down to be provided by audio page. (*) - See above
GPIO_EXT_01
F1
=I2C_I2_NB_SCL
=I2C_I2_NB_SDA
SCCB/VIA
22 25
5%
1/16W
SM-LF
EXT_15
EXT_16
GPIO_EXT_00
SCCA
5% (*) - Rev 1.0: Missing internal pull-up to 3.3V PWRON

1/16W
MF-LF
402
(I2_EXT_14)
PCI_SLOTE_REQ_L
10K
3
EXT_14
5%
1/16W
MF-LF
402
R2452
10K
SPIREQ
(When SPISReqEn = 1)
PCI_GNT_2_L (When PCI1_Slot2En = 10)
R2462
5%
1/16W
MF-LF
402
5%
1/16W
SM-LF
RP2450
F3
MOD_DTI_B_H
10K
(I2_EXT_13)
PCI_SLOTE_GNT_L
J5
R2490 1
11 22
10K
AUD_BITCLK_A_H
J3
(Master)
AUD_SYNC_A_H
RP2450
AUD_DTO_A_H
AUD_CLKOUT_A_H
C1
I2S 1
5%
1/16W
MF-LF
402

AUD_DTI_A_H
25
EXT_09
EXT_10
EXT_11
EXT_12
E1
5%
1/16W
MF-LF
402
(*) - Rev 1.0: Internal pull-up to 3.3V PWRON
5%
1/16W
MF-LF
402
I2S0_DEV_TO_SB_DTI
74 22 7
22 10
(I2_EXT_08)
PCI_SLOTE_INT_L
IIC_CLK_2_H
IIC_D_2_H
F4
I2S 0
NO STUFF
I2_REV1_NOT
R2455
J1
NO STUFF
R2460
EXT_00
EXT_01
EXT_02
EXT_03
EXT_04
EXT_05
EXT_06
EXT_07
IIC_CLK_0_H
IIC_D_0_H
PCI_SLOTE_INT_L
PCI_SLOTE_GNT_L
PCI_SLOTE_REQ_L
10 22
10
PCI_GNT_2_L (When PCI1_Slot2En = 11)

PCI_REQ_2_L (When PCI1_Slot2En = 11)
I2C
Use MAKE_BASE to force net name

22 11
Pin
EXT_00_H (Int PU)

EXT_01_H (Int PU)
EXT_02_H
EXT_03_H
EXT_04_H
EXT_05_H - See Ethernet Sym
EXT_06_H
EXT_07_H
EXT_08_H (Int PU - rev 1)
EXT_09_H (Int PU)
EXT_10_H
EXT_11_H (Int PU)
EXT_12_H (Int PU)
EXT_13_H
EXT_14_H
EXT_15_H
EXT_16_H (Int PU - rev 1)
GPIO INTERFACE
10K
22pF
I2_GPIO_11
22
5%
1/16W
MF-LF
402
50V
CERM
402
22pF
5%
C2410
5%
SIZE
50V
CERM
402
APPLE COMPUTER INC.
D
SCALE
Crystal load capacitance is 16pF
DRAWING NUMBER
REV.
C
051-6929
24
115
SHT
OF
NONE
8
I72
I73
I74
I75
I76
PCI_ZDBOUT0
PCI_ZDBOUT1
PCI_ZDBOUT2
PCI_ZDBOUT3
7
NET_TYPE
SPACING PHYSICAL
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
DIFFERENTIAL_PAIR
=PCI_CLK33M_ZDB_IN
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
11 23
11 23
11 23
11 23
11 23
Page Notes
D

- =PP3V3_PWRON_I2_GPIO
- =PP3V3_I2_PCISLOTEGPIOS (PWRON or PCI)
Should be same as =PP3V3_PCI if slot E
is used, or else =PP3V3_PWRON_I2_GPIO.
(NONE)
- I2_REV1_NOT
Use for I2 revisions > 1.0
C
10
=PP3V3_PCI_ZDB
C2500
0.1uF
CRITICAL
23 11
6
VDD
CDCVF2505
1 CLKIN 1Y0
1Y1
U2500
1Y2
SOIC
1Y3
CLKOUT
GND
4
=PCI_CLK33M_ZDB_IN
20%
10V
CERM 2
402
3
2
5
7
8
C2501
1uF
10%
2 6.3V
CERM
402
PCI_CLK_DELAY_ADJ
11 23
11 23
11 23
11 23
NO STUFF
C2502
0.001uF
20%
50V
CERM 2
402
PCI Clock Buffer
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
25
115
SHT
OF
NONE
PMU RESET CIRCUIT

25 24 10
=PP3V3_ALL_PMU
R2680
100K
5%
1/16W
MF-LF
2 402
DP2680
BAS16TW-X-F
12
PMU_RESET_L
SOT-363
6
1
SYS_AC_DET_L
DP2680
Q2680
BAS16TW-X-F
2N7002DW-X-F
SOT-363
SOT-363
25 12
SYS_BATT0_DET_L
SERIAL DEBUG INTERFACE
24 25
PMU_CUSTOMER_RESET
DEVELOPMENT
CRITICAL
J2690
Q2680
2N7002DW-X-F
57 36 30 25 24
SYS_POWER_BUTTON_L
QT500166-L020
M-ST-SM
(WAS COMM_GPIO_L)
SOT-363
22 7
NC
SCCA_RXD
(WAS COMM_TRXC)
25 24
NC
PMU_RESET_L
(WAS PMU_BOOT_CE)
10
=PP3V3_ALL_DEBUG
25
25
NC
PMU_BOOT_SCLK
PMU_BOOT_CNVSS
SCCA_TXD_L
COMM_RTS_L
10
11
12
13
14
15
16
7 22
NO_TEST=TRUE
COMM_DTR_L
NO_TEST=TRUE
PMU_BOOT_TXD 25
DEVELOPMENT
PMU_BOOT_RXD 25
1
PMU_BOOT_BUSY 25
10K
PMU_BOOT_RP_L 25
5%
R2695
1/16W
MF-LF
402 2
DEVELOPMENT
1
R2696
10K
5%
1/16W
MF-LF
2 402
SLEEP LED
DEBUGGING AIDS
PLACE ON TOP SIDE NEAR FRONT EDGE OF BOARD
10
OMIT
=PP5V_PWRON_SLEEPLED
R2692
R26011
R26001
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
2.2K
100
SLEEP_LED_L
SLEEP_LED_I
R2602
4.7K
R2690
1
2N3906
SOT23-LF
1
OMIT
470K 2
5%
1/10W
MF-LF
603
PMU_RESET_L
24 25
PLACE "PMU RESET" IN SILK NEAR RESISTOR
R2691
470K 2
1
5%
1/16W
MF-LF
402
=SLEEP_LED_IOUT
Q2601
SYS_POWER_BUTTON_L 24 25 30 36 57
PLACE "POWER BTN" IN SILK NEAR RESISTOR
OMIT
Q2600
SLEEP_LED_SW_L
470K 2
5%
1/10W
MF-LF
603
5%
1/10W
MF-LF
603
11
SYS_RESET_BUTTON_L 25 36
PLACE "SYS RESET" IN SILK NEAR RESISTOR
2N7002
25
SYS_LED
SOT23-LF
S
2
CHARGE LED
25 24 10
=PP3V3_ALL_PMU
R2610
470K
5%
1/16W
MF-LF
2 402
25
SYS_ONEWIRE
SYS_CHARGE_LED_L
7 74
LEDs/Reset/Debug
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
26
115
SHT
OF
NONE
NET_TYPE
SPACING
PMU_CLK10M_XTAL
PMU_CLK32K_XTAL
PHYSICAL
XTAL
DIFFERENTIAL_PAIR
PMU_CLK10M_XIN
PMU_CLK10M_XOUT
PMU_CLK10M_XOUT_R
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
PMU_CLK32K_XIN
PMU_CLK32K_XOUT
PMU_CLK32K_XOUT_R
25
25
25
25
25
Power Management Unit
25
Page Notes
25 24 10

- =PP3V3_ALL_PMU
- =PP3V3_PWRON_PMU
- =PPVREF_PMU (PMU AVCC or 2.5V reference)
C2702
11
11
11
11
11
25
25
25 22
22
11
11
36 25 24
57 36 30 25 24
30
30 22
PMU Pull-ups / pull-downs

8
8
10 24 25
8
R2760
PMU_POWER_UP_L
9
25 26
9
5%
1/16W
MF-LF
402
R2761
10K
1
SYS_POWER_BUTTON_L
25 11
25 11
25 11
10
25 11
R2765
2
10K
22
SYS_PME_L
22 25 62
25 24 10
11
=PP3V3_ALL_PMU
26 25
5%
1/16W
MF-LF
402
R2766
100K
1
25
SYS_RESET_BUTTON_L
24 25 36
3
5%
1/16W
MF-LF
402
10K
5%
1/16W
MF-LF
402
R2768
10K
1
VIA_REQ_L
SOT23
7 11 25 30
22 25
C2710
R2770
5%
1/16W
MF-LF
402
SYS_COLD_RESET_L
100K
2
100K
PCI_RESET_L
2
5%
1/16W
MF-LF
402
2
5%
1/16W
MF-LF
402
R2774
100K
1
25
NB_SUSPENDREQ_L
NB_SUSPENDACK_L
PMU_CPU_CLK_EN
PMU_SYS_CLK_EN
SYS_RESET_BUTTON_L
SYS_POWER_BUTTON_L
SYS_LID_OPEN
MODEM_RING2SYS_L
59
=I2C_PMU_SMB_SDA
=I2C_PMU_SMB_SCL
=I2C_PMU_SDA
=I2C_PMU_SCL
=JTAG_BBANGER_TRST_L
=JTAG_BBANGER_TMS
=JTAG_BBANGER_TDI
=JTAG_BBANGER_TCK
51
TP_PMU_P3_0
TP_PMU_P3_1
TP_PMU_P3_2
TP_PMU_P3_3
SYS_WATCHDOG
PMU_CPU_HRESET_L
PMU_POWER_UP_L
SYS_SLEEP
39
66
65
64
63
62
61
60
58
57
56
55
54
53
52
50
49
48
47
46
45
44
SYS_SLEEP
RTS0*/
CTS0*
QFP-80
AN00
OMIT
AN01
CLK0
AN02
RxD0
AN03
TxD0
AN04
RTS1*/BUSY
AN05
CLK1
AN06
RxD1
AN07
TxD1
P1[0]
P1[1]
P1[2]
P1[3]
P1[4]
P1[5]
P1[6]
P1[7]
AN20
SDA/TxD2/
TA0out
AN21
SCL/RxD2/TA0in
AN22
CLK2/TA1out
P2[0]
P2[1]
P2[2]
P2[3]
P2[4]
P2[5]
P2[6]
P2[7]
ICOC0/SDAmm
TA4out
ICOC1/SCLmm
TA4in
ICOC2
INT0*
ICOC3
INT1*
ICOC4
INT2*
38
P3[0]
P3[1]
P3[2]
P3[3]
P3[4]
P3[5]
P3[6]
P3[7]
CLK3
TB0in
Sin3
TB1in
37
36
Sout3
TB2in
35
34
33
32
AN23
TA1in
TA2out
INT3*/ADtrig
TA2in
INT4*
TA3out
INT5*
TA3in
ICOC5
RP/NMI*
ICOC6
CE*/Xcout
ICOC7
Xcin
PMU_BOOT_CNVSS
PMU_RESET_L
PMU_CLK10M_XOUT_R
PMU_CLK10M_XIN
CLK4/AN25
Sout4/AN26
Sin4//AN27
P7[0]
P7[1] 26
P7[2] 25
P7[3] 24
P7[4] 23
P7[5] 22
P7[6] 21
P7[7] 20
GOV_RESET_L
PCI_RESET_L
SYS_WARM_RESET_L
SYS_COLD_RESET_L
PMU_BOOT_BUSY
PMU_BOOT_SCLK
PMU_BOOT_RXD
PMU_BOOT_TXD
PMU_BOOT_RP_L
TP_PMU_P7_0
TP_PMU_P7_1
TP_PMU_P7_2
SYS_ACIN
TP_PMU_P7_4
TP_PMU_P7_5
SYS_KBDLED
SYS_OVERTEMP_L
P8[0] 19
P8[1] 18
P8[2] 17
P8[3] 16
P8[4] 15
P8[5] 14
P8[6] 8
P8[7] 7
SYS_LED
PMU_BATT0_CHARGE
SYS_BATT0_DET_L
SYS_PME_L
SYS_AC_DET
SYS_ONEWIRE
PMU_CLK32K_XOUT_R
PMU_CLK32K_XIN
P6[0] 43
P6[1] 42
P6[2] 41
P6[3] 40
P6[4] 31
P6[5] 30
P6[6] 29
P6[7] 28
27
25
25
11
11 25
22 25 62
25
24
24
24
24
24
25
25
25
12 13 18
11 25
11 25
28
7 11 25 30
24
13
12 24
22 25 62
12
24
6
9
10
12
R2715 1
PCNVSS
RESET*
XOUT
XIN
VREF
AN3
KI0*/AN4
KI1*/AN5
KI2*/AN6
KI3*/AN7
NO STUFF
22
R2750
22 25
22
10M
22
5%
1/16W
MF-LF
402
22
22
R2751
0
CRITICAL
OMIT
22
TP_PMU_AN_P10_0
TP_PMU_AN_P10_1
TP_PMU_AN_P10_2
TP_PMU_AN_P10_3
TP_PMU_AN_P10_4
TP_PMU_AN_P10_5
TP_PMU_AN_P10_6
TP_PMU_AN_P10_7
P10[0] 76
P10[1] 74
P10[2] 73
P10[3] 72
P10[4] 71
P10[5] 70
P10[6] 69
P10[7] 68
5%
1/16W
MF-LF
402 2
Y2750
1
25
25
5%
1/16W
MF-LF
2 402
SM1
PMU_CLK32K_XOUT
25
25
25
25
11 25
2
11 25
C2750
12pF
5%
50V
CERM
402
5%
50V
CERM
402
C2751
12pF
25
QTY
DESCRIPTION
CRITICAL
BOM OPTION
CRITICAL
TABLE_5_ITEM
XTAL,32.768KHZ,4.1X1.5X0.9MM,SMD
Y2750
SM
1
C2740
18pF
18pF
5%
50V
CERM
402
5%
50V
CERM
402
TABLE_5_HEAD
PART#
197S0163
XW2700
Y2740
GND_PMU_AVSS
8X4.5MM-SM1
1
5%
1/16W
MF-LF
402
10.0000M
1
PMU_CLK10M_XOUT
C2741
1uF
10%
6.3V
CERM
402
R2730
4.7K
C2720
CRITICAL
2
11 25
AVSS
75
11
1
4.7K
5%
1/16W
MF-LF
402
22 25 62
25
VIA_ACK_L
VIA_REQ_L
PMU_INT_L
PMU_SB_NMI_L
VIA_CLK
VIA_PMU_TO_SB
VIA_SB_TO_PMU
P9[0] 5
P9[1] 4
P9[2] 3
P9[3] 2
P9[5] 1
P9[6] 80
P9[7] 79
Spares (Analog capable)
VSS
10M
22 25
AN24
AN1
R2740
1
25
NB_SUSPENDREQ_L
P0[0]
P0[1]
P0[2]
P0[3]
P0[4]
P0[5]
P0[6]
P0[7]
NO STUFF
25
R2773
100K
78
AVCC
AN2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R2772
25 28 29 31
32.768K
24
R2741
SYS_WARM_RESET_L
10%
6.3V
CERM
402
U2700
67
77
R2771
1
10%
6.3V
CERM-X5R
402
M30280F8-LF
TP_PMU_AN_P0_0
TP_PMU_AN_P0_1
TP_PMU_AN_P0_2
TP_PMU_AN_P0_3
TP_PMU_AN_P0_4
TP_PMU_AN_P0_5
TP_PMU_AN_P0_6
TP_PMU_AN_P0_7
0.22uF
100K
C2705
1uF
=PPVREF_PMU
25
5%
1/16W
MF-LF
402
AN0
10
24
R2710
5%
1/16W
MF-LF
2 402
MMBD914XXG
SYS_OVERTEMP_L
20%
10V
CERM
402
150K
D2710
R2767
1
0.1uF
24 25 30 36 57
5%
1/16W
MF-LF
402
=PP3V3_PWRON_PMU
C2700
20%
10V
CERM
402
Spares (Analog capable)
NOTE: All analog inputs to PMU should have

a 100pF capacitor to the PMU AVSS
signal (GND_PMU_AVSS). None of
those capacitors are provided on
this page.
0.1uF
VCC
NOTE: TP_PMU_Px_x signals are generalpurpose spares. Some pins are

reserved for alternate functions.
TP_PMU_AN_Px_x signals are generalpurpose spares that can also be used
as analog inputs.
10K
C2701
20%
6.3V
X5R
603
10
VOLTAGE=3.3V
13
11
10UF
PP3V3_ALL_PMU_AVCC
5%
1/16W
MF-LF
402
GND_PMU_AVSS

(NONE)
=PP3V3_ALL_PMU
4.7

- =I2C_PMU_SCL
- =I2C_PMU_SDA
- =I2C_PMU_SMB_SCL
- =I2C_PMU_SMB_SDA
- =JTAG_BBANGER_TCK
- =JTAG_BBANGER_TDI
- =JTAG_BBANGER_TMS
- =JTAG_BBANGER_TRST_L
NOTE: Boot-banger pins can be aliased to
TP_ or NC_ if not implemented.
R2705
=PP3V3_ALL_PMU
25 28 29 31
VOLTAGE=0V
Keep crystal subcircuit close to PMU.
Y2740s load capacitance is 12pF
5%
1/16W
MF-LF
402
Power Management Unit (PMU05)
SYNC_MASTER=N/A
Additional PMU05 "Modules"

MMM
25
25
25
25
25
25
25
TP_PMU_AN_P10_0
TP_PMU_AN_P10_1
TP_PMU_AN_P10_2
TP_PMU_P7_0
TP_PMU_P7_1
TP_PMU_AN_P0_7
TP_PMU_AN_P0_6
ALS
MMM_X_AXIS
MMM_Y_AXIS
MMM_Z_AXIS
MMM_FFIRQ_L
MMM_SIRQ_L
MMM_ACC_SELFTEST
MMM_ACC_PWRDOWN
29
25
29
25
29
25
TP_PMU_AN_P10_3
TP_PMU_AN_P10_4
TP_PMU_P7_2
SPI Dual Battery Charger

ALS_0_OUT
ALS_1_OUT
ALS_GAIN_BOOST
7 31
25 11
28
25 11
7 28 31
25 11
22
CPU T-Diodes
22
25 11
25 11
29
25 11
29
25 11
TP_PMU_AN_P10_5
TP_PMU_AN_P10_6
CPU0_TEMP
CPU1_TEMP
25 11
TP_PMU_P3_0
TP_PMU_P3_1
TP_PMU_P3_2
TP_PMU_P3_3
TP_PMU_P7_4
TP_PMU_P7_5
SYNC_DATE=N/A

Battery Current Mon
SPI_PMU_CHGR_CLK
SPI_CHGR_TO_PMU_MISO
SPI_PMU_TO_CHGR_MOSI
SPI_PMU_CHGR_CS
PMU_BATT1_DET_L
PMU_BATT1_CHARGE
25
TP_PMU_AN_P10_7
BATT_ISNS

12

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
27
115
SHT
OF
NONE
7
25
SYS_POWER_UP_L
R2901
100K
5V3V3PWRON_EN_L
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
11
R2902
1
=5V3V3PWRON_EN_L
5%
1/16W
MF-LF
2 402
15
10
5%
1/16W
MF-LF
402 1
Q2900
SOT-363
R2929
5%
1/16W
MF-LF
402 2
2N7002DW-X-F
5%
1/16W
MF-LF
402
SOT-363
100K 2
100K 2
3V3RUN_EN_L
15
26 10
11
26 10
2V5RUN_EN_L
2V5PWRON_EN_L
MAKE_BASE=TRUE
=2V5PWRON_EN_L
17
5VTPAD_EN_L
MAKE_BASE=TRUE
=5VPWRONTPAD_EN_L
15
TPAD_SEQ_PMU
R29481
TPAD_SEQ_PMU
1
5%
1/16W
MF-LF
402 2
17
5%
1/16W
MF-LF
402
=PP5V_RUN_PWRSEQ
16
=PP3V3_PWRON_PWRSEQ
100K
5%
1/16W
MF-LF
402
R2922
R2930
0
15
=1V8_1V5PWRON_EN_L
R2943
SOT-363
1V8_1V5PWRON_EN_L
MAKE_BASE=TRUE
TPAD_SEQ_HW
2N7002DW-X-F
5VRUNHD_EN_L
5%
1/16W
MF-LF
402
Q2900
D
5
5%
1/16W
MF-LF
402
ACTIVE-LOW, OUTPUT, PUSH-PULL

SYS_PWRSEQ_3_L
15
5%
1/16W
MF-LF
402
R2921
Q2910
5VRUN_EN_L
18
R2912
SYS_PWRSEQ_1_L
100K 2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
R2920
SYS_PWRSEQ_2_L
R2910
=FWPWR_PWRON
R2911
100K
FWPWR_PWRON
MAKE_BASE=TRUE
100K
ACTIVE-HIGH, OUTPUT, PUSH-PULL

SYS_PWRSEQ_2
5%
1/16W
MF-LF
402
2N7002DW-X-F
=PP5V_PWRON_PWRSEQ
100K
11
6
D
R2903
SYS_POWERUP
ACTIVE-HIGH, OUTPUT, PUSH-PULL

SYS_PWRSEQ_1
R29132
=PP3V3_ALL_PWRSEQ
26 10
5%
1/16W
MF-LF
402
R2900
ACTIVE-LOW, OUTPUT, OPEN-COLLECTOR

PMU_POWER_UP_L
100K pull-up to 3.3V_ALL on pg 13
11
SYS_PWRSEQ_TPAD_L
Q2948
2N7002
SOT23-LF
2 S
R29351
100K
5%
1/16W
MF-LF
402 2
R2936
SYS_PWRSEQ_3_LS5
1V5RUN_EN
16
5%
1/16W
MF-LF
402
Q2910
100K 2
D
2
2N7002DW-X-F
POWER-UP
SLEEP
WAKE
SHUT-DOWN
SOT-363
2N7002DW-X-F
SOT-363
1 S
4
26 10
=PP3V3_PWRON_PWRSEQ
NO STUFF
R2940
R2941
100K
11
Q2941
ACTIVE-HIGH, OUTPUT/INPUT, OPEN-COLLECTOR

SYS_PWRSEQ_4
5%
1/16W
MF-LF
2 402
VCORE_CPU0_SHDN_L
5%
1/16W
MF-LF
402
1V8RUN_EN_L 16
6
NO STUFF
2N7002DW-X-F
10
=PP3V3_RUN_PWRSEQ
20
=5V3VPWRON_PGOOD
=1V8_1V5PWRON_PGOOD
=2V5PWRON_PGOOD
=I2VCORE_PGOOD
11
ACTIVE-HIGH, OUTPUT/INPUT, OPEN-COLLECTOR

SYS_PWRSEQ_5
15
16
17
Q2940
R29491
5%
1/16W
MF-LF
402 2
36
PWRON_REGS_PGOOD
MAKE_BASE=TRUE
26 10
SOT-363
S
1
=PP3V3_ALL_PWRSEQ
R2958
10K
5%
1/16W
MF-LF
2 402
Q2941
2N7002DW-X-F
SOT-363
4 S
GPUVCORE_SHDN_L
45
CPU_AVDD_EN
37
R2951
1
5%
1/16W
MF-LF
402
36
11
=VCORE_PGOOD
TP_VCORE_PGOOD
MAKE_BASE=TRUE
ACTIVE-LOW, OUTPUT, PUSH-PULL

SYS_PWRSEQ_6_L
26 10
=PP5V_RUN_PWRSEQ
1
R2965
100K
5%
1/16W
MF-LF
2 402
NO STUFF
R2969
45
=GPUVCORE_PGOOD
GPUVCORE_PGOOD
MAKE_BASE=TRUE
R2966
5%
1/16W
MF-LF
402
Q2940
SOT-363
100K 2
R2967
D
2N7002DW-X-F
SYS_PWRSEQ_6_LS5
MAKE_BASE=TRUE
GPUVDD15_EN
46
GPUPVDD_EN
51
5%
1/16W
MF-LF
402
Power Sequencing
SYNC_MASTER=N/A
5%
1/16W
MF-LF
402
SYNC_DATE=N/A
4
11
XW2970
SM
ANALOG INPUT, SENSE > 1.7V

SYS_PWRSEQ_FINAL
PP1V8_GPU_PVDD
51
SIZE
Used to see if last rail is up
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
29
115
SHT
OF
NONE
8
I528
I529
I530
I531
I532
I533
I534
I535
I536
I537
I539
I538
7
NET_TYPE
SPACING PHYSICAL
DIFFERENTIAL_PAIR
THERM
THERM
THERM
THERM
THERM1_M
THERM1_M
THERM1_M_P
THERM1_M_N
THERM
THERM
THERM
THERM
THERM2_M
THERM2_M
THERM2_M_P
THERM2_M_N
THERM
THERM
THERM
THERM
THERM1_A
THERM1_A
THERM1_A_P
THERM1_A_N
THERM
THERM
THERM
THERM
THERM2_A
THERM2_A
THERM2_A_P
THERM2_A_N
THERM
THERM
THERM
THERM
THERM_D1
THERM_D1
THERM_D1_P
27
THERM_D1_N
27
THERM
THERM
THERM
THERM
THERM_D2
THERM_D2
THERM_D2_P
THERM_D2_N
27
27
27
27
27
27
27
27
FAN CONTROLLER
27
27
R3000
10
=PP3V3_ADT7467
10
5%
1/16W
MF-LF
402
PP3V3_ADT7467
VOLTAGE=3.3V
MIN_LINE_WiDTH=0.25 mm
mm
10
C3001MIN_NECK_WIDTH=0.25
C3000
1uF
10K
20%
10V
CERM
402
5%
1/16W
MF-LF
2 402
R30021
10
2N3904LF
27
SOT23
THERM1_M_P
THERM1_M_N
27
THERM1_M_N
27
27
THERM2_M_N
27
THERM_D1_N
27
THERM_D2_P
R3012
1
1000pF
10%
25V
X7R
402
THERM_D2_P 27
27
THERM_D2_N
=PPVCORE_CPU_ADT7467 14
=I2C_ADT7467_SDA
16
=I2C_ADT7467_SCL
1
13
12
11
10
1000pF
R30041
R3003
10K
R3005
10K
5%
1/16W
MF-LF
2 402
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
10%
25V
X7R
402
PWM1/15
XTO
6
TACH1
ADT7467
PWM2/ 5
SMBALERT#
TACH2 7
QSOP-LF
VCCP
SDA
SCL
D1+
D1D2+
D2-
CRITICAL
PWM3
TACH3 4
TACH4/ 9
THERM#/
SMBALERT#/GPIO
GND
ADT7467_ADR_ENABLE_L
7 31
FAN1_TACH
7 31
FAN2_PWM
7 31
FAN2_TACH
7 31
I2C READ ADDR = 0x5C, WRITE ADDR = 0x5D

(Device is connected so as to be backward
compatible with the ADT7460.)
NC
=ADT7467_THERM_L
FAN1_PWM
11
5%
1/16W
MF-LF
402
R3013
Q3002
C3002
C3003
THERM2_M_P
THERM_D1_P
THERM_D1_P 27
THERM_D1_N 27
THERM2_M_P
5%
1/16W
MF-LF
402
PLACE IN BETWEEN 3/5/1.5/2.5V PWR SUPPLY

MAIN2
THERM_D2_N 27
5%
1/16W
MF-LF
402
2N3904LF
SOT23
2
27
5%
1/16W
MF-LF
402
R3011
27
27
R3010
Q3001
2
27
5%
1/16W
MF-LF
402 2
U3000
THERM1_M_P
10K
VCC
PLACE CLOSE TO CPU

MAIN1
27
=PP3V3_RUN_FANTACH
10
R3001
0.1uF
10%
6.3V
CERM
603
=PP5V_RUN_FANPWM
THERM2_M_N
KEEP STUFFING RESISTORS CLOSE TO ADT7467 CONTROLLER
PLACE UNDERNEATH UPPER RAM

ALTERNATE1
27
THERM1_A_P
NO STUFF
R3020
Q3003
27
THERM1_A_P
THERM1_A_N
27
THERM1_A_N
PLACE CLOSE TO BATTERY CHARGER/VCORE

ALTERNATE2
27
27
THERM_D1_N 27
1
NO STUFF
27
THERM_D2_P 27
5%
1/16W
MF-LF
402
THERM_D2_N 27
5%
1/16W
MF-LF
402
Q3004
THERM2_A_N
R3022
R3023
3
THERM_D1_P 27
NO STUFF
THERM2_A_P
THERM2_A_P
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R3021
SOT23
2
27
1
NO STUFF
2N3904LF
2N3904LF
SOT23
2
27
THERM2_A_N
Fan Controller
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
30
115
SHT
OF
NONE
10
=PP3V3_PWRON_RT_ALS
RT ALS SENSOR
C3100
0.1UF
20%
10V
2 CERM
402
CRITICAL
V+
R3101
1
RT_ALS_PHOTODIODE
1K
6 MAX4236EUTT
SOT23-6-LF
1
RT_ALS_OUT_FB
U3100
V2
1%
1/16W
MF-LF
402
SHDN_L
R3100
5.1M
ALS_1_OUT
MAKE_BASE=TRUE
1
20%
16V
2 CERM
402
R3104
1
RT_ALS_OP_COMP
R31021
R3103
1K
1%
1/16W
MF-LF
402 2
25 29 31
5%
1/16W
MF-LF
402
15.0K
Place cap at PMU!
GND_PMU_AVSS
120K 2
25
C3105
0.001uF
C3101
0.01UF
5%
1/16W
MF-LF
2 402
TH
10%
2 50V
CERM
402
CRITICAL
PD3100
BS520EOF
1K
1%
1/16W
MF-LF
402
RT_ALS_OP_IN
D
R3105
C3104
1%
1/16W
MF-LF
2 402
0.22uF
1
GAIN_SETTING2
10%
6.3V
CERM-X5R
402
Q3103
2N7002DW-X-F
31 25 7
ALS_GAIN_BOOST
MAKE_BASE=TRUE
SOT-363
S
1
C
IS
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
353S1191
353S1186
BOM OPTION
REF DES
COMMENTS:
U3100
Primary is unity gain stable/Alt is stable at G=5
TABLE_ALT_ITEM
Keyboard LED Driver
L3130
22UH
10
=PP5V_RUN_KEYBRD_LED
MM3120_SW
3.8X3.8X1.5MM
10
=PP3V3_RUN_KEYBRD_LED
NO STUFF
R31321
1
VDD
10K
5%
1/16W
MF-LF
402 2
25
7
SW
U3130
MM3120
SYS_KBDLED
NC
R31301
LLP
3 CNTRL
VOUT 8
KBDLED_ANODE
7 30
6 NC
KBDLED_RETURN
7 30
THRML_PAD 9
C3130 1
10K
1UF
5%
1/16W
MF-LF
402 2
10%
6.3V
CERM 2
603
FB 4
NC
PGND
5
AGND
2
C3131 R3131
25.5
0.22uF
10%
50V
2 CERM
1210
1%
1/8W
MF-LF
2 805
ALS Support
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
31
115
SHT
OF
NONE
8
THERM
THERM
THERM
I57
I58
I59
7
NET_TYPE
SPACING PHYSICAL
DIFFERENTIAL_PAIR
MMM_X_AXIS
MMM_Y_AXIS
MMM_Z_AXIS
THERM
THERM
THERM
25 29
25 29
25 29
10
=PP3V3_PWRON_MMM
MMM_ACCEL_KIONIX
C3220 1
MMM_ACCEL_KIONIX
0.1uF
R32201
10K
8
VDD
5%
1/16W
MF-LF
402 2
25
25
20%
10V
CERM 2
402
U3220
KXM52
10 SELF
TEST
9 PS
MMM_ACC_SELFTEST
MAKE_BASE=TRUE
MMM_ACC_PWRDOWN
MAKE_BASE=TRUE
NC
QFN
OUTPUTX 2
5 PARITY
Package Top
MMM_X_AXIS
MAKE_BASE=TRUE
MMM_Y_AXIS
MAKE_BASE=TRUE
MMM_Z_AXIS
MAKE_BASE=TRUE
OUTPUTY 13
OUTPUTZ 14
4 RSVD
6 RSVD
OMIT
DNC 1
NC
OMIT
1
7 RSVD
11 RSVD
0.1uF
20%
2 10V
CERM
402
THRML
GND PAD
3 12 15
+Y
C3204
OMIT
1
25 29
25 29
25 29
OMIT
C3205
0.1uF
C3206
0.1uF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
GND_PMU_AVSS
+X
25 28 31
+Z (up)
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
CRITICAL
BOM OPTION
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
BOM OPTION
TABLE_5_ITEM
338S0222
IC,KIONIX,KXM52-2050,3AXIS ACCELEROMETER,SMD
U3220
CRITICAL
MMM_ACCEL_KIONIX
TABLE_5_ITEM
132S0131
CAP,CER,0.033UF,10%,16V,X5R/X7R,0402,SMD
C3204,C3205,C3206
MMM_ACCEL_KIONIX
Sudden Motion Sensor
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
32
115
SHT
OF
NONE
USB Trackpad Connector

D
D
R3352
10
=PP3V3_PWRON_DS1775
R3353
7
5%
1/16W
MF-LF
402
PP3V3_PWRON_DS1775_R
VOLTAGE=3.3V
PP3V3_ALL_HALL_EFFECT_R
VOLTAGE=3.3V
=PP5V_TPAD
2
SM-1
=PP3V3_ALL_HALL_EFFECT
10
5%
1/16W
MF-LF
402
L3350
C3353 1
400-OHM-EMI
10
22
0.001uF
CRITICAL
7
PP5V_TPAD_F
VOLTAGE=5V
25 11 7
11 7
11 7
20%
50V
CERM 2
402
J3350
QT500166-L020
SYS_OVERTEMP_L
USB_TPAD_P
USB_TPAD_N
L3354
R3355
400-OHM-EMI
M-ST-SM
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
SYS_POWER_BUTTON_L_F
=I2C_DS1775_SDA 7 8
=I2C_DS1775_SCL 7 8
SYS_POWER_BUTTON_L
100K
24 25 36 57
SM-1
C3354
KBDLED_ANODE
KBDLED_RETURN
5%
1/16W
MF-LF
2 402
0.001uF
7 28
20%
50V
CERM 2
402
7 28
L3355
400-OHM-EMI
1
SYS_LID_OPEN_F
SYS_LID_OPEN
25
SM-1
C3350
0.001uF
C3352 1
C3355
0.001uF
20%
50V
CERM 2
402
0.001uF
20%
50V
CERM 2
402
20%
50V
CERM 2
402
NO STUFF
D3354
15V
SOT23LF
2
3 NC
1
SLEEP LED CONNECTOR
SOFT MODEM CONN
11
=SLEEP_LED_CONN
1
10
=PP3V3_PWRON_MODEM
NOTE: KEEP FERRITE CLOSE TO CAP
L3300
R33211
=FTP_SLEEP_LED
R3320
10K
5%
1/16W
MF-LF
402 2
CRITICAL
10K
J3320
5%
1/16W
MF-LF
2 402
QT500166-L020
M-ST-SM
6
25 22
I2S1_MCLK
I2S1_BITCLK
SOFTMODEM_FC_RGDT
MODEM_RING2SYS_L
10
11
12
13
14
15
16
I2S1_DEV_TO_SB_DTI
MODEM_RESET_L
I2S1_SYNC
I2S1_SB_TO_DEV_DTO
J3300
SM
NO STUFF
SM-2MT-LF
MAKE_BASE=TRUE
C3300
22
470pF
3
1
SLEEP_LED_CONN
SLEEP_LED_DGND
22
CRITICAL
400-OHM-EMI
VOLTAGE=0V
10%
50V
CERM
603
R3300
0
PLACE NEAR CONNECTOR PINS
5%
1/16W
MF-LF
2 402
C3320
4.7uF
20%
6.3V
CERM
603
R3301
0
5%
1/16W
MF-LF
2 402
=GND_CHASSIS_SLEEP_LED
Q16C Internal I/O I
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
33
115
SHT
OF
NONE
ADAPTER CONNECTOR
CRITICAL
10
J3400
=PP24V_PBUSA_HOLDUP_CAPS
10
C3450
M-RT-SM-LF
=PP24V_ADAPTER_CONN
1
CRITICAL
1
C3460 1
100uF
220uF
20%
35V 2
ELEC
SM1-LF
10
C3400
=PP12V8_PBUSB_HOLDUP_CAPS
CRITICAL
87438-0443
1
2
3
4
PBUS HOLD-UP CAPS
20%
25V 2
ELEC
SM-LF
0.1uF
10%
50V
2 X7R
603-1
LEFT ALS CONNECTOR
RIGHT USB BOARD
CRITICAL
10 7
J3430
=PP5V_PWRON_RIGHT_USB
SM-2MT-LF
5
CRITICAL
J3410
QT500166-L020
10 7
M-ST-SM
MAKE_BASE=TRUE
MAKE_BASE=TRUE
28 25 7
25 7
=PP3V3_PWRON_LEFT_ALS
ALS_GAIN_BOOST
ALS_0_OUT
1
2
3
4
11 7
11 7
USB2_RIGHT_PORT_N
USB2_RIGHT_PORT_P
10
12
11
14
13
16
15
Place cap at PMU!
C3430
0.001uF
10%
50V
CERM 2
402
NC
NC
29 28 25
GND_PMU_AVSS
CPU FAN
B
10 7
27 7
BACKUP BATTERY CONNECTOR
27 7
=PP5V_FAN1_PWR
FAN1_TACH
FAN1_PWM
GPU FAN
B
CRITICAL
CRITICAL
J3450
J3460
SM04B-SSR
SM04B-SSR
M-RT-SM-LF
5
M-RT-SM-LF
5
10 7
27 7
27 7
=PP5V_FAN2_PWR
FAN2_TACH
FAN2_PWM
1
2
3
BACKUP_BATT
CRITICAL
J3420
53780-0370
M-RT-SM
4
=PPVIO_BU_BATT
1
2
3
7 10
INPUT TO AND OUTPUT

FROM BATTERY
=PPVOUT_BU_BATT
7 10
OUTPUT FROM BATTERY
Q16C Internal I/O II
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
34
115
SHT
OF
NONE
SPACING
MAXBUS_CLK_CPU0
CLOCK
NET_TYPE
OMIT
PHYSICAL
MAXBUS_CLK_CPU1
CLOCK
CLOCK
I2_MAXBUS_FBCLK
I2_FBCLK
I2_FBCLK
MaxBus Pull-ups / Pull-downs
DIFFERENTIAL_PAIR
U2100
MAXBUS_CLK_CPU0_R
CLOCK
11 32
I2
11 32
BGA
I2_FBCLK
I2_FBCLK
MAXBUS_CPUS_BIDIR
MAXBUS
MAXBUS
MAXBUS_CPUS_BIDIR
MAXBUS
MAXBUS
MAXBUS_DATA41
MAXBUS
MAXBUS
MAXBUS_DATA42
MAXBUS
MAXBUS
MAXBUS_DATA43
MAXBUS
MAXBUS
MAXBUS_DATA44
MAXBUS
MAXBUS
MAXBUS_CPUS_BIDIR
MAXBUS
MAXBUS
MAXBUS_DATA54
MAXBUS
MAXBUS
MAXBUS_CPUS_BIDIR
MAXBUS
MAXBUS
MAXBUS_DATA62
MAXBUS
MAXBUS
MAXBUS_CPUS_BIDIR
MAXBUS
MAXBUS
I2_MAXBUS_FBCLK_OUT_R
I2_MAXBUS_FBCLK_OUT
PROCESSOR INTERFACE
32
MAXBUS
MAXBUS
9 32 33
33 32
9 21 32 33
33 32 6
9 21 32 33
33 32 6
9 21 32 33
33 32 6
MAXBUS_NB_TO_CPUS_R
MAXBUS
MAXBUS
MAXBUS_NB_TO_CPUS_R
MAXBUS
MAXBUS
MAXBUS_NB_TO_CPUS_R
MAXBUS
MAXBUS
MAXBUS_CPUS_BIDIR_R
MAXBUS
MAXBUS
MAXBUS_CPUS_TO_NBIO
MAXBUS
MAXBUS
MAXBUS_DTI
MAXBUS
MAXBUS
MAXBUS_GBL_L
MAXBUS
MAXBUS
MAXBUS_CPUS_TO_NBIO
MAXBUS
MAXBUS
MAXBUS_CPUS_TO_NBIO
MAXBUS
MAXBUS
MAXBUS_CPUS_BIDIR
MAXBUS
MAXBUS
MAXBUS_WT_L
MAXBUS
MAXBUS
MAXBUS_NB_TO_CPU0_R
MAXBUS
MAXBUS
MAXBUS_CPU0_TO_NB_R
MAXBUS
MAXBUS
MAXBUS
MAXBUS
MAXBUS_CPU0_DRDY_L
MAXBUS
MAXBUS
MAXBUS_CPU0_TO_NB_R
MAXBUS
MAXBUS
MAXBUS_NB_TO_CPU1_R
MAXBUS
MAXBUS
MAXBUS_CPU1_TO_NB_R
MAXBUS
MAXBUS
MAXBUS_NB_TO_CPU1_R
MAXBUS
MAXBUS
MAXBUS_CPU1_DRDY_L
MAXBUS
MAXBUS
MAXBUS_CPU1_TO_NB_R
MAXBUS
32
9 32 33
32 6
9 21 32 33
32 6
9 32 33
6 32 33
33 32 6
9 32 33
33 32 9
9 32 33
33 32 9
9 32 33
33 32 9
9 32 33
33 32 9
9 32 33
33 32 9
9 32 33
33 32 9
9 32 33
6 32 33
33 32 9
6 32 33
33 32 9
6 32 33
33 32 9
6 32 33
33 32 9
6 32 33
33 32 9
33 32 9
6 32
33 32 9
6 32
33 32 9
6 32
33 32 9
6 32
33 32 9
6 32
Page Notes
33 32 9
33 32 9
33 32 9
33 32 9
33 32 9
33 32 9
33 32 9
PP1V5R1V8_I2_MAXBUS
VOLTAGE=1.5V
33 32 9
1 X 10uF (0603)
41 X 1uF (0402)
33 32 9
33 32 9
33 32 9
33 32 9
I2
33 32 9
C3550
MAXBUS POWER
(6 of 14)
VDD18_0
VDD18_1
VDD18_2
VDD18_3
VDD18_4
VDD18_5
VDD18_6
VDD18_7
VDD18_8
VDD18_9
VDD18_10
VDD18_11
VDD18_12
VDD18_13
VDD18_14
VDD18_15
VDD18_16
VDD18_17
VDD18_18
VDD18_19
VDD18_20
VDD18_21
VDD18_22
VDD18_23
VDD18_24
VDD18_25
VDD18_26
VDD18_27
VDD18_28
VDD18_29
VDD18_30
VDD18_31
VDD18_32
VDD18_33
VDD18_34
VDD18_35
VDD18_36
VDD18_37
VDD18_38
VDD18_39
VDD18_40
1uF
C11
10%
6.3V
CERM
402
C3551
C3552
1uF
2
10%
6.3V
CERM
402
1uF
10%
6.3V
CERM
402
C3553
1uF
2
10%
6.3V
CERM
402
C3554
1uF
2
10%
6.3V
CERM
402
C3555
1uF
2
10%
6.3V
CERM
402
C3599
33 32 9
10uF
2
33 32 9
20%
6.3V
X5R
603
33 32 9
33 32 9
C14
C17
33 32 9
C20
33 32 9
C23
33 32 9
C26
C29
C3
C3556
C3557
C3558
C3559
C3560
C3561
1uF
1uF
1uF
1uF
1uF
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
G21
F25
C21
MAX_QREQ_1_L
MAX_BR_1_L
MAX_DRDY_1_L
MAX_HIT_1_L
B27
MAXBUS_TS_L
MAXBUS_ARTRY_L
C30
MAX_TS_L
MAX_ARTRY_L
6 32 33

- =PP1V5R1V8_RUN_I2_MAXBUS - =PP1V5R1V8_PWRON_I2_MAXBUS - =I2_MAXBUS_FBCLK_IN - MaxBus feedback
clock input. Length should match that
of clock(s) from I2 to CPU(s).
- MAXBUS_1V8 - Provides required voltage
divider for FBCLK if MaxBus OVdd=1.8V.
BGA
33 32 9
33 32 9
2
33 32 9
33 32 9
C32
D18
MAXBUS_ADDR<0>
MAXBUS_ADDR<1>
MAXBUS_ADDR<2>
MAXBUS_ADDR<3>
MAXBUS_ADDR<4>
MAXBUS_ADDR<5>
MAXBUS_ADDR<6>
MAXBUS_ADDR<7>
MAXBUS_ADDR<8>
MAXBUS_ADDR<9>
MAXBUS_ADDR<10>
MAXBUS_ADDR<11>
MAXBUS_ADDR<12>
MAXBUS_ADDR<13>
MAXBUS_ADDR<14>
MAXBUS_ADDR<15>
MAXBUS_ADDR<16>
MAXBUS_ADDR<17>
MAXBUS_ADDR<18>
MAXBUS_ADDR<19>
MAXBUS_ADDR<20>
MAXBUS_ADDR<21>
MAXBUS_ADDR<22>
MAXBUS_ADDR<23>
MAXBUS_ADDR<24>
MAXBUS_ADDR<25>
MAXBUS_ADDR<26>
MAXBUS_ADDR<27>
MAXBUS_ADDR<28>
MAXBUS_ADDR<29>
MAXBUS_ADDR<30>
MAXBUS_ADDR<31>
A28
A19
A23
D21
A25
A18
C28
D25
B31
B24
G28
C25
D31
F19
E30
D27
A27
B28
B25
E19
G27
D30
C31
F28
F27
B30
E28
B18
C22
A17
B19
A26
MAXBUS_CI_L
MAXBUS_GBL_L
MAXBUS_TBST_L
MAXBUS_TSIZ<0>
MAXBUS_TSIZ<1>
MAXBUS_TSIZ<2>
MAXBUS_TT<0>
MAXBUS_TT<1>
MAXBUS_TT<2>
MAXBUS_TT<3>
MAXBUS_TT<4>
MAXBUS_WT_L
A24
E16
D19
C18
B21
B22
D22
E18
A21
A22
D24
MAX_A_00_H
MAX_A_01_H
MAX_A_02_H
MAX_A_03_H
MAX_A_04_H
MAX_A_05_H
MAX_A_06_H
MAX_A_07_H
MAX_A_08_H
MAX_A_09_H
MAX_A_10_H
MAX_A_11_H
MAX_A_12_H
MAX_A_13_H
MAX_A_14_H
MAX_A_15_H
MAX_A_16_H
MAX_A_17_H
MAX_A_18_H
MAX_A_19_H
MAX_A_20_H
MAX_A_21_H
MAX_A_22_H
MAX_A_23_H
MAX_A_24_H
MAX_A_25_H
MAX_A_26_H
MAX_A_27_H
MAX_A_28_H
MAX_A_29_H
MAX_A_30_H
MAX_A_31_H
MAX_CI_L
MAX_GBL_L
MAX_TBST_L
MAX_TSIZ_0_H
MAX_TSIZ_1_H
MAX_TSIZ_2_H
MAX_TT_0_H
MAX_TT_1_H
MAX_TT_2_H
MAX_TT_3_H
MAX_TT_4_H
MAX_WT_L
C8
F11
F14
F17
F20
C3562
C3563
C3564
C3565
C3566
C3567
1uF
1uF
1uF
1uF
1uF
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
R3550
1
F26
J12
J14
=PP1V5R1V8_RUN_I2_MAXBUS
10
NO STUFF
F29
J11
5%
1/10W
MF-LF
603
F23
F8
R3551
C3568
C3569
C3570
C3573
1uF
1uF
1uF
1uF
1uF
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C3571
C3572
1
2
=PP1V5R1V8_PWRON_I2_MAXBUS
10
5%
1/10W
MF-LF
603
J15
I2_ACS_REF
K9
ACS_REF_H
J17
J18
J20
C3574
1uF
J23
J24
10%
6.3V
CERM
402
C3575
C3576
1uF
2
10%
6.3V
CERM
402
1uF
10%
6.3V
CERM
402
C3577
1uF
2
10%
6.3V
CERM
402
C3578
1uF
2
10%
6.3V
CERM
402
C3579
10%
6.3V
CERM
402
R3500
1K
1uF
2
10K
F18
MAXBUS_CPU0_QACK_L
MAXBUS_CPU0_BG_L
MAXBUS_CPU0_DBG_L
MAXBUS_CPU0_INT_L
MAXBUS_CLK_CPU0_R
E22
F24
J19
H21
33
MAX_QACK_1_L
MAX_BG_1_L
MAX_DBG_1_L
CPU_INT_1_L
MAX_CLK_1_H
G18
G24
H19
J21
6 32 33
6 34
11 32
11
6 32
6 32
6
11 32
2
2
1%
1/16W
MF-LF
402
J27
L14
C3580
L23
1uF
M20
N15
10%
6.3V
CERM
402
C3581
C3582
1uF
2
10%
6.3V
CERM
402
1uF
10%
6.3V
CERM
402
C3583
1uF
2
10%
6.3V
CERM
402
C3584
1uF
2
10%
6.3V
CERM
402
C3585
10%
6.3V
CERM
402
MAX_AACK_L
D16
MAX_DTI_0_H
MAX_DTI_1_H
MAX_DTI_2_H
C27
MAXBUS_AACK_L
=I2_MAXBUS_FBCLK_IN
R3506 1
N22
1
C3587
10%
6.3V
CERM
402
1uF
P18
21
MAXBUS_1V8
C3586
10%
6.3V
CERM
402
C3588
10%
6.3V
CERM
402
1uF
1uF
C3589
1uF
2
10%
6.3V
CERM
402
C3590
360
5%
1/16W
MF-LF
402 2
1uF
2
10%
6.3V
CERM
402
RP3510
10K
4
=RP3510P4
MAXBUS_DATA<0>
MAXBUS_DATA<1>
MAXBUS_DATA<2>
MAXBUS_DATA<3>
MAXBUS_DATA<4>
MAXBUS_DATA<5>
MAXBUS_DATA<6>
MAXBUS_DATA<7>
MAXBUS_DATA<8>
MAXBUS_DATA<9>
MAXBUS_DATA<10>
MAXBUS_DATA<11>
MAXBUS_DATA<12>
MAXBUS_DATA<13>
MAXBUS_DATA<14>
MAXBUS_DATA<15>
MAXBUS_DATA<16>
MAXBUS_DATA<17>
MAXBUS_DATA<18>
MAXBUS_DATA<19>
MAXBUS_DATA<20>
MAXBUS_DATA<21>
MAXBUS_DATA<22>
MAXBUS_DATA<23>
MAXBUS_DATA<24>
MAXBUS_DATA<25>
MAXBUS_DATA<26>
MAXBUS_DATA<27>
MAXBUS_DATA<28>
MAXBUS_DATA<29>
MAXBUS_DATA<30>
MAXBUS_DATA<31>
MAXBUS_DATA<32>
MAXBUS_DATA<33>
MAXBUS_DATA<34>
MAXBUS_DATA<35>
MAXBUS_DATA<36>
MAXBUS_DATA<37>
MAXBUS_DATA<38>
MAXBUS_DATA<39>
MAXBUS_DATA<40>
MAXBUS_DATA<41>
MAXBUS_DATA<42>
MAXBUS_DATA<43>
MAXBUS_DATA<44>
MAXBUS_DATA<45>
MAXBUS_DATA<46>
MAXBUS_DATA<47>
MAXBUS_DATA<48>
MAXBUS_DATA<49>
MAXBUS_DATA<50>
MAXBUS_DATA<51>
MAXBUS_DATA<52>
MAXBUS_DATA<53>
MAXBUS_DATA<54>
MAXBUS_DATA<55>
MAXBUS_DATA<56>
MAXBUS_DATA<57>
MAXBUS_DATA<58>
MAXBUS_DATA<59>
MAXBUS_DATA<60>
MAXBUS_DATA<61>
MAXBUS_DATA<62>
MAXBUS_DATA<63>
A10
A9
D12
A11
B10
C10
G16
D9
C9
F15
G15
B9
D10
E15
C7
B7
A8
F16
G13
E13
E12
D7
A7
G12
F12
F13
A6
E10
B6
C6
D6
G7
A3
E6
F7
C4
D3
G9
D4
B16
C16
A13
A16
C13
B15
D15
B12
A14
A12
D13
B13
A15
C15
C5
C12
F6
A5
F9
E9
E7
G10
B4
F10
MAXBUS_DTI<0>
MAXBUS_DTI<1>
MAXBUS_DTI<2>
A30
A29
=RP3511P1
8
5%
1/16W
SM-LF
9 32 33
RP3511
10K
2
=RP3511P2
P22
9 32 33
9 32 33
I2 CPU0 Support
9 32 33
9 32 33
9 32 33
RP3511
9 32 33
10K
9 32 33
=RP3511P3
6
5%
1/16W
SM-LF
9 32 33
9 32 33
9 32 33
9 32 33
9 32 33
9 32 33
9 32 33
9 32 33
9 32 33
10K
4
10K
6
=RP3512P1
8
5%
1/16W
SM-LF
=RP3512P2
=RP3512P3
=RP3512P4
RP3512
10K
3
6
5%
1/16W
SM-LF
9 32 33
9 32 33
RP3512
10K
4
9 32 33
9 32 33
33 32
MAXBUS_CPU0_QREQ_L
10K
5
5%
1/16W
SM-LF
R3513
9 32 33
7
5%
1/16W
SM-LF
RP3512
9 32 33
H22
1.5V IN
MAX_CLK_FB_IN_H
G19
MAXBUS_TA_L
MAXBUS_TEA_L
D28
MAX_TBEN_H
C24
MAX_FBCLK_OUT_H
J22
5%
1/16W
MF-LF
402
9 32 33
9 32 33
9 32 33
I2 CPU1 Support
9 32 33
9 32 33
9 32 33
RP3513
9 32 33
10K
9 32 33
=RP3513P2
7
5%
1/16W
SM-LF
9 32 33
9 32 33
9 32 33
9 32 33
9 21 32 33
9 21 32 33
9 21 32 33
9 21 32 33
10K
3
10K
6
=RP3513P4
5
5%
1/16W
SM-LF
RP3514
10K
6
=RP3514P2
=RP3514P3
7
5%
1/16W
SM-LF
9 32 33
9 32 33
RP3514
10K
3
9 32 33
32
MAXBUS_CPU1_QREQ_L
10K
6
5%
1/16W
SM-LF
R3514
9 32 33
9 32 33
8
5%
1/16W
SM-LF
RP3514
9 32 33
5%
1/16W
MF-LF
402
9 32 33
9 21 32 33
9 32 33
9 32 33
9 32 33
9 32 33
9 32 33
9 32 33
9 32 33
9 21 32 33
9 32 33
I2 Processor Interface
9 32 33
9 32 33
SYNC_MASTER=N/A
SYNC_DATE=N/A
9 32 33
6 32 33

6 32 33

R3505
10
I2_MAXBUS_FBCLK_OUT_R
I2_MAXBUS_FBCLK_OUT

21 32
5%
1/16W
MF-LF
402
1.5V-1.8V OUT (Matches MaxBus OVdd)

Output impedance is 50 Ohms
10K
1
=RP3514P1
9 32 33
9 32 33
6
5%
1/16W
SM-LF
RP3513

- MAXBUS_CPU1_BR_L
- MAXBUS_CPU1_BG_L
- MAXBUS_CPU1_DBG_L
- MAXBUS_CPU1_DRDY_L
- MAXBUS_CPU1_HIT_L
- MAXBUS_CPU1_INT_L
9 32 33
RP3513
=RP3513P3
9 32 33
TP_MAXBUS_TBEN_I2
32
10K
2
9 32 33
9 32 33
5
5%
1/16W
SM-LF
RP3512

- MAXBUS_CPU0_BR_L
- MAXBUS_CPU0_BG_L
- MAXBUS_CPU0_DBG_L
- MAXBUS_CPU0_DRDY_L
- MAXBUS_CPU0_HIT_L
- MAXBUS_CPU0_INT_L
9 32 33
RP3511
=RP3511P4
SIZE
APPLE COMPUTER INC.
DRAWING NUMBER
REV.
C
051-6929
35
115
SHT
OF
NONE
7
5%
1/16W
SM-LF
9 32 33
SCALE
5
5%
1/16W
SM-LF
RP3511
6 32 33
6
5%
1/16W
SM-LF
A31
MAX_D_00_H
MAX_D_01_H
MAX_D_02_H
MAX_D_03_H
MAX_D_04_H
MAX_D_05_H
MAX_D_06_H
MAX_D_07_H
MAX_D_08_H
MAX_D_09_H
MAX_D_10_H
MAX_D_11_H
MAX_D_12_H
MAX_D_13_H
MAX_D_14_H
MAX_D_15_H
MAX_D_16_H
MAX_D_17_H
MAX_D_18_H
MAX_D_19_H
MAX_D_20_H
MAX_D_21_H
MAX_D_22_H
MAX_D_23_H
MAX_D_24_H
MAX_D_25_H
MAX_D_26_H
MAX_D_27_H
MAX_D_28_H
MAX_D_29_H
MAX_D_30_H
MAX_D_31_H
MAX_D_32_H
MAX_D_33_H
MAX_D_34_H
MAX_D_35_H
MAX_D_36_H
MAX_D_37_H
MAX_D_38_H
MAX_D_39_H
MAX_D_40_H
MAX_D_41_H
MAX_D_42_H
MAX_D_43_H
MAX_D_44_H
MAX_D_45_H
MAX_D_46_H
MAX_D_47_H
MAX_D_48_H
MAX_D_49_H
MAX_D_50_H
MAX_D_51_H
MAX_D_52_H
MAX_D_53_H
MAX_D_54_H
MAX_D_55_H
MAX_D_56_H
MAX_D_57_H
MAX_D_58_H
MAX_D_59_H
MAX_D_60_H
MAX_D_61_H
MAX_D_62_H
MAX_D_63_H
MAX_TA_L
MAX_TEA_L
N21
P15
=RP3510P3
7
5%
1/16W
SM-LF
N19
P14
10K
2
10K
1uF
2
RP3510
=RP3510P2
RP3510

- MAXBUS_TS_L
- MAXBUS_TA_L
- MAXBUS_TEA_L
- MAXBUS_ARTRY_L
- MAXBUS_AACK_L
- (Spare)
J26
L17
8
5%
1/16W
SM-LF
6 32 33
TP_MAXBUS_CPU1_QACK_L
MAXBUS_CPU1_BG_L
MAXBUS_CPU1_DBG_L
MAXBUS_CPU1_INT_L
E24
=RP3510P1
10K
33 32 6
33 32 9
(41 Balls on I2)
RP3510
MAX_QACK_0_L
MAX_BG_0_L
MAX_DBG_0_L
CPU_INT_0_L
MAX_CLK_0_H
MAXBUS INTERFACE
6 32 33
33 32 9
U2100
E27
MAXBUS_CPU1_QREQ_L
MAXBUS_CPU1_BR_L
MAXBUS_CPU1_DRDY_L
MAXBUS_CPU1_HIT_L
6 32 33
MAXBUS_CPU1_BG_L
MAXBUS_CPU1_BR_L
MAXBUS_CPU1_DBG_L
MAXBUS_CPU1_DRDY_L
MAXBUS_CPU1_HIT_L
MaxBus I/O DECOUPLING
E21
6 32 33
33 32 9
OMIT
G25
MAX_QREQ_0_L
MAX_BR_0_L
MAX_DRDY_0_L
MAX_HIT_0_L
PROCESSOR 1
9 21 32 33
MAXBUS_CPU0_BG_L
MAXBUS_CPU0_BR_L
MAXBUS_CPU0_DBG_L
MAXBUS_CPU0_DRDY_L
MAXBUS_CPU0_HIT_L
MAXBUS
F21
9 32 33
33 32 9
MAXBUS_NB_TO_CPU0_R
E25
MAXBUS_CPU0_QREQ_L
MAXBUS_CPU0_BR_L
MAXBUS_CPU0_DRDY_L
MAXBUS_CPU0_HIT_L
9 21 32 33
MAXBUS_TS_L
MAXBUS_TA_L
MAXBUS_TEA_L
MAXBUS_AACK_L
MAXBUS_ARTRY_L
MAXBUS_CI_L
MAXBUS_DTI<0..2>
MAXBUS_GBL_L
MAXBUS_TBST_L
MAXBUS_TSIZ<0..2>
MAXBUS_TT<0..4>
MAXBUS_WT_L
=PP1V5R1V8_MAXBUS
PROCESSOR 0
9 32 33
32 6
MAXBUS_CPUS_BIDIR_R
34 33 21 10
(5 of 14)
21 32
MAXBUS_ADDR<0..31>
MAXBUS_DATA<0..40>
MAXBUS_DATA<41>
MAXBUS_DATA<42>
MAXBUS_DATA<43>
MAXBUS_DATA<44>
MAXBUS_DATA<45..53>
MAXBUS_DATA<54>
MAXBUS_DATA<55..61>
MAXBUS_DATA<62>
MAXBUS_DATA<63>
NET_TYPE
DIFFERENTIAL_PAIR
=MAXBUS_CPU0_CLK
11 33
32 9
32 9
32 9
Page Notes
32 9
32 9
32 9
- =PP1V5R1V8_MAXBUS
32 9
32 9

32 9
- =MAXBUS_CPU0_CLK
32 9
32 9
(NONE)
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
34 33 32 21 10
32 9
=PP1V5R1V8_MAXBUS
32 9
32 9
32 9
32 9
32 9
B4
U3600
C2
P11
32 9
R4
32 9
R13
32 9
R16
32 9
BGA
C12
D5
F2
H3
OVDD
J5
A8-X.X
XXGHZ-XXV
(5 OF 6)
32 9
T6
32 9
T9
OVDD
32 21 9
U2
K2
U12
32 21 9
L5
U16
32 21 9
M3
V4
32 21 9
N6
V7
32 9
P2
V10
32 9
V14
32 9
OMIT
P8
CRITICAL
E18
TP_CPU0_OVDDSENSE1
TP_CPU0_OVDDSENSE2
G18
32 9
OVDDSENSE1
OVDDSENSE2
32 9
32 9
(Kelvin sense points)
32 9
32 9
32 9
32 21 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 21 9
32 9
=PP1V5R1V8_MAXBUS
C3670
1uF
2
C3671
1uF
C3672
1uF
C3673
1uF
C3674
1uF
C3675
1uF
C3676
1uF
C3677
1uF
C3678
10%
10%
10%
10%
10%
10%
10%
10%
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
C3680
T14
V16
W16
T15
U15
P14
V13
W13
T13
P13
U14
W14
R12
T12
W12
V12
N11
N10
R11
U11
W11
T11
R10
N9
P10
U10
R9
W10
U9
V9
W5
U6
T5
U5
W7
R6
P7
V6
P17
R19
V18
R18
V19
T19
U19
W19
U18
W17
W18
T16
T18
T17
W3
V17
U4
U8
U7
R7
P6
R8
W8
T8
CERM
402
C3681
CERM
402
C3682
CERM
402
C3683
CERM
402
C3684
CERM
402
C3685
CERM
402
C3686
1uF
10%
2
W15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7
T3
DBG*
DRDY*
DTI0
DTI1
DTI2
DTI3
M2
TA*
TEA*
K6
L1
MAXBUS_TA_L
MAXBUS_TEA_L
HIT*
B2
MAXBUS_CPU0_HIT_L
U3600
BGA
(2 OF 6)
W4
T4
W9
M6
V3
N8
W6
NC
NC
NC
NC
NC
NC
NC
NC
PLACE RC GLITCH FILTER
OMIT
CRITICAL
MAXBUS_CPU0_DBG_L
MAXBUS_CPU0_DRDY_L_R
MAXBUS_EDTI
MAXBUS_DTI<0>
MAXBUS_DTI<1>
MAXBUS_DTI<2>
R3
G1
K1
P1
N1
R3600
6 32
CLOSE TO CPU PIN
MAXBUS_CPU0_DRDY_L
5%
1/16W
MF-LF
402
33
9 32
6 32
C3600
10PF
9 32
5%
2
9 32
50V
CERM
402
6 32
6 32
6 32
U3600
32 6
32 6
32 6
MAXBUS_CPU0_BR_L
MAXBUS_CPU0_BG_L
MAXBUS_TS_L
D2
M1
L4
R3601
470
1
CPU0_PULLDOWN
E11
H1
5%
1/16W
MF-LF
402
C11
G3
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
32 9
MAXBUS_ADDR<0>
MAXBUS_ADDR<1>
MAXBUS_ADDR<2>
MAXBUS_ADDR<3>
MAXBUS_ADDR<4>
MAXBUS_ADDR<5>
MAXBUS_ADDR<6>
MAXBUS_ADDR<7>
MAXBUS_ADDR<8>
MAXBUS_ADDR<9>
MAXBUS_ADDR<10>
MAXBUS_ADDR<11>
MAXBUS_ADDR<12>
MAXBUS_ADDR<13>
MAXBUS_ADDR<14>
MAXBUS_ADDR<15>
MAXBUS_ADDR<16>
MAXBUS_ADDR<17>
MAXBUS_ADDR<18>
MAXBUS_ADDR<19>
MAXBUS_ADDR<20>
MAXBUS_ADDR<21>
MAXBUS_ADDR<22>
MAXBUS_ADDR<23>
MAXBUS_ADDR<24>
MAXBUS_ADDR<25>
MAXBUS_ADDR<26>
MAXBUS_ADDR<27>
MAXBUS_ADDR<28>
MAXBUS_ADDR<29>
MAXBUS_ADDR<30>
MAXBUS_ADDR<31>
F10
L2
D11
D1
C10
G2
D12
L3
G4
T2
F4
V1
J4
R2
K5
W2
J2
K4
N4
J3
M5
P5
N3
T1
V2
U1
N5
W1
B12
C4
G10
B11
BR*
BG*
TS*
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
AP0
AP1
AP2
AP3
AP4
C1
TT0
TT1
TT2
TT3
TT4
TBST*
TSIZ0
TSIZ1
TSIZ2
GBL*
WT*
CI*
AACK*
ARTRY*
SHD0*
SHD1*
SYSCLK
CLK_OUT
TBEN
QREQ*
QACK*
CKSTP_IN*
CKSTP_OUT*
E5
BGA
(1 OF 6)
OMIT
CRITICAL
E3
H6
F5
G7
E6
F6
E9
C5
F11
G6
F7
E7
E2
D3
J1
R1
N2
E4
H5
A10
H2
E1
P4
G5
NC
NC
NC
NC
NC
MAXBUS_TT<0>
MAXBUS_TT<1>
MAXBUS_TT<2>
MAXBUS_TT<3>
MAXBUS_TT<4>
MAXBUS_TBST_L
MAXBUS_TSIZ<0>
MAXBUS_TSIZ<1>
MAXBUS_TSIZ<2>
MAXBUS_GBL_L
MAXBUS_WT_L
MAXBUS_CI_L
MAXBUS_AACK_L
MAXBUS_ARTRY_L
MAXBUS_SHD0_L
MAXBUS_SHD1_L
=MAXBUS_CPU0_CLK
TP_CPU0_CLKOUT
MAXBUS_TBEN
MAXBUS_CPU0_QREQ_L
MAXBUS_CPU0_QACK_L
9 32
9 32
9 32
9 32
9 32
9 32
9 32
9 32
9 32
9 32
9 32
9 32
6 32
6 32
33
33
11 33
ADD GND TP NEAR CLKOUT TP
21
32
32
A3
B1
CPU_CHKSTP_OUT_L
34
26 X 1UF (0402)
2 X 10UF (0603)
6.3V
CERM
402
R15
10 21 32 33 34
VIO DECOUPLING (28 PINS)

1
MAXBUS_DATA<0>
MAXBUS_DATA<1>
MAXBUS_DATA<2>
MAXBUS_DATA<3>
MAXBUS_DATA<4>
MAXBUS_DATA<5>
MAXBUS_DATA<6>
MAXBUS_DATA<7>
MAXBUS_DATA<8>
MAXBUS_DATA<9>
MAXBUS_DATA<10>
MAXBUS_DATA<11>
MAXBUS_DATA<12>
MAXBUS_DATA<13>
MAXBUS_DATA<14>
MAXBUS_DATA<15>
MAXBUS_DATA<16>
MAXBUS_DATA<17>
MAXBUS_DATA<18>
MAXBUS_DATA<19>
MAXBUS_DATA<20>
MAXBUS_DATA<21>
MAXBUS_DATA<22>
MAXBUS_DATA<23>
MAXBUS_DATA<24>
MAXBUS_DATA<25>
MAXBUS_DATA<26>
MAXBUS_DATA<27>
MAXBUS_DATA<28>
MAXBUS_DATA<29>
MAXBUS_DATA<30>
MAXBUS_DATA<31>
MAXBUS_DATA<32>
MAXBUS_DATA<33>
MAXBUS_DATA<34>
MAXBUS_DATA<35>
MAXBUS_DATA<36>
MAXBUS_DATA<37>
MAXBUS_DATA<38>
MAXBUS_DATA<39>
MAXBUS_DATA<40>
MAXBUS_DATA<41>
MAXBUS_DATA<42>
MAXBUS_DATA<43>
MAXBUS_DATA<44>
MAXBUS_DATA<45>
MAXBUS_DATA<46>
MAXBUS_DATA<47>
MAXBUS_DATA<48>
MAXBUS_DATA<49>
MAXBUS_DATA<50>
MAXBUS_DATA<51>
MAXBUS_DATA<52>
MAXBUS_DATA<53>
MAXBUS_DATA<54>
MAXBUS_DATA<55>
MAXBUS_DATA<56>
MAXBUS_DATA<57>
MAXBUS_DATA<58>
MAXBUS_DATA<59>
MAXBUS_DATA<60>
MAXBUS_DATA<61>
MAXBUS_DATA<62>
MAXBUS_DATA<63>
A8-X.X
CLOCK
XXGHZ-XXV
PHYSICAL
CLOCK
32 9
I1020
A8-X.X
SPACING
XXGHZ-XXV
CERM
402
C3687
C3679
1uF
10%
CERM
402
C3688
6.3V
CERM
402
MAXBUS Straps
1
1uF
1uF
10%
2
6.3V
1uF
10%
CERM
402
C3690
6.3V
1uF
10%
CERM
402
C3691
6.3V
1uF
10%
CERM
402
C3692
1uF
10%
6.3V
CERM
402
C3693
6.3V
1uF
10%
CERM
402
C3694
6.3V
CERM
402
1uF
10%
2
6.3V
CERM
402
1uF
10%
2
6.3V
CERM
402
1uF
10%
2
6.3V
CERM
402
C3689
34 33 32 21 10
10%
2
=PP1V5R1V8_MAXBUS
6.3V
CERM
402
R3610
1uF
1uF
1uF
1uF
1uF
1uF
10%
10%
10%
10%
10%
10%
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
33
C3695
CERM
402
33
MAXBUS_SHD0_L
A8 MaxBus (CPU0)
10K
1
SYNC_MASTER=MULLET
5%
1/16W
MF-LF
402
MAXBUS_SHD1_L
R3611
1

1%
1/16W
MF-LF
402
C3698
10uF
4V
X5R
603

R3620
20%
2
C3699
10uF
20%
2
SYNC_DATE=08/02/2005
10K
4V
X5R
603
33
MAXBUS_EDTI
1K
SIZE
1%
1/16W
MF-LF
402
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
36
115
SHT
OF
NONE
Page Notes
- =PP1V5R1V8_MAXBUS
- =PP3V3_PWRON_PLLSEL
34
CPU0 PLL CONFIG CIRCUITRY

U3600
B7
BVSEL0
CPU0_PLL_CFG<0>
CPU0_PLL_CFG<1>
CPU0_PLL_CFG<2>
CPU0_PLL_CFG<3>
CPU0_PLL_CFG<4>
B8
PLL_CFG0
(3 OF 6)
PLL_CFG1
PLL_CFG2
PLL_CFG3
PLL_CFG4 CFGEXT
A7PM
TDI
TDO
OMIT
TMS
TCK
CRITICAL
TRST*
LSSD_MODE*
TEST0
L1_TSTCLK
TEST2
L2_TSTCLK
A7PM
TEST3
TEST1
TEST4
INT*
SMI*
MCP*
SRESET*
HRESET*
D4
PMON_IN*
PMON_OUT*
D9
BMODE0*
BMODE1*
G9
34
34
34
9
9
9

- CPU0_PLL0_0/1
- CPU0_PLL1_0/1
- CPU0_PLL2_0/1
- CPU0_PLL3_0/1
- CPU0_PLL4_0/1
- CPU0_PLL5_0/1
These must be selected to set the CPU core to Maxbus
frequency ratio to attain the desired spec
- MAXBUS_1V5
- MAXBUS_1V8
One of these must be selected to set the Maxbus voltage
* the MAXBUS_1V5 option does not exist for A7PM
- CPU_A7PM
- CPU_A8
One of these must be selected to ensure the the above
strap is interpreted correctly
9
9
34
34
34
C8
C7
D7
A7
=JTAG_CPU0_TDI
=JTAG_CPU0_TDO
=JTAG_CPU0_TMS
=JTAG_CPU0_TCK
=JTAG_CPU0_TRST_L
CPU_LSSD_MODE_L
CPU0_L1TSTCLK
CPU0_L2TSTCLK
B9
A4
F1
C6
A5
E8
G8
B3
XXGHZ-XXV
34
A8-X.X
BGA
34

- =CPU0_JTAG_TDI
- =CPU0_JTAG_TDO
- =CPU0_JTAG_TMS
- =CPU0_JTAG_TCK
- =CPU0_JTAG_TRST_L
- =CPU_HRESET_L (Reset given to all processors)
A7PM
BVSEL
CPU_BVSEL<0>
MAXBUS_CPU0_INT_L
CPU0_SMI_L
CPU_MCP_L
CPU0_SRESET_L
=CPU_HRESET_L
F9
C9
A2
D8
CPU_PMON_IN_L
TP_CPU0_PMON_OUT_L
A9
EXT_QUAL
F8
CPU0_BMODE0_L
CPU0_BMODE1_L
A11
CPU0_EXT_QUAL
DFS2*
LVRAM*
BVSEL1
DFS4*
PLL_CFG5
A12
TEMP_ANODE
TEMP_CATHODE
HPR_N
N18
B10
E10
B6
D10
N19
A6
CPU0_DFS2_L
CPU0_LVRAM_L
CPU_BVSEL<1>
CPU0_DFS4_L
CPU0_PLL_CFG<5>
6 32
34
34 33 32 21 10
=PP1V5R1V8_MAXBUS
34
CPU0_PLL0_1
34
11 34
34
CPU0_PLL1_1
1
R3720
R3722
CPU0_PLL2_1
1
R3724
CPU0_PLL3_1
1
CPU0_PLL4_1
1
R3726
R3728
10K
10K
10K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
CPU0_PLL5_1
1
R3730
10K
5%
1/16W
MF-LF
402
CPU0_PLL_CFG<0>
CPU0_PLL_CFG<1>
CPU0_PLL_CFG<2>
CPU0_PLL_CFG<3>
CPU0_PLL_CFG<4>
CPU0_PLL_CFG<5>
34
34
34
34
34
CPU0_PLL0_0
34
34
34
TP_CPU0_TEMP_ANODE
TP_CPU0_TEMP_CATHODE
TP_CPU0_HPR_N
CPU0_PLL1_0
1
R3721
R3723
CPU0_PLL2_0
1
R3725
CPU0_PLL3_0
1
CPU0_PLL4_0
1
R3727
R3729
10K
10K
10K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
34
34
34
34
34
34
CPU0_PLL5_0
1
R3731
10K
5%
1/16W
MF-LF
402
BUS TYPE SELECT

SIGNAL
TIED
CPU0_BMODE0_L
(PROCESSOR)
MODE
MAXBUS VSEL
R3704
HIGH
60X BUS MODE
CPU_HRESET_L
MAX BUS MODE
34
CPU0_BMODE0_L
22
=CPU_HRESET_L
11 34
CPU_BVSEL<0>
10
BVSEL0
R3702
BVSEL1
1.8V INTERFACE
GND
OVDD
2.5V INTERFACE
OVDD
OVDD
2.5V INTERFACE
CPU_HRESET_L
OVDD
RESERVED(1.5V)
CPU_HRESET_INV
OVDD
10 21 32 33 34
() Indicates DFS setting supported by A8 only
BOM GROUP
5%
1/16W
MF-LF
402
MAXBUS_1V8
OVDD
=PP1V5R1V8_MAXBUS
R3703
34
A7PM
CPU0 FREQUENCY CONFIGURATION
MAXBUS_1V5
5%
1/16W
MF-LF
402
DFS SUPPORT
F/2
PLL BITS
F/4
TABLE_BOMGROUP_HEAD
BOM OPTIONS
012345
TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_1.0X
001100
CPU0_PLL0_0,CPU0_PLL1_0,CPU0_PLL2_1,CPU0_PLL3_1,CPU0_PLL4_0,CPU0_PLL5_0
CPU0_BUSRATIO_2.0X
010000
CPU0_BUSRATIO_3.0X
100000
CPU0_BUSRATIO_4.0X
2.0X
101000
CPU0_BUSRATIO_5.0X
2.5X
101100
(2.75X)
100100
10
TABLE_BOMGROUP_ITEM
5%
1/16W
MF-LF
402 2
TABLE_BOMGROUP_ITEM
(SPEC request this pull down

resistor should less than 250 ohm)
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_5.5X
CPU_A7PM
A8
TABLE_BOMGROUP_ITEM
=PP1V5R1V8_MAXBUS
R3705
OVDD
BVSEL0
34
BVSEL1
1.8V INTERFACE
GND
GND
1.5V INTERFACE
OVDD
GND
CPU_BVSEL<1>
CPU_A8
10K
CPU0_BUSRATIO_6.0X
10 21 32 33 34
CPU0_BUSRATIO_6.5X
5%
1/16W
MF-LF
402
R3706 1
RESERVED
CPU_HRESET_L
GND
RESERVED
CPU_HRESET_INV
GND
110100
010100
3.5X
001000
(3.75X)
000100
4.0X
2.0X
110000
(4.25X)
011000
011110
TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_7.0X
TABLE_BOMGROUP_ITEM
1K
5%
1/16W
MF-LF
402
3.0X
(3.25X)
TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_7.5X
TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_8.0X
2
TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_8.5X
TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_9.0X
2.5V INTERFACE
GND
OVDD
2.5V INTERFACE
OVDD
OVDD
4.5X
(2.25X)
TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_9.5X
(4.75X)
011100
5.0X
2.5X
101010
(5.25X)
100010
100110
TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_10.0X
RESERVED
CPU_HRESET_L
OVDD
RESERVED
CPU_HRESET_INV
OVDD
TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_10.5X
TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_11.0X
5.5X
(2.75X)
TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_11.5X
CPU PULLUPS
(5.75X)
000000
6.0X
3.0X
101110
TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_12.0X
TABLE_BOMGROUP_ITEM
34 33 32 21 10
=PP1V5R1V8_MAXBUS
CPU0_BUSRATIO_12.5X
(6.25X)
111110
010110
TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_13.0X
R3752
33
CPU_CHKSTP_OUT_L
INTERRUPT PULL-UPS
10K
1
6.5X
(3.25X)
TABLE_BOMGROUP_ITEM
(6.75X)
111000
CPU0_BUSRATIO_14.0X
7.0X
3.5X
110010
CPU0_BUSRATIO_15.0X
7.5X
(3.75X)
000110
CPU0_BUSRATIO_16.0X
8.0X
4.0X
110110
CPU0_BUSRATIO_17.0X
8.5X
(4.25X)
000010
CPU0_BUSRATIO_18.0X
9.0X
4.5X
001010
CPU0_BUSRATIO_20.0X
10.0X
5.0X
001110
CPU0_BUSRATIO_21.0X
10.5X
(5.25X)
010010
CPU0_BUSRATIO_24.0X
12.0X
6.0X
011010
CPU0_BUSRATIO_28.0X
14.0X
7.0X
111010
CPU0_BUSRATIO_13.5X
TABLE_BOMGROUP_ITEM
34
5%
1/16W
MF-LF
402
CPU_LSSD_MODE_L
34 33 32 21 10
CPU_MCP_L
34
CPU0_LVRAM_L
10K
34
CPU0_L2TSTCLK
5%
1/16W
MF-LF
402
CPU0_BMODE1_L
PID<0> SELECT
34 11
=CPU_HRESET_L
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
5%
1/16W
MF-LF
402
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
R3767
10K
1
CPU PULLDOWNS
10K
2
5%
1/16W
MF-LF
402
R3761
2
5%
1/16W
MF-LF
402
34
SYNC_MASTER=MULLET
5%
1/16W
MF-LF
402

R3772
5%
1/16W
MF-LF
402
34
1K
CPU0_EXT_QUAL
1K
2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
A8 Configuration Straps
1K
2
10K
1
CPU0_L1TSTCLK
R3758
R3707
34
TABLE_BOMGROUP_ITEM
CPU_PMON_IN_L
5%
1/16W
MF-LF
402
10K
R3759
34
5%
1/16W
MF-LF
402
10K
1
CPU0_SRESET_L
R3765
1
CPU0_DFS4_L
TABLE_BOMGROUP_ITEM
34
CPU0_DFS2_L
TABLE_BOMGROUP_ITEM
10K
CPU0_SMI_L
R3771
R3766
34
34
2
5%
1/16W
MF-LF
402
34
R3769
5%
1/16W
MF-LF
402
10K
1
TABLE_BOMGROUP_ITEM
10K
1
R3756
34
=PP1V5R1V8_MAXBUS
R3753

R3757
10K
1
SIZE
5%
1/16W
MF-LF
402
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
37
115
SHT
OF
NONE
Page Notes
VCORE BULK CAPS

- =PPVCORE_CPU0
35 10
=PPVCORE_CPU0
40 X 1 UF (0402)

(NONE)
(NONE)
1
C3830
1UF
D
1
P12
U3600
C3
D6
CERM
402
C3838
F3
G17
A8-X.X
XXGHZ-XXV
E17
U3600
A18
BGA
B17
(4 OF 6)
B19
H10
XXGHZ-XXV
H12
J7
J9
J11
J13
A8-X.X
H8
U17
H9
V5
H11
V8
H13
V11
J6
V15
C3841
1UF
1UF
CERM
402
C3842
1UF
C3836
CERM
402
C3843
1UF
10%
C3844
10%
10%
10%
10%
10%
6.3V
6.3V
6.3V
6.3V
6.3V
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
C3845
1UF
10%
2
6.3V
CERM
402
6.3V
CERM
402
1UF
6.3V
10%
2
C3837
10%
6.3V
6.3V
CERM
402
1UF
10%
2
1UF
10%
6.3V
CERM
402
CERM
402
C3846
C3847
C3848
C3849
C3850
C3851
C3852
1UF
1UF
1UF
1UF
1UF
1UF
1UF
10%
10%
10%
10%
10%
10%
10%
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
C3853
1UF
10%
6.3V
CERM
402
CERM
402
A17
GND
A19
OMIT
GND
CRITICAL
B13
B16
K3
B18
K9
E12
K11
E19
K13
F13
L6
F16
L8
F18
L10
G19
C3854
C3855
C3856
C3857
C3858
C3859
C3860
1UF
1UF
1UF
1UF
1UF
1UF
1UF
10%
10%
10%
10%
10%
10%
10%
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
CERM
402
C3861
1UF
10%
6.3V
CERM
402
CERM
402
H18
L12
M4
J14
M7
L14
M9
M15
M11
M17
M13
M19
N7
N14
P3
N16
P9
P15
E16
F12
K8
F17
F19
35 10
24 X 10 UF (0603)
=PPVCORE_CPU0
G11
VDD
VDD
L7
G16
1
H14
L9
H17
OMIT
P19
L11
H19
CRITICAL
M14
M8
M16
N13
TP_CPU0_SENSEGND1
TP_CPU0_SENSEGND2
G12
SENSEGND1
SENSEGND2
M10
M18
NC
A14
N/C_1
N/C_21
C17 NC
N15
NC
B14
M12
N/C_2
N17
A16
P16
NC
N/C_3
N/C_4
N/C_22
N/C_23
D17 NC
C14
A13
NC
N/C_24
D18 NC
NC
N/C_25
N/C_26
C19
P18
N/C_27
H16 NC
N/C_28
N/C_29
J16
N/C_30
N/C_31
L16 NC
N/C_32
K17 NC
N/C_33
N/C_34
L17 NC
N/C_35
K18 NC
N/C_36
N/C_37
L18
N/C_38
K19 NC
N/C_39
L19
NC
TP_CPU0_SENSEVDD1
TP_CPU0_SENSEVDD2
C3840
CERM
402
C3835
1UF
6.3V
E13
K12
L13
1UF
10%
2
C13
K10
K14
C3839
CERM
402
C3834
1UF
6.3V
U3
U13
K7
CERM
402
10%
2
T7
H7
J12
C3833
1UF
6.3V
R17
H4
J10
=PPVCORE_CPU0
10%
2
T10
J8
35 10
C3832
1UF
6.3V
R14
(6 OF 6)
D13
R5
BGA
10%
6.3V
1UF
B5
C3831
1UF
10%
2
N12
SENSEVDD1
G13
SENSEVDD2
AVDD
A8
=PPAVDD_CPU0
NC
10
NC
NC
NC
D14
E14
F14
G14
N/C_5
N/C_6
N/C_7
A15
N/C_8
B15
N/C_9
N/C_10
C15
NC
D15
NC
E15
NC
F15
N/C_13
NC
G15
NC
H15
N/C_14
N/C_15
N/C_11
N/C_12
J15
N/C_16
NC
K15
NC
L15
N/C_17
N/C_18
NC
NC
NC
C16
N/C_19
D16
N/C_20
C18 NC
2
NC
C3800
C3801
C3802
C3803
C3804
C3805
C3806
C3807
C3808
10uF
10uF
10uF
10uF
10uF
10uF
10uF
10uF
10uF
20%
20%
20%
20%
20%
20%
20%
20%
20%
4V
4V
4V
4V
4V
4V
4V
4V
4V
X5R
603
C3810
X5R
603
C3811
X5R
603
C3812
X5R
603
C3813
X5R
603
C3814
X5R
603
C3815
X5R
603
C3816
X5R
603
C3817
10uF
10uF
10uF
10uF
10uF
10uF
10uF
20%
20%
20%
20%
20%
20%
20%
20%
4V
4V
4V
4V
4V
4V
4V
4V
4V
C3820
X5R
603
C3821
X5R
603
X5R
603
X5R
603
X5R
603
X5R
603
X5R
603
20%
C3818
10uF
20%
C3809
10uF
X5R
603
10uF
X5R
603
4V
X5R
603
C3819
10uF
20%
X5R
603
4V
X5R
603
D19 NC
NC
K16 NC
2
J17 NC
C3822
10uF
10uF
10uF
20%
20%
20%
4V
X5R
603
4V
X5R
603
4V
X5R
603
C3823
10uF
20%
4V
X5R
603
J18 NC
NC
J19 NC
NC
A8 Power (CPU0)
SYNC_MASTER=MULLET

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
38
115
SHT
OF
NONE
NET_TYPE
SPACING PHYSICAL
"Low" and "Mid" States
DIFFERENTIAL_PAIR
36 10
THERM
THERM
I400
I401
VCORE_SNS
VCORE_GNDSNS
THERM
THERM
DESCRIPTION
Q16BST&Q41 Q16BST&Q41 Q16BST&Q41

1
RES,3.48K,1%,1/16W,MF-LF,402,SMD
R3946
CPU0_VCORE_1V22
114S0258
RES,2.61K,1%,1/16W,MF-LF,402,SMD
R3944
CPU0_VCORE_1V22
TABLE_5_ITEM
114S0246
RES,2.0K,1%,1/16W,MF-LF,402,SMD
R3946
470K
5%
1/16W
MF-LF
2 402
470K
5%
1/16W
MF-LF
2 402
114S0294
RES,6.04K,1%,1/16W,MF-LF,402,SMD
R3944
CPU0_VCORE_1V28
114S0276
RES,4.02K,1%,1/16W,MF-LF,402,SMD
R3946
CPU0_VCORE_1V30
TABLE_5_ITEM
Q16BST&Q41 NO STUFF
1.320V -> 0.940V

1.67GHZ
114S0254
RES,2.43K,1%,1/16W,MF-LF,402,SMD
R3944
CPU0_VCORE_1V30
114S0246
RES,2.0K,1%,1/16W,MF-LF,402,SMD
R3946
CPU0_VCORE_1V33
114S0294
RES,6.04K,1%,1/16W,MF-LF,402,SMD
R3944
CPU0_VCORE_1V33
TABLE_5_ITEM
1.67GHZ
470K
5%
1/16W
MF-LF
2 402
NO STUFF
470K
5%
1/16W
MF-LF
2 402
CPU_VCORE_3STATES
CRITICAL
5%
1/16W
MF-LF
2 402
VCORE_VID_B<1>
VCORE_VID_B<2>
VCORE_VID_B<3>
VCORE_VID_B<4>
36
36
36
NO STUFF
NO STUFF
NO STUFF
R3981 1R3983 1R3985 1R3987
36
36
36
36
36
36
36
36
470K
(CPU SPEC: 1.280V -> 0.930V)
470K
5%
1/16W
MF-LF
2 402
(CPU SPEC: 1.300V -> 0.930V)
470K
5%
1/16W
MF-LF
2 402
<D4>
<D3>
470K
5%
1/16W
MF-LF
2 402
<D2>
NO STUFF
NO STUFF
36
R3971 1R3973 1R3975 1R3977
470K
5%
1/16W
MF-LF
2 402
NO STUFF
470K
5%
1/16W
MF-LF
2 402
<D1>
470K
5%
1/16W
MF-LF
2 402
<D4>
5%
1/16W
MF-LF
2 402
<D3>
36
470K
5%
1/16W
MF-LF
2 402
<D2>
36
11
<D1>
(CPU SPEC: 1.330V -> 0.930V)
0.1uF
U3990
74CBTLV3257 4
A1 QSOP Y1
3
B1
5
Y2 7
A2
6
B2
9
11
A3
Y3
10
B3
12
14
A4
Y4
13
B4
2
VCORE_VID_A<1>
VCORE_VID_B<1>
VCORE_VID_A<2>
VCORE_VID_B<2>
VCORE_VID_A<3>
VCORE_VID_B<3>
VCORE_VID_A<4>
VCORE_VID_B<4>
=CPU0_VID_AB_SEL 1
15
VID_MUX_OE_L
CPU_VCORE_3STATES
SEL
OE
R39601
1K
VCORE_VCC
VOLTAGE=12.8V
10
(VCORE_GNDSNS) 11
36 11
16
SKP/SDN
FBS
ILIM
GNDS
A/B
NO STUFF
R3988
MAX1717 VID CAN TAKE 3.3V TO 5.5V INPUTS

36
36
36
36
36
<D0>
VCORE_VID<0>
VCORE_VID<1>
VCORE_VID<2>
VCORE_VID<3>
VCORE_VID<4>
V+
BST 22
DH 24
VCORE_BST2
2.2
TON
LX
23
VCORE_LX
VCORE_CC
CC
DL
14
VCORE_DL
D0
D1
D2
D3
D4
GND
13
Q16BST&Q41
R39891
66.5K
0.01UF
5%
1/16W
MF-LF
402 2
R39641 R39631
C3964 1
1%
1/16W
MF-LF
402 2
20%
16V
CERM 2
402
C3962 C3963
1UF
12.7K
18
17
10uF
10%
25V
2 X5R
1206
10%
25V
2 X5R
1206
CRITICAL
36
C3943
36
10uF
36
10%
25V
2 X5R
1206
VCORE_VID_A<1>
VCORE_VID_A<2>
VCORE_VID_A<3>
VCORE_VID_A<4>
CRITICAL
C3948
10uF
C3942
10%
25V
2 X5R
1206
CRITICAL
C3947
10uF
10uF
10%
25V
2 X5R
1206
CRITICAL
1
CRITICAL
C3941
C3949
10uF
10%
25V
2 X5R
1206
FB 4
TIME 3
VGATE 12
0.1UF
390K
5%
1/16W
MF-LF
402 2
Keep trace fat and short!!
LFPAK
CRITICAL
C3950 1
0.001UF
20%
50V
CERM 2
402
1%
1W
MF-LF
2512
CRITICAL
NO STUFF
1
Q3903 R3901
2.2
HAT2160H
HAT2160H
5%
1/4W
MF-LF
1206 2
LFPAK
LFPAK
CRITICAL
CRITICAL
D3900
PWRMITE
CPU_VCORE_SNUB
0.0022UF
CRITICAL
CRITICAL
C3918 1
20%
2.5V-ESR9V 2
POLY
CASE-D2E-LF
20%
20%
20%
2.5V-ESR9V 2
2.5V-ESR9V 2 2.5V-ESR9V 2
POLY
POLY
POLY
CASE-D2E-LF
CASE-D2E-LF
CASE-D2E-LF
20%
2.5V-ESR9V 2
POLY
CASE-D2E-LF
330uF
330uF
CRITICAL
1
330uF
CRITICAL
1
C3911
330uF
330uF
20%
1
CRITICAL
C3913
330uF
C3915
20%
2 2.5V-ESR9V
POLY
NO STUFF
C3901
CRITICAL
C3912 1 C3914 1 C3916 1
10%
50V
CERM 2
402
5%
1/16W
MF-LF
402
CRITICAL
C3910 1
330uF
SNM540XF
1 2 3
C3903 1
1 2 3
10
0.0012
L3900
Q3902
=PPVCORE_CPU_REG
R3900
SM1
CRITICAL
4
CRITICAL
1.0uH-20.5
VCORE_GND
VOLTAGE=0V
MIN_NECK_WIDTH=0.25 mm SM
VCORE_FB
VCORE_TIME
R3910
=VCORE_PGOOD 26
100 2
1
R39501
HAT2168H
1 2 3
5%
25V
CERM 2
402
CPUVCORE_VSENSE_R
Q3900
C3902
XW3910
220PF
20%
2 10V
CERM
603
1%
1/16W
MF-LF
402 2
19
XW3900
SM
C3951
20%
25V
2 CERM
603
VCORE_TON
20
10%
25V
2 X5R
1206
CRITICAL
10%
2 25V
CERM
402
VCORE_DH
REF
21
C3946
10uF
10%
25V
2 X5R
1206
10uF
10%
25V
2 X5R
1206
CRITICAL
1
CRITICAL
C3940
0.0047uF
5%
1/10W
MF-LF
603
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
R3951
VCORE_REF
MIN_LINE_WIDTH=0.25
MIN_NECK_WIDTH=0.15
MIN_LINE_WIDTH=0.25
MIN_NECK_WIDTH=0.15
MIN_LINE_WIDTH=0.25
MIN_NECK_WIDTH=0.15
MIN_LINE_WIDTH=0.25
MIN_NECK_WIDTH=0.15
MIN_LINE_WIDTH=0.25
MIN_NECK_WIDTH=0.15
10uF
NO STUFF
(VCORE_VPLUS)
5%
1/16W
MF-LF
2 402
C3945
MIN_LINE_WIDTH=0.5 mm 4
CRITICAL
10uF
CRITICAL
1
(VCORE_SNS)
VCORE_ILIM
=PP3V3_PWRON_CPUVCORE_VID
VDD
QSOP-LF
5
C3939
10%
25V
2 X5R
1206
CRITICAL
C3944
10%
25V
2 X5R
1206
MAX1717
2
CRITICAL
1
1%
1/16W
MF-LF
402 2
2 3
U3900
20%
10V
CERM 2
603
CPU_VCORE_2STATES
5%
1/16W
SM-LF
27.4K
7 6
15
VCC
1UF
5%
1/16W
MF-LF
402 2
R39621
36
RP3990
5%
1/16W
MF-LF
2 402
R39611 C3960
0
36
VCORE_VID<4>
VCORE_CPU0_SHDN_L
10uF
10uF
20%
2 10V
CERM
603
36
VCORE_VID<3>
26
B0530WXF
C3938
10%
25V
2 X5R
1206
CRITICAL
D3901
SOD-123
VCORE_BOOST
1%
1/16W
MF-LF
2 402
36 10
C3900
1UF
5%
1/16W
MF-LF
402 2
100K
20
R3965
10%
25V
2 X5R
1206
PLACE CLOSE TO
TO PINS 15 & 13
CRITICAL
C3937
10uF
=PP5V_PWRON_CPUVCORE_VDD
=PP5V_PWRON_CPUVCORE_PWRSEQ
VCORE_VID<2>
GND
36
CRITICAL
10
36
=PPVIN_CPUVCORE_MAX1717
1
10
VCORE_VID<1>
SYM_VER-2
R3990
Keep trace fat (1.00-2.54 mm) and short!!

10
C3990
20%
2 10V
CERM
402
VCC
Pullup on =CPU0_VID_AB_SEL
will set default mux state
to VID_B.
1.370V -> 0.940V
TABLE_5_ITEM
16
470K
5%
1/16W
MF-LF
2 402
36
1.340V -> 0.940V
TABLE_5_ITEM
NO STUFF
1
36
CPU0_VCORE_1V28
TABLE_5_ITEM
470K
VCORE_VID_A<1>
VCORE_VID_A<2>
VCORE_VID_A<3>
VCORE_VID_A<4>
(CPU SPEC: 1.220V -> 0.930V)
R3970 R3972 R3974 R3976
5%
1/16W
MF-LF
2 402
1.260V -> 0.940V

1.67GHZ
NO STUFF
470K
5%
1/16W
MF-LF
2 402
1.5GHZ
TABLE_5_ITEM
NO STUFF
(WITH VCORE OFFSET)

TABLE_5_ITEM
R3980 R3982 R3984 R3986
BOM OPTION
114S0270
"High" State
CPU_VCORE_3STATES
NO STUFF
36
36
TABLE_5_HEAD
QTY
=PP3V3_PWRON_CPUVCORE_VID
470K
PART#
330uF
20%
CRITICAL
1
C3917
330uF
20%
2 2.5V-ESR9V
2 2.5V-ESR9V
2 2.5V-ESR9V
POLY
POLY
POLY
CASE-D2E-LF
CASE-D2E-LF
CASE-D2E-LF
CASE-D2E-LF
0.0022uF
10%
50V
CERM 2
603
XW3911
SM
VCORE_GNDA
VCORE_OFFSET_SW
VCORE_OFFSET
R3943
10
=PP3V3_PWRON_CPUVCORE_OFFSET
OUTPUT VOLTAGE
VDAC D3 D2 D1 D0
36 11
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
NO CPU
NO CPU
Q3940
2N7002DW-X-F
1%
1/10W
MF-LF
2 603
Connect MAX1717 GND pin 13

to GND at bottom-side FET
This allows for an offset to the ground sense to adjust the output voltage.
VREF = 2.0V WITH A 0.85 SCALE FACTOR, HENCE VOFFSET = 1.7V * (R1/(R1+R2)) AND VCORE = VDAC + VOFFSET.
36
SOT-363
R3946
2.0K
1%
1/16W
MF-LF
2 402
PLACE THIS SHORT AT

PIN OF 1000uF CAP
CLOSEST TO CPU
R1
NOTE: R3945 (R2) NO STUFFED FOR NO OFFSET CASE
36
ROUTE AS DIFFERENTIAL PAIR
Q3940
2N7002DW-X-F
NO STUFF
R3942
OMIT
36
VCORE_GNDDIV
2.05K2
5%
1/16W
MF-LF
402 2
J3999
M-ST-SM-52465-1217
OMIT
R3999
<=
>=
>=
<=
D<4..0>
1K PU
100K PU
100K PD
1K PD
Hi/Fast
1
1
0
0
Lo/Slow
0
1
1
0
1%
1/16W
MF-LF
57
402
FOR V-STEP:
A/B_ =
VCORE_GNDSNS
100
2
25 24
30 25 24
VCORE_GNDDIV_TEST
VCORE_GNDSNS_TEST
SYS_RESET_BUTTON_L
SYS_POWER_BuTTON_L
NC (RFU)
When A/B_ is high (fast): D4-D0 read as-is

When A/B_ is low (slow): <=1K-ohm -> 0
>=100K-ohm -> 1
If all pull-ups are >=100K and all
pull-downs are <=1K, V A = V B .
CRITICAL
OMIT
1%
1/16W
MF-LF
402
100K
VCORE_GNDSNS
2
VOLTAGE=0V MIN_LINE_WIDTH=0.25 mm
VCORE_SNS
VOLTAGE=1.3V MIN_LINE_WIDTH=0.25 mm
FMAX CONNECTOR
R3998
SOT-363
36
XW3901
SM
4
6 VCORE_OFFSET_SW
5%
1/16W
MF-LF
402
GROUND SENSE VOLTAGE DIVIDER
R2
36
AB_SEL_LOW
162K
OMIT
3 VCORE_OFFSET_SW
R3941
1
R3945
VCORE_GNDDIV
VCORE_OFFSET_SW
VCORE_SEL_ON
6.04K
1%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
402
D4=0 D4=1
OMIT
R3944
5%
1/16W
MF-LF
402
NO STUFF
R3940
0
100K 2 VCORE_SEL_OFF_PU
VOLTAGE=0V
1
2
3
4
5
6
12
11
10
9
8
7
VCORE_VID<0>
VCORE_VID<1>
VCORE_VID<2>
VCORE_VID<3>
VCORE_VID<4>
CPU VCore Supply

36
SYNC_MASTER=N/A
SYNC_DATE=N/A
36
36
36

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
39
115
SHT
OF
NONE
CPU PLL POWER SUPPLY

R4600
10
=PPVIN_CPU0_AVDD
PPVIN_CPU0_AVDD
VOLTAGE=3.3V
CRITICAL
5%
1/16W
MF-LF
402
C4600 1
D4610
SOT23
2.2uF
10%
6.3V
CERM1
603-1
VOLTAGE=1.22V
PPVOUT_CPU0_AVDD_R
CRITICAL
CPU_AVDD_EN
100K 2
1%
1/16W
MF-LF
402
10%
2 16V
CERM
402
SOT23-6-LF
BAT54E3
FAN2558_EN_CPU0
NO STUFF
C4610
0.1UF
R4611
OMIT
1
R4621
=PPVOUT_CPU0_AVDD
10
5%
1/16W
MF-LF
402
FAN2558_ADJ_CPU0
357K
1%
1/16W
MF-LF
2 402
10
C4625
1UF
ADJ 5
GND
20%
10V
CERM 2
402
VOUT 6
VIN
4 PG
3 EN
1
C4620 R4620
24.9K
0.01UF
FAN2558
R4610
26
U4600
R4625
10%
2 6.3V
CERM
402
C4626
0.1UF
20%
2 10V
CERM
402
C4627
4.7UF
20%
6.3V
2 CERM
805
23.2K
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
AVDD=0.59*(1+R4620/R4621)
TABLE_5_HEAD
PART#
QTY
DESCRIPTION
BOM OPTION
TABLE_5_ITEM
114S0349
RES,23.2K,1%,1/16W,MF-LF,402,SMD
R4621
CPU0_AVDD_1V22
114S0346
RES,21.5K,1%,1/16W,MF-LF,402,SMD
R4621
CPU0_AVDD_1V28
114S0344
RES,20.5K,1%,1/16W,MF-LF,402,SMD
R4621
CPU0_AVDD_1V30
114S0342
RES,19.6K,1%,1/16W,MF-LF,402,SMD
R4621
CPU0_AVDD_1V33
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CPU AVDD Supply
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
46
115
SHT
OF
NONE
NET_TYPE
SPACING
PHYSICAL
RAM_CLK_0
RAM_DIFF
RAM_DIFF
RAM_CLK_0_R
RAM_CLK_0
RAM_DIFF
RAM_DIFF
RAM_CLK_0_R
RAM_CLK_1
RAM_DIFF
RAM_DIFF
RAM_CLK_1_R
RAM_CLK_1
RAM_DIFF
RAM_DIFF
RAM_CLK_1_R
RAM_CLK_2
RAM_DIFF
RAM_DIFF
RAM_CLK_2_R
RAM_CLK_2
RAM_DIFF
RAM_DIFF
RAM_CLK_2_R
RAM_CLK_3
RAM_DIFF
RAM_DIFF
RAM_CLK_3_R
RAM_CLK_3
RAM_DIFF
RAM_DIFF
RAM_CLK_3_R
OMIT
DIFFERENTIAL_PAIR
RAM_CLKDDR_0_P_R
RAM_CLKDDR_0_N_R
U2100
38 39
I2
38 39
DDR2 I/O DECOUPLING
RAM_CLKDDR_1_P_R
RAM_CLKDDR_1_N_R
38 39
10
RAM_CKE_0
RAM
RAM
RAM_CKE_1
RAM
RAM
RAM_CS_0
RAM
RAM
RAM_CS_1
RAM
RAM
RAM_ADDR_CTL
RAM
RAM_ADDR_CTL
RAM
RAM
RAM_ADDR_CTL
RAM
RAM
RAM_ADDR_CTL
RAM_ADDR_CTL
RAM_ODT0
RAM
RAM
RAM
RAM_ODT1
RAM
RAM_CLKDDR_2_P_R
RAM_CLKDDR_2_N_R
RAM
AA26
38 39
38 39
RAM
RAM
RAM_DQS1
RAM
RAM
RAM_DQS2
RAM
RAM
RAM_DQS3
RAM
RAM
RAM_DQS4
RAM
RAM
RAM_DQS5
RAM
RAM
RAM_DQS6
RAM
RAM
RAM_DQS7
RAM
RAM
RAM_DQM0
RAM
RAM_DQM1
RAM
RAM_DQM2
RAM
RAM_DQM3
RAM
RAM_DQM4
RAM
RAM_DQM5
RAM
RAM_DQM6
RAM
RAM_DQM7
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM_DATA_0
RAM
RAM
RAM_DATA_1
RAM
RAM
RAM_DATA_2
RAM
RAM
RAM_DATA_3
RAM
RAM
RAM_DATA_4
RAM
RAM
RAM_DATA_5
RAM
RAM
RAM_DATA_6
RAM
RAM
RAM_DATA_7
RAM
RAM
1uF
AB26
20%
6.3V
X5R
603
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C4751
C4752
C4753
AC24
AC27
AC31
OMIT
AC34
1
I2
BGA
38 39
C4755
1uF
38 39
MEMORY INTERFACE
10%
6.3V
CERM
402
C4756
1uF
2
10%
6.3V
CERM
402
C4757
1uF
2
C4758
1uF
10%
6.3V
CERM
402
C4759
AD24
1uF
10%
6.3V
CERM
402
AD28
10%
6.3V
CERM
402
AF28
AF31
38 39
38 39
39 38
BI
(7 of 14)
RAM_DATA_R<63..0>
AK31
38 39
AK32
1
38 39
AL33
38 39
AH31
38 39
38 39
38 39
38 39
38 39
38 39
38 39
10
38 39
11
AK34
AK33
AK35
AK36
AF36
AG36
AG35
AG34
AG33
12
38 39
AH36
13
38 39
AH35
14
38 39
AH34
15
38 39
AE33
16
38 39
AE34
17
38 39
AE35
18
38 39
AD33
19
38 39
AE36
20
RAM_DATA_R<7..0>
RAM_DATA_R<15..8>
RAM_DATA_R<23..16>
RAM_DATA_R<31..24>
RAM_DATA_R<39..32>
RAM_DATA_R<47..40>
RAM_DATA_R<55..48>
RAM_DATA_R<63..56>
38 39
21
38 39
22
38 39
23
38 39
24
38 39
25
38 39
26
38 39
27
38 39
28
AD34
AD35
AD36
Y36
AA36
AA35
AA34
AA33
AA32
29
AB36
30
Page Notes
AB34
31
M36
32

- =PP1V8_PWRON_I2_RAM
- =PP1V8_RAM_I2_VREF
M35
33
M34
34
M33
35

(NONE)
M32
36
L36
37
M31
38

(NONE)
M30
39
K32
40
H36
41
J36
42
J33
43
J34
44
J35
45
K33
46
K34
47
G34
48
F36
49
F35
50
G33
51
F34
52
G32
53
E36
54
F33
55
A32
56
A34
57
10
F30
58
=PP1V8_RAM_I2_VREF
B33
59
R4700
C33
60
D33
61
1K
1%
1/16W
MF-LF
402 2
D34
62
D35
63
AG28
I2_MEM_VREF
Y21
R4701 1
1K
1%
1/16W
MF-LF
402
1uF
U2100
38 39
RAM_DQM_R<0>
RAM_DQM_R<1>
RAM_DQM_R<2>
RAM_DQM_R<3>
RAM_DQM_R<4>
RAM_DQM_R<5>
RAM_DQM_R<6>
RAM_DQM_R<7>
RAM
1uF
C4750
38 39
RAM_DQS_P_R<0>
RAM_DQS_P_R<1>
RAM_DQS_P_R<2>
RAM_DQS_P_R<3>
RAM_DQS_P_R<4>
RAM_DQS_P_R<5>
RAM_DQS_P_R<6>
RAM_DQS_P_R<7>
RAM
AA28
1uF
AC28
RAM_DQS0
C4754
1uF
38 39
RAM_ADDR_R<13..0>
RAM_BA_R<2..0>
RAM_RAS_L_R
RAM_CAS_L_R
RAM_WE_L_R
RAM_ODT_R<0>
RAM_ODT_R<1>
RAM
AA24
10UF
C4749
38 39
RAM_CS_L_R<1..0>
RAM_CS_L_R<3..2>
RAM
DDR2 POWER
1 X 10uF (0603)
40 X 1uF (0402)
38 39
RAM_CKE_R<1..0>
RAM_CKE_R<3..2>
RAM
(40 Balls on I2)
=PP1V8_PWRON_I2_RAM
38 39
RAM_CLKDDR_3_P_R
RAM_CLKDDR_3_N_R
RAM
BGA
38 39
2
2
C4706
V21
0.1UF
0.1UF
T21
20%
10V
CERM
402
20%
10V
CERM
402
C4705
U2100.AG28
DDR_D_00_H
DDR_D_01_H
DDR_D_02_H
DDR_D_03_H
DDR_D_04_H
DDR_D_05_H
DDR_D_06_H
DDR_D_07_H
DDR_D_08_H
DDR_D_09_H
DDR_D_10_H
DDR_D_11_H
DDR_D_12_H
DDR_D_13_H
DDR_D_14_H
DDR_D_15_H
DDR_D_16_H
DDR_D_17_H
DDR_D_18_H
DDR_D_19_H
DDR_D_20_H
DDR_D_21_H
DDR_D_22_H
DDR_D_23_H
DDR_D_24_H
DDR_D_25_H
DDR_D_26_H
DDR_D_27_H
DDR_D_28_H
DDR_D_29_H
DDR_D_30_H
DDR_D_31_H
DDR_D_32_H
DDR_D_33_H
DDR_D_34_H
DDR_D_35_H
DDR_D_36_H
DDR_D_37_H
DDR_D_38_H
DDR_D_39_H
DDR_D_40_H
DDR_D_41_H
DDR_D_42_H
DDR_D_43_H
DDR_D_44_H
DDR_D_45_H
DDR_D_46_H
DDR_D_47_H
DDR_D_48_H
DDR_D_49_H
DDR_D_50_H
DDR_D_51_H
DDR_D_52_H
DDR_D_53_H
DDR_D_54_H
DDR_D_55_H
DDR_D_56_H
DDR_D_57_H
DDR_D_58_H
DDR_D_59_H
DDR_D_60_H
DDR_D_61_H
DDR_D_62_H
DDR_D_63_H
DDR_VREF_0_H
DDR_VREF_1_H
DDR_VREF_2_H
DDR_VREF_3_H
DDR_A_00_H
DDR_A_01_H
DDR_A_02_H
DDR_A_03_H
DDR_A_04_H
DDR_A_05_H
DDR_A_06_H
DDR_A_07_H
DDR_A_08_H
DDR_A_09_H
DDR_A_10_H
DDR_A_11_H
DDR_A_12_H
DDR_A_13_H
DDR_BA_0_H
DDR_BA_1_H
DDR_BA_2_H
RAM_ADDR_R<13..0>
R33
OUT
AF34
38 39
AJ31
R34
1
R35
T32
R36
4
T33
AJ34
1uF
1uF
1uF
1uF
AM34
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
T34
DDR_DM_0_L
DDR_DM_1_L
DDR_DM_2_L
DDR_DM_3_L
DDR_DM_4_L
DDR_DM_5_L
DDR_DM_6_L
DDR_DM_7_L
DDR_RAS_L
DDR_CAS_L
DDR_WE_L
DDR_CKE_0_L
DDR_CKE_1_L
DDR_CKE_2_L
DDR_CKE_3_L
C4762
C4763
AP34
C34
E34
H31
T36
7
T35
H34
1
U36
P36
10
V32
11
C4765
C4766
C4767
C4768
C4769
1uF
1uF
1uF
1uF
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
K28
L28
L31
L34
V33
12
N32
M25
13
RAM_BA_R<2..0>
N36
OUT
N26
38 39
R32
1
V34
RAM_CS_L_R<3..0>
AM36
OUT
38 39
C4770
C4771
C4772
C4773
C4774
P28
P31
1uF
1uF
1uF
1uF
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
P34
R24
AL31
R26
AL35
R28
AL32
T25
1
C4775
1uF
DDR_DQS_0_L
DDR_DQS_1_L
DDR_DQS_2_L
DDR_DQS_3_L
DDR_DQS_4_L
DDR_DQS_5_L
DDR_DQS_6_L
DDR_DQS_7_L
C4761
DDR_CS_0_L
DDR_CS_1_L
DDR_CS_2_L
DDR_CS_3_L
C4764
1uF
C4760
RAM_DQS_P_R<7..0>
AH30
BI
38 39
AG32
AD32
10%
6.3V
CERM
402
C4776
1uF
2
10%
6.3V
CERM
402
C4777
1uF
2
C4778
1uF
10%
6.3V
CERM
402
C4779
U24
1uF
10%
6.3V
CERM
402
U27
10%
6.3V
CERM
402
U29
U31
U34
AB33
3
M29
V25
1
J32
G35
6
E31
RAM_DQM_R<7..0>
AJ36
AH33
OUT
C4784
V26
1uF
1uF
1uF
1uF
1uF
V29
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C4780
C4781
C4782
C4783
W24
Y25
Y28
38 39
Y31
Y34
AE32
AB35
C4786
C4787
C4788
C4789
1uF
1uF
1uF
1uF
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C4790
C4791
C4792
C4794
N28
C4785
K35
(8 of 14)
VTT18_0
VTT18_1
VTT18_2
VTT18_3
VTT18_4
VTT18_5
VTT18_6
VTT18_7
VTT18_8
VTT18_9
VTT18_10
VTT18_11
VTT18_12
VTT18_13
VTT18_14
VTT18_15
VTT18_16
VTT18_17
VTT18_18
VTT18_19
VTT18_20
VTT18_21
VTT18_22
VTT18_23
VTT18_24
VTT18_25
VTT18_26
VTT18_27
VTT18_28
VTT18_29
VTT18_30
VTT18_31
VTT18_32
VTT18_33
VTT18_34
VTT18_35
VTT18_36
VTT18_37
VTT18_38
VTT18_39
VTT18_40
VTT18_41
VTT18_42
VTT18_43
VTT18_44
VTT18_45
VTT18_46
VTT18_47
C36
N35
RAM_RAS_L_R
RAM_CAS_L_R
RAM_WE_L_R
N33
N34
RAM_CKE_R<3..0>
AN35
OUT
38 39
OUT
38 39
OUT
38 39
OUT
38 39
1uF
2
10%
6.3V
CERM
402
1uF
2
10%
6.3V
CERM
402
1uF
2
C4793
1uF
10%
6.3V
CERM
402
C4795
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
AL36
AP36
AL34
3
ODT0
ODT1
J31
DDR_MCLK_0_P
DDR_MCLK_0_N
W31
DDR_MCLK_1_P
DDR_MCLK_1_N
V36
DDR_MCLK_2_P
DDR_MCLK_2_N
W29
DDR_MCLK_3_P
DDR_MCLK_3_N
W35
AB30
W30
V35
W28
W34
RAM_ODT_R<0>
RAM_ODT_R<1>
OUT
38 39
OUT
38 39
RAM_CLKDDR_0_P_R
RAM_CLKDDR_0_N_R
OUT
38 39
OUT
38 39
RAM_CLKDDR_1_P_R
RAM_CLKDDR_1_N_R
OUT
38 39
OUT
38 39
RAM_CLKDDR_2_P_R
RAM_CLKDDR_2_N_R
OUT
38 39
OUT
38 39
RAM_CLKDDR_3_P_R
RAM_CLKDDR_3_N_R
OUT
38 39
OUT
38 39
C4796
1uF
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C4797
1uF
10%
6.3V
CERM
402
I2 Memory Interface
AC22

SD_REF_H
R4710
1K
SYNC_DATE=N/A
U2100.V21
I2_SD_REF
1%
1/16W
MF-LF
402
SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
47
115
SHT
OF
NONE
F32
SYNC_MASTER=N/A
Main Memory Series Termination

SERIES RESISTORS FOR CONTROL SIGNALS
SERIES RESISTORS FOR CLOCKS
PINS ARE SWAPPABLE FOR RPAKS RP4800-RP4804

RP4800
38
38
38
38
RAM_ADDR_R<0>
RAM_ADDR<0>
5%
1/16W
SM-LF
RP4803
RP4803
5%
1/16W
SM-LF
RAM_ADDR_R<1>
4
RAM_ADDR_R<2>
22
22
RP4803
38
RAM_ADDR_R<4>
38
RAM_ADDR_R<5>
38
RAM_ADDR_R<6>
22
38
38
38
RAM_ADDR_R<10>
38
38
38
RAM_ADDR_R<12>
22
RP4801
5%
1/16W
SM-LF
39 40 41
RAM_ADDR<6>
39 40 41
22
22
IN
38
39 40 41
IN
38
IN
39 40 41
RAM_ADDR<9>
39 40 41
RAM_ADDR<10>
39 40 41
RAM_ADDR<11>
39 40 41
RAM_ADDR<12>
39 40 41
RAM_ADDR<13>
R4855
5%
1/16W
MF-LF
402
IN
RAM_CLKDDR_3_N_R
R4860
5%
1/16W
MF-LF
402
22
RAM_BA_R<0>
R4865
5%
1/16W
MF-LF
402
22
38
RAM_BA_R<1>
38
RAM_BA_R<2>
RAM_BA<0>
RP4801
1
22
22
5%
1/16W
SM-LF
RP4804
38
38
RAM_CAS_L_R
22
22
38
IN
38
IN
39 40 41
39 40
RAM_CLKDDR_1_P
OUT
39 40
RAM_CLKDDR_1_N
OUT
39 40
RAM_CLKDDR_2_P
OUT
39 41
RAM_CLKDDR_2_N
OUT
39 41
RAM_CLKDDR_3_P
OUT
39 41
RAM_CLKDDR_3_N
OUT
39 41
RAM_CS_L_R<0>
RAM_CS_L_R<2>
RAM_CS_L<0>
RAM_CS_L<2>
OUT
39 40
OUT
39 41
38
IN
38
IN
39 40 41
RAM_BA<1>
39 40 41
RAM_BA<2>
39 40 41
22
RAM_CS_L_R<1>
RAM_CS_L_R<3>
RAM_CS_L<1>
RAM_CS_L<3>
OUT
39 40
OUT
39 41
RAM_CKE<0>
RAM_CKE<2>
OUT
39 40
OUT
39 41
RAM_CKE<1>
RAM_CKE<3>
OUT
39 40
OUT
39 41
5%
1/16W
SM-LF
38
IN
38
IN
22
RAM_CKE_R<0>
RAM_CKE_R<2>
3
5%
1/16W
SM-LF
RAM_RAS_L
RP4876
39 40 41
38
RAM_CAS_L
39 40 41
IN
38
IN
22
RAM_CKE_R<1>
RAM_CKE_R<3>
RAM_WE_L
3
5%
1/16W
SM-LF
39 40 41
38
RAM_DATA_R<63..0>
39
RAM_DATA<63..0>
MAKE_BASE=TRUE
RAM_DATA_A<63..0>
RAM_DATA_B<63..0>
R4810
38
38
RAM_ODT_R<0>
RAM_ODT_R<1>
RAM_ODT<0>
5%
1/16W
MF-LF
402
39 40
38
RAM_DQM_R<7..0>
RAM_DQM<7..0>
MAKE_BASE=TRUE
39
R4811
1
5%
1/16W
SM-LF
5%
1/16W
SM-LF
22
22
RP4804
2
OUT
RP4875
5%
1/16W
SM-LF
5%
1/16W
SM-LF
RAM_WE_L_R
22
RAM_CLKDDR_0_N
R4866
RP4804
RAM_RAS_L_R
39 40
RP4870
5%
1/16W
SM-LF
38
OUT
SERIES RESISTORS FOR CS / CKE

Do not swap with other RPAKs
RP4800
4
5%
1/16W
MF-LF
402
22
RAM_CLKDDR_0_P
RP4871
5%
1/16W
SM-LF
R4861
RP4800
38
22
5%
1/16W
MF-LF
402
5%
1/16W
SM-LF
22
R4856
RAM_CLKDDR_2_N_R
RAM_CLKDDR_3_P_R
22
22
5%
1/16W
MF-LF
402
RAM_CLKDDR_1_N_R
RAM_CLKDDR_2_P_R
R4851
RAM_CLKDDR_0_N_R
RAM_CLKDDR_1_P_R
22
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
RP4804
5%
1/16W
SM-LF
RAM_ADDR_R<13>
RAM_ADDR<5>
IN
38
RP4801
22
39 40 41
RAM_ADDR<7>
5%
1/16W
SM-LF
IN
RAM_CLKDDR_0_P_R
39 40 41
RAM_ADDR<4>
RAM_ADDR<8>
5%
1/16W
SM-LF
RAM_ADDR_R<11>
39 40 41
RP4802
RP4800
22
22
IN
38
5%
1/16W
SM-LF
38
38
RP4802
22
RAM_ADDR<3>
5%
1/16W
SM-LF
5%
1/16W
SM-LF
RAM_ADDR_R<9>
22
IN
38
RP4802
38
22
5%
1/16W
SM-LF
RAM_ADDR_R<7>
RAM_ADDR_R<8>
RAM_ADDR<2>
39 40 41
RP4801
RP4802
22
RAM_ADDR<1>
5%
1/16W
SM-LF
5%
1/16W
SM-LF
RP4803
5%
1/16W
SM-LF
RAM_ADDR_R<3>
22
R4850
38
39 40 41
RAM_ODT<1>
RAM_DQM_A<7..0>
RAM_DQM_B<7..0>
40
41
40
41
39 41
5%
1/16W
MF-LF
402
38
RAM_DQS_P_R<7..0>
RP4872
2
7
10K
3
4
5%
1/16W
SM-LF
6
5
39
RAM_DQS<7..0>
MAKE_BASE=TRUE
RAM_DQS_A_N<3>
RAM_DQS_B_N<3>
RAM_DQS_A_N<2>
RAM_DQS_B_N<2>
40
41
40
41
RAM_DQS_A_P<7..0>
RAM_DQS_B_P<7..0>
RP4877
2
7
10K
3
4
5%
1/16W
SM-LF
6
5
40
41
RAM_DQS_B_N<1>
RAM_DQS_A_N<1>
RAM_DQS_A_N<0>
RAM_DQS_B_N<0>
41
40
40
41
NET_TYPE
SPACING
PHYSICAL
I196
RAM_DIFF
RAM_DIFF
RAM_CLK_0
I194
RAM_DIFF
RAM_DIFF
RAM_CLK_0
RP4873
7
10K
DIFFERENTIAL_PAIR
I193
I197
I199
I198
I200
I205
I204
I203
I202
I201
I208
I207
memory controller.
I195
ECSETs provided by
RAM_DIFF
RAM_DIFF
RAM_CLK_1
RAM_DIFF
RAM_DIFF
RAM_CLK_1
RAM_DIFF
RAM_DIFF
RAM_CLK_2
RAM_DIFF
RAM_DIFF
RAM_CLK_2
RAM_DIFF
RAM_DIFF
RAM_CLK_3
RAM_DIFF
RAM_DIFF
RAM_CLK_4
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
I209
RAM
RAM
I206
RAM
RAM
I210
RAM
RAM
I259
RAM_CLKDDR_0_P
RAM_CLKDDR_0_N
RAM_CLKDDR_1_P
RAM_CLKDDR_1_N
RAM_CLKDDR_2_P
RAM_CLKDDR_2_N
RAM_CLKDDR_3_P
RAM_CLKDDR_3_N
RAM_CKE<3..0>
RAM_CS_L<3..0>
RAM_ADDR<13..0>
RAM_BA<2..0>
RAM_RAS_L
RAM_CAS_L
RAM_WE_L
RAM_ODT<1..0>
39 40
39 40
5%
1/16W
SM-LF
6
5
RAM_DQS_B_N<5>
RAM_DQS_A_N<5>
RAM_DQS_B_N<4>
RAM_DQS_A_N<4>
41
40
41
40
RP4878
7
10K
2
3
4
5%
1/16W
SM-LF
6
5
RAM_DQS_B_N<7>
RAM_DQS_A_N<7>
RAM_DQS_B_N<6>
RAM_DQS_A_N<6>
41
40
41
40
39 40
39 40
39 41
39 41
Memory Series Termination
39 41
39 41
SYNC_MASTER=N/A
SYNC_DATE=N/A
39 40 41
39 40 41
39 40 41

39 40 41
39 40 41

39 40 41

39 40 41

39 40 41
SIZE
RAM_DQS<7..0>
RAM_DQM<7..0>
RAM_DATA<63..0>
39
APPLE COMPUTER INC.
39
D
SCALE
39
DRAWING NUMBER
REV.
C
051-6929
48
115
SHT
OF
NONE
40
403
=PP1V8_PWRON_DDR2
1A
=RAM_VREF_A
3A
39
39
5A
RAM_DATA_A<1>
RAM_DATA_A<2>
7A
9A
39
39
11A
RAM_DQS_A_N<0>
RAM_DQS_A_P<0>
13A
15A
39
39
17A
RAM_DATA_A<6>
RAM_DATA_A<7>
19A
21A
39
39
23A
RAM_DATA_A<14>
RAM_DATA_A<13>
25A
27A
39
39
29A
RAM_DQS_A_N<1>
RAM_DQS_A_P<1>
31A
33A
39
39
35A
RAM_DATA_A<10>
RAM_DATA_A<8>
37A
39A
41A
39
39
43A
RAM_DATA_A<17>
RAM_DATA_A<16>
45A
47A
39
39
49A
RAM_DQS_A_N<2>
RAM_DQS_A_P<2>
51A
53A
39
39
55A
RAM_DATA_A<22>
RAM_DATA_A<19>
57A
59A
39
39
61A
RAM_DATA_A<26>
RAM_DATA_A<25>
63A
65A
39
67A
RAM_DQM_A<3>
69A
NC
71A
SLOT "A"
LOWER SLOT
FACTORY SLOT
39
39
73A
RAM_DATA_A<27>
RAM_DATA_A<29>
75A
77A
39
79A
RAM_CKE<0>
81A
83A
NC
41 39
85A
RAM_BA<2>
87A
41 39
41 39
41 39
89A
RAM_ADDR<12>
RAM_ADDR<9>
RAM_ADDR<8>
91A
93A
95A
41 39
41 39
41 39
97A
RAM_ADDR<5>
RAM_ADDR<3>
RAM_ADDR<1>
99A
101A
103A
41 39
41 39
41 39
105A
RAM_ADDR<10>
RAM_BA<0>
RAM_WE_L
107A
109A
111A
41 39
39
113A
RAM_CAS_L
RAM_CS_L<1>
115A
117A
(ODT<1>)
119A
121A
39
39
123A
RAM_DATA_A<36>
RAM_DATA_A<35>
125A
127A
39
39
129A
RAM_DQS_A_N<4>
RAM_DQS_A_P<4>
131A
133A
39
39
135A
RAM_DATA_A<34>
RAM_DATA_A<37>
137A
139A
39
39
141A
RAM_DATA_A<47>
RAM_DATA_A<43>
143A
145A
41 40 10
DDR2 VREF
=PP1V8_PWRON_DDR2
1
R5001
39
149A
ADD ONE 0.1UF PER SLOT
39
1K
39
1%
1/16W
MF-LF
2 402
147A
RAM_DQM_A<5>
151A
RAM_DATA_A<42>
RAM_DATA_A<41>
153A
155A
39
RAM_VREF
MAKE_BASE=TRUE
R5002
39
=RAM_VREF_A
40
=RAM_VREF_B
41
157A
RAM_DATA_A<51>
RAM_DATA_A<49>
159A
161A
NC
163A
165A
1K
1%
1/16W
MF-LF
2 402
39
39
RAM_DQS_A_N<6>
RAM_DQS_A_P<6>
167A
169A
171A
39
39
RAM_DATA_A<52>
RAM_DATA_A<55>
173A
175A
177A
39
39
RAM_DATA_A<63>
RAM_DATA_A<61>
179A
181A
183A
39
RAM_DQM_A<7>
185A
187A
39
39
RAM_DATA_A<59>
RAM_DATA_A<56>
189A
191A
193A
41 8
41 8
41 10
=I2C_SODIMM_SDA
=I2C_SODIMM_SCL
=PP3V3_PWRON_VDDSPD
195A
197A
199A
VREF
VSS1
DQ0
DQ1
VSS0
CRITICAL
J5000
VSS4
F-RT-SM
(2 OF 2)
DQS0*
DQS0
VSS6
DQ2
DQ3
VSS8
DQ8
DQ9
VSS10
DQS1*
=PP1V8_PWRON_DDR2
NC
DQ4
DQ5
VSS2
DM0
VSS5
DQ6
DQ7
VSS7
DQ12
DQ13
VSS9
DM1
VSS11
CK0
DQS1
CK0*
VSS12
DQ10
VSS13
DQ14
DQ11
VSS14
DQ15
VSS15
KEY
VSS16
VSS17
DQ16
DQ20
DQ17
VSS18
DQ21
VSS19
DQS2*
NC0
DQS2
VSS21
DM2
VSS22
DQ18
DQ22
DQ19
VSS23
DQ23
VSS24
DQ24
DQ25
DQ28
DQ29
VSS25
VSS26
DM3
NC1
DQS3*
DQS3
VSS27
VSS28
DQ30
DQ31
DQ26
DQ27
VSS29
CKE0
VDD0
VSS30
NC/CKE1
VDD1
NC2
BA2
NC/A15
NC/A14
VDD2
VDD3
A12
A9
A11
A7
A8
A6
VDD4
A5
VDD5
A4
A3
A2
A1
VDD6
A0
VDD7
A10/AP
BA0
BA1
RAS*
S0*
WE*
VDD8
CAS*
VDD9
ODT0
NC/S1*
NC/A13
VDD10
NC/ODT1
VDD11
NC3
VSS31
VSS32
DQ32
DQ33
DQ36
DQ37
VSS33
DQS4*
VSS34
DM4
DQS4
VSS35
VSS36
DQ34
DQ38
DQ39
DQ35
VSS37
VSS38
DQ40
DQ44
DQ45
DQ41
VSS39
VSS40
DM5
DQS5*
DQS5
VSS41
DQ42
VSS42
DQ46
DQ47
DQ43
VSS43
DQ48
VSS44
DQ52
DQ49
DQ53
VSS45
NC_TEST
VSS46
CK1
VSS47
CK1*
DQS6*
DQS6
VSS48
DM6
VSS49
DQ50
VSS50
DQ54
DQ51
DQ55
VSS51
DQ56
VSS52
DQ60
DQ57
DQ61
VSS53
DM7
VSS54
DQS7*
VSS55
DQS7
DQ58
DQ59
VSS56
DQ62
VSS57
SDA
DQ63
VSS58
SCL
SA0
VDDSPD
SA1
404
5
41 40 10
DDR2-SODIMM-DUAL
10 40 41
2A
4A
RAM_DATA_A<0>
RAM_DATA_A<3>
6A
39
39
8A
10A
RAM_DQM_A<0>
39
12A
14A
RAM_DATA_A<5>
RAM_DATA_A<4>
16A
39
39
18A
20A
RAM_DATA_A<15>
RAM_DATA_A<12>
22A
39
39
24A
26A
RAM_DQM_A<1>
DDR2 VREF
39
28A
30A
RAM_CLKDDR_0_P
RAM_CLKDDR_0_N
32A
ONE 0.1UF PER SLOT
39
39
34A
36A
RAM_DATA_A<9>
RAM_DATA_A<11>
38A
39
=RAM_VREF_A
40
39
40A
C5001
0.1uF
42A
44A
RAM_DATA_A<18>
RAM_DATA_A<20>
46A
20%
10V
2 CERM
402
39
39
48A
50A
NC
52A
RAM_DQM_A<2>
39
RAM_DATA_A<23>
RAM_DATA_A<21>
39
54A
56A
58A
39
60A
62A
RAM_DATA_A<31>
RAM_DATA_A<30>
64A
39
39
DDR2 BYPASS
SLOT "A"
66A
68A
RAM_DQS_A_N<3>
RAM_DQS_A_P<3>
70A
39
39
72A
74A
76A
RAM_DATA_A<24>
RAM_DATA_A<28>
39
RAM_CKE<1>
39
39
41 40 10
=PP1V8_PWRON_DDR2
78A
80A
82A
84A
86A
20%
2 6.3V
X5R
603
88A
90A
RAM_ADDR<11>
RAM_ADDR<7>
RAM_ADDR<6>
92A
94A
C5008
10UF
NC
NC
100A
102A
10UF
39 41
39 41
C5010
0.1uF
RAM_ADDR<4>
RAM_ADDR<2>
RAM_ADDR<0>
C5009
20%
6.3V
2 X5R
603
39 41
96A
98A
20%
2 10V
CERM
402
39 41
39 41
C5011
0.1uF
C5012
0.1uF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C5013
0.1uF
20%
2 10V
CERM
402
C5014
0.1uF
20%
2 10V
CERM
402
39 41
104A
106A
RAM_BA<1>
RAM_RAS_L
RAM_CS_L<0>
108A
110A
39 41
39 41
114A
RAM_ODT<0>
RAM_ADDR<13>
116A
C5015
0.1uF
39
20%
2 10V
CERM
402
112A
39
C5016
0.1uF
20%
2 10V
CERM
402
C5017
0.1uF
20%
2 10V
CERM
402
C5018
0.1uF
20%
2 10V
CERM
402
C5019
0.1uF
20%
2 10V
CERM
402
39 41
118A
120A
NC
122A
124A
126A
C5020
0.1uF
RAM_DATA_A<39>
RAM_DATA_A<38>
20%
2 10V
CERM
402
39
39
C5021
0.1uF
20%
2 10V
CERM
402
C5022
0.1uF
20%
2 10V
CERM
402
C5023
0.1uF
20%
2 10V
CERM
402
128A
130A
RAM_DQM_A<4>
Distribute C502x caps along connector
39
132A
134A
136A
RAM_DATA_A<33>
RAM_DATA_A<32>
39
39
138A
140A
142A
RAM_DATA_A<40>
RAM_DATA_A<46>
39
39
144A
146A
148A
RAM_DQS_A_N<5>
RAM_DQS_A_P<5>
39
39
150A
152A
154A
RAM_DATA_A<45>
RAM_DATA_A<44>
39
39
156A
158A
160A
RAM_DATA_A<53>
RAM_DATA_A<48>
39
39
162A
164A
166A
RAM_CLKDDR_1_P
RAM_CLKDDR_1_N
39
39
168A
170A
RAM_DQM_A<6>
39
172A
174A
176A
RAM_DATA_A<50>
RAM_DATA_A<54>
39
DDR2 SO-DIMM Slot A
39
178A
180A
182A
RAM_DATA_A<58>
RAM_DATA_A<62>
SYNC_MASTER=N/A
SYNC_DATE=N/A
39
39
184A
186A
188A
RAM_DQS_A_N<7>
RAM_DQS_A_P<7>

39
39
190A
192A
194A
RAM_DATA_A<57>
RAM_DATA_A<60>

39

39
196A
SIZE
198A
200A
ADDR=0XA0(WR)/0XA1(RD)
APPLE COMPUTER INC.
D
SCALE
NC
DRAWING NUMBER
REV.
C
051-6929
50
115
SHT
OF
NONE
6
41 40
401
=PP1V8_PWRON_DDR2
1B
=RAM_VREF_B
3B
39
39
5B
RAM_DATA_B<1>
RAM_DATA_B<2>
7B
9B
39
39
11B
RAM_DQS_B_N<0>
RAM_DQS_B_P<0>
13B
15B
39
39
17B
RAM_DATA_B<6>
RAM_DATA_B<7>
19B
21B
39
39
23B
RAM_DATA_B<14>
RAM_DATA_B<13>
25B
27B
39
39
29B
RAM_DQS_B_N<1>
RAM_DQS_B_P<1>
31B
33B
39
39
35B
RAM_DATA_B<10>
RAM_DATA_B<8>
37B
39B
41B
39
39
43B
RAM_DATA_B<17>
RAM_DATA_B<16>
45B
47B
39
39
49B
RAM_DQS_B_N<2>
RAM_DQS_B_P<2>
51B
53B
39
39
55B
RAM_DATA_B<22>
RAM_DATA_B<19>
57B
59B
39
39
61B
RAM_DATA_B<26>
RAM_DATA_B<25>
63B
65B
39
67B
RAM_DQM_B<3>
69B
NC
71B
SLOT "B"
UPPER SLOT
CUSTOMER SLOT
39
39
73B
RAM_DATA_B<27>
RAM_DATA_B<29>
75B
77B
39
79B
RAM_CKE<2>
81B
83B
NC
40 39
85B
RAM_BA<2>
87B
40 39
40 39
40 39
89B
RAM_ADDR<12>
RAM_ADDR<9>
RAM_ADDR<8>
91B
93B
95B
40 39
40 39
40 39
97B
RAM_ADDR<5>
RAM_ADDR<3>
RAM_ADDR<1>
99B
101B
103B
40 39
40 39
40 39
105B
RAM_ADDR<10>
RAM_BA<0>
RAM_WE_L
107B
109B
111B
40 39
39
113B
RAM_CAS_L
RAM_CS_L<3>
115B
117B
(ODT<1>)
119B
121B
39
39
123B
RAM_DATA_B<36>
RAM_DATA_B<35>
125B
127B
39
39
129B
RAM_DQS_B_N<4>
RAM_DQS_B_P<4>
131B
133B
39
39
135B
RAM_DATA_B<34>
RAM_DATA_B<37>
137B
139B
39
39
141B
RAM_DATA_B<47>
RAM_DATA_B<43>
143B
145B
39
147B
RAM_DQM_B<5>
149B
39
39
151B
RAM_DATA_B<42>
RAM_DATA_B<41>
153B
155B
39
39
157B
RAM_DATA_B<51>
RAM_DATA_B<49>
159B
161B
NC
163B
165B
39
39
RAM_DQS_B_N<6>
RAM_DQS_B_P<6>
167B
169B
171B
39
39
RAM_DATA_B<52>
RAM_DATA_B<55>
173B
175B
177B
39
39
RAM_DATA_B<63>
RAM_DATA_B<61>
179B
181B
183B
39
RAM_DQM_B<7>
185B
187B
39
39
RAM_DATA_B<59>
RAM_DATA_B<56>
189B
191B
193B
40 8
40 8
41 40 10
=I2C_SODIMM_SDA
=I2C_SODIMM_SCL
=PP3V3_PWRON_VDDSPD
195B
197B
199B
VREF
VSS1
DQ0
DQ1
VSS0
CRITICAL
J5000
VSS4
F-RT-SM
(1 OF 2)
DQS0*
DQS0
VSS6
DQ2
DQ3
VSS8
DQ8
DQ9
VSS10
DQS1*
=PP1V8_PWRON_DDR2
NC
DQ4
DQ5
VSS2
DM0
VSS5
DQ6
DQ7
VSS7
DQ12
DQ13
VSS9
DM1
VSS11
CK0
CK0*
DQS1
VSS12
DQ10
VSS13
DQ14
DQ11
VSS14
DQ15
VSS15
KEY
VSS16
VSS17
DQ16
DQ20
DQ17
VSS18
DQ21
VSS19
DQS2*
NC0
DQS2
VSS21
DM2
VSS22
DQ18
DQ22
DQ19
VSS23
DQ23
VSS24
DQ24
DQ25
DQ28
DQ29
VSS25
VSS26
DM3
NC1
DQS3*
DQS3
VSS27
VSS28
DQ26
DQ27
DQ30
DQ31
VSS29
CKE0
VDD0
VSS30
NC/CKE1
VDD1
NC2
BA2
NC/A15
NC/A14
VDD2
VDD3
A12
A9
A11
A7
A8
A6
VDD4
A5
VDD5
A4
A3
A2
A1
VDD6
A0
VDD7
A10/AP
BA0
BA1
RAS*
WE*
S0*
VDD8
CAS*
VDD9
ODT0
NC/S1*
NC/A13
VDD10
NC/ODT1
VDD11
NC3
VSS31
VSS32
DQ32
DQ33
DQ36
DQ37
VSS33
DQS4*
VSS34
DM4
DQS4
VSS35
VSS36
DQ34
DQ38
DQ39
DQ35
VSS37
VSS38
DQ40
DQ44
DQ45
DQ41
VSS39
VSS40
DM5
DQS5*
DQS5
VSS41
DQ42
VSS42
DQ46
DQ43
DQ47
VSS43
DQ48
VSS44
DQ52
DQ49
DQ53
VSS45
NC_TEST
VSS46
CK1
CK1*
VSS47
DQS6*
DQS6
VSS48
DM6
VSS49
DQ50
VSS50
DQ54
DQ51
DQ55
VSS51
DQ56
VSS52
DQ60
DQ57
DQ61
VSS53
DM7
VSS54
DQS7*
VSS55
DQS7
DQ58
DQ59
VSS56
DQ62
VSS57
SDA
DQ63
VSS58
SCL
SA0
VDDSPD
SA1
402
5
41 40 10
DDR2-SODIMM-DUAL
10 40 41
2B
4B
RAM_DATA_B<0>
RAM_DATA_B<3>
6B
39
39
8B
10B
RAM_DQM_B<0>
39
12B
14B
RAM_DATA_B<5>
RAM_DATA_B<4>
16B
39
39
18B
20B
RAM_DATA_B<15>
RAM_DATA_B<12>
22B
39
39
24B
26B
RAM_DQM_B<1>
DDR2 VREF
39
28B
30B
RAM_CLKDDR_2_P
RAM_CLKDDR_2_N
32B
ONE 0.1UF PER SLOT
39
39
34B
36B
RAM_DATA_B<9>
RAM_DATA_B<11>
38B
39
=RAM_VREF_B
41 40
39
40B
C5201
0.1uF
42B
44B
RAM_DATA_B<18>
RAM_DATA_B<20>
46B
20%
10V
2 CERM
402
39
39
48B
50B
NC
52B
RAM_DQM_B<2>
39
54B
56B
RAM_DATA_B<23>
RAM_DATA_B<21>
58B
39
39
60B
62B
RAM_DATA_B<31>
RAM_DATA_B<30>
64B
39
39
DDR2 BYPASS
SLOT "B"
66B
68B
RAM_DQS_B_N<3>
RAM_DQS_B_P<3>
70B
39
39
72B
74B
RAM_DATA_B<24>
RAM_DATA_B<28>
76B
39
39
41 40 10
=PP1V8_PWRON_DDR2
78B
80B
RAM_CKE<3>
39
82B
84B
86B
20%
6.3V
2 X5R
603
88B
90B
RAM_ADDR<11>
RAM_ADDR<7>
RAM_ADDR<6>
92B
94B
C5208
10UF
NC
NC
100B
102B
10UF
39 40
39 40
C5210
0.1uF
RAM_ADDR<4>
RAM_ADDR<2>
RAM_ADDR<0>
C5209
20%
6.3V
2 X5R
603
39 40
96B
98B
20%
2 10V
CERM
402
39 40
39 40
C5211
0.1uF
C5212
0.1uF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
C5213
0.1uF
20%
2 10V
CERM
402
C5214
0.1uF
20%
2 10V
CERM
402
39 40
104B
106B
RAM_BA<1>
RAM_RAS_L
RAM_CS_L<2>
108B
110B
39 40
39 40
114B
RAM_ODT<1>
RAM_ADDR<13>
116B
C5215
0.1uF
39
20%
2 10V
CERM
402
112B
39
C5216
0.1uF
20%
2 10V
CERM
402
C5217
0.1uF
20%
2 10V
CERM
402
C5218
0.1uF
20%
2 10V
CERM
402
C5219
0.1uF
20%
2 10V
CERM
402
39 40
118B
120B
NC
122B
124B
126B
C5220
0.1uF
RAM_DATA_B<39>
RAM_DATA_B<38>
20%
2 10V
CERM
402
39
39
C5221
0.1uF
20%
2 10V
CERM
402
C5222
0.1uF
20%
2 10V
CERM
402
C5223
0.1uF
20%
2 10V
CERM
402
128B
130B
RAM_DQM_B<4>
Distribute C522x caps along connector
39
132B
134B
136B
RAM_DATA_B<33>
RAM_DATA_B<32>
39
39
138B
140B
142B
RAM_DATA_B<40>
RAM_DATA_B<46>
39
39
144B
146B
148B
RAM_DQS_B_N<5>
RAM_DQS_B_P<5>
39
39
150B
152B
154B
RAM_DATA_B<45>
RAM_DATA_B<44>
39
39
156B
158B
160B
RAM_DATA_B<53>
RAM_DATA_B<48>
39
39
162B
164B
166B
RAM_CLKDDR_3_P
RAM_CLKDDR_3_N
39
39
168B
170B
RAM_DQM_B<6>
39
172B
174B
176B
RAM_DATA_B<50>
RAM_DATA_B<54>
39
DDR2 SO-DIMM Slot B
39
178B
180B
182B
RAM_DATA_B<58>
RAM_DATA_B<62>
SYNC_MASTER=N/A
SYNC_DATE=N/A
39
39
184B
186B
188B
RAM_DQS_B_N<7>
RAM_DQS_B_P<7>

39
39
190B
192B
194B
RAM_DATA_B<57>
RAM_DATA_B<60>

39

39
196B
198B
200B
SIZE
=PP3V3_PWRON_VDDSPD
10 40 41
ADDR=0XA2(WR)/0XA3(RD)
APPLE COMPUTER INC.
D
SCALE
NC
DRAWING NUMBER
REV.
C
051-6929
52
115
SHT
OF
NONE
NET_TYPE
I1059
I1060
I1062
FB_A_CLK_0
(provided above)
FB_A_CLK_1
SPACING
PHYSICAL
RAM_DIFF
RAM_DIFF
FB_A_CLK_0_R
RAM_DIFF
RAM_DIFF
FB_A_CLK_0_R
RAM_DIFF
RAM_DIFF
FB_A_CLK_1_R
RAM_DIFF
FB_A_CLK_1_R
I1061
(provided above)
RAM_DIFF
I1068
FB_A_ADDR_CTL
RAM
RAM
I1069
FB_A_ADDR_CTL
RAM
RAM
I1071
FB_A_ADDR_CTL
RAM
RAM
I1072
FB_A_ADDR_CTL
RAM
RAM
I1073
FB_A_ADDR_CTL
RAM
RAM
I1074
FB_A_ADDR_CTL
RAM
RAM
I1075
FB_A_ADDR_CTL
RAM
RAM
I1076
FB_A_DQS0
RAM
RAM
I1078
FB_A_DQS1
RAM
RAM
I1079
FB_A_DQS2
RAM
RAM
I1080
FB_A_DQS3
RAM
RAM
I1081
FB_A_DQS4
RAM
RAM
I1082
FB_A_DQS5
RAM
RAM
I1084
FB_A_DQS6
RAM
RAM
I1083
FB_A_DQS7
RAM
RAM
I1085
FB_A_DQM0
RAM
RAM
I1086
FB_A_DQM1
RAM
RAM
I1087
FB_A_DQM2
RAM
RAM
I1088
FB_A_DQM3
RAM
RAM
I1089
FB_A_DQM4
RAM
RAM
I1090
FB_A_DQM5
RAM
RAM
I1091
FB_A_DQM6
RAM
RAM
I1092
FB_A_DQM7
RAM
RAM
I1093
FB_A_DQ0
RAM
RAM
I1094
FB_A_DQ1
RAM
RAM
I1095
FB_A_DQ2
RAM
RAM
I1096
FB_A_DQ3
RAM
RAM
I1097
FB_A_DQ4
RAM
RAM
I1098
FB_A_DQ5
RAM
RAM
I1099
FB_A_DQ6
RAM
RAM
I1100
FB_A_DQ7
RAM
RAM
DIFFERENTIAL_PAIR
FB_A_CLKDDR_0_P_R
FB_A_CLKDDR_0_N_R
FB_A_CLKDDR_1_P_R
FB_A_CLKDDR_1_N_R
FB_A_CKE_R
FB_A_CS_L_R
FB_A_ADDR_R<12..0>
FB_A_BA_R<2..0>
FB_A_RAS_L_R
FB_A_CAS_L_R
FB_A_WE_L_R
FB_A_DQS_R<0>
FB_A_DQS_R<1>
FB_A_DQS_R<2>
FB_A_DQS_R<3>
FB_A_DQS_R<4>
FB_A_DQS_R<5>
FB_A_DQS_R<6>
FB_A_DQS_R<7>
FB_A_DQM_R<0>
FB_A_DQM_R<1>
FB_A_DQM_R<2>
FB_A_DQM_R<3>
FB_A_DQM_R<4>
FB_A_DQM_R<5>
FB_A_DQM_R<6>
FB_A_DQM_R<7>
FB_A_DQ_R<7..0>
FB_A_DQ_R<15..8>
FB_A_DQ_R<23..16>
FB_A_DQ_R<31..24>
FB_A_DQ_R<39..32>
FB_A_DQ_R<47..40>
FB_A_DQ_R<55..48>
FB_A_DQ_R<63..56>
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
NET_TYPE
I1104
I1103
I1102
FB_B_CLK_0
(provided above)
FB_B_CLK_1
SPACING
PHYSICAL
RAM_DIFF
RAM_DIFF
FB_B_CLK_0_R
RAM_DIFF
RAM_DIFF
FB_B_CLK_0_R
RAM_DIFF
RAM_DIFF
FB_B_CLK_1_R
RAM_DIFF
FB_B_CLK_1_R
I1101
(provided above)
RAM_DIFF
I1105
FB_B_ADDR_CTL
RAM
RAM
I1109
FB_B_ADDR_CTL
RAM
RAM
I1108
FB_B_ADDR_CTL
RAM
RAM
I1107
FB_B_ADDR_CTL
RAM
RAM
I1106
FB_B_ADDR_CTL
RAM
RAM
I1110
FB_B_ADDR_CTL
RAM
RAM
I1114
FB_B_ADDR_CTL
RAM
RAM
I1113
FB_B_DQS0
RAM
RAM
I1112
FB_B_DQS1
RAM
RAM
I1111
FB_B_DQS2
RAM
RAM
I1115
FB_B_DQS3
RAM
RAM
I1116
FB_B_DQS4
RAM
RAM
I1117
FB_B_DQS5
RAM
RAM
I1118
FB_B_DQS6
RAM
RAM
I1119
FB_B_DQS7
RAM
RAM
I1123
FB_B_DQM0
RAM
RAM
I1122
FB_B_DQM1
RAM
RAM
I1121
FB_B_DQM2
RAM
RAM
I1120
FB_B_DQM3
RAM
RAM
I1124
FB_B_DQM4
RAM
RAM
I1128
FB_B_DQM5
RAM
RAM
I1127
FB_B_DQM6
RAM
RAM
I1126
FB_B_DQM7
RAM
RAM
I1125
FB_B_DQ0
RAM
RAM
I1129
FB_B_DQ1
RAM
RAM
I1133
FB_B_DQ2
RAM
RAM
I1132
FB_B_DQ3
RAM
RAM
I1131
FB_B_DQ4
RAM
RAM
I1130
FB_B_DQ5
RAM
RAM
I1134
FB_B_DQ6
RAM
RAM
I1135
FB_B_DQ7
RAM
RAM
DIFFERENTIAL_PAIR
FB_B_CLKDDR_0_P_R
FB_B_CLKDDR_0_N_R
FB_B_CLKDDR_1_P_R
FB_B_CLKDDR_1_N_R
FB_B_CKE_R
FB_B_CS_L_R
FB_B_ADDR_R<12..0>
FB_B_BA_R<2..0>
FB_B_RAS_L_R
FB_B_CAS_L_R
FB_B_WE_L_R
FB_B_DQS_R<0>
FB_B_DQS_R<1>
FB_B_DQS_R<2>
FB_B_DQS_R<3>
FB_B_DQS_R<4>
FB_B_DQS_R<5>
FB_B_DQS_R<6>
FB_B_DQS_R<7>
FB_B_DQM_R<0>
FB_B_DQM_R<1>
FB_B_DQM_R<2>
FB_B_DQM_R<3>
FB_B_DQM_R<4>
FB_B_DQM_R<5>
FB_B_DQM_R<6>
FB_B_DQM_R<7>
FB_B_DQ_R<7..0>
FB_B_DQ_R<15..8>
FB_B_DQ_R<23..16>
FB_B_DQ_R<31..24>
FB_B_DQ_R<39..32>
FB_B_DQ_R<47..40>
FB_B_DQ_R<55..48>
FB_B_DQ_R<63..56>
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
M11 Frame Buffer Constraints
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
55
115
SHT
OF
NONE
NET_TYPE
AGP_CLK
I2_AGP_FBCLK
PHYSICAL
CLOCK
CLOCK
I2_FBCLK
I2_FBCLK
I2_FBCLK
I2_FBCLK
AGP_AD_0
AGP
AGP
AGP_AD_1
AGP
AGP
AGP_AD_0
AGP
AGP
AGP_AD_1
SPACING
AGP
DIFFERENTIAL_PAIR
AGP_CLK66M_GPU_R
AGP
AGP_STB
AGP_AD_STB0
AGP_AD_STB_0
AGP_STB
AGP_STB
AGP_AD_STB0
AGP_AD_STB_1
AGP_STB
AGP_STB
AGP_AD_STB1
AGP_STB
AGP_STB
AGP
21 43
43 44
AGP_CBE_L<1..0>
AGP_CBE_L<3..2>
AGP_STB
AGP_SBA
43
AGP_AD<15..0>
AGP_AD<31..16>
AGP_AD_STB_0
AGP_AD_STB_1
11 43
I2_AGP_FBCLK_OUT_R
I2_AGP_FBCLK_OUT
AGP_AD_STB1
AGP_STB
AGP_STB
AGP_SB_STB
AGP_SB_STB
AGP_STB
AGP_STB
AGP_SB_STB
U2100
I2
BGA
43 44
43 44
(9 of 14)
43 44
43 44
AGP_SB_STB_P
AGP_SB_STB_N
AGP INTERFACE
43 44
AGP_SBA<7..0>
AGP_SB_STB
OMIT
43 44
43 44
AGP_AD_STB0_P
AGP_AD_STB0_N
AGP_AD_STB1_P
AGP_AD_STB1_N
AGP
43 44
AP19
AGP_BUSY_L
44 43
43 44
44 43 6
43 44
AR19
AGP_REQ_L
AGP_CLK_H
(3.3V SIGNALS)
AGP_BUSY_L
AGP_STP_L
(VDDAGP SIGNALS)
AGP_REQ_L
AGP_GNT_L
AH19
AGP PULL-UPS/PULL DOWNS
AGP_CLK66M_GPU_R
11 43
AT21
STOP_AGP_L
43 44
AL16
AGP_GNT_L
6 43 44
44 10
R5610
44 43
AGP_ST
AGP
AGP_CTL
AGP
AGP
AGP_CTL
AGP
AGP
AGP_CTL
AGP
AGP
AGP_CTL
AGP
AGP
AGP_CTL
AGP
AGP
AGP_PAR
AGP
AGP
AGP_DEV_CTL
AGP
AGP
AGP_DEV_CTL
AGP
AGP
AGP_DEV_CTL
AGP
AGP_ST<3..0>
AGP
10K
AGP_BUSY_L
44 43
6 43 44
44 43 6
6 43 44
44 43 6
6 43 44
44 43 6
6 43 44
44 43 6
6 43 44
44 43 6
43 44
43
43
44 43
43 44
44 43 6
AT15
AGP_PAR
AGP_FRAME_L
AGP_TRDY_L
AGP_IRDY_L
AGP_STOP_L
AGP_DEVSEL_L
AGP_PIPE_L
AGP_WBF_L
AGP_RBF_L
AK16
AM16
AR15
AT14
AP15
AN19
AT18
AM19
AGP_PAR_H
AGP_FRAME_L
AGP_TRDY_L
AGP_IRDY_L
AGP_STOP_L
AGP_DEVSEL_L
AGP_PIPE_L
AGP_WBF_L
AGP_RBF_L
AGP_AD_00_H
AGP_AD_01_H
AGP_AD_02_H
AGP_AD_03_H
AGP_AD_04_H
AGP_AD_05_H
AGP_AD_06_H
AGP_AD_07_H
AGP_CBE_0_L
AP6
AGP_AD_08_H
AGP_AD_09_H
AGP_AD_10_H
AGP_AD_11_H
AGP_AD_12_H
AGP_AD_13_H
AGP_AD_14_H
AGP_AD_15_H
AGP_CBE_1_L
AN9
AGP_AD<0>
AGP_AD<1>
AGP_AD<2>
AGP_AD<3>
AGP_AD<4>
AGP_AD<5>
AGP_AD<6>
AGP_AD<7>
AGP_CBE_L<0>
AP4
AR4
AT5
AN7
AL13
AR6
AT6
AT3
R5611
43 44
44 43
43 44
10K
STOP_AGP_L
43 44
43 44
44 22
2
5%
1/16W
MF-LF
402
43 44
AGP_INT_L
R5620
10K
1
43 44
43 44
43 44
47 44 43 10
AGP
AGP
AGP
AGP
AGP_REQ_L
AGP_GNT_L
6 43 44
44 43
6 43 44
44 43
44 43
44 43
Page Notes
C
44 43
44 43

- =PP3V3_AGP
- =PP1V5_AGP
- =PP1V5_I2_AGP
44 43
44 43
44 43

- =I2_AGP_VREF - VRef from graphics
card or on-board graphics controller
- =I2_AGP_FBCLK_IN - AGP feedback clock
input. Length should match that of
clock from I2 to AGP device.
AGP I/O DECOUPLING

10
44 43
AGP_SB_STB_P
AGP_SB_STB_N
AH16
AR18
AP18
AN18
AM18
AK18
AT16
AT17
AJ16
1 X 10uF (0603)
25 X 1uF (0402)
(25 Balls on I2)
=PP1V5_I2_AGP
AGP_SBA<0>
AGP_SBA<1>
AGP_SBA<2>
AGP_SBA<3>
AGP_SBA<4>
AGP_SBA<5>
AGP_SBA<6>
AGP_SBA<7>
AD15
AD17
C5649
10UF
20%
6.3V
X5R
603

(NONE)
C5650
1uF
10%
6.3V
CERM
402
C5651
1uF
2
10%
6.3V
CERM
402
C5652
1uF
2
10%
6.3V
CERM
402
C5653
1uF
2
C5654
1uF
10%
6.3V
CERM
402
1uF
10%
6.3V
CERM
402
C5655
10%
6.3V
CERM
402
C5656
AD19
1uF
AE13
10%
6.3V
CERM
402
AE16
AE18
AF14
NOTE: I2 implements an AGP 4x bridge.

AGP 8x signals are not provided
by this page.
AG13
AG16
1
C5657
1uF
2
10%
6.3V
CERM
402
C5658
1uF
2
10%
6.3V
CERM
402
C5659
1uF
2
10%
6.3V
CERM
402
C5660
1uF
2
C5661
1uF
10%
6.3V
CERM
402
1uF
10%
6.3V
CERM
402
C5662
C5663
AH11
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
AH13
AL11
AL12
AL14
AL17
C5664
C5665
C5666
C5667
C5668
C5669
C5670
AL20
1uF
1uF
1uF
1uF
1uF
1uF
1uF
AL8
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
AP11
AL9
AP14
AP17
AP20
1
C5671
C5672
C5673
C5674
1uF
1uF
1uF
1uF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
AP3
AP5
AP8
AGP_SBA_0_H
AGP_SBA_1_H
AGP_SBA_2_H
AGP_SBA_3_H
AGP_SBA_4_H
AGP_SBA_5_H
AGP_SBA_6_H
AGP_SBA_7_H
AGP_SB_STB_P
AGP_SB_STB_N
VDDAGP_0
VDDAGP_1
VDDAGP_2
VDDAGP_3
VDDAGP_4
VDDAGP_5
VDDAGP_6
VDDAGP_7
VDDAGP_8
VDDAGP_9
VDDAGP_10
VDDAGP_11
VDDAGP_12
VDDAGP_13
VDDAGP_14
VDDAGP_15
VDDAGP_16
VDDAGP_17
VDDAGP_18
VDDAGP_19
VDDAGP_20
VDDAGP_21
VDDAGP_22
VDDAGP_23
VDDAGP_24
AGP_AD_STB0_P
AGP_AD_STB0_N
AGP_AD<8>
AGP_AD<9>
AGP_AD<10>
AGP_AD<11>
AGP_AD<12>
AGP_AD<13>
AGP_AD<14>
AGP_AD<15>
AGP_CBE_L<1>
AP7
AR7
AT7
AN10
AR9
AT8
AT9
AP9
AH9
AGP_AD_16_H
AGP_AD_17_H
AGP_AD_18_H
AGP_AD_19_H
AGP_AD_20_H
AGP_AD_21_H
AGP_AD_22_H
AGP_AD_23_H
AGP_CBE_2_L
AM12
AGP_AD_24_H
AGP_AD_25_H
AGP_AD_26_H
AGP_AD_27_H
AGP_AD_28_H
AGP_AD_29_H
AGP_AD_30_H
AGP_AD_31_H
AGP_CBE_3_L
AL15
AGP_AD_STB1_P
AGP_AD_STB1_N
AK13
AGP_ST_0_H
AGP_ST_1_H
AGP_ST_2_H
AR16
43 44
AN12
AT10
AK15
AM13
AP12
AT11
AR10
AR12
AT12
AR13
AT13
AM15
AN15
AP13
43 44
10K
2
10K
43 44

- AGP_RBF_L
- AGP_GNT_L
- AGP_FRAME_L
- AGP_REQ_L
- AGP_STOP_L
- AGP_DEVSEL_L
- AGP_IRDY_L
- AGP_TRDY_L
43 44
43 44
43 44
43 44
43 44
43 44
43 44
=RP5610P3
RP5611
10K
2
=RP5611P2
10K
3
=RP5611P3
6
5%
1/16W
SM-LF
RP5611
10K
4
=RP5611P4
43 44
10K
6
=RP5611P1
8
5%
1/16W
SM-LF
43 44
43 44
RP5610
10K
1
=RP5610P1
R5612
43 44
44 43
AGP_WBF_L
43 44
43 44
43
10K
5%
1/16W
MF-LF
402
43 44
AGP_PIPE_L
R5613
10K
1
R5614
43 44
10K
AGP_AD_STB0_P
2
5%
1/16W
MF-LF
402
43 44
43 44
AGP_AD_STB1_P
10K
44 43
10K
AGP_SB_STB_P
2
5%
1/16W
MF-LF
402
R5616
43 44
R5615
1
43 44
43 44
2
5%
1/16W
MF-LF
402
43 44
44 43
8
5%
1/16W
SM-LF
43 44
43 44
5
5%
1/16W
SM-LF
RP5611
43 44
43 44
7
5%
1/16W
SM-LF
RP5611
6
6
5%
1/16W
SM-LF
7
5%
1/16W
SM-LF
RP5610
43 44
AGP_ST<0>
AGP_ST<1>
AGP_ST<2>
AP16
RP5610
=RP5610P2
43 44
44 43
AN16
5
5%
1/16W
SM-LF
43 44
AGP_AD_STB1_P
AGP_AD_STB1_N
AJ13
=RP5610P4
43 44
AGP_AD<24>
AGP_AD<25>
AGP_AD<26>
AGP_AD<27>
AGP_AD<28>
AGP_AD<29>
AGP_AD<30>
AGP_AD<31>
AGP_CBE_L<3>
AN13
10K
43 44
AGP_AD<16>
AGP_AD<17>
AGP_AD<18>
AGP_AD<19>
AGP_AD<20>
AGP_AD<21>
AGP_AD<22>
AGP_AD<23>
AGP_CBE_L<2>
AP10
=PP1V5_AGP
RP5610
43 44
AGP_AD_STB0_P
AGP_AD_STB0_N
AJ9
2
5%
1/16W
MF-LF
402
43 44
6 43 44
AL18
2
5%
1/16W
MF-LF
402
43 44
AGP_FRAME_L
AGP_DEVSEL_L
AGP_IRDY_L
AGP_TRDY_L
AGP_STOP_L
AGP_PAR
AGP_PIPE_L
AGP_WBF_L
AGP_RBF_L
AGP
=PP3V3_AGP
2
5%
1/16W
MF-LF
402
11
=I2_AGP_VREF
AD18
AGP_VREF_0_H
R5617
47 44 43 10
44 43
=PP1V5_AGP
AGP_AD_STB0_N
R5600
44 43
60.4
1%
1/16W
MF-LF
2 402
I2_AGP_PVTREF
44 43
AJ18
AGP_PVTREF_H
AM10
AGP_FB_CLK_IN_H
AGP_AD_STB1_N
10K
5%
1/16W
MF-LF
402
AGP_SB_STB_N
R5619
1
=I2_AGP_FBCLK_IN
1.5V IN
AGP_FBCLK_OUT_H
AM9
43
I2_AGP_FBCLK_OUT_R
22
1
10K
5%
1/16W
MF-LF
402
R5605
21
5%
1/16W
MF-LF
402
R5618
1
10K
I2_AGP_FBCLK_OUT
21 43
5%
1/16W
MF-LF
402
1.5V OUT
I2 AGP Interface
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
56
115
SHT
OF
NONE
NET_TYPE
SPACING PHYSICAL
I798
CLOCK
DIFFERENTIAL_PAIR
AGP_CLK66M_GPU
CLOCK
11 44
Page Notes
- =PP3V3_AGP
- =PP1V5_AGP

- =AGP_VREF - VRef divider output for
both GPU and NB
- =AGP_GPU_RESET_L - Active low reset for GPU

(NONE)
OMIT
CRITICAL
NOTE: AGP 8x signals are not provided

by this page.
R5700
U5700
11
=AGP_GPU_RESET_L
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
43
44 43 10
=PP3V3_AGP
47 44 43 10
43
=PP1V5_AGP
43
R57201
R57251
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
10K
47K
R5726
43
47K
43
5%
1/16W
MF-LF
2 402
43
43
43
43
43
43
43
AGP_AD<0>
AGP_AD<1>
AGP_AD<2>
AGP_AD<3>
AGP_AD<4>
AGP_AD<5>
AGP_AD<6>
AGP_AD<7>
AGP_AD<8>
AGP_AD<9>
AGP_AD<10>
AGP_AD<11>
AGP_AD<12>
AGP_AD<13>
AGP_AD<14>
AGP_AD<15>
AGP_AD<16>
AGP_AD<17>
AGP_AD<18>
AGP_AD<19>
AGP_AD<20>
AGP_AD<21>
AGP_AD<22>
AGP_AD<23>
AGP_AD<24>
AGP_AD<25>
AGP_AD<26>
AGP_AD<27>
AGP_AD<28>
AGP_AD<29>
AGP_AD<30>
AGP_AD<31>
H29
H28
J29
J28
K29
K28
L29
L28
N28
P29
P28
R29
R28
T29
T28
U29
N25
R26
P25
R27
R25
T25
T26
U25
V27
W26
W25
Y26
Y25
AA26
AA25
AA27
M11P
(1 OF 8)
AD_0
AD_1
AD_2
AD_3
AD_4
AD_5
AD_6
AD_7
AD_8
AD_9
AD_10
AD_11
AD_12
AD_13
AD_14
AD_15
AD_16
AD_17
AD_18
AD_19
AD_20
AD_21
AD_22
AD_23
AD_24
AD_25
AD_26
AD_27
AD_28
AD_29
AD_30
AD_31
PCICLK
AGP/PCI INTERFACE
43
AGP ONLY
ATI_DBI_HI_PU AB25 DBI_HI
ATI_DBI_LO_PU AB26 DBI_LO AGP 8X
47 44 43 10
=PP1V5_AGP
43
43
R57211
47
1%
1/16W
MF-LF
402 2
43
43
43
43
43
43
AGP8X_DET_PU
AC25 AGP8X_DET*
AGP_SBA<0>
AGP_SBA<1>
AGP_SBA<2>
AGP_SBA<3>
AGP_SBA<4>
AGP_SBA<5>
AGP_SBA<6>
AGP_SBA<7>
AD28
AD29
AC28
AC29
AA28
AA29
Y28
Y29
GPU_AGPTEST
SBA_0
SBA_1
SBA_2
SBA_3
SBA_4
SBA_5
SBA_6
SBA_7
47
5%
1/16W
MF-LF
402
BGA
RST*
AG30 AGP_CLK66M_GPU
AG28 AGP_ATI_RESET_L
INTA*
AE26 AGP_INT_L
GNT*
REQ*
AD26 AGP_GNT_L
AF28 AGP_REQ_L
FRAME*
TRDY*
IRDY*
DEVSEL*
STOP*
PAR
W28
V28
W29
V29
N26
M25
AGP_FRAME_L
AGP_TRDY_L
AGP_IRDY_L
AGP_DEVSEL_L
AGP_STOP_L
AGP_PAR
C_BE_0*
C_BE_1*
C_BE_2*
C_BE_3*
N29
U28
P26
U26
AGP_CBE_L<0>
AGP_CBE_L<1>
AGP_CBE_L<2>
AGP_CBE_L<3>
RBF*
WBF*
AE29 AGP_RBF_L
AC26 AGP_WBF_L
ST_0
ST_1
ST_2
AF29 AGP_ST<0>
AD27 AGP_ST<1>
AE28 AGP_ST<2>
SB_STBF
SB_STBS
11 44
AB29 AGP_SB_STB_P
AB28 AGP_SB_STB_N
22 43
6 43
6 43
6 43
6 43
6 43
6 43
6 43
43
43
43
43
43
6 43
43
43
43
43
43
43
44 43 10
=PP3V3_AGP
47 44 43 10
AD_STBF_0
AD_STBS_0
M27 AGPTEST
M28
M29
AGP_AD_STB0_P
AGP_AD_STB0_N
AD_STBF_1
AD_STBS_1
V25
V26
AGP_AD_STB1_P
AGP_AD_STB1_N
AGPREF
M26
=GPU_AGP_VREF
STP_AGP*
AGP_BUSY*
SUS_STAT*
AH30 STOP_AGP_L
AH29 AGP_BUSY_L
43
43
43
43
=PP1V5_AGP
R5722
R5730
11
1%
1/16W
MF-LF
2 402
=AGP_VREF
43
C5732
43
0.1uF
C5731
0.1uF
10%
16V 2
X5R
402
AG26 AGP_SUS_STAT_L_PU
1K
CONNECT TO GPU AGP REF

CAN ALSO CONNECT TO NB
IF CHIPS ARE CO-LOCATED
5%
1/16W
MF-LF
2 402
11
20K
10%
2 16V
X5R
402
R5731
1K
1%
1/16W
MF-LF
2 402
PLACE C5731 AT GPU

PLACE C5732 AT NB
PLACE RESISTORS MIDWAY BETWEEN
GPU (M11) AGP Interface
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
57
115
SHT
OF
NONE
8
Page Notes

- =PPVIN_LTC1778_GPU
- =PP5V_PWRON_LTC1778_GPU_EXTVCC
- =PPVCORE_GPU_REG
- =GPUVCORE_PGOOD - Active high Power Good
signal for power sequencing
- GPU_PWRPLAY
NOTE: Implements "Power Miser" feature

for ATI GPUs
GPU VCORE SUPPLY

=PP5V_PWRON_LTC1778_GPU_EXTVCC
10
R58221
1%
1/16W
MF-LF
2 402
R5828 1R5826
63.4K
C5825
R5823
0.1uF
11
LTC1778
20.0K
1778_ITH_RC
C5830
470pF
10%
50V
CERM 2
402
NO STUFF
1
1
1
R5827
C5831 R5829
0
0
220pF
5%
2 25V
CERM
402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
SO-8-PWRPK-LF
ION 7
5 ITHCRITICAL
1778_ITH
B00ST 16
TG 15
3 VRNG
2 1778_VRNG
SW 14
4 FCB
1778_FCB
BG 12
2 PGOOD
=GPUVCORE_PGOOD
VFB 8
SGND
PGND
26
C5822
0.1uF
20%
2 10V
CERM
402
2.1uH-11A
SM
CRITICAL
1
D5800
SMB
C5804
0.1uF
20%
10V
2 CERM
402
20%
2 2.5V
TANT
7343-H2.9
C
R58801
B340LBXF
5
Q5801
SI7892DP
1778_BG
SO-8-PWRPK-LF
6.34K
CRITICAL
CRITICAL
C5801 1
C5803 1
22uF
470uF
20%
10V
CERM 2
1210
20%
2.5V
TANT
7343-H2.9
C5805
1%
1/16W
MF-LF
402 2
0.1uF
Ra
20%
10V
CERM 2
402
NO STUFF
1778_VFB
C5824 1
0.0022UF
C5802
470uF
CRITICAL
R58831
2 3
20.0K
10%
50V
CERM 2
402
XW5800
SM
1778_GND
VOLTAGE=0V
L5800
1778_BST
1778_TG
13
=PPVCORE_GPU_REG
3
GPU_VCORE_SW
20%
25V
CERM 2
603
1778_ION
10
CRITICAL
1 2 3
0.1uF
SSOP-LF
1 RUN/SS
R58301
C5823
U5800
GPUVCORE_SHDN_L
2.2
5%
1/10W
MF-LF
603
10
EXT INT VIN

VCC VCC
1%
1/16W
MF-LF
402 2
SI7860DP
1778_BST_RC
C5820 1
20%
25V
CERM 2
603
26
Q5800
4
20%
2 10V
CERM
1206
20%
25V
CERM 2
1206
CRITICAL
PPVOUT_1778_VCC
VOLTAGE=5V
1
PPVIN_1778_VIN
VOLTAGE=12.8V
MIN_LINE_WIDTH=0.38SOD-123
mm
MIN_NECK_WIDTH=0.25
mm
MBR0540XXG
4.7UF
1%
1/16W
MF-LF
2 402
4.7uF
20%
25V
CERM 2
1206
D5823
4.7uF
576K
5%
1/10W
MF-LF
2 603
NO STUFF
5%
1/16W
MF-LF
2 402
R5821
5%
1/16W
MF-LF
402 2
C5810 1 C5811 1
R5820
100K
=PPVIN_LTC1778_GPU
10
1%
1/16W
MF-LF
402 2
Rb
GPU_PWRPLAY
1
R5881
18.2K
1%
1/16W
MF-LF
402 2
Rc
10
R5882
WHEN VCORE_CNTL HIGH => 1.307V
1.82K
GPU_PWRPLAY
1
1%
1/16W
MF-LF
402 2
R5884
1.307V = 0.8V * (1 + Ra*(Rc+Rb) / (Rc*Rb))
100K
WHEN VCORE_CNTL LOW => 1.054V
5%
1/16W
MF-LF
402 2
1.054V = 0.8V * (1 + Ra / Rb)
GPU_VCORE_HI_L
10K
5%
1/16W
MF-LF
402
20%
10V
CERM
402
0.1uF
Q5884
Q5884
R5885
C5882
HIGH_GPU_VCORE_L
6 GPU_PWRPLAY
GPU_PWRPLAY
GPU_PWRPLAY
3 GPU_PWRPLAY
GPU_VCORE_HI
51
HIGH_GPU_VCORE_DIV
GPU_PWRPLAY
1
=PP5V_PWRON_GPUVCORE_PWRPLAY
2N7002DW-X-F
5
SOT-363
2N7002DW-X-F
GPU_VCORE_HI_L_RC
SOT-363
NO STUFF
1
C5885 1
0.1uF
20%
10V
CERM 2
402
GPU VCore Supply
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
58
115
SHT
OF
NONE
1
Page Notes
- =PP1V5_GPU_VDD15
- =PP1VR1V3_GPU_VCORE
(NONE)
(NONE)
C5900
10UF
20%
6.3V
2 X5R
603
C5905
0.22UF
10%
6.3V
2 CERM-X5R
402
C5910
0.22UF
10%
2 6.3V
CERM-X5R
402
C5915
0.22UF
10%
6.3V
2 CERM-X5R
402
C5920
0.22UF
10%
2 6.3V
CERM-X5R
402
C5901
10UF
10%
6.3V
2 CERM-X5R
402
C5906
0.22UF
10%
6.3V
2 CERM-X5R
402
C5911
C5907
0.22UF
C5912
0.22UF
10%
2 6.3V
CERM-X5R
402
10%
2 6.3V
CERM-X5R
402
C5916
0.22UF
10%
6.3V
2 CERM-X5R
402
10%
6.3V
2 CERM-X5R
402
0.22UF
C5902
0.22UF
20%
6.3V
2 X5R
603
C5917
0.22UF
10%
6.3V
2 CERM-X5R
402
C5921
0.22UF
C5922
0.22UF
10%
2 6.3V
CERM-X5R
402
10%
2 6.3V
CERM-X5R
402
C5903
0.22UF
10%
6.3V
2 CERM-X5R
402
C5908
0.22UF
10%
6.3V
2 CERM-X5R
402
C5913
0.22UF
10%
2 6.3V
CERM-X5R
402
C5918
0.22UF
10%
6.3V
2 CERM-X5R
402
C5923
0.22UF
10%
2 6.3V
CERM-X5R
402
AC13
AC15
AC17
AD13
AD15
M12
M13
M14
M17
M18
M19
N12
N13
N14
N17
N18
N19 VDDC
P12
P13
P14
P17
P18
P19
U12
U13
U14
U17
U18
U19
V12
V13
V14
V17
V18
V19
W12
W13
W14
W17
W18
W19
C5904
0.22UF
10%
6.3V
2 CERM-X5R
402
C5909
0.22UF
10%
6.3V
2 CERM-X5R
402
C5914
0.22UF
10%
2 6.3V
CERM-X5R
402
C5919
0.22UF
10%
6.3V
2 CERM-X5R
402
C5924
0.22UF
10%
2 6.3V
CERM-X5R
402
Internal I/O - 1.5V

=PP1V5_GPU_VDD15
5
U5700
M11P
BGA
(8 OF 8)
VDDCI
M15
R19
T12
W16
C5990
10UF
PP1VR1V3_GPU_VDDCI
VOLTAGE=1.3V
0.01uF
20%
2 16V
CERM
402
20%
2 6.3V
X5R
603
C5991
C5992
0.01uF
20%
16V
2 CERM
402
C5993
0.01uF
20%
2 16V
CERM
402
C5994
0.01uF
20%
16V
2 CERM
402
VDD15
AC11
AC20
H11
H20
L23
P8
Y23
Y8
L5950
10
OMIT
CRITICAL
FERR-220-OHM
26
1
PP1V5_GPU_VDD15_F
VOLTAGE=1.5V
GPUVDD15_EN
C5950 1
(500mA)
2
0805
1
C5951 1 C5952 1 C5953 1 C5954 1 C5955

0.01uF
1000pF
20%
2 16V
CERM
402
10%
25V 2
X7R
402
0.01uF
20%
2 16V
CERM
402
0.01uF
20%
2 16V
CERM
402
10UF
20%
2 6.3V
X5R
603
C5956 1 C5957 1 C5958 1 C5959

0.01uF
20%
2 16V
CERM
402
VSS
0.01uF
20%
2 16V
CERM
402
PP1V5_GPU_VDD15
VOLTAGE=1.5V
0.01uF
20%
2 16V
CERM
402
0.01uF
20%
2 16V
CERM
402
0.01uF
20%
2 16V
CERM
402
GPU (M11) Core Power

SYNC_MASTER=N/A
SYNC_DATE=N/A

VSS
SIZE
D12
D15
D18
D21
D24
D25
D27
D4
D6
D9
E4
F27
G12
G16
G18
G21
G24
G9
H12
H14
H16
H18
H21
A10
A16
A2
A22
A29
AA30
AB1
AB23
AB24
AB27
AB4
AB7
AB8
AC12
AC14
AC16
AC18
AC4
AD12
AD16
AD18
AD25
AD30
AE27
AG11
AG15
AG18
AG22
AG27
AG5
AG9
AJ1
AJ30
AK2
AK29
C1
C28
C3
C30
D10
I/O GROUND
CORE GND
VSS
2
SM
=PP1V05R1V3_GPU_VCORE
HOST GROUND
(6 OF 8)
10
BGA
L5990
60-OHM-EMI
TSOP-LF
M11P
Internal I/O - 1.3V/1.05V

1
Q5950
U5700
GPU VCORE - 1.3V/1.05V
SI3446DV
OMIT
CRITICAL
CRITICAL
H23
H27
H4
H8
H9
K1
K23
K24
K27
K30
K7
K8
L4
M16
M30
M7
M8
N15
N16
N23
N24
N27
P15
P16
P4
R12
R13
R14
R15
R16
R17
R18
R23
R24
R30
R7
R8
T1
T13
T14
T15
T16
T17
T18
T19
T27
U15
U16
U23
U4
U8
V15
V16
V30
W15
W23
W24
W27
W7
W8
Y4
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
59
115
SHT
OF
NONE
8
Page Notes
10

- =PP1V8R2V5_GPU_FB_VIO
- =PP1V8_GPU_PANEL_IO
- =PP1V8_GPU_LVDS_PLL
- =PP3V3_GPU_VDDR3
- =PP1V5_GPU_DVO
- =PP2V5_GPU_LVDS_IO
- =PP2V5_GPU_LVDS_IO
- =PP1V8_GPU_DVO
- =PP1V5R3V3_DVO_VREF
- =PP1V5_AGP
OMIT
CRITICAL
U5700
M11P
NOTE: Implements a low-swing DVO bus only
MEMORY I/O - 1.8V/2.5V
FERR-220-OHM
48 10
=PP1V8R2V5_GPU_FB_VIO1
(1200mA)
0805
C6050
10UF
20%
2 6.3V
X5R
603
C6055
0.1uF
20%
10V
2 CERM
402
C6060
0.1uF
20%
2 10V
CERM
402
C6065
10UF
20%
2 6.3V
X5R
603
=PP3V3_GPU_VDDR3
L6000

- DVO_1V5
- GPU_LVDDR_2V5
- DVO_1V8
- GPU_LVDDR_2V8
L6050
FERR-10-OHM-500MA

(NONE)
C6070
0.1uF
20%
2 10V
CERM
402
C6051
10UF
20%
2 6.3V
X5R
603
C6056
0.1uF
20%
2 10V
CERM
402
C6061
0.1uF
20%
2 10V
CERM
402
C6066
10UF
20%
2 6.3V
X5R
603
C6071
0.1uF
20%
2 10V
CERM
402
C6052
0.1uF
20%
10V
2 CERM
402
C6057
0.1uF
20%
10V
2 CERM
402
C6062
0.01uF
20%
2 16V
CERM
402
C6067
0.1uF
20%
2 10V
CERM
402
C6072
0.1uF
20%
2 10V
CERM
402
C6053
0.1uF
20%
10V
2 CERM
402
C6058
0.1uF
0.1uF
20%
10V
2 CERM
402
C6063
0.01uF
20%
2 16V
CERM
402
C6068
0.1uF
20%
2 10V
CERM
402
C6073
C6059
0.1uF
20%
2 10V
CERM
402
C6064
0.01uF
20%
2 16V
CERM
402
C6069
0.1uF
20%
2 10V
CERM
402
0.1uF
20%
2 10V
CERM
402
C6054
20%
2 10V
CERM
402
C6074
0.1uF
20%
PP1V8R2V5_GPU_FB_VIO
VOLTAGE=1.8V
A15
A21
A28
A3
A9
AA1
AA4
AA7
AA8
AD4
B1
B30
D11
D13
D14
D17
D19
D20
D23
D26
D5
D8
E27
F4
G10
G13 VDDR1
G15
G19
G22
G27
G7
H10
H13
H15
H17
H19
H22
J1
J23
J24
J4
J7
J8
L27
L8
M4
N4
N7
N8
R1
R4
T4
T7
T8
V4
V7
V8
VDDR3
BGA
(7 OF 8)
AC19
AC21
AC22
AC8
AD19
AD21
AD22
AD7
51
C6000
10UF
0.1uF
20%
2 6.3V
X5R
603
20%
2 10V
CERM
402
C6002
0.1uF
20%
2 10V
CERM
402
C6003
0.1uF
SM
VOLTAGE=3.3V
20%
2 10V
CERM
402
GPIO - 3.3V
1
C6004
0.1uF
AC10
AC9
AD10
AD9
AG7
C6005
0.1uF
20%
2 10V
CERM
402
VDDR4
C6001
PP3V3_GPU_VDDR3
20%
2 10V
CERM
402
C6010
10UF
C6006
20%
10V
2 CERM
402
C6011
0.1uF
20%
2 6.3V
X5R
603
(Max Current varies, depends on usage)
0.1uF
C6012
0.1uF
20%
10V
2 CERM
402
20%
2 10V
CERM
402
DVO I/O (EXT.TMDS) - 1.5V/1.8V
C6013
0.1uF
20%
10V
2 CERM
402
10
=PP1V8_GPU_DVO
DVO_1V8
C6014
0.1uF
L6010
C6015
FERR-10-OHM-500MA
0.1uF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
53
PP1V5R3V3_GPU_VDDR4
MAKE_BASE=TRUE
VOLTAGE=1.8V
44 43 10
10
DVO_1V5
L6011
FERR-10-OHM-500MA
FERR-10-OHM-500MA
VDDP
(20mA)
1
SM
1
2
PP1V5_GPU_AGP
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5 mmSM
=PP1V5R3V3_DVO_VREF
0.1uF
0.1uF
0.1uF
20%
10V
2 CERM
402
20%
10V
2 CERM
402
0.1uF
20%
10V
2 CERM
402
10UF
AGP 4X I/O - 1.5V
20%
6.3V
2 X5R
603
C6025 1 C6026 1 C6027 1 C6028 1 C6029

0.01uF
0.01uF
0.01uF
20%
16V
2 CERM
402
20%
2 16V
CERM
402
20%
16V
2 CERM
402
0.01uF
20%
16V
2 CERM
402
0.01uF
20%
2 16V
CERM
402
51
=PP1V8_GPU_LVDS_PLL
L6048
(40mA)
FERR-220-OHM
C6030 1 C6031 1 C6032 1 C6033

0.1uF
0.1uF
0.1uF
20%
2 10V
CERM
402
20%
2 10V
CERM
402
20%
2 10V
CERM
402
0.1uF
20%
2 10V
CERM
402
C6048
10UF
PP1V8_GPU_LVDS_PLL
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.25
C6049
2
0402
mm
LVDS PLL - 1.8V
0.01uF
20%
2 6.3V
X5R
603
20%
2 16V
CERM
402
L6043
FERR-220-OHM
10
=PP1V8_GPU_PANEL_IO 1
PP1V8_GPU_PANEL_IO 53
VOLTAGE=1.8V
0402
LPVDD
AJ20
LVDDR_18_0
LVDDR_18_1
AE15
AF21
LVDDR_25_0
LVDDR_25_1
AE17
AE20
LVDS I/O - 1.8V

1
C6043 1 C6044
10UF
2 10V
CERM
402
0.1uF
20%
2 6.3V
X5R
603
C6045
0.1uF
20%
2 10V
CERM
402
C6046
0.01uF
20%
2 10V
CERM
402
20%
2 16V
CERM
402
ALSO TXVDDR
(180mA)
C6047
0.01uF
20%
2 16V
CERM
402
10
C6075
0.1uF
20%
10V
2 CERM
402
C6076
0.1uF
20%
10V
2 CERM
402
C6077
0.01uF
20%
16V
2 CERM
402
C6078
0.01uF
20%
16V
2 CERM
402
L6040
0.01uF
20%
16V
2 CERM
402
N6
F18
1
1
C6080
10UF
20%
2 6.3V
X5R
603
C6085
0.1uF
20%
10V
2 CERM
402
C6081
10UF
20%
2 6.3V
X5R
603
C6086
0.1uF
20%
10V
2 CERM
402
C6082
0.1uF
20%
2 10V
CERM
402
C6087
0.1uF
20%
10V
2 CERM
402
C6083
0.1uF
20%
2 10V
CERM
402
C6088
20%
10V
2 CERM
402
C6084
VSSRH0
VSSRH1
20%
2 10V
CERM
402
C6095
10UF
0.1uF
0.1uF
=PP2V5_GPU_LVDS_IO
GPU_LVDDR_2V5
C6079
VDDRH1
VDDRH0
54
C6020 1 C6021 1 C6022 1 C6023 1 C6024
20%
10V
2 CERM
402
=PP1V5_GPU_DVO
=PP1V5_AGP
L6020
AA23
AA24
AB30
AC23
AC27
AE30
AF27
J30
M23
M24
N30
P23
P27
T23
T24
T30
U27
V23
V24
W30
Y27
SM
20%
2 6.3V
X5R
603
F19
M6
C6096
0.01uF
20%
2 16V
CERM
402
C6040
10UF
C6097
20%
2 6.3V
X5R
603
0.01uF
20%
2 16V
CERM
402
C6041
0.01uF
20%
2 16V
CERM
402
FERR-10-OHM-500MA
(350mA)
1
2
PP2V5R2V8_GPU_LVDS_IO
VOLTAGE=2.8V
SM
MIN_NECK_WIDTH=0.25
mm
10 =PP2V8_GPU_LVDS_IO
1 C6042
GPU_LVDDR_2V8
0.01uF
L6041
20%
2 16V
CERM
402
FERR-10-OHM-500MA
1
2
SM
LVDS I/O - 2.5V/2.8V
C6089
0.1uF
20%
10V
2 CERM
402
GPU (M11) I/O Power
C6090
0.1uF
20%
2 10V
CERM
402
C6091
0.1uF
20%
2 10V
CERM
402
C6092
0.01uF
20%
2 16V
CERM
402
C6093
0.01uF
20%
2 16V
CERM
402
SYNC_MASTER=N/A
C6094
0.01uF
SYNC_DATE=N/A
20%
2 16V
CERM
402

L6095
FERR-220-OHM
1
0402
PP1V8_GPU_VDD_MEM_CLK
VOLTAGE=1.8V
SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
60
115
SHT
OF
NONE
8
Page Notes

(NONE)
48 42
RP6101
FB_A_ADDR_R<11..0>
NO_TEST=YES

- GPU_MEMIO_1V8
- GPU_MEMIO_2V5
5%
1/16W
SM-LF
OMIT
CRITICAL
FB_A_DQ_R<63..0>
48 42
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
M11P
BGA
(4 OF 8)
MEMORY INTERFACE A
L25
L26
K25
K26
J26
H25
H26
G26
G30
D29
D28
E28
E29
G29
G28
F28
G25
F26
E26
F25
E24
F23
E23
D22
B29
C29
C25
C27
B28
B25
C26
B26
F17
E17
D16
F16
E15
F14
E14
F13
C17
B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10
C9
B9
B10
E13
E12
E10
F12
F11
E9
F9
F8
DQMA_0*
DQMA_1*
DQMA_2*
DQMA_3*
DQMA_4*
DQMA_5*
DQMA_6*
DQMA_7*
J25
F29
E25
A27
F15
C15
C11
E11
42 48
0
1
2
3
4
5
6
7
8
9
10
11
42 48
12
13
14
42 48
15
16
17
18
19
20
21
22
23
FB_A_DQS_R<7..0>
24
42 48
25
QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7
J27
F30
F24
B27
E16
B16
B11
F10
0
26
1
27
2
28
3
29
4
30
5
31
6
32
7
33
34
35
36
37
38
39
40
41
42
43
CLKA0
CLKA0*
B21 FB_A_CLKDDR_0_P_R
C20 FB_A_CLKDDR_0_N_R
CLKA1
CLKA1*
C18 FB_A_CLKDDR_1_P_R
A18 FB_A_CLKDDR_1_N_R
44
42 48
45
42 48
46
42 48
47
42 48
48
49
CKEA
B19 FB_A_CKE_R
42 48
50
51
RASA*
A19 FB_A_RAS_L_R
42 48
52
53
CASA*
E18 FB_A_CAS_L_R
42 48
54
55
WEA*
E19 FB_A_WE_L_R
CSA_0*
CSA_1*
E20 FB_A_CS_L_R
F20 NC
42 48
56
57
42 48
58
59
60
61
62
63
B7 MVREFD
B8 MVREFS
47 10
E22 0
B22 1
B23 2
B24 3
C23 4
C22 5
F22 6
F21 7
C21 8
A24 9
C24 10
A25 11
FB_A_BA_R<1..0>
E21 0
B20 1
C19 NC
FB_A_DQM_R<7..0>
DIMA_0
DIMA_1
D7
F7
E7
G6
G5
F5
E5
C4
B5
C5
A4
B4
C2
D3
D1
D2
G4
H6
H5
J6
K5
K4
L6
L5
G2
F3
H2
E2
F2
J3
F1
H3
U6
U5
U3
V6
W5
W4
Y6
Y5
U2
V2
V1
V3
W3
Y2
Y3
AA2
AA6
AA5
AB6
AB5
AD6
AD5
AE5
AE4
AB2
AB3
AC2
AC3
AD3
AE1
AE2
AE3
FB_B_ADDR_R<11..0>
U5700
DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
M11P
BGA
(5 OF 8)
MEMORY INTERFACE B
FB_A_ADDR_R<11..0>
U5700
0
=PP1V8R2V5_GPU_FB_VIO
10
R6190
VOLTAGE=0.9V
GPU_MVREFS
C6190 1
10uF
20%
6.3V
X5R 2
603
1%
1/16W
MF-LF
2 402
1K
VOLTAGE=0.9V
GPU_MVREFD
1
C6191 R6191
C6192 1
1K
0.1uF
10%
16V
2 X5R
402
1%
1/16W
MF-LF
2 402
10uF
10%
16V
2 X5R
402
6
7
11
FB_B_BA_R<1..0>
42 48
F6
B3
K6
G1
V5
W1
AC5
AD1
10
48 42
FB_A_BA_R<1..0>
NO_TEST=YES
0
48 42
FB_B_BA_R<1..0>
NO_TEST=YES
5%
1/16W
SM-LF
10
RP6150
0
11
5%
1/16W
SM-LF
R6153
0
FB_A_CS_L_R
NO_TEST=YES
5%
1/16W
MF-LF
402
FB_B_BA<1..0>
NO_TEST=YES
50
FB_B_CS_L
50
FB_B_RAS_L
NO_TEST=YES
50
FB_B_CAS_L
NO_TEST=YES
50
FB_B_WE_L
NO_TEST=YES
50
FB_B_CKE
50
5%
1/16W
MF-LF
402
R6154
R6155
5%
1/16W
MF-LF
402
CLKB1
CLKB1*
T2
T3
FB_B_CLKDDR_1_P_R
FB_B_CLKDDR_1_N_R
CKEB
R3
FB_B_CKE_R
42 48
48 42
42 48
48 42
42 48
5%
1/16W
MF-LF
402
42 48
WEB*
T6
FB_B_WE_L_R
42 48
CSB_0*
CSB_1*
R5
R6
FB_B_CS_L_R
42 48
NC
FB_A_RAS_L
NO_TEST=YES
FB_A_CAS_L
NO_TEST=YES
R6109
0
FB_B_CS_L_R
NO_TEST=YES
49
48 42
FB_A_WE_L
NO_TEST=YES
FB_A_CKE
49
49
49
48 42
48 42
48 42
5%
1/16W
MF-LF
402
FB_A_CLKDDR_0_P_R
NO_TEST=YES
10
FB_A_CLKDDR_0_P
FB_A_CLKDDR_1_P_R
NO_TEST=YES
10
5%
1/16W
SM-LF
48 42
FB_A_CLKDDR_1_N_R
NO_TEST=YES
FB_B_CAS_L_R
NO_TEST=YES
FB_B_CKE_R
NO_TEST=YES
48 42
FB_A_DQM_R<7..0>
48 42
FB_A_DQS_R<7..0>
E3 NC
AA3 NC
R6194
48 42
FB_A_DQ_R<63..0>
10
R6159
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
49
48 42
FB_B_CLKDDR_0_P_R
NO_TEST=YES
FB_A_CLKDDR_0_N
49
48 42
FB_A_CLKDDR_1_P
49
48 42
FB_B_CLKDDR_0_N_R
NO_TEST=YES
FB_B_CLKDDR_1_P_R
NO_TEST=YES
10
5%
1/16W
SM-LF
FB_A_CLKDDR_1_N
49
48 42
NO_TEST=YES
NO_TEST=YES
FB_B_CLKDDR_0_P
50
FB_B_CLKDDR_0_N
50
FB_B_CLKDDR_1_P
50
FB_B_CLKDDR_1_N
50
RP6158
RP6159
10
10
5%
1/16W
SM-LF
5%
1/16W
SM-LF
NO_TEST=YES
45.3
R6158
10
5%
1/16W
SM-LF
RP6159
1
FB_B_CLKDDR_1_N_R
NO_TEST=YES
5%
1/16W
SM-LF
GPU_MEMTEST
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
FB_B_WE_L_R
NO_TEST=YES
RP6109
1
R6156
FB_B_RAS_L_R
NO_TEST=YES
RP6158
FB_A_CLKDDR_0_N_R
NO_TEST=YES
5%
1/16W
MF-LF
402
RP6108
RP6109
48 42
R6157
5%
1/16W
MF-LF
402
5%
1/16W
SM-LF
FB_B_CAS_L_R
R6108
48 42
RP6108
42 48
FB_B_RAS_L_R
B6
E8
C8
FB_A_CKE_R
NO_TEST=YES
42 48
5%
1/16W
MF-LF
402
FB_A_WE_L_R
NO_TEST=YES
42 48
49
R6106
FB_A_RAS_L_R
NO_TEST=YES
FB_A_CAS_L_R
NO_TEST=YES
FB_A_CS_L
10
5%
1/16W
SM-LF
FB_A_DQM<7..0>
MAKE_BASE=TRUE
FB_A_DQS<7..0>
MAKE_BASE=TRUE
FB_A_DQ<63..0>
MAKE_BASE=TRUE
49
48 42
FB_B_DQM_R<7..0>
49
48 42
FB_B_DQS_R<7..0>
49
48 42
FB_B_DQ_R<63..0>
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
FB_B_DQM<7..0>
MAKE_BASE=TRUE
FB_B_DQS<7..0>
MAKE_BASE=TRUE
FB_B_DQ<63..0>
MAKE_BASE=TRUE
=PP1V8_GPU_MEMVMODE
R6198
5%
1/16W
MF-LF
2 402
SYNC_MASTER=N/A
SYNC_DATE=N/A

GPU_MEMIO_2V5
R61971
4.7K
5%
1/16W
MF-LF
402 2
GPU_MEMIO_1V8
R6199
4.7K
5%
1/16W
MF-LF
2 402
SIZE
DRAWING NUMBER
REV.
C
051-6929
61
115
SHT
OF
NONE
50
GPU (M11) Frame Buffer I/F
4.7K
SCALE
50
GPU_MEMIO_2V5
1
APPLE COMPUTER INC.
50
1%
1/16W
MF-LF
2 402
GPU_MEMVMODE1
GPU_MEMVMODE0
1%
1/16W
MF-LF
2 402
11
49
5%
1/16W
MF-LF
402
R6105
48 42
5%
1/16W
MF-LF
402 2
48 42
1%
1/16W
MF-LF
2 402
11
RP6150
R6104
FB_B_CLKDDR_0_P_R
FB_B_CLKDDR_0_N_R
DIMB_0
DIMB_1
5%
1/16W
SM-LF
FB_A_BA<1..0>
NO_TEST=YES
5%
1/16W
MF-LF
402
N1
N2
TEST_MCLK
TEST_YCLK
MEMTEST
RP6151
5%
1/16W
SM-LF
CLKB0
CLKB0*
T5
10
RP6151
5%
1/16W
SM-LF
R6103
48 42
CASB*
R6107
R2
5%
1/16W
SM-LF
5%
1/16W
SM-LF
10
5%
1/16W
SM-LF
RP6100
42 48
48 42
RASB*
RP6152
RP6152
5%
1/16W
SM-LF
5%
1/16W
SM-LF
RP6100
5%
1/16W
SM-LF
RP6150
RP6100
5%
1/16W
SM-LF
5
RP6151
5%
1/16W
SM-LF
RP6150
5%
1/16W
SM-LF
50
RP6152
5%
1/16W
SM-LF
RP6102
42 48
5%
1/16W
SM-LF
5%
1/16W
SM-LF
RP6102
NC
5%
1/16W
SM-LF
FB_B_ADDR<11..0>
NO_TEST=YES
10
5%
1/16W
SM-LF
5%
1/16W
SM-LF
RP6101
RP6102
RP6152
5%
1/16W
SM-LF
48 42
4.7K
1
C6193 R6193
1K
0.1uF
20%
6.3V
X5R 2
603
RP6151
FB_B_ADDR_R<11..0>
NO_TEST=YES
5%
1/16W
SM-LF
RP6101
48 42
RP6100
11
QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7
R61961
R6192
1K
E6
B2
J5
G3
W6
W2
AC6
AD2
5%
1/16W
SM-LF
42 48
FB_B_DQS_R<7..0>
GPU_MEMIO_1V8
1
FB_B_DQM_R<7..0>
DQMB_0*
DQMB_1*
DQMB_2*
DQMB_3*
DQMB_4*
DQMB_5*
DQMB_6*
DQMB_7*
C6 MEMVMODE_0
C7 MEMVMODE_1
D30 NC
B13 NC
N5
M1
M3
L3
L2
M2
M5
P6
N3
K2
K3
J2
P5
P3
P2
49
RP6102
RP6101
OMIT
CRITICAL
FB_B_DQ_R<63..0>
FB_A_ADDR<11..0>
NO_TEST=YES
48 42
GPU Frame Buffer Series Term

- =PP1V8R2V5_GPU_FB_VIO
- =PP1V8_GPU_MEMVMODE
CRITICAL
OMIT
CRITICAL
OMIT
U6200
U6250
K4D553235F
SDRAM_GDDR-2MX32X4
50 49 10
=PP1V8_FB_VDD
1
C6200
10uF
20%
2 4V
X5R
603
C6201
0.1uF
10%
2 16V
X5R
402
C6202
0.1uF
10%
2 16V
X5R
402
C6203
0.1uF
10%
2 16V
X5R
402
C6204
0.1uF
10%
2 16V
X5R
402
D8
E7
E4
E8
E11
L4
50 49 10
VDD
VSS
D7
=PP1V8_FB_VDD
1
C6250
10uF
20%
2 4V
X5R
603
E10
L7
K6
C6251
0.1uF
10%
2 16V
X5R
402
C6252
0.1uF
C6253
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
C6254
0.1uF
10%
2 16V
X5R
402
E5
(2 OF 2)
D8
E7
E4
E8
E11
L4
K7
VDD
VSS
L7
C6210
10uF
20%
4V
2 X5R
603
C6214
10uF
C6218
0.1uF
10%
16V
2 X5R
402
C6215
K8
L8
K8
K9
L11
K9
C6216
C6219
0.1uF
0.1uF
C6217
0.1uF
I245
F6
I246
C8
F7
I247
C10
F8
F9
C12
F9
G6
E3
G6
E12
G7
C6220
C6221
0.1uF
10%
16V
2 X5R
402
10%
16V
2 X5R
402
F7
C10
F8
C12
E3
E12
G7
10uF
H6
G11
H7
J4
H8
J11
H9
K4
J6
K11
J7
C6264
10%
16V
2 X5R
402
C6268
0.1uF
10%
16V
2 X5R
402
C6261
10uF
20%
4V
2 X5R
603
0.1uF
G9
G4
C6260
20%
4V
2 X5R
603
G8
VSS_THERM
C6265
0.1uF
0.1uF
10%
16V
2 X5R
402
C6266
0.1uF
C5
C6263
0.1uF
C6267
0.1uF
F4
10%
16V
2 X5R
402
10%
16V
2 X5R
402
C6269
10%
16V
2 X5R
402
10%
16V
2 X5R
402
0.1uF
10%
16V
2 X5R
402
C6262
C6270
0.1uF
C6271
10%
16V
2 X5R
402
R6240
J4
H8
I255
J11
H9
I256
K4
J6
I257
K11
J7
VREF
1K
5%
1/16W
MF-LF
2 402
VSSQ
R6291
1K
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
49 48
N5
C6291
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
B2
FB_A_DQS<3>
FB_A_DQS<2>
FB_A_DQS<1>
FB_A_DQS<0>
H13
H2
B13
B3
FB_A_DQM<3>
FB_A_DQM<2>
FB_A_DQM<1>
FB_A_DQM<0>
H12
H3
B12
N4
FB_A_BA<0>
FB_A_BA<1>
M5
M11
FB_A_CLKDDR_0_P
FB_A_CLKDDR_0_N
FB_A_CKE
FB_A_CS_L
FB_A_RAS_L
FB_A_CAS_L
FB_A_WE_L
M12
N12
N2
M2
L2
L3
1
R6245
R6246
56
56
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
FB_A_DDRCLK_0_RC
1
C6245
470pF
10%
2 50V
CERM
402
NC
NC
NC
NC
NC
NC
NC
NC
NC
C4
C11
L12
VSSQ
NC
L13
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
FB_A_CKE
FB_A_CS_L
FB_A_ADDR<11..0>
FB_A_BA<1..0>
FB_A_RAS_L
FB_A_CAS_L
FB_A_WE_L
FB_A_DQS<7..0>
FB_A_DQM<7..0>
FB_A_DQ<63..0>
F10
G5
G10
G10
H5
H5
H10
H10
J5
J5
J10
J10
K5
K5
K10
K10
CRITICAL
OMIT
48 49
48 49
48 49
48 49
48 49
48 49
48 49
48 49
48 49
K4D553235F
SDRAM_GDDR-2MX32X4
49 48
B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
FB_A_DQ<26> 48
FB_A_DQ<29> 48
FB_A_DQ<30> 48
FB_A_DQ<31> 48
FB_A_DQ<24> 48
FB_A_DQ<25> 48
FB_A_DQ<28> 48
FB_A_DQ<27> 48
FB_A_DQ<16> 48
FB_A_DQ<17> 48
FB_A_DQ<21> 48
FB_A_DQ<19> 48
FB_A_DQ<23> 48
FB_A_DQ<22> 48
FB_A_DQ<18> 48
FB_A_DQ<20> 48
FB_A_DQ<8> 48
FB_A_DQ<13> 48
FB_A_DQ<12> 48
FB_A_DQ<9> 48
FB_A_DQ<15> 48
FB_A_DQ<10> 48
FB_A_DQ<11> 48
FB_A_DQ<14> 48
FB_A_DQ<0> 48
FB_A_DQ<1> 48
FB_A_DQ<2> 48
FB_A_DQ<3> 48
FB_A_DQ<5> 48
FB_A_DQ<7> 48
FB_A_DQ<4> 48
FB_A_DQ<6> 48
49
49 48
49
49 48
49
49 48
49
49 48
49
49 48
49
49 48
49
49 48
49
49 48
49
49 48
49
49 48
49
49 48
49
49 48
49
49 48
49
49 48
49
49 48
N5
FB_A_ADDR<0>
FB_A_ADDR<1>
FB_A_ADDR<2>
FB_A_ADDR<3>
FB_A_ADDR<4>
FB_A_ADDR<5>
FB_A_ADDR<6>
FB_A_ADDR<7>
FB_A_ADDR<8>
FB_A_ADDR<9>
FB_A_ADDR<10>
FB_A_ADDR<11>
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
B2
FB_A_DQS<6>
FB_A_DQS<4>
FB_A_DQS<7>
FB_A_DQS<5>
H13
H2
B13
49
49
49 48
49
49 48
49
49 48
49
49 48
49
49 48
49
49 48
B3
FB_A_DQM<6>
FB_A_DQM<4>
FB_A_DQM<7>
FB_A_DQM<5>
H12
H3
B12
N4
FB_A_BA<0>
FB_A_BA<1>
M5
49
49
49 48
49
49 48
49
49 48
49
49 48
49
49 48
49
49 48
49
49 48
M11
FB_A_CLKDDR_1_P
FB_A_CLKDDR_1_N
FB_A_CKE
FB_A_CS_L
FB_A_RAS_L
FB_A_CAS_L
FB_A_WE_L
M12
N12
N2
M2
L2
L3
49
49
M13
R6295
R6296
56
56
5%
1/16W
MF-LF
402 2
L9
NC
M10 NC
5%
1/16W
MF-LF
402 2
FB_A_DDRCLK_1_RC
1
M3
C6295
470pF
M4
10%
2 50V
CERM
402
N3
48 49
F5
G5
NC
NC
NC
NC
NC
NC
NC
NC
NC
C4
C11
A0 300MHZ-BGA-LF
(1 OF 2)
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8/AP
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQS0
DQ12
DQS1
DQ13
DQS2
DQ14
DQS3
DQ15
DQ16
DM0
DQ17
DM1
DQ18
DM2
DQ19
DM3
DQ20
BA0
DQ21
BA1
DQ22
DQ23
CLK
DQ24
CLK*
DQ25
CKE
DQ26
CS*
DQ27
RAS*
DQ28
CAS*
DQ29
WE*
DQ30
DQ31
MCL
H4
H11
L12
L13
NC
RFU1
RFU2
B7
FB_A_DQ<54> 48
FB_A_DQ<53> 48
FB_A_DQ<55> 48
FB_A_DQ<52> 48
FB_A_DQ<49> 48
FB_A_DQ<51> 48
FB_A_DQ<50> 48
FB_A_DQ<48> 48
FB_A_DQ<34> 48
FB_A_DQ<36> 48
FB_A_DQ<35> 48
FB_A_DQ<38> 48
FB_A_DQ<33> 48
FB_A_DQ<39> 48
FB_A_DQ<32> 48
FB_A_DQ<37> 48
FB_A_DQ<60> 48
FB_A_DQ<59> 48
FB_A_DQ<63> 48
FB_A_DQ<62> 48
FB_A_DQ<56> 48
FB_A_DQ<61> 48
FB_A_DQ<58> 48
FB_A_DQ<57> 48
FB_A_DQ<41> 48
FB_A_DQ<40> 48
FB_A_DQ<42> 48
FB_A_DQ<47> 48
FB_A_DQ<43> 48
FB_A_DQ<45> 48
FB_A_DQ<46> 48
FB_A_DQ<44> 48
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
GPU Frame Buffer A
49
49
SYNC_MASTER=N/A
49
49
49

M13
L9
SYNC_DATE=N/A
NC
M10 NC

M3
M4
SIZE
N3
APPLE COMPUTER INC.
DRAWING NUMBER
REV.
C
051-6929
62
115
SHT
OF
NONE
48 49
SCALE
48 49
E9
F10
U6250
RFU1
RFU2
FB_A_CLK_1
E6
10%
16V
2 X5R
402
CRITICAL
OMIT
MCL
H4
H11
RAM_DIFF
48 49
D11
U6200
A0 300MHZ-BGA-LF
(1 OF 2)
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8/AP
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQS0
DQ12
DQS1
DQ13
DQS2
DQ14
DQS3
DQ15
DQ16
DM0
DQ17
DM1
DQ18
DM2
DQ19
DM3
DQ20
BA0
DQ21
BA1
DQ22
DQ23
CLK
DQ24
CLK*
DQ25
CKE
DQ26
CS*
DQ27
RAS*
DQ28
CAS*
DQ29
WE*
DQ30
DQ31
RAM_DIFF
FB_A_CLKDDR_1_P
FB_A_CLKDDR_1_N
D9
0.1uF
5%
1/16W
MF-LF
2 402
E9
F5
FB_A_ADDR<0>
FB_A_ADDR<1>
FB_A_ADDR<2>
FB_A_ADDR<3>
FB_A_ADDR<4>
FB_A_ADDR<5>
FB_A_ADDR<6>
FB_A_ADDR<7>
FB_A_ADDR<8>
FB_A_ADDR<9>
FB_A_ADDR<10>
FB_A_ADDR<11>
FB_A_CLK_1
D10
K4D553235F
SDRAM_GDDR-2MX32X4
49 48
FB_A_CLK_0
RAM_DIFF
D6
E6
10%
16V
2 X5R
402
RAM_DIFF
RAM_DIFF
48 49
D5
FB_C1_VREF
D11
0.1uF
RAM_DIFF
FB_A_CLKDDR_0_P
FB_A_CLKDDR_0_N
D4
D9
C6241
FB_A_CLK_0
DIFFERENTIAL_PAIR
B11
5%
1/16W
MF-LF
2 402
D10
R6241
RAM_DIFF
B4
1K
D5
I254
PHYSICAL
RAM_DIFF
J9
D6
I252
H7
R6290
D4
FB_C0_VREF
I253
G9
G11
B11
5%
1/16W
MF-LF
2 402
I251
SPACING
J8
B4
1K
I250
H6
J9
I249
G4
N13
VREF
I248
G8
VSS_THERM
F11
0.1uF
10%
16V
2 X5R
402
VDDQ
J8
N13
I244
L10
C8
F11
L5
C7
F6
VDDQ
NET_TYPE
C3
=PP1V8_FB_VDDQ
1
C7
F4
10%
16V
2 X5R
402
0.1uF
10%
16V
2 X5R
402
50 49 10
C5
C6213
10%
16V
2 X5R
402
10%
16V
2 X5R
402
10%
16V
2 X5R
402
0.1uF
10%
16V
2 X5R
402
0.1uF
C6212
0.1uF
20%
4V
2 X5R
603
0.1uF
10%
16V
2 X5R
402
C6211
K7
L8
L10
1
K6
L11
C3
=PP1V8_FB_VDDQ

(NONE)
E10
L5
50 49 10

(NONE)
300MHZ-BGA-LF
E5
(2 OF 2)
1
Page Notes
- =PP1V8_FB_VDD
- =PP1V8_FB_VDDQ
K4D553235F
SDRAM_GDDR-2MX32X4
300MHZ-BGA-LF
D7
ECSETs provided by GPU
CRITICAL
OMIT
CRITICAL
OMIT
U6300
U6350
K4D553235F
SDRAM_GDDR-2MX32X4
50 49 10
=PP1V8_FB_VDD
1
C6300
10uF
20%
2 4V
X5R
603
C6301
0.1uF
10%
2 16V
X5R
402
C6302
0.1uF
10%
2 16V
X5R
402
C6303
0.1uF
10%
2 16V
X5R
402
C6304
0.1uF
10%
2 16V
X5R
402
D8
E7
E4
E8
E11
L4
50 49 10
VDD
VSS
D7
=PP1V8_FB_VDD
1
C6350
10uF
20%
2 4V
X5R
603
E10
L7
K6
C6351
0.1uF
10%
2 16V
X5R
402
C6352
0.1uF
C6353
0.1uF
10%
2 16V
X5R
402
10%
2 16V
X5R
402
C6354
0.1uF
10%
2 16V
X5R
402
E5
(2 OF 2)
D8
E7
E4
E8
E11
L4
K7
VDD
VSS
L7
C6310
10uF
20%
4V
2 X5R
603
C6314
10uF
C6318
0.1uF
10%
16V
2 X5R
402
C6315
K8
L8
K8
K9
L11
K9
C6316
C6319
0.1uF
0.1uF
C6317
0.1uF
I244
F6
I245
C8
F7
I247
C10
F8
F9
C12
F9
G6
E3
G6
E12
G7
C6320
C6321
0.1uF
10%
16V
2 X5R
402
10%
16V
2 X5R
402
F7
C10
F8
C12
E3
E12
G7
10uF
H6
G11
H7
J4
H8
J11
H9
K4
J6
K11
J7
C6364
10%
16V
2 X5R
402
C6368
0.1uF
10%
16V
2 X5R
402
C6361
10uF
20%
4V
2 X5R
603
0.1uF
G9
G4
C6360
20%
4V
2 X5R
603
G8
VSS_THERM
C6365
0.1uF
0.1uF
10%
16V
2 X5R
402
C6366
10%
16V
2 X5R
402
C6369
C5
C6363
0.1uF
0.1uF
10%
16V
2 X5R
402
10%
16V
2 X5R
402
0.1uF
10%
16V
2 X5R
402
C6362
C6370
0.1uF
C6367 removed
due to MCO
violation
F4
C6371
10%
16V
2 X5R
402
R6340
J4
H8
I254
J11
H9
I255
K4
J6
I256
K11
J7
VREF
1K
5%
1/16W
MF-LF
2 402
VSSQ
R6391
1K
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
50 48
N5
C6391
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
B2
FB_B_DQS<3>
FB_B_DQS<0>
FB_B_DQS<1>
FB_B_DQS<2>
H13
H2
B13
B3
FB_B_DQM<3>
FB_B_DQM<0>
FB_B_DQM<1>
FB_B_DQM<2>
H12
H3
B12
N4
FB_B_BA<0>
FB_B_BA<1>
M5
M11
FB_B_CLKDDR_0_P
FB_B_CLKDDR_0_N
FB_B_CKE
FB_B_CS_L
FB_B_RAS_L
FB_B_CAS_L
FB_B_WE_L
M12
N12
N2
M2
L2
L3
1
R6345
R6346
56
56
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
FB_B_DDRCLK_0_RC
1
C6345
470pF
10%
2 50V
CERM
402
NC
NC
NC
NC
NC
NC
NC
NC
NC
C4
C11
L12
VSSQ
NC
L13
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
FB_B_CKE
FB_B_CS_L
FB_B_ADDR<11..0>
FB_B_BA<1..0>
FB_B_RAS_L
FB_B_CAS_L
FB_B_WE_L
FB_B_DQS<7..0>
FB_B_DQM<7..0>
FB_B_DQ<63..0>
F10
G5
G10
G10
H5
H5
H10
H10
J5
J5
J10
J10
K5
K5
K10
K10
CRITICAL
OMIT
48 50
48 50
48 50
48 50
48 50
48 50
48 50
48 50
48 50
K4D553235F
SDRAM_GDDR-2MX32X4
50 48
B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
FB_B_DQ<31> 48
FB_B_DQ<24> 48
FB_B_DQ<29> 48
FB_B_DQ<26> 48
FB_B_DQ<30> 48
FB_B_DQ<25> 48
FB_B_DQ<28> 48
FB_B_DQ<27> 48
FB_B_DQ<1> 48
FB_B_DQ<2> 48
FB_B_DQ<3> 48
FB_B_DQ<4> 48
FB_B_DQ<5> 48
FB_B_DQ<0> 48
FB_B_DQ<7> 48
FB_B_DQ<6> 48
FB_B_DQ<12> 48
FB_B_DQ<10> 48
FB_B_DQ<11> 48
FB_B_DQ<8> 48
FB_B_DQ<13> 48
FB_B_DQ<9> 48
FB_B_DQ<14> 48
FB_B_DQ<15> 48
FB_B_DQ<23> 48
FB_B_DQ<20> 48
FB_B_DQ<21> 48
FB_B_DQ<22> 48
FB_B_DQ<19> 48
FB_B_DQ<17> 48
FB_B_DQ<18> 48
FB_B_DQ<16> 48
50
50 48
50
50 48
50
50 48
50
50 48
50
50 48
50 48
50
50
50 48
50
50 48
50
50 48
50
50 48
50
50 48
50
50 48
50
50 48
50
50 48
50
50 48
N5
FB_B_ADDR<0>
FB_B_ADDR<1>
FB_B_ADDR<2>
FB_B_ADDR<3>
FB_B_ADDR<4>
FB_B_ADDR<5>
FB_B_ADDR<6>
FB_B_ADDR<7>
FB_B_ADDR<8>
FB_B_ADDR<9>
FB_B_ADDR<10>
FB_B_ADDR<11>
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
B2
FB_B_DQS<6>
FB_B_DQS<4>
FB_B_DQS<7>
FB_B_DQS<5>
H13
H2
B13
50
50
50 48
50
50 48
50
50 48
50
50 48
50
50 48
50
50 48
B3
FB_B_DQM<6>
FB_B_DQM<4>
FB_B_DQM<7>
FB_B_DQM<5>
H12
H3
B12
N4
FB_B_BA<0>
FB_B_BA<1>
M5
50
50
50 48
50
50 48
50
50 48
50
50 48
50
50 48
50
50 48
50
50 48
M11
FB_B_CLKDDR_1_P
FB_B_CLKDDR_1_N
FB_B_CKE
FB_B_CS_L
FB_B_RAS_L
FB_B_CAS_L
FB_B_WE_L
M12
N12
N2
M2
L2
L3
50
50
M13
R6395
R6396
56
56
5%
1/16W
MF-LF
402 2
L9
NC
M10 NC
5%
1/16W
MF-LF
402 2
FB_B_DDRCLK_1_RC
1
M3
C6395
470pF
M4
10%
2 50V
CERM
402
N3
48 50
F5
G5
NC
NC
NC
NC
NC
NC
NC
NC
NC
C4
C11
A0 300MHZ-BGA-LF
(1 OF 2)
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8/AP
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQS0
DQ12
DQS1
DQ13
DQS2
DQ14
DQS3
DQ15
DQ16
DM0
DQ17
DM1
DQ18
DM2
DQ19
DM3
DQ20
BA0
DQ21
BA1
DQ22
DQ23
CLK
DQ24
CLK*
DQ25
CKE
DQ26
CS*
DQ27
RAS*
DQ28
CAS*
DQ29
WE*
DQ30
DQ31
MCL
H4
H11
L12
L13
NC
RFU1
RFU2
B7
FB_B_DQ<51> 48
FB_B_DQ<53> 48
FB_B_DQ<55> 48
FB_B_DQ<54> 48
FB_B_DQ<48> 48
FB_B_DQ<52> 48
FB_B_DQ<49> 48
FB_B_DQ<50> 48
FB_B_DQ<32> 48
FB_B_DQ<35> 48
FB_B_DQ<33> 48
FB_B_DQ<34> 48
FB_B_DQ<36> 48
FB_B_DQ<37> 48
FB_B_DQ<38> 48
FB_B_DQ<39> 48
FB_B_DQ<63> 48
FB_B_DQ<60> 48
FB_B_DQ<62> 48
FB_B_DQ<61> 48
FB_B_DQ<56> 48
FB_B_DQ<58> 48
FB_B_DQ<59> 48
FB_B_DQ<57> 48
FB_B_DQ<40> 48
FB_B_DQ<41> 48
FB_B_DQ<42> 48
FB_B_DQ<43> 48
FB_B_DQ<47> 48
FB_B_DQ<45> 48
FB_B_DQ<44> 48
FB_B_DQ<46> 48
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
GPU Frame Buffer B
50
50
SYNC_MASTER=N/A
50
50

M13
L9
SYNC_DATE=N/A
50
NC
M10 NC

M3
M4
SIZE
N3
APPLE COMPUTER INC.
DRAWING NUMBER
REV.
C
051-6929
63
115
SHT
OF
NONE
48 50
SCALE
48 50
E9
F10
U6350
RFU1
RFU2
FB_B_CLK_1
E6
10%
16V
2 X5R
402
CRITICAL
OMIT
MCL
H4
H11
RAM_DIFF
48 50
D11
U6300
A0 300MHZ-BGA-LF
(1 OF 2)
DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8/AP
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQS0
DQ12
DQS1
DQ13
DQS2
DQ14
DQS3
DQ15
DQ16
DM0
DQ17
DM1
DQ18
DM2
DQ19
DM3
DQ20
BA0
DQ21
BA1
DQ22
DQ23
CLK
DQ24
CLK*
DQ25
CKE
DQ26
CS*
DQ27
RAS*
DQ28
CAS*
DQ29
WE*
DQ30
DQ31
RAM_DIFF
FB_B_CLKDDR_1_P
FB_B_CLKDDR_1_N
D9
0.1uF
5%
1/16W
MF-LF
2 402
E9
F5
FB_B_ADDR<0>
FB_B_ADDR<1>
FB_B_ADDR<2>
FB_B_ADDR<3>
FB_B_ADDR<4>
FB_B_ADDR<5>
FB_B_ADDR<6>
FB_B_ADDR<7>
FB_B_ADDR<8>
FB_B_ADDR<9>
FB_B_ADDR<10>
FB_B_ADDR<11>
FB_B_CLK_1
D10
K4D553235F
SDRAM_GDDR-2MX32X4
50 48
FB_B_CLK_0
RAM_DIFF
D6
E6
10%
16V
2 X5R
402
RAM_DIFF
RAM_DIFF
48 50
D5
FB_D1_VREF
D11
0.1uF
RAM_DIFF
FB_B_CLKDDR_0_P
FB_B_CLKDDR_0_N
D4
D9
C6341
FB_B_CLK_0
DIFFERENTIAL_PAIR
B11
5%
1/16W
MF-LF
2 402
D10
R6341
RAM_DIFF
B4
1K
D5
I253
PHYSICAL
RAM_DIFF
J9
D6
I250
H7
R6390
D4
FB_D0_VREF
I249
G9
G11
B11
5%
1/16W
MF-LF
2 402
I251
SPACING
J8
B4
1K
I252
H6
J9
I248
G4
N13
VREF
I246
G8
VSS_THERM
F11
0.1uF
10%
16V
2 X5R
402
VDDQ
J8
N13
I243
L10
C8
F11
L5
C7
F6
VDDQ
NET_TYPE
C3
=PP1V8_FB_VDDQ
1
C7
F4
10%
16V
2 X5R
402
0.1uF
10%
16V
2 X5R
402
50 49 10
C5
C6313
10%
16V
2 X5R
402
10%
16V
2 X5R
402
10%
16V
2 X5R
402
0.1uF
10%
16V
2 X5R
402
0.1uF
C6312
0.1uF
20%
4V
2 X5R
603
0.1uF
10%
16V
2 X5R
402
C6311
K7
L8
L10
1
K6
L11
C3
=PP1V8_FB_VDDQ

(NONE)
E10
L5
50 49 10

(NONE)
300MHZ-BGA-LF
E5
(2 OF 2)
1
Page Notes
- =PP1V8_FB_VDD
- =PP1V8_FB_VDDQ
K4D553235F
SDRAM_GDDR-2MX32X4
300MHZ-BGA-LF
D7
ECSETs provided by GPU
8
Page Notes

- =PP3V3_GPU_GPIOS
- =PP2V5_PVDD
- =PP1V8_GPU_LVDS_PLL
- =I2C_GPU_TMDS_SDA - I2C data line for
external TMDS transmitters
- =I2C_GPU_TMDS_SCL - I2C clock line for
external TMDS transmitters

(NONE)
CRITICAL
U6400
MM1571J
SOT-25A-LF
(150mA MAX)
10
=PP2V5_GPU_PVDD
C6400 1
26
GPUPVDD_EN
VIN
CONT NOISE
1uF
VOUT 5
26
VOLTAGE=1.8V
PP1V8_GPU_PVDD
MAKE_BASE=TRUE
1
ATI_PVDD_BYP
47
R6400
0
GND
20%
10V
CERM 2
603
=PP1V8_GPU_LVDS_PLL
5%
1/16W
MF-LF
2 402
C6401 1
0.01uF
20%
16V
CERM 2
402
1_8V_PVDD_STD
C6402
10UF
20%
2 6.3V
X5R
603
OMIT
CRITICAL
PP1V8_GPU_PLL
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.25 mm 1
U5700
M11P
BGA
(2 OF 8)
MPVDD
MPVSS
XTALIN
XTALOUT
=PP3V3_GPU_GPIOS
HPD1
NO STUFF
NO STUFF
NO STUFF
10K
10K
10K
10K
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
NO STUFF
R64701
10K
5%
1/16W
MF-LF
402 2
45
NO STUFF
NO STUFF
NO STUFF
NO STUFF
NO STUFF
NO STUFF
NO STUFF
51
ATI_AGP_FBSKEW<0>
ATI_AGP_FBSKEW<1>
ATI_X1CLK_SKEW<0>
ATI_X1CLK_SKEW<1>
ATI_BUS_CFG<0>
ATI_BUS_CFG<1>
ATI_BUS_CFG<2>
TP_EXTTMDS_RESET_L
TP_ATI_GPIO8
TP_ATI_GPIO9
TP_ATI_GPIO10
TP_ATI_GPIO11
TP_ATI_GPIO12
ATI_MEMTYPE
57
HPD_PWR_SNS_EN
52
ATI_CLK27M_SS
AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2
GPU_VREFG
AG4 VREFG
11
R6451 1R6453 1R6455 1R6457 1R6459 1R6461 1R6463
10K
10K
10K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
10K
10K
10K
10K
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
5%
GPU_VCORE_HI_L
47
PP3V3_GPU_VDDR3
PROPERTIES PROVIDED BY
PAGE INDICATED BY CREF
1
R6420
53 51 10
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
MULTI-FUNCTION GENERAL PURPOSE I/O
10K
MONITOR
INTERFACE
NO STUFF
R6450 1R6452 1R6454 1R6456 1R6458 1R6460 1R6462
TEST
ROM
AK28
AJ28
PP1V8_GPU_MEMPLL
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.25 mm 1
A7
A6
AH28 ATI_CLK27M
AJ29 NC
AF12 GPU_DVI_HPD
AF25 GPU_DVI_DDC_DATA
AF24 GPU_DVI_DDC_CLK
DDC2DATA
DDC2CLK
AE14 LVDS_DDC_DATA
AE13 LVDS_DDC_CLK
DDC3DATA
DDC3CLK
AG24 =I2C_GPU_TMDS_SDA
AG23 =I2C_GPU_TMDS_SCL
TESTEN
ROMCS*
C6404
0.1uF
20%
2 10V
CERM
402
C6405
0.01uF
20%
2 16V
CERM
402
C
L6410
FERR-220-OHM
(20mA)
2
0402
C6410
10UF
20%
2 6.3V
X5R
603
C6411
0.01uF
20%
2 16V
CERM
402
57
57
57
7 56
7 56
8
8
R6499
1
1K
5%
1/16W
MF-LF
402
NC
R6498
AK25 GPU_SSIN_PD
1K
5%
1/16W
MF-LF
402
BUS POWER
MGMT
RSTB_MSK
52
AH27 GPU_TESTEN
AF5
MEMORY PLL - 1.8V
DDC1DATA
DDC1CLK
EXTERNAL
SSC
SSIN
LVDS PLL
AND I/O
GND
NO STUFF
1
C6403
20%
2 6.3V
X5R
603
AE25 NC
AF11 NC
AE11 NC
FERR-220-OHM
(21mA)
0402
10UF
PLLTEST
DPLUS
DMINUS
PVDD
PVSS
53 51 10
L6403
GPU PLL - 1.8V
AG29 GPU_RSTB_MSK
LPVSS
AJ19
LVSSR_0
LVSSR_1
LVSSR_2
LVSSR_3
AE16
AE19
AF15
AF20
R6490
1
5%
1/16W
MF-LF
402
1K
=PP3V3_GPU_GPIOS
1%
1/16W
MF-LF
2 402
VRAM_HYNIX
1
R6422
10K
5%
1/16W
MF-LF
2 402
R6421
1K
ATI_MEMTYPE 51
1%
1/16W
MF-LF
2 402
VRAM_SAMSUNG
1
R6423
C6421
0.1uF
10%
2 16V
X5R
402
10K
5%
1/16W
MF-LF
2 402
GPU (M11) GPIOs/Straps
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
64
115
SHT
OF
NONE
8
Page Notes

- =PP3V3_GPU_CLOCKS
- =PP3V3_GPU_PWRSEQ
- =PPVIN_GPU_LVDDR_LDO
- =PP2V5_GPU_PWRSEQ
- =PP2V5_GPU_LVDDR_LDO
- =PP1V8_GPU_PWRSEQ
- =PP1V5_GPU_PWRSEQ
(NONE)
M11 Power Shutdown Sequencing

- GPU_SS
- GPU_LVDDR_2V8
D
NET_TYPE
SPACING
CLOCK
CLOCK
I54
CLOCK
CLOCK
I55
CLOCK
CLOCK
I50
I51
ATI_CLK27M
PHYSICAL
ATI_CLK27M_SS
I52
CLOCK
CLOCK
CLOCK
CLOCK
10
ATI_CLK27M_R
ATI_CLK27M
ATI_CLK27M_SSIN
10
52
=PP2V5_GPU_PWRSEQ
XW6590
SM
51 52
52
10
=PP1V8_GPU_PWRSEQ
51 52
=PP1V5_GPU_PWRSEQ
52 10
L6500
=PP3V3_GPU_CLOCKS
VOLTAGE=1.8V
DP6590
BAS16TW-X-F
SOT-363
3
PP1V5_GPU_PSNECK
VOLTAGE=1.5V
PP3V3_GPU_OSC
SM
C6500 1
NO STUFF
1
R6503
G6500
C6501
4.7uF
20%
10V
CERM 2
402
VCC
5%
1/16W
MF-LF
402 2
0.1uF
CRITICAL 14
100K
20%
6.3V
2 CERM
805
GPU_SS
27MHZ
ATI_OSC_OE
SM
OE
OUT
GND
(PLACE R6500 CLOSE TO OSC)
R6500
OSC
1
VOLTAGE=3.3V
VOLTAGE=3.3V
FERR-EMI-100-OHM
1
PP3V3_GPU_PSNECK
SOT-363
PP1V8_GPU_PSNECK
XW6592
SM
27M OSC
DP6590
BAS16TW-X-F
XW6591
SM
1
10
VOLTAGE=2.5V
52
ATI_CLK27M_SS_R
ATI_CLK27M_SS
XW6593
SM
BAS16TW-X-F
SOT-363
PP2V5_GPU_PSNECK
=PP3V3_GPU_PWRSEQ
DP6590
DIFFERENTIAL_PAIR
52
ATI_CLK27M_SSIN
52
5%
1/16W
MF-LF
402
R6501
287
ATI_CLK27M_R 1
1%
1/16W
MF-LF
402 2
(PLACE THE OSCILLATOR AND R6501/R6502

CLOSE TO M18 IC)
LVDDR 2.8V LDO

ATI_CLK27M
51 52
GPU_LVDDR_2V8
R65021
CRITICAL
162
U6530
1%
1/16W
MF-LF
402 2
MAX8860EUA27+T
10
=PPVIN_GPU_LVDDR_LDO
GPU_LVDDR_2V8
C6530 1
2.2uF
IN
UMAX1OUT1 1
GND
20%
6.3V
CERM1 2
603
10
GPU_LVDDR_2V8
1
FAULT* 8
CC 6
SET
=PP2V8_GPU_LVDDR_LDO
OUT2 4
SHDN*
MAX8860_FAULT_L
MAX8860_CC
GPU_LVDDR_2V8
C6531
R6530
GPU_LVDDR_2V8
100K
5%
1/16W
MF-LF
2 402
C6532
2.2uF
20%
6.3V
2 CERM1
603
0.033uF
20%
10V
X7R 2
402
IS
SPREAD SPECTRUM SUPPORT
S0=1;S1=M => -1.5% DOWN-SPREAD

52 10
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
353S1188
353S1140
GPU_LVDDR_2V8
U6530
Primary is 2.77V/Alt is 2.82V
TABLE_ALT_ITEM
GPU_SS
=PP3V3_GPU_CLOCKS
L6510
VOLTAGE=3.3V
PP3V3_GPU_SS
FERR-EMI-100-OHM
1
2
SM
GPU_SS
1
C6510
10UF
20%
2 6.3V
X5R
603
NO STUFF
1
R6511
0
5%
1/16W
MF-LF
402 2
GPU_SS
1
R6513
GPU_SS
1
R6512
0
5%
1/16W
MF-LF
402 2
GPU_SS
0.1uF
7 CRITICAL
20%
2 10V
CERM
402
VDD
U6510
CY25811
SOI-LF
52
NC
1 XIN/CLKIN
8 XOUT
SSCLK 5
NC
FRSEL
3
4
S1
S0
ATI_CLK27M_SSIN
5%
1/16W
MF-LF
2 402
CY25811_S1
CY25811_S0
NO STUFF
1
C6511
NO STUFF
1
GPU_SS
R6510
52
ATI_CLK27M_SS_R 1
33
ATI_CLK27M_SS
51 52
5%
1/16W
MF-LF
402
VSS
R6514
5%
1/16W
MF-LF
2 402
GPU (M11) Clocks/Misc
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
65
115
SHT
OF
NONE
Page Notes
NET_TYPE

- =PP2V5_GPU_A2VDD
- =PP1V8_GPU_AVDD
- =PP3V3_GPU_GPIOS
- =PP1V8_GPU_TPVDD
SPACING
I108
I109
ECSETs provided by SI TMDS
I111

(NONE)
I110
I112

- DVO_1V5
- GPU_VDDR4_3V3
- DVO_1V8
- DVO_3V3
LVDS_DATA
I113
I114
LVDS_DATA
I115
I116
LVDS_DATA
I117
I118
LVDS_CLK_UPPER
I119
I120
LVDS_DATA
I125
I124
LVDS_DATA
I123
PP1V5R3V3_GPU_VDDR4
53 47
=PP1V8_GPU_TPVDD
10
I122
DVO_1V5&DVO_1V8
R6640
OMIT
CRITICAL
10K
5%
1/16W
MF-LF
2 402
GPU_DVOVMODE
5%
1/16W
MF-LF
402
53 6
53 6
53 6
53 6
53 6
53 6
53 6
53 6
53 6
53 6
53 6
53 6
53 6
53 6
53 6
53 6
53 6
53 47
53 6
PP1V5R3V3_GPU_VDDR4
53 6
53 6
R6642
10K
53 6
5%
1/16W
MF-LF
402 2
53 6
53 6 2
53 6
53 6
53 6
53 6
53 6
56
AE10 DVOVMODE
GPU_DVO_VSYNC_R AJ10
GPU_DVO_HSYNC_R AK10
GPU_DVO_DE_R
AJ11
GPU_DVO_CLKP_R AH11
BGA
(3 OF 8)
ZV_LCDCNTL_0
ZV_LCDCNTL_1
ZV_LCDCNTL_2
ZV_LCDCNTL_3
GPU_DVOD_R<0>
AH6 ZV_LCDDATA_0
GPU_DVOD_R<1>
AJ6 ZV_LCDDATA_1
GPU_DVOD_R<2>
AK6 ZV_LCDDATA_2
GPU_DVOD_R<3>
AH7 ZV_LCDDATA_3
GPU_DVOD_R<4>
AK7 ZV_LCDDATA_4
GPU_DVOD_R<5>
AJ7 ZV_LCDDATA_5
GPU_DVOD_R<6>
AH8 ZV_LCDDATA_6
GPU_DVOD_R<7>
AJ8 ZV_LCDDATA_7
GPU_DVOD_R<8>
AH9 ZV_LCDDATA_8
GPU_DVOD_R<9>
AJ9 ZV_LCDDATA_9
GPU_DVOD_R<10>
AK9 ZV_LCDDATA_10
GPU_DVOD_R<11> AH10 ZV_LCDDATA_11
GPU_DVOD_R<12>
AE6 ZV_LCDDATA_12
GPU_DVOD_R<13>
AG6 ZV_LCDDATA_13
GPU_DVOD_R<14>
AF6 ZV_LCDDATA_14
GPU_DVOD_R<15>
AE7 ZV_LCDDATA_15
GPU_DVOD_R<16>
AF7 ZV_LCDDATA_16
GPU_DVOD_R<17>
AE8 ZV_LCDDATA_17
GPU_DVOD_R<18>
AG8 ZV_LCDDATA_18
GPU_DVOD_R<19>
AF8 ZV_LCDDATA_19
GPU_DVOD_R<20>
AE9 ZV_LCDDATA_20
GPU_DVOD_R<21>
AF9 ZV_LCDDATA_21
GPU_DVOD_R<22> AG10 ZV_LCDDATA_22
GPU_DVOD_R<23> AF10 ZV_LCDDATA_23
INV_ON_PWM
INTEGRATED TMDS
M11P
DAC/CRT
R6641
I128
TXCM
TXCP
AH13 NC
AK13 NC
TX0M
TX0P
AJ13 NC
AH14 NC
TX1M
TX1P
AJ14 NC
AH15 NC
C6600
1uF
10%
6.3V
2 CERM
402
C6601
I126
VOLTAGE=1.8V
LVDS_CLK_LOWER
I130
0.01uF
I129
20%
16V
I133
2 CERM
402
I136
I135
I137
AJ15 NC
AK15 NC
TPVDD
TPVSS
AK12
AJ12
TXVDDR1
TXVDDR0
AF14
AF13
TXVSSR0
TXVSSR1
TXVSSR2
AG13
AG14
AH12
R
G
B
AK27
AJ27
AJ26
C6605
0.1uF
20%
2 10V
CERM
402
C6606
0.1uF
C6607
I134
51 10
=PP3V3_GPU_GPIOS
0.01uF
20%
2 10V
CERM
402
I138
I139
20%
16V
2 CERM
402
R6690
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS_U0
LVDS_U0
LVDS_U1
LVDS_U1
LVDS_U2
LVDS_U2
LVDS_UCLK
LVDS_UCLK
LVDS_U0_P
LVDS_U0_N
LVDS_U1_P
LVDS_U1_N
LVDS_U2_P
LVDS_U2_N
CLKLVDS_U_P
CLKLVDS_U_N
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS_L0
LVDS_L0
LVDS_L1
LVDS_L1
LVDS_L2
LVDS_L2
LVDS_LCLK
LVDS_LCLK
LVDS_L0_P
LVDS_L0_N
LVDS_L1_P
LVDS_L1_N
LVDS_L2_P
LVDS_L2_N
CLKLVDS_L_P
CLKLVDS_L_N
VGA
VGA
VGA
VGA_CONN
VGA_CONN
VGA_CONN
VGA
VGA
VGA
VGA_CONN
VGA_CONN
VGA_CONN
TV
TV
TV
TV_CONN
TV_CONN
TV_CONN
TV
TV
TV
TV_CONN
TV_CONN
TV_CONN
I140
AUXWIN
RSET
AF26
AH26
GPU_AUXWIN_PU
ATI_RSET
AVDD
AH24
(PP1V8_GPU_AVDD)
AVSSQ
AVSSN
AD24
AH23
VDD1DI
VSS1DI
AE24
AE23
R6650
499
1%
1/16W
MF-LF
2 402
53
1%
1/16W
MF-LF
2 402
75
1%
1/16W
MF-LF
2 402
AE12 DIGON
10K
5%
1/16W
MF-LF
402 2
R6681
56 53 7
56 53 7
56 53 7
56 53 7
56 53 7
NO_TEST=YES
NO_TEST=YES
56 53 7
56 53 7
56 53 7
56 53 7
56 53 7
56 53 7
56 53 7
56 53 7
NO_TEST=YES
NO_TEST=YES
56 53 7
56 53 7
7 53 56
7 53 56
7 53 56
7 53 56
7 53 56
7 53 56
7 53 56
7 53 56
7 53 56
7 53 56
7 53 56
7 53 56
53 57
53 57
53 57
57
57
57
53 57
53 57
53 57
57
57
57
=PP1V8_GPU_AVDD
L6610
1
PP1V8_GPU_AVDD
75
1%
1/16W
MF-LF
2 402
C6610
10UF
20%
2 6.3V
X5R
603
VOLTAGE=1.8V
C6611
0402
0.01uF
20%
2 16V
CERM
402
L6615
(PP1V8_GPU_VDDDI)
1
LVDS_U0_P
LVDS_U0_N
LVDS_U1_P
LVDS_U1_N
LVDS_U2_P
LVDS_U2_N
TP_LVDS_U3_P
TP_LVDS_U3_N
AF16
AG16
AF17
AG17
AE18
AF18
AG20
AH20
CLKLVDS_U_P
CLKLVDS_U_N
AG19 TXCLK_UP
AF19 TXCLK_UN
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
C6615
LVDS_L0_P
LVDS_L0_N
LVDS_L1_P
LVDS_L1_N
LVDS_L2_P
LVDS_L2_N
TP_LVDS_L3_P
TP_LVDS_L3_N
AH16
AK16
AJ16
AH17
AJ17
AH18
AH19
AK19
CLKLVDS_L_P
CLKLVDS_L_N
AJ18 TXCLK_LP
AK18 TXCLK_LN
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
20%
6.3V
2 X5R
603
H2SYNC
V2SYNC
AJ24 NC
AK24 NC
Y_G
C_R
COMP_B
AJ22
AJ23
AK22
R2SET
AK21
A2VDD0
A2VDD1
AG21
AH21
A2VSSN0
A2VSSN1
AH22
AJ21
A2VDDQ
A2VSSQ
AF22
AF23
(PP1V8_GPU_A2VDDQ)
VDD2DI
VSS2DI
AE22
AE21
(PP1V8_GPU_VDDDI)
C6616
0.01uF
20%
16V
2 CERM
402
C6617
PP1V8_GPU_VDDDI
VOLTAGE=1.8V
ATI_R2SET
(PP2V5_GPU_A2VDD)
1
1
R6651
715
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
20%
402
1%
1/16W
MF-LF
2 402
=PP2V5_GPU_A2VDD
53 57
53 57
53 57
L6620
(140mA)
75
0402
0.01uF
R6670 R6671 R6672

75
16V
2 CERM
10
GPU_TV_Y
GPU_TV_C
GPU_TV_COMP
FERR-220-OHM
1
PP2V5_GPU_A2VDD
75
1%
1/16W
MF-LF
2 402
C6620
10UF
20%
2 6.3V
X5R
603
C6621
0.01uF
20%
2 16V
CERM
402
C6622
VOLTAGE=2.5V
0402
0.01uF
20%
2 16V
CERM
402
L6625
1
C6625
10UF
20%
2 6.3V
X5R
603
C6626
FERR-220-OHM
(2mA)
1
2
PP1V8_GPU_A2VDDQ
VOLTAGE=1.8V
0402
0.01uF
20%
2 16V
CERM
402
GPU (M11) DVI/DAC Outputs
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
66
115
SHT
OF
NONE
7 53 56
FERR-220-OHM
53 57
10UF
56 53 7
7 53 56
GPU_TV_Y
GPU_TV_C
GPU_TV_COMP
TV_Y
TV_C
TV_COMP
53 57
NC AJ25 SSOUT
10K
5%
1/16W
MF-LF
402 2
EXTERNAL SSC
DAC2
(TV/CRT2)
R6680
7 53 56
FERR-220-OHM
LVDS CHANNEL
6 53
53 57
R6660 1R6661 1R6662

75
6 53
GPU_AUXWIN_PU
57
6 53
7 53 56
GPU_VGA_R
GPU_VGA_G
GPU_VGA_B
VGA_R
VGA_G
VGA_B
10
57
6 53
5%
1/16W
MF-LF
402 2
GPU_VGA_R
GPU_VGA_G
GPU_VGA_B
GPU_VGA_HSYNC
GPU_VGA_VSYNC
2 6 53
10K
53
AG25
AH25
HSYNC
VSYNC
I131
PP1V8_GPU_PANEL_IO 47
PROPERTIES PROVIDED BY
PAGE INDICATED BY CREF
1
GPU_DVOD_R<23..0>
GPU_DVO_HSYNC_R
GPU_DVO_VSYNC_R
GPU_DVO_DE_R
GPU_DVO_CLKP_R
0402
I132
TX2M
TX2P
DIFFERENTIAL_PAIR
DVO
DVO
DVO
DVO
DVO
AG12 BLON
PANEL_PWR_EN
FERR-220-OHM
PHYSICAL
DVO
DVO
DVO
DVO
DVO
(AVDD+VDDDI=75mA)
CONTROL AND
56
L6600
I127
PP1V8_GPU_TPVDD
U5700
VIP HOST/ EXTERNAL TMDS
DVO_3V3&GPU_VDDR4_3V3
LVDS_DATA
I121
10K
Page Notes
SILICON IMAGE TMDS

- =PP3V3_RUN_SI
TERMINATION NETWORK SHOULD BE CONNECTED AS SHOWN
TMDS_EXT&TMDS_DUAL

- =SI_TMDS_RESET_L
SI_TMDS_CLKN
TMDS_EXT&TMDS_DUAL
- =SI_I2C_DATA
- DVO_1V5
- DVO_1V8
10
4
TMDS_CLKN
54 57
54 2
SI_TMDS_DN<1>
54 2
SI_TMDS_CLKP
TMDS_CLKP
54 57
54
57 54
SI_TMDS_DP<1>
TMDS_EXT&TMDS_DUAL
RP6708
TMDS_DP<1>
Net Physical Type: TMDS
SI_TMDS_DN<0>
TMDS_EXT&TMDS_DUAL
TMDS_DN<0>
54 57
54 2
NOTE: Target differential impedance for

54
SI_TMDS_DP<0>
49.9
TMDS_EXT&TMDS_DUAL
TMDS_DN<2>
TMDS_DP<0>
54 57
54
SI_TMDS_DP<2>
NET_TYPE
SPACING
PHYSICAL
I309
I310
I311
I312
DVO
DVO
DVO
DVO
DVO
50V
TMDS_DP<2>
57 54
GPU_DVOD<0..11>
GPU_DVO_HSYNC
GPU_DVO_VSYNC
GPU_DVO_DE
GPU_DVO_CLKP
L6723
6 54 55
180-OHM-1.5A
=PP3V3_RUN_SI
50V
TMDS_DN<1>
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
I317
TMDS_DATA
I319
I318
TMDS_DATA
I321
I320
TMDS_DATA
I322
I323
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
SI_TMDS_CLK
SI_TMDS_CLK
SI_TMDS_D0
SI_TMDS_D0
SI_TMDS_D1
SI_TMDS_D1
SI_TMDS_D2
SI_TMDS_D2
SI_TMDS_CLKP
SI_TMDS_CLKN
SI_TMDS_DP<0>
SI_TMDS_DN<0>
SI_TMDS_DP<1>
SI_TMDS_DN<1>
SI_TMDS_DP<2>
SI_TMDS_DN<2>
2 54
C6764
EXT_TMDS_D2_CMF
50V
VOLTAGE=3.3V
PP3V3_SI_M_AVCC
TMDS_EXT&TMDS_DUAL
54
L6720
2 54
=PP3V3_RUN_SI
10 54 55
180-OHM-1.5A
54
TMDS_EXT&TMDS_DUAL
R6766
1
57 54
TMDS_DP<2>
10%
CERM
402
0603
54
CERM
402
54 57
1%
1/16W
MF-LF
402
0.001uF
TMDS_CLK
I316
54 57
C6762
TMDS_EXT&TMDS_DUAL
10 54 55
TMDS_DN<0>
1%
1/16W
MF-LF
402
TMDS_EXT&TMDS_DUAL
TMDS_EXT&TMDS_DUAL
49.9
10%
49.9
2
1%
1/16W
MF-LF
402
6 54 55
0.001uF
R6765
49.9
TMDS_DP<1>
6 54
R6763
TMDS_EXT&TMDS_DUAL
TMDS_EXT&TMDS_DUAL
R6764
6 54 55
49.9
EXT_TMDS_D1_CMF
TMDS_EXT&TMDS_DUAL
6 54 55
TMDS_DP<0>
1%
1/16W
MF-LF
402
54 57
5%
1/16W
SM-LF
TMDS_EXT&TMDS_DUAL
R6762
10%
CERM
402
DIFFERENTIAL_PAIR
DVO
DVO
DVO
DVO
DVO
EXT_TMDS_D0_CMF
0.001uF
57 54
GPU_DVO_LOWER
GPU_DVO_BOTH
GPU_DVO_BOTH
GPU_DVO_BOTH
GPU_DVO_CLKP
I306
54 57
TMDS_EXT&TMDS_DUAL
TMDS data pairs is 100 ohms.

5%
1/16W
SM-LF
TMDS_CLKN
1%
1/16W
MF-LF
402
C6760
54 57
10
3
TMDS_EXT&TMDS_DUAL
5%
1/16W
SM-LF
RP6710
1%
1/16W
MF-LF
402
RP6710
SI_TMDS_DN<2>
10
R6761
49.9
54 57
10
5%
1/16W
SM-LF
RP6708
TMDS_CLKP
TMDS_EXT&TMDS_DUAL
R6760
TMDS_EXT&TMDS_DUAL
5%
1/16W
SM-LF
10
54 2
54 57
10
3
5%
1/16W
SM-LF
Net Spacing Type: TMDS
EXT_TMDS_CLK_CMF
TMDS_DN<1>
5%
1/16W
SM-LF
RP6709
10
- DVO_3V3
TMDS_EXT&TMDS_DUAL
TMDS_EXT&TMDS_DUAL
5%
1/16W
SM-LF
RP6707

- TMDS_DUAL
RP6709
10
54
- TMDS_EXT
TMDS_EXT&TMDS_DUAL
RP6707
- =RP67xxPy (pinswappable series R)
- =SI_I2C_CLK
EXTERNAL TMDS TERMINATION
- =PP1V5R3V3_DVO_VREF
49.9
R6767
1%
1/16W
MF-LF
402
49.9
TMDS_DN<2>
54 57
1%
1/16W
MF-LF
402
TMDS_EXT&TMDS_DUAL
C6766
0.001uF
1
2 54
TMDS_EXT&TMDS_DUAL
1
0603
54
VOLTAGE=3.3V
PP3V3_SI_M_VCC
2 54
C6723
10UF
C6724
6.3V
X5R
805
50V
CERM
402
C6725
100pF
TMDS_EXT&TMDS_DUAL
10%
10%
TMDS_EXT&TMDS_DUAL
5%
1
100pF
50V
CERM
402
5%
Lower DVO Termination
C6720
Place close to GPU
10UF
One each for: GPU_DVOD<0..11>

GPU_DVO_HSYNC
GPU_DVO_VSYNC
GPU_DVO_DE
GPU_DVO_CLKP
TMDS_EXT&TMDS_DUAL
TMDS_EXT&TMDS_DUAL
C6722
100pF
C6721
5%
50V
100pF
10%
5%
6.3V
50V
X5R
805
50V
CERM
402
L6726
180-OHM-1.5A
CERM
402
VOLTAGE=3.3V
TMDS_EXT&TMDS_DUAL
TMDS_EXT&TMDS_DUAL
1
=RP6720P8
TMDS_EXT&TMDS_DUAL
10
2
TMDS_EXT&TMDS_DUAL
=RP6720P7
10
6
=RP6720P6
R6752 1
10K
301
5%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
=RP6721P2
55
=RP6721P7
6
55
TMDS_EXT&TMDS_DUAL
5%
1/16W
SM-LF
RP6721
54 6
10
6
=RP6721P3
54 6
=RP6721P6
6
54 6
TMDS_EXT&TMDS_DUAL
5%
1/16W
SM-LF
54 6
RP6721
54 6
10
6
=RP6721P4
TMDS_EXT&TMDS_DUAL
=RP6721P5
54 6
5%
1/16W
SM-LF
RP6722
54 6
54 6
10
6
=RP6722P1
54 6
=RP6722P8
6
54 6
TMDS_EXT&TMDS_DUAL
5%
1/16W
SM-LF
54 6
RP6722
54 6
10
6
=RP6722P2
TMDS_EXT&TMDS_DUAL
=RP6722P7
55 54 6
5%
1/16W
SM-LF
RP6722
55 54 6
55 54 6
10
6
=RP6722P3
55 54 6
=RP6722P6
6
55 54
TMDS_EXT&TMDS_DUAL
5%
1/16W
SM-LF
TMDS_EXT&TMDS_DUAL
=RP6722P5
DVO_3V3
1
R6733
1K
=RP6723P8
5%
1/16W
MF-LF
402 2
TMDS_EXT&TMDS_DUAL
5%
1/16W
SM-LF
=RP6723P2
TMDS_EXT&TMDS_DUAL
=RP6723P7
=RP6723P3
4.99K
1%
1/16W
MF-LF
2 402
NET_TYPE
CRITICAL
GPU_DVOD<0>
GPU_DVOD<1>
GPU_DVOD<2>
GPU_DVOD<3>
GPU_DVOD<4>
GPU_DVOD<5>
GPU_DVOD<6>
GPU_DVOD<7>
GPU_DVOD<8>
GPU_DVOD<9>
GPU_DVOD<10>
GPU_DVOD<11>
GPU_DVO_DE
GPU_DVO_HSYNC
GPU_DVO_VSYNC
GPU_DVO_CLKP
18
17
16
15
14
13
10
9
8
7
6
5
19
20
21
12
NO STUFF
R6732 1
10K
100K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SI_TMDS_CLKP
SI_TMDS_CLKN
TXC+ 33
TXC- 32
U6700
D0
SIL1178CS48
D1
TX0+ 36
TSSOP
D2
TX0- 35
D3
TX1+ 39
D4
TX1- 38
D5
D6
TX2+ 42
D7
TX2- 41
D8
D9
D10
D11
DE
HSYNC
EXT_SWING 30
VSYNC
IDCK+
VREF 2
IDCK-
SI_TMDS_DP<0>
SI_TMDS_DN<0>
I329
54
I330
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
I331
54
I332
2 54
I333
SI_TMDS_DP<1>
SI_TMDS_DN<1>
SI_TMDS_DP<2>
SI_TMDS_DN<2>
54
I334
2 54
I335
I336
=RP6723P6
PHYSICAL
DIFFERENTIAL_PAIR
SI_VREF
=PP1V5R3V3_DVO_VREF
R6740
54 57
54 57
Lower TMDS Transmitter
1%
1/16W
MF-LF
2 402
DVO_1V5&DVO_1V8
R6742
R6731
55 54
SI_IDCK_N
5%
1/16W
MF-LF
402
55 54
SI_VREF
SYNC_MASTER=N/A
SYNC_DATE=N/A
TMDS_EXT&TMDS_DUAL
C6740
10V

DVO_1V5&DVO_1V8
1
R6741
1K
2
2
1%
1/16W
MF-LF
402

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
67
115
SHT
OF
NONE
54 57
47
1K
20%
54 57
TMDS_EXT&TMDS_DUAL
1
CERM
402
54 57
The DVO bus can be run with 3.3V or 1.5V/1.8V

signaling. The power rail for the reference
should be connected to the GPU DVO rail.
5%
1/16W
SM-LF
54 57
54 55
=RP6723P5
54 57
2 54
RP6723
5
54 57
54
TMDS_EXT&TMDS_DUAL
=RP6723P4
TMDS_CLKP
TMDS_CLKN
TMDS_DP<0>
TMDS_DN<0>
TMDS_DP<1>
TMDS_DN<1>
TMDS_DP<2>
TMDS_DN<2>
TMDS_CLK
TMDS_CLK
TMDS_D0
TMDS_D0
TMDS_D1
TMDS_D1
TMDS_D2
TMDS_D2
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
SI_M_EXTSWING
TMDS_EXT&TMDS_DUAL
1
2 54
SPACING
10
6
50V
CERM
402
Place C6728/C6729 at pin 46
0.1uF
6
5%
1/16W
SM-LF
Place C6726/C6727 at pin 28
TMDS_EXT&TMDS_DUAL
SYNCO/SYNCI
EHTPLG
10
6
SI_M_MSEN
MSEN 48
5%
1/16W
MF-LF
2 402
5%
1/16W
SM-LF
RP6723
44
SCL
SDA
CTL3/A1
RST*
10K
RP6723
10
47
R6730 1
10
1
=RP6723P1
SI_SYNC
SI_HTPLG
TMDS_EXT&TMDS_DUAL
5%
1/16W
SM-LF
RP6723
6
24
25
11
RP6722
=RP6722P4
26
SI_IDCK_N
10
6
27
10
6
5%
6.3V
X5R
805
R6754
49
55 11
RP6721
=I2C_SI_M_SCL
=I2C_SI_M_SDA
SI_M_A1
=SI_TMDS_RESET_L
TMDS_EXT&TMDS_DUAL
5%
1/16W
SM-LF
37
23
=RP6721P8
10
1
C6729
100pF
10%
50V
CERM
402
28
6
43
RP6721
=RP6721P1
NO STUFF
1
PGND
PGND
AGND
AGND
AGND
GND
GND
GND
THRML
PAD
=RP6720P5
45
5
5%
1/16W
SM-LF
29
=RP6720P4
TMDS_EXT&TMDS_DUAL
X5R
805
10UF
5%
6.3V
TMDS_EXT&TMDS_DUAL
C6728
PVCC1 46
PVCC2
40
AVCC 34
AVCC 22
VCC 3
VCC
RP6720
10
100pF
TMDS_EXT&TMDS_DUAL
5%
1/16W
SM-LF
31
TMDS_EXT&TMDS_DUAL
R6734 1
5%
1/16W
SM-LF
RP6720
=RP6720P3
TMDS_EXT&TMDS_DUAL
C6727
RP6720
=RP6720P2
TMDS_EXT&TMDS_DUAL
10%
8
5%
1/16W
SM-LF
6
TMDS_EXT&TMDS_DUAL
C6726
10UF
10
1
10 54 55
PP3V3_SI_M_PVCC
RP6720
=RP6720P1
=PP3V3_RUN_SI
2
0603
TMDS_EXT&TMDS_DUAL
TMDS_EXT&TMDS_DUAL
2
CERM
402
Page Notes
Upper Channel Series Termination
- =PP3V3_RUN_SI
TMDS_DUAL
- =SI_I2C_CLK
- =SI_TMDS_RESET_L
- =SI_I2C_DATA
- =RP68xxPy (pinswappable series R)
RP6811
Net Spacing Type: TMDS

Net Physical Type: TMDS
NET_TYPE
SPACING
GPU_DVO_UPPER
GPU_DVOD20
GPU_DVO_UPPER
PHYSICAL
DVO
DVO
DVO
I58
PROVIDED BY LOWER TXMR
I59
TMDS_DATA
I75
TMDS_DATA
I76
I77
TMDS_DATA
I78
I79
I80
I81
I82
I83
I84
I85
10 54 55
RP6811
TMDS_DN<3>
55 57
TMDS_DP<3>
55 57
TMDS_DN<4>
55 57
TMDS_DP<4>
55 57
TMDS_DN<5>
55 57
TMDS_DP<5>
55 57
5%
1/16W
SM-LF
TMDS_DUAL
C6837
100pF
CERM
402
X5R
805
TMDS_DUAL
RP6812
10
C6839
55 2
SI_TMDS_DN<4>
5%
6.3V
3
5%
1/16W
SM-LF
100pF
10%
50V
X5R
805
SI_TMDS_DP<3>
TMDS_DUAL
C6838
10UF
5%
6.3V
55 2
TMDS_DUAL
50V
CERM
402
5%
1/16W
SM-LF
RP6812
10
GPU_DVOD<12..19>
GPU_DVOD<20>
GPU_DVOD<21..23>
GPU_DVO_VSYNC
GPU_DVO_DE
GPU_DVO_CLKP
I60
I74
TMDS_DUAL
C6836
DIFFERENTIAL_PAIR
DVO
DVO
DVO
=PP3V3_RUN_SI
10
10%
2
SI_TMDS_DN<3>
TMDS_DUAL
0603
10UF
TMDS data pairs is 100 ohms.
I56
TMDS_DUAL
1
I55
180-OHM-1.5A
VOLTAGE=3.3V
PP3V3_SI_S_PVCC
- TMDS_DUAL
I54
55
L6836
10
TMDS_DUAL
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
SI_TMDS_D3
SI_TMDS_D3
SI_TMDS_D4
SI_TMDS_D4
SI_TMDS_D5
SI_TMDS_D5
SI_TMDS_DP<3>
SI_TMDS_DN<3>
SI_TMDS_DP<4>
SI_TMDS_DN<4>
SI_TMDS_DP<5>
SI_TMDS_DN<5>
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS_D3
TMDS_D3
TMDS_D4
TMDS_D4
TMDS_D5
TMDS_D5
TMDS_DP<3>
TMDS_DN<3>
TMDS_DP<4>
TMDS_DN<4>
TMDS_DP<5>
TMDS_DN<5>
Place C6836/C6837
at pin 28.
6 55
TMDS_DUAL
Place C6838/C6839
at pin 46.
55
SI_TMDS_DP<4>
L6833
180-OHM-1.5A
6 55
6 55
=PP3V3_RUN_SI
10 54 55
SI_TMDS_DN<5>
2 55
TMDS_DUAL
VOLTAGE=3.3V
6 54 55
RP6813
10
55 2
PP3V3_SI_S_AVCC
6 54 55
TMDS_DUAL
2
0603
6 54 55
4
5%
1/16W
SM-LF
TMDS_DUAL
1
TMDS_DUAL
C6833
10UF
55
2
55
100pF
55
SI_TMDS_DP<5>
100pF
10%
5%
5%
50V
50V
10
C6835
6.3V
X5R
805
RP6813
TMDS_DUAL
C6834
CERM
402
5%
1/16W
SM-LF
4
5%
1/16W
SM-LF
CERM
402
TMDS_DUAL
2 55
L6830
180-OHM-1.5A
55
2 55
=PP3V3_RUN_SI
55 57
10 54 55
2
0603
55 57
Upper Channel Common-mode Termination
PP3V3_SI_S_VCC
55 57
VOLTAGE=3.3V
55 57
55 57
TMDS_DUAL
1
55 57
C6830
TMDS_DUAL
1
C6831
C6832
100pF
100pF
10%
5%
5%
6.3V
50V
50V
X5R
805
CERM
402
TMDS_D3_CMF
TMDS_DUAL
1
10UF
CERM
402
57 55
TMDS_DP<3>
TMDS_DUAL
TMDS_DUAL
R6804
R6805
49.9
49.9
1%
1/16W
MF-LF
402
TMDS_DN<3>
55 57
1%
1/16W
MF-LF
402
TMDS_DUAL
C6804
0.001uF
10%
50V
CERM
402
TMDS_DUAL
R6880
TMDS_DUAL
R6881 1
10K
301
28
Upper DVO series termination

Place close to GPU
8
One for each of: GPU_DVOD<12..23>

8
TMDS_DUAL
54 11
RP6821
54
10
=RP6821P8
55 6
RP6821
55 6
10
=RP6821P7
55 6
55 6
10
6
=RP6821P3
55 6
=RP6821P6
6
55 6
TMDS_DUAL
5%
1/16W
SM-LF
55 6
RP6821
55 6
10
6
=RP6821P4
TMDS_DUAL
=RP6821P5
5%
1/16W
SM-LF
RP6822
55 6
55 6
10
6
=RP6822P1
55 54 6
=RP6822P8
6
54 6
TMDS_DUAL
5%
1/16W
SM-LF
55 54 6
RP6822
55 54 6
10
2
=RP6822P2
TMDS_DUAL
=RP6822P7
=RP6822P6
=RP6822P5
=RP6823P8
54
5%
1/16W
SM-LF
RP6822
3
=RP6822P3
15
14
13
10
9
8
7
6
5
19
20
21
12
11
R6803
57 55
49.9
TMDS_DP<4>
49.9
TMDS_DN<4>
1%
1/16W
MF-LF
402
55 57
1%
1/16W
MF-LF
402
TMDS_DUAL
SI_S_MSEN
C6802
CERM
402
TMDS_DUAL
SYNCO/SYNCI
EHTPLG
TXC+ 33
CRITICAL
TXC- 32
U6800
D0
SIL1178CS48
TX0+ 36
D1
TSSOP
D2
TX0- 35
D3
TX1+ 39
D4
TX1- 38
D5
TX2+ 42
D6
D7
TX2- 41
D8
D9
D10
D11
DE
HSYNC
EXT_SWING 30
VSYNC
IDCK+
VREF 2
IDCK-
29
10
6
16
R6802
1%
1/16W
MF-LF
2 402
TMDS_D5_CMF
NC
NC
SI_TMDS_DP<3>
SI_TMDS_DN<3>
SI_TMDS_DP<4>
SI_TMDS_DN<4>
SI_TMDS_DP<5>
SI_TMDS_DN<5>
2 55
57 55
55
TMDS_DP<5>
TMDS_DUAL
TMDS_DUAL
R6800
R6801
49.9
1
49.9
2
1%
1/16W
MF-LF
402
55
2 55
TMDS_DN<5>
55 57
1%
1/16W
MF-LF
402
TMDS_DUAL
55
C6800
2 55
0.001uF
10%
50V
CERM
402
SI_S_EXTSWING
SI_VREF
54
PGND
PGND
AGND
AGND
AGND
GND
GND
GND
THRML
PAD
55 6
17
TMDS_DUAL
4.99K
50V
RP6821
55 6
18
TMDS_DUAL
49
7
5%
1/16W
SM-LF
GPU_DVOD<12>
GPU_DVOD<13>
GPU_DVOD<14>
GPU_DVOD<15>
GPU_DVOD<16>
GPU_DVOD<17>
GPU_DVOD<18>
GPU_DVOD<19>
GPU_DVOD<20>
GPU_DVOD<21>
GPU_DVOD<22>
GPU_DVOD<23>
GPU_DVO_DE
GPU_DVO_HSYNC
GPU_DVO_VSYNC
GPU_DVO_CLKP
SI_IDCK_N
TMDS_D4_CMF
R6882
10%
TMDS_DUAL
47
44
0.001uF
37
=RP6821P2
SI_SYNC
SI_HTPLG
25
MSEN 48
23
54
TMDS_DUAL
24
SCL
SDA
CTL3/A1
RST*
43
8
5%
1/16W
SM-LF
26
31
=RP6821P1
27
45
=I2C_SI_S_SCL
=I2C_SI_S_SDA
SI_S_A1
=SI_TMDS_RESET_L
1%
1/16W
MF-LF
402 2
PVCC1
46
PVCC2
40
AVCC
34
AVCC
22
VCC 3
VCC
5%
1/16W
MF-LF
402 2
NO STUFF
TMDS_DUAL
5%
1/16W
SM-LF
RP6822
10
=RP6822P4
TMDS_DUAL
5
5%
1/16W
SM-LF
RP6823
10
6
=RP6823P1
Upper TMDS Transmitter
TMDS_DUAL
5%
1/16W
SM-LF
RP6823
SYNC_MASTER=N/A
10
6
=RP6823P2
TMDS_DUAL
=RP6823P7
5%
1/16W
SM-LF
RP6823

10
6
=RP6823P3
6
5%
1/16W
SM-LF
=RP6823P6
TMDS_DUAL
RP6823
10
6
=RP6823P4
SYNC_DATE=N/A
=RP6823P5
SIZE
5%
1/16W
SM-LF
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
68
115
SHT
OF
NONE
LCD (LVDS) INTERFACE
10
=PP3V3_PWRON_LCD
C6900
2200pF
R69001
100K
5%
1/16W
MF-LF
402 2
R6901
1
100K 2
5%
50V
CERM
603
LCD_PWREN_L
L6900
5%
1/16W
MF-LF
402
PP3V3_LCD_SW
TSOP-LF
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 mm SM
Q6900
Q6901
2N7002
56 53
PANEL_PWR_EN
SOT23-LF
10 7
C6920
=GND_CHASSIS_LCD2
J6900
MSC-RB30-5-FA
0.001uF
C6901 1
20%
50V
CERM 2
402
34
51 7
51 7
R69101
100K
5%
1/16W
MF-LF
402 2
10
R6911
100K
10
53 7
53 7
20%
50V
CERM 2
402
LVDS_DDC_CLK
LVDS_DDC_DATA
53 7
53 7
0.001uF
53 7
20%
50V
CERM 2
402
53 7
53 7
2
=GND_CHASSIS_LCD3
53 7
D2
4 S2
100K
FP_PWR_EN_L
12
13
D1
15
10UF
CLKLVDS_L_N
CLKLVDS_L_P
53 7
56 53
PANEL_PWR_EN
SC70-6-LF
17
53 7
53 7
24
26
LVDS_U2_N
LVDS_U2_P
53 7
INV_ON_PWM
5
1
27
CLKLVDS_U_N
CLKLVDS_U_P
29
C6921
33
NC7S32
C6955
20%
2 50V
CERM
402
L6955
FERR-250-OHM
SM
SC70-LF
4
BRIGHT_PWM_F
7 BRIGHT_PWM
GND_INVERTER
VOLTAGE=0V
0.001uF
20%
50V
CERM 2
402
U6953
20%
10V
CERM 2
402
53
0.001uF
0.1uF
28
53 7
C6954 1
C6953
25
53 7
2
SM-1
23
LVDS_U1_N
LVDS_U1_P
20%
50V
2 CERM
402
=PP3V3_PWRON_INVERTER
21
Y
B
0.001uF
L6953
400-OHM-EMI
1
10
C6951
18
22
53 7
PP5V_INV_SW
VOLTAGE=5V
FDG6324L
S1
20
LVDS_U0_N
LVDS_U0_P
Q6950
16
20%
50V
2 CERM
402
5 G1
J6950
SM-2MT-LF
C6952
0.001uF
20%
6.3V
2 X5R
603
14
LVDS_L2_N
LVDS_L2_P
1
SM-1
C6950
G2
6
CRITICAL
VOLTAGE=5V
MIN_NECK_WIDTH=0.25 1
mm
19
53 7
PP5V_INV_SW_F
11
LVDS_L1_N
LVDS_L1_P
NO STUFF
C6911 1
400-OHM-EMI
R69501
10
L6950
5%
1/16W
MF-LF
402 2
PPBUS_INVERTER
VOLTAGE=12.8V
FDG6324L
SC70-6-LF
LVDS_L0_N
LVDS_L0_P
Q6950
=PP5V_PWRON_INVERTER
0.001uF
1
SM
C6910 1
FERR-1K-OHM-EMI
5%
1/16W
MF-LF
2 402
=PPBUS_INVERTER
VOLTAGE=3.3V
7 PP3V3_LCD_CONN
NC
100K pull-ups are for

no-panel case (development)
Panel has 2K pull-ups
L6952
F-RT-SM
20%
50V
CERM 2
402
=PP3V3_DDC_LCD
INVERTER INTERFACE
CRITICAL
0.001uF
SI3443DV
3
D
=GND_CHASSIS_LCD1
LCD_DIGON_L
FERR-250-OHM
INVERTER EXPECTS ACTIVE HIGH SIGNAL

3
30
0.001uF
2
20%
50V
CERM
402
R6999
0
1
2
=GND_CHASSIS_LCD4
5%
1/16W
MF-LF
402
C6999
0.01uF
1
20%
50V
CERM
603
Internal Display Conns
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
69
115
SHT
OF
NONE
7
NET_TYPE
SPACING
I548
I549
I550
I551
I552
I553
I554
I555
I559
I558
I560
I561
I562
I563
DIFFERENTIAL_PAIR
PHYSICAL
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN_CLK
TMDS_CONN_CLK
TMDS_CONN_D0
TMDS_CONN_D0
TMDS_CONN_D1
TMDS_CONN_D1
TMDS_CONN_D2
TMDS_CONN_D2
TMDS_CONN_CLKP
TMDS_CONN_CLKN
TMDS_CONN_DP<0>
TMDS_CONN_DN<0>
TMDS_CONN_DP<1>
TMDS_CONN_DN<1>
TMDS_CONN_DP<2>
TMDS_CONN_DN<2>
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN_D3
TMDS_CONN_D3
TMDS_CONN_D4
TMDS_CONN_D4
TMDS_CONN_D5
TMDS_CONN_D5
TMDS_CONN_DP<3>
TMDS_CONN_DN<3>
TMDS_CONN_DP<4>
TMDS_CONN_DN<4>
TMDS_CONN_DP<5>
TMDS_CONN_DN<5>
2 57
(55mA requirement per DVI spec)

CRITICAL
SYM_VER-1
57
54
TMDS_DN<0>
54
TMDS_DP<0>
57
TMDS_CONN_DP<0>
57
10 =PP5V_RUN_DVI_DDC
SM-LF
SM-1
Isolation required for DVI power switch
D7010
CRITICAL
57
L7001
57
SYM_VER-1
57
54
TMDS_DN<1>
J7000
TMDS_EXT&TMDS_DUAL
4
TMDS_CONN_DN<1>
QH81127-CK1
F-RT-TH-LF
57
33
57
57
54
TMDS_DP<1>
TMDS_CONN_DP<1>
CRITICAL
57
31
=GND_CHASSIS_DVI1
L7002
90-OHM-300mA
17
TMDS_CONN_DN<0>
TMDS_CONN_DN<2>
TMDS_CONN_DN<1>
TMDS_CONN_DP<2>
TMDS_CONN_DP<1>
TMDS_EXT&TMDS_DUAL
2012H
SYM_VER-1
57
18
TMDS_CONN_DP<0>
10
54
TMDS_DN<2>
54
TMDS_DP<2>
TMDS_CONN_DN<2>
57
TMDS_CONN_DP<2>
57
19
R7011
57
20
TMDS_CONN_DN<5>
12
L7006
370-OHM
57
54
TMDS_CLKP
21
TMDS_CONN_DP<5>
5
13
TMDS_EXT&TMDS_DUAL
SM
SYM_VER-1
TMDS_CONN_CLKP
22
6
14
2 57
57 2
23
TMDS_CONN_CLKP
C7011
ANALOG FILTERING
PLACE CLOSE TO CONNECTOR
54
TMDS_CLKN
TMDS_CONN_CLKN
57
57
24
TMDS_CONN_CLKN
CRITICAL
16
L7003
90-OHM-300mA
TMDS_DUAL
2012H
SYM_VER-1
FL7040
55
TMDS_DN<3>
57 53
C3
VGA_B
C1
C5B
TMDS_CONN_DN<3>
57
57
5%
2 50V
CERM
402
VGA_VSYNC
DVI_HPD_UF
57
C2
53 57
VGA_G
53 57
53
GPU_VGA_B
VGA_B
CRITICAL
SM-220MHZ-LF
C7040
75
TMDS_CONN_DP<3>
34
57
GPU_DVI_DDC_DATA 51
1
R7022
100K
2N7002DW-X-F
SOT-363
R7014
100
DVI_HPD
5%
1/16W
MF-LF
2 402
S 4
GPU_DVI_HPD
VGA_G
75
SM-220MHZ-LF
1
2
3 4
3.3pF
0.1uF
1
57 10 =PP3V3_PWRON_VGASYNC
PLACE NEAR C5A & C5B
57
TMDS_CONN_DP<4>
GPU_VGA_VSYNC 1
53
R7030
TMDS_CONN_DN<4>
=GND_CHASSIS_DVI3
TMDS_DN<5>
TMDS_DP<5>
33
VGA_VSYNC
57
5%
1/16W
MF-LF
402
PLACE R7050 & R7051 CLOSE TO DVI CONNECTOR
C7051
TMDS_DUAL
4
TMDS_CONN_DN<5>
TMDS_CONN_DP<5>
0.1uF
=GND_CHASSIS_DVI4
57
57 10 =PP3V3_PWRON_VGASYNC
2
5%
1/16W
MF-LF
402
53 57
55
R7050
PLACE NEAR 3, 11 & 19

57
NO STUFF
U7051
20%
10V
74AHC1G32 CERM
402
SM-LF
4
GPU_HSYNC_BUF1
R7051
GPU_VGA_HSYNC 1
53
33
VGA_HSYNC
57
5%
1/16W
MF-LF
402
32
1%
1/16W
MF-LF
2 402
0.25%
2 50V
CERM
402
20%
10V
74AHC1G32 CERM
402
SM-LF
4
GPU_VSYNC_BUF
R7031
SYM_VER-1
55
U7050
32
5%
1/16W
MF-LF
402
57
L7005
R7042
75
90-OHM-300mA
2012H
C7042
5%
50V
2 CERM
402
CRITICAL
NO STUFF
VGA_R
1%
1/16W
MF-LF
2 402
0.25%
2 50V
CERM
402
CRITICAL
TMDS_DP<4>
R7041
C7041
=GND_CHASSIS_DVI2
4
53 57
3.3pF
FL7042
C7050
C7014
100pF
20%
50V
CERM 2
603
TMDS_DUAL
2012H
TMDS_DN<4>
0.01uF
32
51
NOTE: Pulldown for DVI_HPD provided by DVI power switch interface
SYM_VER-1
55
55
LCFILTER
S 1
VGA SYNC BUFFERS
35
L7004
90-OHM-300mA
NO STUFF
1%
1/16W
MF-LF
2 402
0.25%
2 50V
CERM
402
GPU_VGA_R
R7040
3 4
53
TMDS_DP<3>
3.3pF
FL7041
GPU_VGA_G
55
53 57
CRITICAL
3 4
53
6 D
2 DVI_DDC_DATA
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
C7010 1
LCFILTER
5%
1/16W
MF-LF
2 402
SOT-363
CRITICAL
SM-220MHZ-LF
100
VGA_R
10K
2
Q7014
C5A
C4
VGA_HSYNC
57
R7013
C7013
51
R7021
100pF
15
2
GPU_DVI_DDC_CLK
1
2N7002DW-X-F
1
(PP5V_RUN_DDC)
DVI_DDC_DATA_UF
S 4
Q7011
5%
50V
2 CERM
402
TMDS_CONN_DN<4> 57
TMDS_CONN_DN<3> 57
TMDS_CONN_DP<4> 57
TMDS_CONN_DP<3> 57
57 DVI_DDC_CLK_UF
5%
1/16W
MF-LF
2 402
2 DVI_DDC_CLK3
100pF
CRITICAL
100
5%
1/16W
MF-LF
402
57
1
57
10K
Q7011
57
R7020
5%
1/16W
MF-LF
2 402
2N7002DW-X-F
SOT-363
5%
1/16W
MF-LF
402 2
11
3
4.7K
4.7K
57
R7012
R7010
57
57 10 =PP3V3_DDC_DVI
57
LCFILTER
PP5V_RUN_DDC_PULLUPS
VOLTAGE=5V
B0530WXF
36
57
3V LEVEL SHIFTERS
SOD-123
1
2
CRITICAL
90-OHM-300mA
2012H
57
57
VOLTAGE=5V
PP5V_RUN_DDC_FUSE
VOLTAGE=5V
57
PP5V_RUN_DDC
400-OHM-EMI
0.5AMP-13.2V
TMDS_CONN_DN<0>
57
57
L7010
F7010
TMDS_EXT&TMDS_DUAL
2012H
57
DVI INTERFACE
DVI DDC CURRENT LIMIT
L7000
90-OHM-300mA
5
TMDS FILTERING
PLACE CLOSE
TO CONNECTOR
CRITICAL
DVI POWER SWITCH

Power key detect path when
system is shutdown or asleep..
DDC_CLK is isolated from
GPU during shutdown. When
power key on remote device
is pressed, 5V will be driven
into DDC_CLK. Since host rails
will be low, TP0610 will turn
on, driving SYS_POWER_BUTTON_L low.
As host rails rise, TP0610
will turn off, as will remote
device path into DDC_CLK.
Isolation will be disabled as well.
S-VIDEO/COMP OUT INTERFACE

B
Place GND shorts at

graphics controller
PP5V_RUN_DDC
57
DVI_DDC_CLK_UF
57 10
R7081
D 3
SM
1
1
R7072
C7060
20%
50V
CERM
603
L7062
3.3uH
GPU_TV_Y
53
TV_Y
HPD_4V_REF
2
4
CRITICAL
C7063
560pF
560pF
10%
50V
CERM
402
10%
50V
CERM
402
L7064
3.3uH
RT-TH-LF
GPU_TV_C
53
TV_C
0603
C7064
4
2
8
10
10%
50V
CERM
402
L7066
3.3uH
DVI_HPD_DIV
R70711
GPU_TV_COMP
53
1%
1/16W
MF-LF
402 2
9
11
C7067
10%
50V
CERM
402
10%
50V
CERM
402
560pF
XW7061
SM
L7061
Q7075
Q7076
SOT-363
SOT-363-LF
=PPBUS_DVI_PWRSW
R70751
R7078
R7080
330
2 HPD_ON_RC
5%
1/16W
MF-LF
402
C7079 1
COMP_ENABLE
20K
20%
6.3V
CERM 2
1210
SOT-363-LF
R7079
68K
5%
1/16W
MF-LF
2 402
100K
5%
1/16W
MF-LF
402 2
External Display Conns

SYNC_MASTER=N/A

2N7002DW-X-F
SOT-363

1
R7076
100K
5%
1/16W
MF-LF
402 2
0.01uF
20%
50V
CERM
603
SIZE
APPLE COMPUTER INC.

2
SYNC_DATE=N/A
Q7076
D
2
HPD_PWR_SNS_EN
MMDT3904XF
1
R70771
NEED PULL-DOWN BECAUSE THIS

SIGNAL IS TRISTATED INITIALLY
51
Q7080
GND_TV2
VOLTAGE=0V
SM
HPD_BASE
5%
1/16W
MF-LF
402
47UF
5%
1/16W
MF-LF
402 2
Q16C/514-0265/MH11773-MR8A-7F
Q41C/514-0256/MH11773-MR8N-7F
MMDT3904XF
4
Pulldown prevents
3904 from turning
on when DVI monitor
has active, selfpowered DDC clock
pullup.
2N7002DW-X-F
S0T23-3
100K
C7061
Place GND shorts at

graphics controller
HPD_ON
TP0610
100K
10
Q7080
DVI_TURN_ON_BASE
COMP_DISABLE
GND_GPU_TV2
VOLTAGE=0V
4
S
G
TV_COMP
560pF
FERR-10-OHM-500MA
V-
R70731
1%
1/16W
MF-LF
402 2
U7070
0603
C7066
330
10K
560pF
10%
50V
CERM
402
DVI_HPD_UF
R7082
C7070
10K
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
3
1
5
C7065
560pF
57
MH11773-MR8A-7F
10K
5%
1/16W
MF-LF
402 2
SM-LF
1 HPD_PWR_SW
R7070
MINIDIN
R7083
DVI_TURN_ON_ILIM
LMC7211
V+
J7060
0.1uF
1%
1/16W
MF-LF
402 2
0603
C7062
680
20%
10V
2 CERM
402
68.1K
Power key detect path

when system is running.
HPD normally driven to
3.3V. When power key
on remote device pressed,
HPD will be driven to 5V.
Comparator output enabled
by GPU.
0.01uF
DVI_TURN_ON
=PP3V3_DDC_DVI
VOLTAGE=0V
24 25 30 36
S0T23-3
5%
1/16W
MF-LF
402
GND_TV1
VOLTAGE=0V
53
SYS_POWER_BUTTON_L
TP0610
FERR-10-OHM-500MA
GND_GPU_TV1
53
Q7081
L7060
XW7060
SM
53
57
D
SCALE
=GND_CHASSIS_TV
DRAWING NUMBER
REV.
C
051-6929
70
115
SHT
OF
NONE
Page Notes
- =PP3V3_PCI_ROM
- =ROM_PWD_L
(NONE)
NOTE: This page does not specify a

BootROM part number. Must use a
TABLE_x_ITEM symbol to declare
U7100 part number.
58 10
=PP3V3_PCI_ROM
C7100
C7101
C7102
2.2uF
0.1uF
0.1uF
10%
6.3V
X5R
603
20%
10V
CERM
402
20%
10V
CERM
402
11
VPP
62 61 60 59 11
58 10
21
20
19
18
17
16
15
14
10
36
11
12
R7151
13
10K
10K
14
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
15
=PP3V3_PCI_ROM
R7150
60 59
IN
ROM_CS_L
Allows ROM override module

to intercept ROM chip select
PCI_AD<20:0>
BI
60
IN
60 59
IN
60 59
IN
ROM_ONBOARD_CS_L
ROM_OE_L
ROM_WE_L
IN
=ROM_PWD_L
R7152
1
470
17
40
18
13
19
37
5%
1/16W
MF-LF
402
20
38
22
24
9
ROM_WP_L
11
16
12
10
30
31
1MX8-3.3V-90.0NS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
VCC
U7100
TSOP
OMIT
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
PCI_AD<31:24>
25
24
26
25
27
26
28
27
32
28
33
29
34
30
35
31
BI
59 60 61 62
CE
OE
WE
WP
PWD
B
GND
23
39
BootROM
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
71
115
SHT
OF
NONE
NET_TYPE
SPACING
PCI PULL-UPS
PHYSICAL
PCI_CLK_SLOTA
CLOCK
CLOCK
PCI_CLK_SLOTD
CLOCK
CLOCK
I2_FBCLK
I2_FBCLK
I2_FBCLK
I2_FBCLK
PCI_AD16_0
PCI
PCI
PCI_AD17
PCI
PCI
PCI_AD19_18
PCI
PCI
PCI_AD20
PCI
PCI
PCI_AD21
PCI
PCI
PCI_AD23_22
PCI
PCI
PCI_AD31_24
PCI
PCI
DIFFERENTIAL_PAIR
10
=PP3V3_PCI
11 59
RP7250
11 59
10K
I2_PCI_FBCLK
I2_PCI_FBCLK_OUT_R
I2_PCI_FBCLK_OUT
PCI_AD<16..0>
PCI_AD<17>
PCI_AD<19..18>
PCI_AD<20>
PCI_AD<21>
PCI_AD<23..22>
PCI_AD<31..24>
59
58 59 60 61 62
11 58 59 60 61
62
58 59 60 61 62
11 58 59 60 61
62
11 59 60 61 62
59 60 61 62
58 59 60 61 62
(BOOTROM ADDR)
(BOOTROM ADDR/SLOT A IDSEL)
(BOOTROM ADDR)
(SLOT D IDSEL)
(SLOT E IDSEL)
(PCI ONLY)
(BOOTROM DATA)

- PCI_FRAME_L
- PCI_TRDY_L
- PCI_IRDY_L
- PCI_STOP_L
PCI
PCI
PCI_CTL
PCI
PCI
PCI_CTL
PCI
PCI
PCI_CTL
PCI
PCI
PCI_CTL
PCI
PCI
PCI_CTL
PCI
PCI
PCI_PAR
PCI
PCI
PCI_CBE_L<3..0>
PCI_FRAME_L
PCI_DEVSEL_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L
PCI_PAR
8
5%
1/16W
SM-LF
RP7250
10K
2
=RP7250P2
10K
6
=RP7250P3
6
5%
1/16W
SM-LF
RP7250
62 61 60 59
10K
PCI_DEVSEL_L
2
5%
1/16W
MF-LF
402
6 59 60 61 62
6 59 60 61 62
6 59 60 61 62
OMIT
59 60 61 62
R7253
U2100
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI_SLOTA_REQ_L
PCI_SLOTA_GNT_L
PCI_SLOTD_REQ_L
PCI_SLOTD_GNT_L
11 59
I2
11 59
BGA
11 59
PCI/ROM INTERFACE
11 59
(10 of 14)
22 11
PCI_SLOTA_INT_L
22 11
PCI_SLOTD_INT_L
ROM_CS_L
ROM_OE_L
ROM_WE_L
Page Notes
- =PP3V3_PCI
AP33
AM31
AN34
ROM_CS_L
ROM_OE_L
ROM_WE_L
10K
10K
5%
1/16W
MF-LF
402
R7254
2
5%
1/16W
MF-LF
402
ROM INTERFACE
58 60
58 60
RP7251
58 60
10K
PCI DEVICE 0

- =I2_PCI_FBCLK_IN - PCI feedback clock
input. Length should match that of
longest clock from I2 to PCI device.
5
5%
1/16W
SM-LF
R7252
6 59 60 61 62
10K
4
=RP7250P4
59 60 61 62
59 60 61 62
7
5%
1/16W
SM-LF
RP7250
PCI_CBE
=RP7250P1
21 59
59 11
PCI_SLOTA_REQ_L
AR21
PCI_REQ_0_L
"Slot A" - AD17
PCI_CLK_0_H
AL25
PCI_GNT_0_L
AL19
59 11
PCI_SLOTD_REQ_L
AT20
PCI_REQ_1_L
62 61 60 59
62 61 60 59 6
62 61 60 59 6
62 61 60 59 6
62 61 60 59
PCI_PAR
PCI_FRAME_L
PCI_TRDY_L
PCI_IRDY_L
PCI_STOP_L
PCI_DEVSEL_L
=I2_PCI_FBCLK_IN
11 59
PCI_SLOTA_GNT_L

- PCI_SLOTA_GNT_L
- PCI_SLOTA_REQ_L
- PCI_SLOTD_GNT_L
- PCI_SLOTD_REQ_L
11 59
AN21
11 59
PCI_SLOTD_GNT_L
10K
6
=RP7251P1
8
5%
1/16W
SM-LF
AT24
AN24
AR25
AP27
AM25
PCI_PAR_H
PCI_FRAME_L
PCI_TRDY_L
PCI_IRDY_L
PCI_STOP_L
PCI_DEVSEL_L
RP7251
10K
3
=RP7251P3
AM28
PCI_FB_CLK_IN_H
AP31
PCI_AD_08_H
PCI_AD_09_H
PCI_AD_10_H
PCI_AD_11_H
PCI_AD_12_H
PCI_AD_13_H
PCI_AD_14_H
PCI_AD_15_H
PCI_CBE_1_L
AM27
PCI_AD_16_H
PCI_AD_17_H
PCI_AD_18_H
PCI_AD_19_H
PCI_AD_20_H
PCI_AD_21_H
PCI_AD_22_H
PCI_AD_23_H
PCI_CBE_2_L
AP25
PCI_AD_24_H
PCI_AD_25_H
PCI_AD_26_H
PCI_AD_27_H
PCI_AD_28_H
PCI_AD_29_H
PCI_AD_30_H
PCI_AD_31_H
PCI_CBE_3_L
AM21
PCI_FBCLK_OUT_H
AE23
AT32
AT31
AP30
AN28
AT34
AN30
AR31
AR30
AM30
AT28
AT30
AN27
AT27
AN25
AR28
AT29
AL22
AT26
AP24
AR24
AT25
AK22
AT23
AM24
AP22
AN22
AR22
AK21
AL21
AT22
AP21
AM22
PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_CBE_L<0>
=RP7251P4
5
5%
1/16W
SM-LF
58 59 60 61 62
58 59 60 61 62
58 59 60 61 62
SLOT E REQ/GNT pull-ups
58 59 60 61 62
58 59 60 61 62
not provided by this page.
58 59 60 61 62
58 59 60 61 62
58 59 60 61 62
59 60 61 62
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_CBE_L<1>
58 59 60 61 62
58 59 60 61 62
58 59 60 61 62
58 59 60 61 62
58 59 60 61 62
58 59 60 61 62
58 59 60 61 62
58 59 60 61 62
59 60 61 62
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_CBE_L<2>
58 59 60 61 62
11 58 59 60 61 62
58 59 60 61 62
58 59 60 61 62
11 58 59 60 61 62
11 59 60 61 62
59 60 61 62
59 60 61 62
59 60 61 62
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>
PCI_CBE_L<3>
58 59 60 61 62
58 59 60 61 62
58 59 60 61 62
58 59 60 61 62
58 59 60 61 62
58 59 60 61 62
58 59 60 61 62
58 59 60 61 62
59 60 61 62
R7205
59
3.3V IN
6
5%
1/16W
SM-LF
RP7251
11 59
PCI_AD_00_H
PCI_AD_01_H
PCI_AD_02_H
PCI_AD_03_H
PCI_AD_04_H
PCI_AD_05_H
PCI_AD_06_H
PCI_AD_07_H
PCI_CBE_0_L
7
5%
1/16W
SM-LF
RP7251
PCI INTERFACE
AP28
21
PCI_GNT_1_L
AR27
=RP7251P2
10K
"Slot D" - AD20
62 61 60 59 6
PCI DEVICE 1
PCI_CLK_1_H

(NONE)
33
I2_PCI_FBCLK_OUT_R
3.3V OUT
Output Impedance is about 20 Ohms
I2_PCI_FBCLK_OUT
21 59
5%
1/16W
MF-LF
402
I2 PCI Interface
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
72
115
SHT
OF
NONE
NET_TYPE
SPACING PHYSICAL
I315
CLOCK
DIFFERENTIAL_PAIR
=PCI_CLK33M_AIRPORT
CLOCK
11 60
Page Notes
- =PP3V3_PCI
(802.11g Power)
- =PP3V3_PWRON_BT (Bluetooth Power)

- =PCI_CLK33M_AIRPORT (33MHz PCI clock)
- =PCI_AIRPORT_RESET_L (PCI Reset)
- =USB_BT_P
(Bluetooth USB D+)
- =USB_BT_N
(Bluetooth USB D-)
(NONE)
PCI Devices implemented on this page:
AD17 (Slot "A") - AirPort (0x????/0x????)
NOTE: This AirPort implementation does
not support PME#.
CRITICAL
J7300
QT510806-L111-7F
10
62 61 59 58
62 61 59 58
11
62 61 59 58
62 61 59 58
62 61 59
R7300
11
=PCI_AIRPORT_IDSEL
22
5%
1/16W
MF-LF
402
62 61 59 58
62 61 59
62 61 59 58
62 61 59 11
62 61 59 6
62 61 59 58
62 61 59
62 61 59 58
62 61 59 6
62 61 59 58
62 61 59
62 61 59 58
62 61 59 58
62 61 59
62 61 59 58
62 61 59 58
62 61 59 58
F-ST-SM
84
81
=PP3V3_PWRON_BT
62 61 59 58
62 61 59 58
62 61 59 58
58
59 58
PCI_AD<30>
PCI_AD<27>
=PCI_AIRPORT_REQ_L
PCI_AD<25>
PCI_AD<29>
PCI_CBE_L<3>
PCI_AD<26>
PCI_AD<22>
PCI_AIRPORT_IDSEL
PCI_AD<19>
PCI_AD<21>
PCI_IRDY_L
PCI_AD<18>
PCI_DEVSEL_L
PCI_AD<16>
PCI_STOP_L
PCI_AD<12>
PCI_PAR
PCI_AD<8>
PCI_AD<9>
PCI_CBE_L<0>
PCI_AD<7>
PCI_AD<3>
PCI_AD<6>
PCI_AD<1>
PCI_AD<5>
PCI_AD<0>
ROM_ONBOARD_CS_L
ROM_CS_L
=PP3V3_PCI_AIRPORT
PCI_AD<31>
AIRPORT_CLKRUN_L_PD
TP_AIRPORT_PME_L
=PCI_AIRPORT_GNT_L
10
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
42
41
44
43
46
45
48
47
50
49
52
51
54
53
56
55
58
57
60
59
62
61
64
63
66
65
68
67
70
69
72
71
74
73
76
75
78
77
80
79
83
82
10
58 59 61 62
11
R7305
10K
PCI_AD<24>
=PCI_AIRPORT_RESET_L
PCI_AD<28>
58 59 61 62
58 59 61 62
59 61 62
PCI_AD<20>
PCI_FRAME_L
PCI_AD<17>
6 59 61 62
PCI_CBE_L<2>
=PCI_CLK33M_AIRPORT
11
PCI_AD<23>
PCI_TRDY_L
5%
1/16W
MF-LF
2 402
11 58 59 61 62
11 58 59 61 62
6 59 61 62
59 61 62
11 60
NC
PCI_AD<14>
PCI_AD<13>
PCI_AD<10>
PCI_AD<15>
TP_AIRPORT_ALT_ANTENNA
PCI_CBE_L<1>
PCI_AD<4>
PCI_AD<11>
ROM_WE_L
PCI_AD<2>
=PCI_AIRPORT_INT_L
ROM_OE_L
USB_BT_P
USB_BT_N
58 59 61 62
58 59 61 62
58 59 61 62
58 59 61 62
59 61 62
58 59 61 62
58 59 61 62
58 59
58 59 61 62
11
58 59
11
11
Q85 Connector
Q16C/516S0361/F-ST-SM
Q41C/516S0352/M-ST-SM-LF
Q85 Airport/BT Connector
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
73
115
SHT
OF
NONE
7
10
R7400
0
5%
1/10W
MF-LF
2 603
61
C7400
10UF
20%
2 6.3V
X5R
603
C7401
10UF
20%
2 6.3V
X5R
603
C7402
0.22UF
10%
2 6.3V
CERM-X5R
402
C7403
0.22UF
10%
2 6.3V
CERM-X5R
402
PP3V3_RUN_PCI1510
VOLTAGE=3.3V
C7404
10
=PP5V_PWRON_TPS2211
10
=PP3V3_PWRON_TPS2211
10%
2 6.3V
CERM-X5R
402
C7405
0.22UF
10%
2 6.3V
CERM-X5R
402
C7406
0.22UF
10%
2 6.3V
CERM-X5R
402
C7407
0.22UF
10%
2 6.3V
CERM-X5R
402
=TPS2211_SHDN_L
NC
TPS2211
V_12 SSOI AVPP
V_5_1
V_5_2 AVCC0
V_3_1 AVCC1
V_3_2 AVCC2
9
5
C7408
0.22UF
R74501
10%
2 6.3V
CERM-X5R
402
5%
1/16W
MF-LF
402 2
R7410
10K
5%
1/16W
MF-LF
402
1
15
14
16
TPS2211_SHTDWN_L
C13
D5
E1
M1
N11
N7
=PP2V5_RUN_PCI1510
GND
VCC
1
C7410
4.7uF
20%
6.3V
2 CERM
805
C7411
NC
0.22UF
10%
6.3V
2 CERM-X5R
402
L8
62 60 59 58
62 60 59 58
62 60 59 58
62 60 59 58
62 60 59 58
62 60 59 58
62 60 59 58
62 60 59 58
62 60 59 58
62 60 59 58
PCI1510 PULL-UPS
62 60 59 58
62 60 59 58
62 60 59 58
PP3V3_RUN_PCI1510
61
62 60 59 58
R7420
10K
R7421
1
10K
5%
1/16W
MF-LF
402
62 60 59 58
PCI_PERR_L
62 60 59 58
61
62 60 59 58
5%
1/16W
MF-LF
402
62 60 59 58 11
PCI_SERR_L
62 60 59 58
61
62 60 59 58
R7422
10K
62 60 59 58 11
CBUS_SUSPEND_PU
62 60 59 11
61
62 60 59
5%
1/16W
MF-LF
402
62 60 59
62 60 59 58
62 60 59 58
62 60 59 58
62 60 59 58
62 60 59 58
62 60 59 58
62 60 59 58
62 60 59 58
11
=PCI_CBUS_IDSEL
62 60 59
62 60 59
62 60 59
R74231
62 60 59
22
5%
1/16W
MF-LF
402 2
62 60 59
62 60 59 6
61
61
62 60 59 6
62 60 59 6
R7424
11
=PCI_CBUS_RESET_L
47
5%
1/16W
MF-LF
402
H10
PCI1510_VR_EN_L D4
62 60 59 6
62 60 59
2
11
11
61 11
PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>
PCI_CBE_L<0>
PCI_CBE_L<1>
PCI_CBE_L<2>
PCI_CBE_L<3>
N8
M7
L7
N6
K4
M6
L6
N5
N4
M2
M5
L4
N3
K5
L5
M4
J4
H1
H3
H2
G2
G4
F1
C3
F3
E2
F4
B1
D2
E4
D3
E3
K6
M3
J2
A1
N1
PCI_PAR
K1
PCI_IRDY_L
L2
PCI_SERR_L
PCI_CBUS_IDSEL F2
K3
PCI_PERR_L
J1
PCI_FRAME_L
L1
PCI_STOP_L
J3
PCI_TRDY_L
K2
PCI_DEVSEL_L
G3
PCI_CBUS_RESET_L
=PCI_CBUS_REQ_LC2
=PCI_CBUS_GNT_LC1
=PCI_CLK33M_CBUSG1
RP7410
10K
61
U7400
VR_EN*
VR_PORT
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PCI1510ZGU
VCCD0*
VCCD1*
BGA-LF
VPPD0
VPPD1
INTEGRATED
CD1*/CCD1*
CD2*/CCD2*
IORD*/CAD13
IOWR*/CAD15
OE*/CAD11
CE1*/CC/BE0*
VS1*/CVS1
VS2*/CVS2
WE*/CGNT*
RDY/IREQ*/CINT*
RESET/CRST*
REG*/CC/BE3*
BVD1/CSTSCHG/STSCHG*/RI*
BVD2/SPKR*/CAUDIO
PULL-UP
WP/IOIS16*/CCLKRUN*
CE2/CAD10*
INPACK/CREQ*
WAIT/CSERR*
CBUS_MFUNC5_PD
CBUS_MFUNC6_PD
CBUS_MFUNC3_PD
CBUS_MFUNC1_PD
61
11
61
61
61
61
61
61
1/16W
SM-LF
61
61
R7411
1
10K
61
CBUS_MFUNC4_PD
PAR
IRDY
SERR
IDSEL
PERR
FRAME
STOP
TRDY
DEVSEL
PRST
REQ
GNT
PCLK
N10
CBUS_SUSPEND_PU
=PCI_CBUS_INT_L K7
CBUS_MFUNC1_PD N9
CBUS_MFUNC2_PD L9
CBUS_MFUNC3_PD K10
CBUS_MFUNC4_PD M10
CBUS_MFUNC5_PD N12
CBUS_MFUNC6_PD L10
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
L11
D0/CAD27
D1/CAD29
D2/RSVD
D3/CAD0
D4/CAD1
D5/CAD3
D6/CAD5
D7/CAD7
D8/CAD28
D9/CAD30
D10/CAD31
D11/CAD2
D12/CAD4
D13/CAD6
D14/RSVD
D15/CAD8
GRST
GND
R7412
1
10K
A2
CBUS_MFUNC2_PD
11
12
13
C7450 1
L12
K9
M11
L13
B5
F12
C11
G10
H13
B2
A9
D13
A6
D8
A8
C6
D6
A5
G13
B8
B6
0.1uF
A11
D1
F13
DIFFERENTIAL_PAIR
=PCI_CLK33M_CBUS
CLOCK
OC
A4
C4
A3
K11
K12
J13
J10
H12
C5
B4
B3
M12
J11
K13
J12
H11
C7451
20%
10V
2 CERM
402
0.1UF ARE USED TO INCREASE ESD DISCHARGES OF UP TO 10KV
CBUS_VCCD0_L
CBUS_VCCD1_L
CBUS_VPPD0
CBUS_VPPD1
PC CARD/CARDBUS CONNECTOR
CBUS_DET_1_L 61
CBUS_DET_2_L 61
CBUS_IORD_L 61
CBUS_IOWR_L 61
CBUS_OE_L
61
CBUS_CE1_L
61
CBUS_VS1
61
CBUS_VS2
61
CBUS_WE_L
61
CBUS_READY
61
CBUS_RESET_L 61
CBUS_REG_L
61
CBUS_BVD1_L 61
CBUS_BVD2_L 61
CBUS_WP_L
61
CBUS_CE2_L
61
CBUS_INPACK_L 61
CBUS_WAIT_L 61
CBUS_ADDR<0> 61
CBUS_ADDR<1> 61
CBUS_ADDR<2> 61
CBUS_ADDR<3> 61
CBUS_ADDR<4> 61
CBUS_ADDR<5> 61
CBUS_ADDR<6> 61
CBUS_ADDR<7> 61
CBUS_ADDR<8> 61
CBUS_ADDR<9> 61
CBUS_ADDR<10> 61
CBUS_ADDR<11> 61
CBUS_ADDR<12> 61
CBUS_ADDR<13> 61
CBUS_ADDR<14> 61
CBUS_ADDR<15> 61
CBUS_ADDR_16_R
CBUS_ADDR<17> 61
CBUS_ADDR<18> 61
CBUS_ADDR<19> 61
CBUS_ADDR<20> 61
CBUS_ADDR<21> 61
CBUS_ADDR<22> 61
CBUS_ADDR<23> 61
CBUS_ADDR<24> 61
CBUS_ADDR<25> 61
CRITICAL
J7490
QT500806-L121-9F
M-ST-SM
84
61
61
61
61
61
61
61
61
61
61
61
61
61
61
TI REFERENCE SCHEMATIC DID NOT HAVE BULK ON PPVCC_CBUS_SW
C7490
2.2uF
10%
2 6.3V
X5R
603
C7491
2.2uF
10%
2 6.3V
X5R
603
61
61
61
61
61
61
61
R7430
1
47
61
CBUS_ADDR<16>
61
61
61
5%
1/16W
MF-LF
402
61
61
61
61
61
61
CBUS_DATA<0> 61
CBUS_DATA<1> 61
CBUS_DATA<2> 61
CBUS_DATA<3> 61
CBUS_DATA<4> 61
CBUS_DATA<5> 61
CBUS_DATA<6> 61
CBUS_DATA<7> 61
CBUS_DATA<8> 61
CBUS_DATA<9> 61
CBUS_DATA<10> 61
CBUS_DATA<11> 61
CBUS_DATA<12> 61
CBUS_DATA<13> 61
CBUS_DATA<14> 61
CBUS_DATA<15> 61
61
CBUS_DET_1_L
CBUS_DATA<11>
CBUS_DATA<12>
CBUS_DATA<13>
CBUS_DATA<14>
CBUS_DATA<15>
CBUS_CE2_L
CBUS_VS1
CBUS_IORD_L
CBUS_IOWR_L
CBUS_ADDR<17>
CBUS_ADDR<18>
CBUS_ADDR<19>
CBUS_ADDR<20>
CBUS_ADDR<21>
PPVCC_CBUS_SW
PPVPP_CBUS_SW
CBUS_ADDR<22>
CBUS_ADDR<23>
CBUS_ADDR<24>
CBUS_ADDR<25>
CBUS_VS2
CBUS_RESET_L
CBUS_WAIT_L
CBUS_INPACK_L
CBUS_REG_L
CBUS_BVD2_L
CBUS_BVD1_L
CBUS_DATA<8>
CBUS_DATA<9>
CBUS_DATA<10>
CBUS_DET_2_L
81
10
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
42
41
44
43
46
45
48
47
50
49
52
51
54
53
56
55
58
57
60
59
62
61
64
63
66
65
68
67
70
69
72
71
74
73
76
75
78
77
80
79
83
82
CBUS_DATA<3>
CBUS_DATA<4>
CBUS_DATA<5>
CBUS_DATA<6>
61
61
61
61
CBUS_DATA<7> 61
CBUS_CE1_L
61
CBUS_ADDR<10> 61
CBUS_OE_L
61
CBUS_ADDR<11> 61
CBUS_ADDR<9> 61
CBUS_ADDR<8> 61
CBUS_ADDR<13> 61
CBUS_ADDR<14> 61
CBUS_WE_L
61
CBUS_READY
61
PPVCC_CBUS_SW 61
PPVPP_CBUS_SW
CBUS_ADDR<16>
CBUS_ADDR<15>
CBUS_ADDR<12>
CBUS_ADDR<7>
CBUS_ADDR<6>
CBUS_ADDR<5>
CBUS_ADDR<4>
CBUS_ADDR<3>
CBUS_ADDR<2>
CBUS_ADDR<1>
CBUS_ADDR<0>
CBUS_DATA<0>
CBUS_DATA<1>
CBUS_DATA<2>
CBUS_WP_L
61
61
61
61
61
61
61
61
61
61
61
61
61
61
61
Cardbus
SYNC_DATE=N/A

H4
K8
M13
N2

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
74
115
SHT
OF
NONE
61
SYNC_MASTER=N/A
61
NC
5%
1/16W
MF-LF
402
11 61
0.1uF
20%
10V
CERM 2
402
61
61
5%
1/16W
MF-LF
402
N13
A0/CAD26 C7
A1/CAD25 D7
A2/CAD24 B7
A3/CAD23 D10
A4/CAD22 B12
A5/CAD21 C8
A6/CAD20 C9
A7/CAD18 A12
A8/CC/BE1* E11
A9/CAD14 F11
A10/CAD9 G11
A11/CAD12 G12
A12/CC/BE2* D9
A13/CPAR E12
A14/CPERR* D12
A15/CIRDY* C10
A16/CCLK B13
A17/CAD16 F10
A18/RSVD E13
A19/CBLOCK* A13
A20/CSTOP* E10
A21/CDEVSEL* D11
A22/CTRDY* C12
A23/CFRAME* A10
A24/CAD17 B10
A25/CAD19 B9
5%
1
CLOCK
PPVPP_CBUS_SW 61
VOLTAGE=3.3V
PPVCC_CBUS_SW 61
VOLTAGE=3.3V
CLAMP FOR PC-CARDVCCCB B11

CLAMP FOR PCI
VCCP L3
C/BE0*
C/BE1*
C/BE2*
C/BE3*
SPKROUT
RI_OUT/PME
SUSPEND
NC M9
NC M8
CRITICAL
CLK_48_RSVD/NC
I192
10
VCCD0
VCCD1
VPPD0
VPPD1
SHTDWN
A7
NET_TYPE
SPACING PHYSICAL
MAKE SURE VCC AND VPP ARE WIDE PLANE/TRACES

TO MINIMIZE INDUCTANCE!
U7450
1
0.22UF
10
10
=PP3V3_RUN_PCI1510_R
NET_TYPE
SPACING PHYSICAL
I6
CLOCK
DIFFERENTIAL_PAIR
=PCI_CLK33M_USB2
CLOCK
11 62
Page Notes
- =PPVIO_PCI (to 3.3V or 5V)
- =PP3V3_PCI_USB2 (D3cold rail)
D
10
=PPVIO_PCI_USB2
USB2_NEC

- USB2_NEC
C7500 1
0.1uF
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58 11
61 60 59 58
61 60 59 58
61 60 59 58 11
61 60 59 11
61 60 59
61 60 59
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59 58
61 60 59
11
61 60 59
=PCI_USB2_IDSEL
61 60 59
USB2_NEC
61 60 59
R75001
22
10
5%
1/16W
MF-LF
402 2
=PP3V3_PCI_USB2
61 60 59
61 60 59 6
61 60 59 6
61 60 59 6
USB2_NEC
USB2_NEC
R75011 R75021
USB2_NEC
RP7510
11
=PCI_USB2_INT_L
47
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402 2
61 60 59 6
61 60 59
11
11
USB2_NEC
5%
1/16W
SM-LF
RP7510
2
47
USB2_NEC
5%
1/16W
SM-LF
RP7510
1
47
SYS_WARM_RESET_L
25 22
SYS_PME_L
USB2_NEC
R7510
1
11
=PCI_USB2_RESET_L
47
5%
1/16W
MF-LF
402
47
5%
1/16W
MF-LF
402
USB2_NEC
R7511
1
P5
N5
P4
N4
M3
N3
M1
L2
L1
K2
L3
K1
K3
J2
J1
F2
E3
E1
D3
D1
D2
C2
C1
B4
A4
B5
C4
A5
C5
B6
A6
M2
PCI_CBE_L<0>
PCI_CBE_L<1>
PCI_CBE_L<2>
PCI_CBE_L<3>
J3
F1
C3
PCI_PAR
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L
PCI_USB2_IDSEL
PCI_DEVSEL_L
=PCI_USB2_REQ_L
=PCI_USB2_GNT_L
NEC_PERR_L_PU
NEC_SERR_L_PU
NEC_INTA_L
NEC_INTB_L
NEC_INTC_L
=PCI_CLK33M_USB2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
USB2_NEC
CRITICAL
U7500
NEC_uPD720101_USB2
NEC_VBBRST_L
NEC_CRUN_L_PD
NEC_PME_L
NEC_VCCRST_L
TP_NEC_SMI_L
47
J4
PAR
FRAME
IRDY
G1
TRDY
G3
STOP
B3 IDSEL
G2
DEVSEL
C6
REQ
D6
GNT
H2
PERR
H1
SERR OD
C7
INTA OD
B7
INTB OD
A7
INTC OD
A8
PCLK
F3
F4
B8
N6
D9
C9
L6
VBBRST (CHIP RESET)

CRUN
PME OD
VCCRST (PCI RESET)
SMI OD
USB2_NEC
R7512
FBGA-LF
CBE0
CBE1
CBE2
CBE3
5%
1/16W
SM-LF
25 22
62 11
M5
PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>
VDD_PCI
H3
NOTE: This USB2 implementation supports

D3cold.
C8
20%
10V
CERM 2
402
PCI Devices implemented on this page:

AD27 (Slot "G") - USB2 (0x1033/0x0035)
M4

- =PCI_CLK33M_USB2
- =PCI_USB2_REQ_L
- =PCI_USB2_IDSEL
- =PCI_USB2_RESET_L
- =PCI_USB2_GNT_L
- =PCI_USB2_INT_L
L7
NEC_LEGC_PD
LEGC
B
IPD NTEST1 M8
TP_NEC_NTEST1
IPD
SMC M7
TP_NEC_SMC
IPD
IPD
TEB N7
AMC P7
TP_NEC_TEB
TP_NEC_AMC
IPD
TEST L8
NANDTEST
SRCLK
SRDTA
IPD SRMOD
M10
M9
N9
P9
TP_NEC_TEST
TP_NEC_NANDTEST
TP_NEC_SRCLK
TP_NEC_SRDATA
TP_NEC_SRMOD
USB2_NEC
5%
1/16W
MF-LF
402
RP7510 & R7510-12 required to
facilitate NAND-tree testing
R75031
4.7K
5%
1/16W
MF-LF
402 2
USB2_NEC
1
R7504
47
5%
1/16W
MF-LF
2 402
NEC USB2
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
75
115
SHT
OF
NONE
NET_TYPE
SPACING
PHYSICAL
UATA_DD
UATA
UATA
UATA_DD7
UATA
UATA
UATA_DD
UATA
UATA
UATA_HOST
UATA
UATA
UATA_HOST
UATA
UATA
UATA_HOST
UATA
UATA
UATA_HSTROBE
UATA
UATA
UATA_HOST
UATA
UATA
UATA_HOST_R
UATA
UATA
UATA100 SERIES TERMINATION
DIFFERENTIAL_PAIR
UATA_DD_R<15..8>
UATA_DD_R<7>
UATA_DD_R<6..0>
UATA_DA_R<2..0>
2 6 63
PLACE CLOSE TO I2
6 63
2 6 63
RP8150
2 6 63
33
UATA_HOST_R
UATA
UATA
UATA_DSTROBE
UATA
UATA
UATA_DEV_R
UATA
UATA
UATA_DEV_R
UATA
UATA
UATA
UATA
UATA
UATA
UATA
UATA
UATA
UATA
UATA
UATA
UATA
UATA
UATA
UATA
UATA
UATA_DD<15..0>
UATA_DA<2..0>
UATA_CS0_L
UATA_CS1_L
UATA_HSTROBE
UATA_STOP
UATA_DMACK_L
UATA_RESET_L
UATA_DSTROBE
UATA_DMARQ
UATA_INTRQ
UATA
UATA
UATA
UATA
UATA
UATA
UATA_CS0_L_R
UATA_CS1_L_R
UATA_HSTROBE_R
UATA_STOP_R
UATA_DMACK_L_R
UATA_RESET_L_R
UATA_DSTROBE_R
UATA_DMARQ_R
UATA_INTRQ_R
UATA
6 63
=RP8150P1
RP8150
63
33
63
6
=RP8150P2
63
5%
1/16W
SM-LF
RP8150
63
RP8150
63
33
5%
1/16W
SM-LF
63
6
63
=RP8150P3
=RP8150P4
63
6 7 64
6
RP8151
RP8151
5%
1/16W
SM-LF
=RP8151P2
7 63 64
5%
1/16W
SM-LF
RP8151
7 63 64
RP8151
7 63 64
33
5%
1/16W
SM-LF
7 63 64
6
7 63 64
=RP8151P3
=RP8151P4
7 63 64
Page Notes
(NONE)

- UATA_DD<15..0>(_R)
- UATA_DA<2..0>(_R)
- UATA_CS0_L(_R)
(IDE_CS1FX_L)
OMIT
U2100

(NONE)
I2
=RP8152P2
RP8152
RP8152
5%
1/16W
SM-LF
RP8152
RP8152
5%
1/16W
SM-LF
=RP8152P4
UATA INTERFACE
I2_UATA_VREF
1
AA9
R8100
(11 of 14)
ATA_D_00_H
ATA_D_01_H
ATA_D_02_H
ATA_D_03_H
ATA_D_04_H
ATA_D_05_H
ATA_D_06_H
ATA_D_07_H
ATA_D_08_H
ATA_D_09_H
ATA_D_10_H
ATA_D_11_H
ATA_D_12_H
ATA_VREF_H
ATA_D_13_H
ATA_D_14_H
ATA_D_15_H
AB6
AB5
AD6
AD5
AD7
AE7
AE8
AD8
AB4
AE1
AD2
AE2
AD4
AA6
AD1
AB7
UATA_DD_R<15..0>
ATA_A_0_H
ATA_A_1_H
ATA_A_2_H
ATA_RST_L
ATA_WR_L
ATA_RD_L
63
63
63
UATA_DSTROBE_R
AA5
ATA_CHRDY_H
UATA_INTRQ_R
UATA_DMARQ_R
AB1
ATA_INTRQ_H
ATA_DMARQ_H
Y9
ATA_CS0_L
ATA_CS1_L
ATA_DMACK_L
AC1
AB3
AB2
=RP8153P2
RP8153
5%
1/16W
SM-LF
RP8153
RP8153
5%
1/16W
SM-LF
=RP8153P3
=RP8150P6
BI
=RP8150P5
BI
=RP8151P8
BI
=RP8151P7
BI
=RP8151P6
BI
=RP8151P5
BI
=RP8152P8
BI
=RP8152P7
BI
=RP8152P6
BI
=RP8152P5
BI
=RP8153P8
BI
=RP8153P7
BI
=RP8153P6
BI
=RP8153P5
BI
=RP8154P8
OUT
=RP8154P7
OUT
=RP8154P6
OUT
=RP8154P5
33
3
4
5
33
6
7
10
11
12
=RP8153P4
RP8154
RP8154
5%
1/16W
SM-LF
=RP8154P1
R8151
10K
5
5%
1/16W
SM-LF
8
9
33
1
33
5%
1/16W
MF-LF
2 402
13
=RP8154P2
5%
1/16W
SM-LF
RP8154
RP8154
5%
1/16W
SM-LF
=RP8154P3
33
3
14
15
33
UATA_DA_R<2..0>
=RP8154P4
4
5%
1/16W
SM-LF
1
2
AE6
63
UATA_RESET_L_R
UATA_STOP_R
UATA_HSTROBE_R
AB8
AA8
AE3
UATA_CS0_L_R
UATA_CS1_L_R
UATA_DMACK_L_R
AA4
AA7
OUT
(IDE_CS3FX_L)
UATA_CS1_L
OUT
7 63 64
UATA_RESET_L
OUT
7 63 64
UATA_DMACK_L
OUT
7 63 64
(IDE_DIOR_L)
UATA_HSTROBE
OUT
7 63 64
(IDE_DIOW_L)
UATA_STOP
OUT
7 63 64
UATA_DMARQ
IN
7 63 64
IN
7 63 64
IN
7 63 64
2 6 63
R8160
UATA_CS1_L_R
63
63
UATA_RESET_L_R
33
6 63
63
R8162
UATA_DMACK_L_R
R8163
63
63
UATA_HSTROBE_R
22
R8164
1
63
82
UATA_DMARQ_R
R8166
(IDE_IORDY)
UATA_DSTROBE
82
1
2
5%
1/16W
MF-LF
402
UATA_DSTROBE_R
22
5%
1/16W
MF-LF
402
R8165
63
5%
1/16W
MF-LF
402
UATA_STOP_R
22
5%
1/16W
MF-LF
402
63
63
5%
1/16W
MF-LF
402
63
33
5%
1/16W
MF-LF
402
R8161
63
5%
1/16W
SM-LF
33
33
1K
1%
1/16W
MF-LF
402
2
RP8153
=RP8153P1
2 6 63
BI
33
5%
1/16W
SM-LF
BGA

(NONE)
5%
1/16W
SM-LF
=RP8152P3
=RP8150P7
33
1
33
6
5%
1/16W
SM-LF
=RP8152P1
33
7 63 64
7 63 64
BI
33
33
6 7 64
5%
1/16W
SM-LF
=RP8151P1
6 7 64
=RP8150P8
33
33
8
5%
1/16W
SM-LF
5%
1/16W
MF-LF
402
C8166
10pF
5%
50V
CERM
402
R8167
63
UATA_INTRQ_R
82
1
UATA_INTRQ
2
5%
1/16W
MF-LF
402
I2 UATA Interface
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
81
115
SHT
OF
NONE
HDD CONNECTOR
64 10
ODD CONNECTOR
=PP3V3_RUN_HDD
10 7
NO STUFF
NO STUFF
1
R8210
R8211
10K
R8212
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
=PP5V_RUN_ODD
R8255
4.7K
CRITICAL
J8200
5%
1/16W
MF-LF
2 402
5%
1/8W
MF-LF
2 805
M-ST-SM2-LF
1
50
49
48
47
46
45
44
43
42
10
41
11
40
12
39
13
38
14
37
15
36
16
35
17
34
18
33
19
32
20
31
21
30
22
29
23
28
R8203
24
27
25
26
64 63 7
64 63 7 6
64 63 7 6
64 63 7 6
64 63 7 6
64 63 7 6
64 63 7 6
64 63 7 6
64 63 7 6
64 63 7
64 63 7
64 63 7
64 63 7 6
64
64 63 7 6
64 63 7 6
UATA_RESET_L
UATA_DD<7>
UATA_DD<6>
UATA_DD<5>
UATA_DD<4>
UATA_DD<3>
UATA_DD<2>
UATA_DD<1>
UATA_DD<0>
UATA_DMARQ
UATA_HSTROBE
UATA_DMACK_L
UATA_DA<1>
UATA_PDIAG
UATA_DA<0>
UATA_CS0_L
5V_HD_LOGIC
64 10 7
=PP5V_RUN_HDD
5%
1/16W
MF-LF
402
R82001
64 10
=PP3V3_RUN_HDD
6 7 63 64
CRITICAL
6 7 63 64
J8250
UATA_DD<10>
UATA_DD<11>
UATA_DD<12>
UATA_DD<13>
M-ST-SM2-LF
6 7 63 64
NC
6 7 63 64
6 7 63 64
64 63 7 6
6 7 63 64
64 63 7 6
64 63 7 6
UATA_DD<14>
UATA_DD<15>
6 7 63 64
64 63 7 6
64 63 7 6
UATA_STOP
UATA_DSTROBE
7 63 64
64 63 7 6
7 63 64
64 63 7 6
64 63 7 6
UATA_INTRQ
UATA_DA<2>
UATA_DASP_L
UATA_CS1_L
=PP5V_RUN_HDD
UATA_DD<8>
UATA_DD<9>
UATA_DD<10>
UATA_DD<11>
6 7 63 64
UATA_DD<12>
UATA_DD<13>
UATA_DD<14>
UATA_DD<15>
7 63 64
6 7 63 64
64 63 7
64
64 63 7
7 63 64
64 63 7
UATA_DMARQ
UATA_HSTROBE
UATA_DMACK_L
7 10 64
64 63 7 6
64 63 7
R8201
64
10K
5%
1/16W
MF-LF
402 2
R8202
UATA_DD<8>
UATA_DD<9>
UATA_DA<2>
UATA_CS1_L
20K
3V_HD_LOGIC
PP3V3R5V_RUN_HDD_LOGIC
VOLTAGE=5V
PP5V_RUN_ODD
VOLTAGE=5V
5%
1/16W
MF-LF
2 402
UATA_PDIAG
50
49
48
47
46
45
44
43
42
10
41
11
40
12
39
13
38
14
37
15
36
16
35
17
34
18
33
19
32
20
31
21
30
22
29
23
28
24
27
25
26
UATA_RESET_L
UATA_DD<7>
UATA_DD<6>
UATA_DD<5>
UATA_DD<4>
UATA_DD<3>
UATA_DD<2>
UATA_DD<1>
UATA_DD<0>
UATA_STOP
UATA_DSTROBE
UATA_INTRQ
UATA_DA<1>
UATA_DA<0>
UATA_CS0_L
UATA_DASP_L
7 63 64
6 7 63 64
6 7 63 64
6 7 63 64
6 7 63 64
6 7 63 64
6 7 63 64
6 7 63 64
6 7 63 64
7 63 64
7 63 64
7 63 64
6 7 63 64
6 7 63 64
6 7 63 64
64
5%
1/16W
MF-LF
402
ATA Connectors
Q16C/516S0357/M-ST-SM2-LF
Q41C/516S0335/M-ST-SM1-LF
HDD/ODD Connectors
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
82
115
SHT
OF
NONE
NET_TYPE
ENET_RX_CLK25M
SPACING
PHYSICAL
CLOCK
CLOCK
DIFFERENTIAL_PAIR
ENET_CLK25M_TX
11 65
ENET_RX_CLK125M
CLOCK
CLOCK
ENET_CLK125M_RX
11 65
ENET_GBE_REF
CLOCK
CLOCK
11 65
ENET_TX_CLK
CLOCK
CLOCK
ENET_CLK125M_GTX_R
65 66
ENET_RXD3_0
ENET
ENET
ENET_RXD<3..0>
9 11 65
ENET_RXD7_4
ENET
ENET
ENET_RXD<7..4>
9 11 65
ENET_RX_DV
ENET
ENET
ENET_RX_DV
9 11 65
9 11 65
ENET_RX_CTL
ENET
ENET
ENET_RX_ER
ENET_TXD3_0
ENET
ENET
ENET_TXD_R<3..0>
11 65
ENET_TXD7_4
ENET
ENET
ENET_TXD_R<7..4>
11 65
11 65
ENET_TX_EN
ENET
ENET
ENET_TX_EN_R
ENET_TX_ER
ENET
ENET
ENET_TX_ER_R
11 65
ENET_COL
ENET
ENET
ENET_COL
9 11 65
ENET_RX_CTL
ENET
ENET
ENET_CRS
9 11 65
ENET_MDC
ENET
ENET
ENET_MDC
9 11 65
ENET_MDIO
ENET
ENET
ENET_MDIO
9 11 65
ENET
ENET
I2_ENET_MDIO
65
Page Notes
- =PP2V5R3V3_PWRON_I2_ENET
(NONE)
(NONE)
NOTE: This page does not provide any
series termination. Any
termination, including clock
signals, should be provided by
the PHY page or a non-shared
schematic page.
65 10
OMIT
U2100
C8459
10uF
20%
6.3V
X5R
603
C8450
C8451
C8452
1uF
1uF
1uF
10%
10%
10%
6.3V
CERM
402
NOTE: All I2 GPIOs should have a

pull-up or pull-down resistor.
This page does not provide a
resistor for GPIO 16. It must be
provided by the PHY page or a
non-shared schematic page.
6.3V
CERM
402
C8453
I2
1uF
BGA
10%
6.3V
CERM
402
ETHERNET INTERFACE
6.3V
CERM
402
(12 of 14)
U3
U6
U9
C8454
1uF
C8455
1uF
10%
2
CERM
402
C8456
V13
1uF
10%
6.3V
W14
10%
6.3V
CERM
402
6.3V
Y3
CERM
402
Y6
NOTE: ENET_RX_DV has a hold spec

violation on I2. May want to
lengthen net by ~250ps. Net has a
unique ECSet name to allow this.
VDD25_0
VDD25_1
VDD25_2
VDD25_3
VDD25_4
VDD25_5
VDD25_6
1
65 11
65 11 9
65 11 9
65 11 9
65 11 9
65 11 9
65 11 9
65 11 9
65 11 9
65 11 9
65 11 9
65 10
ENET_CLK25M_TX
ENET_CLK125M_RX
W7
ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
W2
W8
W3
V2
U1
ENET_RXD<4>
ENET_RXD<5>
ENET_RXD<6>
ENET_RXD<7>
V3
ENET_RX_DV
ENET_RX_ER
W9
V1
T1
T3
W1
67 66 18 10
=PP3V3_VESTA
1
R8405
1.5K
2
65 11
10 65
ETH_TXCLK_H
ETH_RXCLK_H
ETH_MDC_H
ETH_MDIO_H
W4
ETH_RXD_0_H
ETH_RXD_1_H
ETH_RXD_2_H
ETH_RXD_3_H
ETH_TXD_0_H
ETH_TXD_1_H
ETH_TXD_2_H
ETH_TXD_3_H
V8
ETH_RXD_4_H
ETH_RXD_5_H
ETH_RXD_6_H
ETH_RXD_7_H
ETH_RXDV_H
ETH_RXER_H
W6
65
V7
V6
ETH_TXD_4_H
ETH_TXD_5_H
ETH_TXD_6_H
ETH_TXD_7_H
9 11 65
ETH_TXEN_H
ETH_TXER_H
T7
T8
ENET_TX_EN_R
ENET_TX_ER_R
ETH_GTXCLK_H
V9
ENET_CLK125M_GTX_R
T6
5%
1/16W
MF-LF
402
SOT-363
6
S 1
ENET_MDIO
9 11 65
11 65
NO STUFF
11 65
ENET_TXD_R<4>
ENET_TXD_R<5>
ENET_TXD_R<6>
ENET_TXD_R<7>
T5
2N7002DW-X-F
ENET_MDC
I2_ENET_MDIO
V5
T4
Q8420
ENET_TXD_R<0>
ENET_TXD_R<1>
ENET_TXD_R<2>
ENET_TXD_R<3>
V4
R8420
10K
5%
1/16W
MF-LF
402
11 65
R8421
11 65
11 65
5%
1/16W
MF-LF
402
11 65
11 65
11 65
11 65
11 65
65 11 9
R8410 1
65 11 9
ENET_COL
ENET_CRS
AA3
AA2
W5
ETH_COL_H
ETH_CRS_H
10K
5%
1/16W
MF-LF
402
65 11
ETH_GREFCLK_H
65 66
Signal
ENET_ENERGYDET
I2_ENET_PVT
1
R8400
1K
1%
1/16W
MF-LF
402
Pin
Y1
U10
EXT_05_H
GPIO_16_H
AA1
Pin
Signal
ENET_RESET_L
11
ETH_PVT_H
These GPIOs are referenced

to the Ethernet I/O rail
I2 Ethernet Interface
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
84
115
SHT
OF
NONE
NET_TYPE
SPACING
PHYSICAL
(PROVIDED BY LINK PAGE)
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
CLOCK
DIFFERENTIAL_PAIR
ENET_CLK125M_GBE_REF_R
ENET_CLK125M_RX_R
ENET_CLK25M_TX_R
ENETCONN
ENETCONN
ENETCONN
ENETCONN_0
ENETCONN
ENETCONN
ENETCONN
ENETCONN_0
ENETCONN
ENETCONN
ENETCONN
ENETCONN_1
ENETCONN
ENETCONN
ENETCONN
ENETCONN_1
ENETCONN
ENETCONN
ENETCONN
ENETCONN_2
ENETCONN
ENETCONN
ENETCONN
ENETCONN_2
ENETCONN
ENETCONN
ENETCONN
ENETCONN_3
ENETCONN
ENETCONN
ENETCONN
ENETCONN_3
VESTA_CLK25M_XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
ENETCONN_0_P
ENETCONN_0_N
ENETCONN_1_P
ENETCONN_1_N
ENETCONN_2_P
ENETCONN_2_N
ENETCONN_3_P
ENETCONN_3_N
L8520
66
FERR-EMI-600-OHM
66
PP2V5_VESTA_XTALVDD1
66
66 67
66 67
C8520
0.001uF
66 67
66 67
10 69
SM
C8521
10UF
20%
50V
CERM
402
66 67
=PP2V5_ENETFW
VOLTAGE=2.5V
20%
6.3V
X5R
603
66 67
FERR-EMI-600-OHM
66 67
VESTA_CLK25M_XTALI
VESTA_CLK25M_XTALO
VESTA_CLK25M_XTALO_R
L8510
66 67
PP2V5_VESTA_BIASVDD1
VOLTAGE=2.5V
66
66
66
SM
C8510
0.1uF
20%
10V
CERM
402
Page Notes
L8530
FERR-EMI-600-OHM

- =PP2V5_ENETFW
- =PP1V2_ENETFW
1
0.001uF
50 mils
Primary Max Sep:
M1
P1
N1
Place close to PHY
R8560
0
1
65
IN
ENET_CLK125M_GTX_R
ENET_CLK125M_GTX
A4
GTXCLK
OMIT
5%
1/16W
MF-LF
402
500 mils
CLK125 D1
66
ENET_CLK125M_GBE_REF_R
TXC A6
66
ENET_CLK25M_TX_R
RXC C1
BCM5462
66
Vesta Ethernet LowPwr
11
IN
11
IN
IN
Disables Vesta Ethernet Circuit
11
IN
11
IN
11
IN
11
11
67 65 18 10
1K
=PP3V3_ENET
5%
1/16W
MF-LF
402
Q8580
IN
SOT-363
2N7002DW-X-F
5
SOT-363
11
IN
11
IN
11
IN
11
BI
20%
10V
CERM
402
Circuit ensures Vesta LOWPWR signal is low when
=VESTA_MDC
=VESTA_MDIO
G1
VESTA_ENET_LOWPWR
H5
LOWPWR
TP_VESTA_PHYA<0>
TP_VESTA_PHYA<1>
TP_VESTA_PHYA<2>
TP_VESTA_PHYA<3>
TP_VESTA_PHYA<4>
L5
PHYA[0]
PHYA[1]
PHYA[2]
PHYA[3]
PHYA[4]
C7
D6
E6
C5
B5
A5
C4
G2
Vesta RESET* is asserted, and allows LOWPWR to

assert when ethernet link is unpowered.
2
2
L4
L3
L2
L1
TP_VESTA_EN_10B
TP_VESTA_RGMIIEN
TP_VESTA_FDX
TP_VESTA_F1000
TP_VESTA_SPD0
TP_VESTA_MANMS
TP_VESTA_HUB
TP_VESTA_ER
K3
B8
C8
K4
K5
D9
A9
H3
Vesta Config Straps:

PHYA<4..0> - PHY Address Select
MANMS - Manual Master/Slave Configuration Select
(Internal Pull-downs)
Sets manual master/slave configuration enable bit
TP_VESTA_TEST<0>
TP_VESTA_TEST<1>
TP_VESTA_TVCO
(Internal Pull-down)
EN_10B - TBI Interface Select
1 - TBI/RTBI Mode
HUB - Repeater Select
0 - GMII/RGMII Mode
Sets Hub/DTE bit and master/slave configuration value bit
RGMIIEN - RGMII Enable
ER - Edge Rate Select
0 - Rise time approx. 4 ns
FDX - Full-Duplex Select
AN_EN - Auto-Negotiation Select
Sets manual duplex mode bit
1 - Auto-negotiation enabled
(Internal Pull-up)
0 - Auto-negotiation disabled
M5
N3
N2
P2
MDC
MDIO
COL F3
CRS G3
RBC0 A3
RBC1 B3
EN_10B
RGMIIEN
FDX
F1000
SPD0
MANMS
HUB
ER
NC?
NC?
OUT
11
OUT
11
OUT
11
OUT
11
OUT
11
OUT
11
OUT
11
=ENET_RX_DV_R
=ENET_RX_ER_R
OUT
11
OUT
11
=ENET_COL_R
=ENET_CRS_R
OUT
11
OUT
11
CRITICAL
Y8500
1
1 - If RGMII Mode enabled, RXC clock and
OUT
11
=VESTA_CLK125M_RX
OUT
11
I2BORG SPECIFIC
Not convention-compliant,
=VESTA_ should be
replaced with ENET_
(6 nets)
TP_VESTA_RBC0
TP_VESTA_RBC1
TEST[0]
TEST[1]
TVCO
ENETCONN_0_P
ENETCONN_0_N
BI
66 67
BI
66 67
TRD+[1] R7
TRD-[1] R6
ENETCONN_1_P
ENETCONN_1_N
BI
66 67
BI
66 67
TRD+[2] R8
TRD-[2] R9
ENETCONN_2_P
ENETCONN_2_N
BI
66 67
BI
66 67
TRD+[3] R11
TRD-[3] R10
ENETCONN_3_P
ENETCONN_3_N
BI
66 67
BI
66 67
SLAVE*/AN_EN
QUALITY*/TXC_RXC_DELAY A8
LINK1* A10
LINK2* B11
FDXLED* B10
XMTLED* B12
ACTLED* A11
C10
=VESTA_ENERGYDET
OUT
11
TP_VESTA_AN_EN
TP_VESTA_TXC_RXC_DELAY
TP_VESTA_LINKSPD1_L
TP_VESTA_LINKSPD2_L
TP_VESTA_FDXLED_L
TP_VESTA_XMTLED_L
TP_VESTA_ACTLED_L
5%
50V
CERM
402
R8590
RDAC1 R1
PLLGND1
R8592
49.9
49.9
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R8591 1
R8594
49.9
R8593 1
49.9
1%
1/16W
MF-LF
402
R8595 1
R8597 1
49.9
49.9
49.9
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402 2
ENET_MDI1
R8596
49.9
ENET_MDI0
XTALI
XTALO
ENET_MDI2
ENET_MDI3
VESTA_RDAC1_PD
R8509 1
1.24K
5%
1/16W
MF-LF
402
VESTA_CLK25M_XTALO
33pF
TXC_RXC_DELAY
=VESTA_CLK25M_TX
1%
1/16W
MF-LF
402
C8590
C8592
C8594
0.01UF
0.01UF
0.01UF
20%
16V
CERM
402
20%
16V
CERM
402
20%
16V
CERM
402
C8596
0.01UF
20%
16V
CERM
402
PLACE RESISTORS CLOSE TO PHY
8X4.5MM-SM2
C8500
F1000 - Speed Select
11
TRD+[0] R4
TRD-[0] R5
INTR*/ENERGYDET D10
XTALGND BIASGND
R8501
0
(Internal Pull-up)
(Internal Pull-up)
RX_DV
RX_ER C2
OUT
11
2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
25.0000M
See table below
M4
Put crystal circuit close to PHY

66 VESTA_CLK25M_XTALI
66 VESTA_CLK25M_XTALO_R
1 - Rise time approx. 5 ns
0 - GMII/TBI Mode
TX_EN
TX_ER
D2
P3
1 - RGMII/RTBI Mode
=ENET_RXD_R<0>
=ENET_RXD_R<1>
=ENET_RXD_R<2>
=ENET_RXD_R<3>
=ENET_RXD_R<4>
=ENET_RXD_R<5>
=ENET_RXD_R<6>
=ENET_RXD_R<7>
RXD[0] F4
RXD[1] F5
RXD[2] E5
RXD[3] E4
RXD[4] E3
RXD[5] D5
RXD[6] D4
RXD[7] D3
OUT
C8580
0.1uF
=ENET_TX_EN
=ENET_TX_ER
B4
C6
TXD[0]
TXD[1]
TXD[2]
TXD[3]
TXD[4]
TXD[5]
TXD[6]
TXD[7]
M2
18
Q8580
2N7002DW-X-F
VESTA_RESET
RC time constant not

critical. R < 3.9K
to counter internal
pulldown.
B6
R2
IN
=PP3V3_VESTA
R8580 1
10
IN
=ENET_TXD<0>
=ENET_TXD<1>
=ENET_TXD<2>
=ENET_TXD<3>
=ENET_TXD<4>
=ENET_TXD<5>
=ENET_TXD<6>
=ENET_TXD<7>
ENET_CLK125M_RX_R
FBGA-200
2 OF 3
=VESTA_CLK125M_GBE_REF
R8561
R8562
U8500
ENET data pairs is 100 ohms.
2
5%
1/16W
MF-LF
402
VESTA ENET
20%
6.3V
CERM
1206-1
R8569
Secondary Max Sep: 100 mils
XTALVDD1 BIASVDD1 PLLVDD1
Place close to link
5 mils
Secondary Length:
SM
C8531
ESR < 0.5 ohms
Net Spacing Type: ENET_MDI

Length Tolerance:
10 69
10uF
20%
50V
CERM
402

(NONE)
0.38 mms
C8530
=PP1V2_ENETFW
VOLTAGE=1.2V

(NONE)
Line To Line:
PP1V2_VESTA_PLLVDD1
66
C8501
Vesta Ethernet PHY
33pF
5%
50V
CERM
402
SYNC_MASTER=N/A
GTXCLK are delayed by 1.9 ns
SYNC_DATE=N/A
SPD0 - Speed Select

0 - No clock delay
See table below

CRYSTAL LOAD CAPACITANCE IS 20PF
AN_EN
F1000
SPD0
Description
Force 10BASE-T
Force 100BASE-TX
Force 1000BASE-T (test use only)
Auto-negotiate advertise 10BASE-T
Auto-negotiate advertise 10/100BASE-TX

SIZE
Auto-negotiate advertise 10/100/1000BASE-T
Auto-negotiate advertise 1000BASE-T
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
85
115
SHT
OF
NONE
NO STUFF
R8620
1
5%
1/10W
MF-LF
603
Q8620
TSSOP
=PP2V5_ENET
R86211
PP2V5_ENET_CTAP
VOLTAGE=2.5V
2 3
10
5 8
SI6467BDQ-E3
100K
5%
1/16W
MF-LF
402 2
C8620
1
C8601
C8602
C8603
1uF
1uF
1uF
1uF
10%
6.3V
CERM
402
1000pF
ENET_CTAP_EN_L
C8600
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
PLACE CAPS AT CONNECTOR PINS 5 & 6

10%
25V
X7R
402
MJRR0076
Q8420
C
=PP3V3_VESTA
F-RT-TH
2N7002DW-X-F
66 65 18 10
CRITICAL
J8600
SOT-363
PRIMARY
1CT:1CT
13
11
5
6
66
66
66
66
66
66
66
66
ENETCONN_0_P
ENETCONN_0_N
ENETCONN_1_P
ENETCONN_1_N
ENETCONN_2_P
ENETCONN_2_N
ENETCONN_3_P
ENETCONN_3_N
75 OHM
ENET_CTAP
ENET_CTAP
MDI_0+
MDI_0-
MDI_1+
4
7
MDI_1MDI_2+
MDI_2-
MDI_3+
MDI_3-
10
1CT:1CT
SECONDARY
J1
75 OHM
J2
J3
J4
1CT:1CT
J5
75 OHM
J6
J7
J8
1CT:1CT
12
14
RJ45
CABLE SIDE
75 OHM
RJ45
CHIP SIDE
=GND_CHASSIS_ENET 2
SHIELD
1000PF, 2000V
Ethernet Connector
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
86
115
SHT
OF
NONE
NET_TYPE
SPACING
PHYSICAL
FW_D
FW
FW
DIFFERENTIAL_PAIR
FW_CTL
FW
FW
FW_D_R<7..0>
FW_CTL_R<1..0>
FW_LREQ
FW
FW
FW_LREQ_R
FW
FW
FW
FW
FW_LPS_R
FW_LINKON
FW_PCLK
CLOCK
CLOCK
FW_CLK98M_PCLK
68 69
FW_LCLK
CLOCK
CLOCK
FW_CLK98M_LCLK_R
68 69
FW_PINT
FW
FW
FW_PINT
68 69
6 9 68
9 68 71
9 68 71
9 68 71
68 69
Page Notes
(NONE)
(NONE)
(NONE)
OMIT
U2100
I2
BGA
FIREWIRE INTERFACE
69 68
FW_CLK98M_PCLK
K7
69 68
FW_LINKON
M4
I2_FW_PVT
1
M9
R8800
1K
1%
1/16W
MF-LF
402
2
69 68
K8
FW_PINT
(13 of 14)
FWR_PCLK_H
49MHz
SYSCLK (Legacy)
FWR_D_0_H
FWR_LINKON_H
FWR_D_1_H
FWR_D_2_H
FWR_PVT
FWR_D_3_H
FWR_D_4_H
FWR_D_5_H
FWR_D_6_H
FWR_D_7_H
M3
FW_D_R<0>
FW_D_R<1>
FW_D_R<2>
FW_D_R<3>
FW_D_R<4>
FW_D_R<5>
FW_D_R<6>
FW_D_R<7>
M2
L1
K4
K3
N9
K2
J4
6 9 68
6 9 68
6 9 68
6 9 68
6 9 68
6 9 68
6 9 68
6 9 68
FWR_CNTL_0_H
FWR_CNTL_1_H
M8
M7
FW_CTL_R<0>
FW_CTL_R<1>
FWR_LREQ_H
K6
FW_LREQ_R
9 68 71
FWR_LPS_H
K5
FW_LPS_R
9 68 71
FW 800 SIGNALS
FWR_PINT_L
FWR_LCLK_H
M5
FW_CLK98M_LCLK_R
68 69
9 68 71
9 68 71
I2 FireWire Interface
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
88
115
SHT
OF
NONE
NET_TYPE
FW_TPA0
PHYSICAL
CLOCK
CLOCK
CLOCK
CLOCK
FW_TP
FW_TP
DIFFERENTIAL_PAIR
FW_CLK98M_PCLK_R
FW_CLK98M_LCLK
FW_TPA0
FW_TP
FW_TP
FW_TPA0
FW_TPB0
FW_TP
FW_TP
FW_TPB0
FW_TPB0
FW_TP
FW_TP
FW_TPB0
FW_TPA1
FW_TP
FW_TP
FW_TPA1
FW_TPA1
FW_TP
FW_TP
FW_TPA1
FW_TPB1
FW_TP
FW_TP
FW_TPB1
FW_TPB1
FW_TP
FW_TP
FW_TPB1
FW_TPA2
FW_TP
FW_TP
FW_TPA2
FW_TPA2
FW_TP
FW_TP
FW_TPA2
FW_TPB2
FW_TP
FW_TP
FW_TPB2
FW_TPB2
FW_TP
FW_TPA0_P
FW_TPA0_N
FW_TPB0_P
FW_TPB0_N
FW_TPA0
FW_TP
69
L8900
69 70
69 66 10
L8906
FERR-EMI-600-OHM
=PP1V2_ENETFW
69 70
FERR-EMI-600-OHM
PP1V2_VESTA_PLLVDD2
VOLTAGE=1.2V
1
SM
69 70
69 70
FW_TPA1_P
FW_TPA1_N
FW_TPB1_P
FW_TPB1_N
C8900
ESR < 0.5 ohms
69 70
69 70
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
20%
50V
CERM
402
C8906
C8907
C8908
0.1uF
0.1uF
0.1uF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
C8917
10UF
20%
6.3V
X5R
603
L8901
69 70
69 70
69 66 10
L8909
FERR-EMI-600-OHM
=PP2V5_ENETFW
69 70
FERR-EMI-600-OHM
VESTA_CLK24M_XTALI
VESTA_CLK24M_XTALO
VESTA_CLK24M_XTALO_R
VOLTAGE=2.5V
69
PP2V5_VESTA_FAVDDM
PP2V5_VESTA_BIASVDD2
69
C8903
69
0.1uF
20%
10V
CERM
402
C8909
C8911
0.1uF
0.1uF
20%
10V
CERM
402
20%
10V
CERM
402
C8918
20%
6.3V
X5R
603
L8913
C8904
C8905
to counter internal pull-up in Vesta.
R8914
390K
See straps table for more information.
5%
1/16W
MF-LF
2 402
- VESTA_DS_ONLY_EN0
If stuffed, adds external pull-up to
counter internal pull-down in Vesta.
69
- VESTA_PORT1_DISABLE
69
Place close to link
69

68
- VESTA_PORT2_DISABLE
IN
FW_CLK98M_LCLK_R
69
BI
9 6
BI
9 6
BI
9 6
BI
9 6
BI
Net Spacing Type: FW_TP

100 mils
Primary Max Sep:
7.5 mils
71 9
BI
R8998
500 mils

FW data pairs is 110 ohms.
D15
9 6
BI
9 6
BI
E12
E11
F11
F12
F13
G13
G12
G11
FW_CTL<0>
FW_CTL<1>
Secondary Max Sep: 100 mils

Secondary Length:
FW_CLK98M_LCLK
FW_D<0>
FW_D<1>
FW_D<2>
FW_D<3>
FW_D<4>
FW_D<5>
FW_D<6>
FW_D<7>
BI
9 6
Length Tolerance:
C13
E14
E13
71 9
R8999
150
150
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
2 402
FW_LPS
FW_LREQ
IN
71 9
IN
69
R8906 1
69
D11
D12
VESTA_LPWR_1394
VESTA_DS_ONLY_EN0
VESTA_PWR_CLASS_MSB
J3
A13
A12
(Int PU)
(Int PU)
VESTA FW
J5
J4
N13
Put crystal circuit close to PHY

69 VESTA_CLK24M_XTALI
69 VESTA_CLK24M_XTALO_R
P14
P13
PLI_LCLK
0
CRITICAL
70 69 10
Y8920
=PP3V3_FW
24.576M
1
VESTA_DS_ONLY_EN0
1
R8911
1K
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
R8904
10UF
20%
6.3V
X5R
603
N12
TPBIAS[0] L13
TPAP[0] L15
TPAN[0] L14
TPBP[0] M15
TPBN[0] M14
TPBIAS[1]
TPAP[1] J15
TPAN[1] J14
TPBP[1] K15
TPBN[1] K14
J13
PLI_CTL[0]
PLI_CTL[1]
PLI_LPS
PLI_LREQ
TPBIAS[2] H13
TPAP[2] G15
TPAN[2] G14
TPBP[2] H15
TPBN[2] H14
LPWR_1394
DS_ONLY_EN0 (Int PD)
PWR_CLASS (Int PU)
TEST_1394[0]
TEST_1394[1]
TVCO_24
SDC H1
SDA H2
RDAC2 R15
XTALI_24
XTALO_24
TP_VESTA_TDBL<0>
TP_VESTA_TDBL<1>
TP_VESTA_TDBL<2>
Place close to PHY
69
FW_CLK98M_PCLK_R
FW_PINT
FW_LINKON
FW_TPBIAS0
FW_TPA0_P
FW_TPA0_N
FW_TPB0_P
FW_TPB0_N
FW_TPBIAS1
OUT
68
OUT
68
OUT
70
BI
69 70
BI
69 70
BI
69 70
BI
OUT
FW_TPA1_P
FW_TPA1_N
FW_TPB1_P
FW_TPB1_N
FW_TPBIAS2
69 70
69 70
BI
FW_TPA2_P
FW_TPA2_N
FW_TPB2_P
FW_TPB2_N
OUT
68
69 70
BI
OUT
FW_CLK98M_PCLK
70
BI
BI
22
5%
1/16W
MF-LF
402
69 70
69 70
70 69 10
=PP3V3_FW
70
BI
69 70
BI
69 70
BI
69 70
BI
69 70
R8916 1
10K
5%
1/16W
MF-LF
402
R8915
10K
5%
1/16W
MF-LF
402
I2C_VESTA_SCL
I2C_VESTA_SDA
VESTA_RDAC2_PD
R8909 1
PLLGND2
2.0K
1%
1/16W
MF-LF
402
10K
C8919
20%
10V
CERM
402
1%
1/16W
MF-LF
402
VESTA_CLK24M_XTALO
8X4.5MM-SM1
69
1K
Vesta Config Straps:

DS_ONLY_EN12 - Port 1&2 Data/Strobe
R8903 1
N11
PLI_INT D13
PLI_LINK D14
PLI_DATA[0]
PLI_DATA[1]
PLI_DATA[2]
PLI_DATA[3]
PLI_DATA[4]
PLI_DATA[5]
PLI_DATA[6]
PLI_DATA[7]
P12
R8921
M10
PLI_PCLK E15
3 OF 3
BIASGND
1
0.1uF
2
FAVDDL
N14
TP_VESTA_TEST_1394<0>
TP_VESTA_TEST_1394<1>
TP_VESTA_TVCO_24
C8915
20%
10V
CERM
402
2
SM
R8902
U8500
1K
1%
1/16W
MF-LF
402 2
C8914
0.1uF
TDBL[0]
TDBL[1] B13
TDBL[2] B14
(Int PU)
OMIT
9 6
If stuffed, adds external pull-down
BI
ESDET0
ESDET1
ESDET2
VOLTAGE=1.2V
1
FBGA-200
- VESTA_PWR_CLASS_0
71 9
CPS
C11
C12
20%
10V
CERM
402
A14
BCM5462
0.38 mms
R13
VESTA_BILINGUAL_EN12_L
VESTA_PORT1_DISABLE_L
FAVDDM
22
5%
1/16W
MF-LF
402
VESTA_CPS
FAVDDH
R8905
1
Line To Line:
XTALVDD2
C8913
0.1uF
L10
=PPFW_PHY_CPS
- VESTA_BILINGUAL_EN12
M12
10
N15
20%
50V
CERM
402
M11
- NONE
0.001uF
20%
6.3V
X5R
603
L12
L11
10UF
K13
- =PP1V2_ENETFW
PP1V2_VESTA_FAVDDL
K12
- =PP2V5_ENETFW
PP2V5_VESTA_XTALVDD2
VOLTAGE=2.5V
1
K11
SM
P15
- =PP3V3_ENETFW
10 66 69
FERR-EMI-600-OHM
R14
=PP1V2_ENETFW
10UF
FERR-EMI-600-OHM
- =PP3V3_FW
10 66 69
SM
L8902
- =PPFW_PHY_CPS
=PP2V5_ENETFW
VOLTAGE=2.5V
Page Notes
10
SM
69 70
0.001uF
20%
6.3V
CERM
1206-1
=PP3V3_ENETFW
VOLTAGE=3.3V
69 70
SM
VESTA_CLK24M_XTAL
PP3V3_VESTA_FAVDDH
C8901
10uF
69 70
FW_TPA2_P
FW_TPA2_N
FW_TPB2_P
FW_TPB2_N
FW_TPB2
69
BIASVDD2
PLLVDD2
SPACING
5%
1/16W
MF-LF
402
C8920
1 - Port 1&2 Data/Strobe mode only
VESTA_DS_ONLY_EN0
69
VESTA_PWR_CLASS_MSB
69
VESTA_BILINGUAL_EN12_L
69
0 - Port 1&2 Bilingual mode

(Internal Pull-up)
C8921
18pF
18pF
5%
50V
CERM
402
5%
50V
CERM
402
DS_ONLY_EN0 - Port 0 Data/Strobe
VESTA_PWR_CLASS_0
1 - Port 0 Data/Strobe mode only
0 - Port 0 Bilingual mode
PORT1_ENABLE - Port 1 Enable

2
1 - Port 1 Enabled
0 - Port 1 Disabled (saves power)
(Internal Pull-up)
R8912
1K
5%
1/16W
MF-LF
402
CRYSTAL LOAD CAPACITANCE IS 12PF
Vesta FireWire PHY
VESTA_BILINGUAL_EN12
1
R8931
1K
SYNC_MASTER=N/A
5%
1/16W
MF-LF
2 402
PORT2_ENABLE - Port 2 Enable

2
1 - Port 2 Enabled
0 - Port 2 Disabled (saves power)
(Internal Pull-up)
5%
1/16W
MF-LF
402
SYNC_DATE=N/A
69
VESTA_PORT1_DISABLE
1
R8933
1K
VESTA_PORT2_DISABLE
69

R8935
1K
5%
1/16W
MF-LF
2 402

SIZE
PWR_CLASS - FireWire Power Class

1 - Sets Power Class to 0x4
APPLE COMPUTER INC.
0 - Sets Power Class to 0x0
D
SCALE
(Internal Pull-up)
DRAWING NUMBER
REV.
C
051-6929
89
115
SHT
OF
NONE
8
PROVIDED
BY
PHY
PAGE
7
NET_TYPE
SPACING PHYSICAL
DIFFERENTIAL_PAIR
FW
FW
FW
FW
FW
FW
FW
FW
FW_PORT1_TPA_FL
FW_PORT1_TPA_FL
FW_PORT1_TPB_FL
FW_PORT1_TPB_FL
FW_PORT1_TPA_P_FL
FW_PORT1_TPA_N_FL
FW_PORT1_TPB_P_FL
FW_PORT1_TPB_N_FL
FW
FW
FW
FW
FW
FW
FW
FW
FW_PORT2_TPA_FL
FW_PORT2_TPA_FL
FW_PORT2_TPB_FL
FW_PORT2_TPB_FL
FW_PORT2_TPA_P_FL
FW_PORT2_TPA_N_FL
FW_PORT2_TPB_P_FL
FW_PORT2_TPB_N_FL
Cable Power
70
"Snapback" & "Late VG" Protection
70
70
70
70
L9010
=PPFW_PORT1
10
PP3V3_FW_ESD
FERR-250-OHM
DP9010
70
BAV99DW-X-F
C9011
70
0.001uF
70
Page Notes
C9014
0.001uF
20%
50V
CERM 2
402
70
1
3
Q16C/514S0106/1394B
Q41C/514S0105/1394B-Q41
20%
50V
2 CERM
402
C9010
Termination
0.001uF
69
C9050
R90501
56.2
1%
1/16W
MF-LF
402 2
69
69
69
69
69
69
1394b implementation based on Apple

FireWire Design Guide (FWDG 0.6, 5/14/03)
69
70
FW_PORT1_TPB_N
70
FW_PORT1_TPB_P
C9060
1uF
10%
2 6.3V
CERM
402
69
14
1
4
12
10
1uF
NOTE: FireWire TPA/TPB pairs are NOT

constrained on this page. It is
assumed that FireWire PHY page will
provide the appropriate constraints
to apply to entire TPA/TPB XNets.
1394B
F-RT-SM-LF
SYM_VER-1
6
1
FW_TPBIAS1
FW_TPBIAS0
1

(NONE)
J9010
FL9010
90-OHM-300mA
2012H
20%
50V
CERM 2
402
Place close to FireWire PHY

69
SOT-363
2
R9051 R90601
56.2
1%
1/16W
MF-LF
2 402
R9061
56.2
1%
1/16W
MF-LF
402 2
FW_PORT1_TPA_N
1%
1/16W
MF-LF
402 2
70
FW_PORT1_TPA_P
56.2
FW_TPA0_C
C9012
0.1uF
DP9011
SOT-363
5
20%
50V
CERM 2
402
5%
25V
CERM 2
402
R9054
4.99K C9064
1%
R9011
3
1
1M
0.001uF
20%
50V
CERM 2
402
20%
16V
2 CERM
402
1%
1/16W
MF-LF
2 402
69
FW_TPB2_P
NO_TEST=YES
69
FW_TPB2_N
NO_TEST=YES
FERR-250-OHM
1.5AMP-33V
2
PPFW_PORT2_VP
VOLTAGE=33V
SM
SM-LF
C9024
0.001uF
20%
50V
2 CERM
402
"Snapback" & "Late VG" Protection
XW9070
SM
L9020
F9020
=PPFW_PORT2
FW_TPA2_N
70
PP3V3_FW_ESD
FW_TPB2_PD
DP9020
SM
DP9020
BAV99DW-X-F
XW9071
SOT-363
2
C9020 1
0.001uF
R90701
20%
50V
CERM 2
402
1K
5%
1/16W
MF-LF
402 2
BAV99DW-X-F
C9021
0.001uF
6
1
70
FW_PORT2_TPA_P
70
FW_PORT2_TPA_N
SOT-363
5
20%
50V
CERM 2
402
PORT 2
1394A
3
4
4
SYM_VER-2
EMI
R9099
CRITICAL
J9020
1
FL9020
0.1uF
20%
10V
CERM 2
402
1%
1/16W
MF-LF
402
400-OHM-EMI
1
PP3V3_FW_ESD 70
VOLTAGE=3.3V
2
SM-1
C9091
0.1uF
20%
10V
2 CERM
402
C9092
10%
50V
2 CERM
402
70
FW_PORT2_TPB_N
2
SM1
DP9021
DP9021
BAV99DW-X-F
BAV99DW-X-F
SOT-363
2
D9090
0.001uF
70
FW_PORT2_TPA_N_FL
70
FW_PORT2_TPB_P_FL
70
FW_PORT2_TPB_N_FL
260-OHM-330MA
(PPFW_PORT2_VP)
FL9021
SOT23
0.001uF
20%
50V
CERM 2
402
C9023
0.001uF
(TPA+)
TPO#
(TPA-)
TPI
(TPB+)
TPI#
(TPB-)
=GND_CHASSIS_FW_EMI
VGND
8
10
FireWire Ports
C9025 C9026 1
0.01uF
20%
50V
CERM 2
402
TPO
(GND_FW_PORT2_VG)
3
VP
7
6
C9022 1
1
2
SOT-363
5
BZX84C2V7-X-F
1
C9090 1
604
SYM_VER-2
L9090
FW_PORT2_TPB_P
FW_PORT2_TPA_P_FL
70
5%
1/16W
MF-LF
402
F-RT-TH-LF
260-OHM-330MA
70
1394A
2
SM1
ESD Rail
PP3V3_FW_ESD_F
VOLTAGE=3.3V
R9090
C
2
BREF should be hard-connected to

logic ground for speed signaling
and connection detection currents
per 1394b V1.33
Cable Power
NC_FW_TPBIAS2
MAKE_BASE=TRUE
NO_TEST=YES
NC_FW_TPA_P2
MAKE_BASE=TRUE
NO_TEST=YES
NC_FW_TPA_N2
MAKE_BASE=TRUE
NO_TEST=YES
69
0.01uF
20%
16V
2 CERM
402
4.99K
10
FW_TPA2_P
C9018
When a bilingual device is

connected to a beta-only device,
there is no DC path between them
(to avoid ground offset issue)
3rd TPA/TPB pair unused
69
AREF needs to be isolated from

all local grounds per 1394b spec
R9064
5%
25V
CERM 2
402
FW_TPBIAS2
20%
16V
CERM 2
402
PPFW_PORT2_VP_F
VOLTAGE=33V
69
15
1
NO STUFF
C9016
0.01uF
5%
1/16W
MF-LF
2 402
1
1
270pF
1/16W
MF-LF
2 402
INPUT
0.01uF
NO STUFF
C9013
NO STUFF
C9019
20%
50V
CERM 2
603
1%
1/16W
MF-LF
2 402
1
1
270pF
NO STUFF
SYM_VER-1
FW_TPA1_C
C9054
C9017 1
0.01uF
2012H
10%
50V
X7R 2
603-1
BAV99DW-X-F
6
1
0.001uF
FL9011
90-OHM-300mA
C9015 1
56.2
1%
1/16W
MF-LF
402 2
OUTPUT
13
SOT-363
2
R9063
56.2
1%
1/16W
MF-LF
2 402
TPBTPB<R>
TPB+
VP
NC
VG
TPATPA<R>
TPA+
11
R9053 R9062
DP9011
FW_PORT2_TPA_P 70
MAKE_BASE=TRUE
FW_PORT2_TPA_N 70
MAKE_BASE=TRUE
FW_PORT2_TPB_P 70
MAKE_BASE=TRUE
FW_PORT2_TPB_N 70
MAKE_BASE=TRUE
56.2
(PPFW_PORT1_VP)
(GND_FW_PORT1_VG)
FW_PORT1_TPA_N_FL
FW_PORT1_AREF
70 FW_PORT1_TPA_P_FL
BAV99DW-X-F
FW_TPA1_P
FW_TPA1_N
FW_TPB1_P
FW_TPB1_N
1
70
1%
1/16W
MF-LF
2 402
FW_PORT1_TPA_P
MAKE_BASE=TRUE
FW_PORT1_TPA_N 70
MAKE_BASE=TRUE
FW_PORT1_TPB_P 70
MAKE_BASE=TRUE
FW_PORT1_TPB_N 70
MAKE_BASE=TRUE
(FW_PORT1_BREF)
FW_PORT1_TPB_P_FL
NC 7
70
56.2
FW_PORT1_TPB_N_FL
70
70
70
R9052
10%
2 6.3V
CERM
402
FW_TPA0_P
FW_TPA0_N
FW_TPB0_P
FW_TPB0_N
=PP3V3_FW
CRITICAL
BAV99DW-X-F

(NONE)
NOTE: This page is expected to contain the
necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.
69 10
PORT 1
BILINGUAL
PPFW_PORT1_VP
VOLTAGE=33V
SM
SOT-363
5
DP9010

- _PPFW_PORT1
- _PPFW_PORT2
- _PPFW_PORT3
- _PP3V3_FW
- _GND_CHASSIS_FW_PORT1
20%
50V
2 CERM
603
0.01uF
20%
16V
CERM 2
402
SYNC_MASTER=N/A
514-0255
SYNC_DATE=N/A



SIZE
APPLE COMPUTER INC.
DRAWING
TITLE=PLASMA
D
SCALE
ABBREV=DRAWING
DRAWING NUMBER
REV.
C
051-6929
90
115
SHT
OF
NONE
LAST_MODIFIED=Fri Sep
9 13:40:50 2005
Place series terminators approximately halfway between Vesta and NB.

(They should probably be slightly closer to Vesta than the NB.).
RP9100
6
=RP9100P1
=RP9100P2
RP9100
6
=RP9100P3
=RP9101P1
=RP9101P3
5%
1/16W
SM-LF
=RP9100P6
=RP9100P5
=RP9101P8
=RP9101P7
=RP9101P6
=RP9101P5
FW_CTL<0>
9 69
FW_CTL<1>
9 69
FW_LPS
9 69
FW_LREQ
9 69
RP9101
5%
1/16W
SM-LF
=RP9101P4
=RP9100P7
RP9101
RP9101
6
5%
1/16W
SM-LF
5%
1/16W
SM-LF
=RP9101P2
RP9100
RP9101
5%
1/16W
SM-LF
5%
1/16W
SM-LF
=RP9100P4
=RP9100P8
RP9100
5%
1/16W
SM-LF
5%
1/16W
SM-LF
R9100
68 9
68 9
FW_CTL_R<0>
FW_CTL_R<1>
5%
1/16W
MF-LF
402
R9101
1
5%
1/16W
MF-LF
402
R9102
68 9
68 9
FW_LPS_R
FW_LREQ_R
5%
1/16W
MF-LF
402
R9103
1
5%
1/16W
MF-LF
402
FireWire Series Term
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
91
115
SHT
OF
NONE
NET_TYPE
SPACING
PHYSICAL
DIFFERENTIAL_PAIR
USB2_0
USB2
USB2
USB2_I2_0
USB2_0
USB2
USB2
USB2_I2_0
USB2_1
USB2
USB2
USB2_I2_1
USB2_1
USB2
USB2
USB2_I2_1
USB2_2
USB2
USB2
USB2_I2_2
USB2_2
USB2
USB2
USB2_I2_2
USB2_3
USB2
USB2
USB2_I2_3
USB2_3
USB2
USB2
USB2_I2_3
USB2_4
USB2
USB2
USB2_I2_4
USB2_4
USB2
USB2
USB2_I2_4
USB2_5
USB2
USB2
USB2_I2_5
USB2_5
USB2
USB2
USB2_I2_5
USB2_I2_XTAL
XTAL
XTAL
(USB2_I2_XTAL)
XTAL
XTAL
(USB2_I2_XTAL)
XTAL
XTAL
USB2_I2_P<0>
USB2_I2_N<0>
11 72
11 72
USB2_I2_P<1>
USB2_I2_N<1>
6 72
6 72
USB2_I2_P<2>
USB2_I2_N<2>
11 72
11 72
USB2_I2_P<3>
USB2_I2_N<3>
6 72
6 72
USB2_I2_P<4>
USB2_I2_N<4>
11 72
11 72
USB2_I2_P<5>
USB2_I2_N<5>
11 72
11 72
I2_CLK30M_USB2_XOUT_R
I2_CLK30M_USB2_XOUT
I2_CLK30M_USB2_XIN
72
72
72
Page Notes
- =PP3V3_PWRON_USB
- =RP92xxPy (pinswappable USB pulldowns)
(NONE)
Net Spacing Type: USB2
Line To Line:
19.5
Length Tolerance:
50
Primary Max Sep:
7.5
Secondary Max Sep: 100
Secondary Length: 500
mils
mils
mils
mils
mils
OMIT
U2100
I2
BGA

USB2 data pairs is 90 ohms.
USB INTERFACE
10
R9250
=PP1V5_PWRON_I2_USBPLL
4.7
1
C9250
1uF
PP1V5_PWRON_I2_PLLUSBAVDD
2
5%
1/16W
MF-LF
402
(14 of 14)
PLLUSB_AVDD
USB_VD_0_P
USB_VD_0_N
0.1uF
10%
6.3V
CERM
402
C9251
R8
VOLTAGE=1.5V
20%
2
10V
CERM
402
R9
Put crystal circuit close to I2

72 I2_CLK30M_USB2_XOUT_R
72 I2_CLK30M_USB2_XIN
NO STUFF
N5
P10
PLLUSB_VSSA
USB_XTALOSC_HI
USB_XTALOSC_LO
R9220
10M
1
R9221 1
R6
USB2_I2_P<0>
USB2_I2_N<0>
R7
USB_VD_1_P
USB_VD_1_N
N7
USB_VD_2_P
USB_VD_2_N
N4
USB_VD_3_P
USB_VD_3_N
N2
USB_VD_4_P
USB_VD_4_N
R4
USB_VD_5_P
USB_VD_5_N
R1
USB2_I2_P<1>
USB2_I2_N<1>
N6
USB2_I2_P<2>
USB2_I2_N<2>
N3
USB2_I2_P<3>
USB2_I2_N<3>
N1
USB2_I2_P<4>
USB2_I2_N<4>
R3
11 72
11 72
6 72
6 72
11 72
11 72
6 72
6 72
11 72
11 72
2
5%
1/16W
MF-LF
402
I2_USB2_VREF
T9
USB_VREF
USB2_I2_P<5>
USB2_I2_N<5>
R2
11 72
11 72
0
5%
1/16W
MF-LF
402 2
CRITICAL
Y9220
1
72
2
2
I2_CLK30M_USB2_XOUT
R9200
1K
30.0000M
1%
1/16W
MF-LF
402
8X4.5MM-SM1
C9221
22pF
22pF
5%
50V
CERM
402
C9220
5%
50V
CERM
402
Crystal load capacitance is 16pF
RP9210
15K
5%
1
=RP9210P8
=RP9210P7
=RP9210P6
=RP9210P5
6
6
6
6
1/16W
SM-LF
RP9211
15K
5%
1
=RP9211P8
=RP9211P7
=RP9211P6
=RP9211P5
6
6
One pair for each port USB2_*<0..5>
6
6
1/16W
SM-LF
I2 USB Interface
RP9212
SYNC_MASTER=N/A
15K
5%
1
7
6
=RP9212P8
=RP9212P7
=RP9212P6
=RP9212P5
SYNC_DATE=N/A

6

6
6
1/16W
SM-LF

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
92
115
SHT
OF
NONE
I31
I33
I32
I34
I35
I36
I37
PROVIDED BY I2 PAGES
I30
7
NET_TYPE
SPACING PHYSICAL
DIFFERENTIAL_PAIR
USB2
USB2
USB2
USB2
USB2_NEC_0
USB2_NEC_0
USB2_NEC_P<0>
USB2_NEC_N<0>
USB2
USB2
USB2
USB2
USB2_NEC_1
USB2_NEC_1
USB2_NEC_P<1>
USB2_NEC_N<1>
USB2
USB2
USB2
USB2
USB2_NEC_2
USB2_NEC_2
USB2_NEC_P<2>
USB2_NEC_N<2>
USB2
USB2
USB2
USB2
USB2_NEC_3
USB2_NEC_3
USB2_NEC_P<3>
USB2_NEC_N<3>
11 73
11 73
11 73
11 73
11 73
11 73
11 73
11 73
D
USB2_NEC
L9335

- =PP3V3_PWRON_USB2
4.7
USB2_NEC
USB2_NEC
C9335
C9336
10uF
0.1uF
20%
6.3V
X5R
603
Net Spacing Type: USB2

USB2 data pairs is 90 ohms.
USB2_NEC
1
20%
10V
CERM 2
402
USB2_NEC
USB2_NEC
C9328 1
0.1uF
0.1uF
0.1uF
20%
10V
CERM 2
402
0.1uF
20%
10V
CERM 2
402
USB2_NEC
20%
10V
CERM 2
402
USB2_NEC
0.1uF
USB2_NEC
CRITICAL
0.1uF
20%
10V
CERM 2
402
20%
10V
CERM 2
402
USB2_NEC
R9300
VDD
20%
10V
CERM 2
402
C9329 1 C9330
20%
10V
CERM 2
402
0.1uF
20%
10V
CERM 2
402
20%
10V
CERM 2
402
C9327 1
USB2_NEC
C9324 1 C9325
E2
0.1uF
A3
USB2_NEC
C9323 1
0.1uF
20%
10V
CERM 2
402
C9326
USB2_NEC
C9322 1
A12
USB2_NEC
1
0.1uF
0.1uF
20%
10V
CERM 2
402
AVDD
20%
6.3V
X5R 2
603
C9321
A13
USB2_NEC
1
10uF
P3
USB2_NEC
C9320

USB2_NEC
P2

(NONE)
P12
5%
1/10W
MF-LF
603
USB2_NEC
C9337
N10
SM
USB2_NEC
R9335
N12
D7
Page Notes
PP3V3_PWRON_NEC_AVDD
VOLTAGE=3.3V
FERR-EMI-100-OHM
H4
=PP3V3_PWRON_USB2
G12
73 10
73
D13
73
F13
73
H13
NEC_CLK30M_XT1
NEC_CLK30M_XT2
NEC_CLK30M_XT2_R
XTAL
XTAL
XTAL
J13
I42
XTAL
XTAL
XTAL
L13
USB2_NEC_XTAL
I41
N8
I40
RSDM1
DM1
DP1
RSDP1
M14
USB_NEC_N<0>
M13
(USB2_NEC_N<0>)
(USB2_NEC_P<0>)
2 USB_NEC_P<0>
L14
K13
U7500
1%
1/16W
MF-LF
402
USB2_NEC_N<0>
USB2_NEC_P<0>
11 73
11 73
USB2_NEC
R9301
1
39.2 2
1%
1/16W
MF-LF
402
NEC_uPD720101_USB2
39.2 2
FBGA-LF
USB2_NEC
R9302
1
73 10
39.2 2
=PP3V3_PWRON_USB2
USB2_NEC
7 6
USB2_NEC
R93102
RSDM2
DM2
DP2
RSDP2
RP9310
10K
K14
K12
J14
J12
(USB2_NEC_N<1>)
(USB2_NEC_P<1>)
USB_NEC_P<1>
10K
5%
1/16W
MF-LF
402 1
5%
1/16W
SM-LF
2 3
1%
1/16W
MF-LF
402
USB_NEC_N<1>
R9304
B10 OCI3
A10 OCI4
B9 OCI5
2
2
39.2 2
USB2_NEC
B11 OCI2
TP_USB2_PWREN<0>
TP_USB2_PWREN<1>
TP_USB2_PWREN<2>
TP_USB2_PWREN<3>
TP_USB2_PWREN<4>
11 73
1%
1/16W
MF-LF
402
B12 OCI1
11 73
R9303
USB2_OC<0>
USB2_OC<1>
USB2_OC<2>
USB2_OC<3>
USB2_OC<4>
USB2_NEC_N<1>
USB2_NEC_P<1>
USB2_NEC
RSDM3 H11
DM3 G11
C12 PPON1
DP3 G13
RSDP3 G14
A11 PPON2
C11 PPON3
C10 PPON4
A9 PPON5
1%
1/16W
MF-LF
402
USB_NEC_N<2>
(USB2_NEC_N<2>)
(USB2_NEC_P<2>)
USB_NEC_P<2>
36
USB2_NEC
USB2_NEC_N<2>
USB2_NEC_P<2>
RP9300
15K
11 73
5%
11 73
R9305
USB2_NEC
36
1%
1/16W
MF-LF
402
USB2_NEC
73 10
RSDM4
DM4
DP4
RSDP4
=PP3V3_PWRON_USB2
USB2_NEC
USB2_NEC
R93401
F12
F14
E12
E14
R9341
1.5K
1.5K
5%
1/16W
MF-LF
402 2
73
5%
USB2_NEC_N<3>
USB2_NEC_P<3>
11 73
11 73
=RP9301P8
=RP9301P7
=RP9301P6
=RP9301P5
6
6
6
6
1/16W
SM-LF
1%
1/16W
MF-LF
402
P6 NC1
M6 NC2
NEC_NC1_PU
NEC_NC2_PU
73
15K
R9307
36
USB2_NEC
USB2_NEC
5%
1/16W
MF-LF
2 402
RP9301
1%
1/16W
MF-LF
402
USB_NEC_N<3>
(USB2_NEC_N<3>)
(USB2_NEC_P<3>)
USB_NEC_P<3>
36
1/16W
SM-LF
R9306
1
=RP9300P8
=RP9300P7
=RP9300P6
=RP9300P5
NEC_CLK30M_XT1
NEC_CLK30M_XT2_R
RSDM5
DM5
DP5
RSDP5
L9 XT1/SCLK
P8 XT2
E13 NC
D14
C13
C14 NC
USB2_NEC
2
R9345
NEC USB2 Interface
100
30.0000M
22pF
5%
50V
CERM 2
402
22pF
5%
50V
2 CERM
402
5%
1/10W
MF-LF
603
N11
M12
R9339
P13
AVSS
D8
VSS
F11
C9346
G4
J11
USB2_NEC
8X4.5MM-SM
1
D12
USB2_NEC
C9345
73
H12
L12
USB2_NEC
M11
CRITICAL
B13
Y9345
N2
XTAL,CER,30.0000MHZ,LW PROF,8X4.5MM,SMD
B2
A2
197S0087
NEC_CLK30M_XT2
AVSS(R)
CRITICAL
Y9345
TABLE_5_ITEM
N13
BOM OPTION
B14
CRITICAL
H14
N14
DESCRIPTION
N1
QTY
RREF P11
B1
PART#
5%
1/16W
MF-LF
1 402
P10
OMIT
TABLE_5_HEAD
NEC_RREF_PD
SYNC_MASTER=N/A
USB2_NEC
R9338
9.09K

1%
1/16W
MF-LF
402 2
Tie to GND at ball N11

GND_NEC_AVSS_R
VOLTAGE=0V
SIZE
USB2_NEC
Y9345 LOAD CAPACITANCE IS 16pF
SYNC_DATE=N/A
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
93
115
SHT
OF
NONE
AUDIO BOARD & LEFT I/O

CRITICAL
JA000
M-ST-SM2-LF
12 7
24 7
SYS_CHARGE_LED_L
7 6
I2S0_SYNC
7 6
I2S0_BITCLK
8 7
8 7
22 7
22 7
10 7
22 7
22 7
=I2C_AUDIO_SCL
=I2C_AUDIO_SDA
AUDIO_LI_DET_L
=PP3V3_RUN_AUDIO
AUDIO_LO_DET_L
NO STUFF
50
49
2
1
48
47
46
45
44
43
42
41
10
40
11
39
12
38
13
37
14
36
15
35
16
AUDIO_I2S_DTIB_SEL
AUDIO_SPKR_MUTE_L
AUDIO_LO_MUTE_L
34
17
AUDIO_EXT_MCLK_SEL
33
18
32
19
AUDIO_SPDIF_RXERR_INT
MAKE_BASE=TRUE
31
20
30
21
CA010 1
29
22
0.001uF
28
23
20%
50V
CERM 2
402
=PP5V_PWRON_LEFT_USB
27
24
26
25
6 7
AUDIO_GPIO_11
6 7
7 22
PLACE SHORTS AT POWER SUPPLY
7 22
7 22
XWA033
SM
7 22
7 22
7
PP3V3_PWRON_AUDIO_AVDD
=PP3V3_PWRON_AUDIO_AVDD
10
=PP5V_PWRON_AUDIO_AVDD
10
VOLTAGE=3.3V
7 22
7 22
XWA050
SM
7
PP5V_PWRON_AUDIO_AVDD
VOLTAGE=5V
CA011 1
CA033
20%
50V
CERM 2
402
10%
2 16V
X5R
402
CA051
0.1uF
10%
2 16V
X5R
402
XWA051
SM
7
PP5V_PWRON_AUDIO_PVDD
=PP5V_PWRON_AUDIO_PVDD
10
VOLTAGE=5V
CA050 1
0.1uF
10%
16V
X5R 2
402
XWA001
SM
7
20%
2 6.3V
POLY
CASE-D2-LF
7 22
AUDIO_CODEC_RESET_L
0.001uF
7 11
I2S0_MCLK
NO STUFF
7 11
I2S0_DEV_TO_SB_DTI
I2S0_SB_TO_DEV_DTO
0.1uF
PLACE SHORTS AT POWER SUPPLY
CA000
150uF
USB2_LEFT_PORT_P
USB2_LEFT_PORT_N
7 10
GND_AUDIO_AGND
VOLTAGE=0V
XWA000
SM
1
GND_AUDIO_PGND
VOLTAGE=0V
Audio Board Connector
SYNC_MASTER=N/A
SYNC_DATE=N/A

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
100 115
SHT
OF
NONE
AGP
TABLE_SPACING_RULE
2
AUDIO
3
TABLE_SPACING_RULE
TABLE_SPACING_RULE
TABLE_SPACING_RULE
AUDIO
AGP
401
0.4 MM
=STANDARD
=STANDARD
=STANDARD
251
0.25 MM
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
TABLE_SPACING_RULE
TABLE_PHYSICAL_RULE
AGP_STB
601
0.6 MM
2.5 MM
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
AUDIO
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
TABLE_PHYSICAL_RULE
AGP
=STANDARD
=60_OHM_SE
=60_OHM_SE
=60_OHM_SE
=STANDARD
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
I2S
TABLE_PHYSICAL_RULE
TABLE_SPACING_RULE
AGP_STB
TABLE_SPACING_RULE
CLOCK
TABLE_SPACING_RULE
I2S
251
0.25 MM
=STANDARD
=STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE
TABLE_SPACING_RULE
TABLE_PHYSICAL_RULE
CLOCK
251
0.25 MM
=STANDARD
=STANDARD
=STANDARD
=STANDARD
I2S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
TABLE_PHYSICAL_RULE
ENETCONN
TABLE_PHYSICAL_RULE
TABLE_SPACING_RULE
CLOCK
=STANDARD
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
TABLE_SPACING_RULE
ENET (Ethernet Digital)
TABLE_SPACING_RULE
ENETCONN
TABLE_SPACING_RULE
ENET_SELF
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
201
0.2 MM
=STANDARD
=STANDARD
=STANDARD
=STANDARD
ENET
501
0.50 MM
3.81 MM
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
ENET
ENET_SELF
ENETCONN
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_SPACING_RULE
ENET
FW_TP
TABLE_PHYSICAL_RULE
TABLE_SPACING_RULE
TABLE_PHYSICAL_RULE
TABLE_SPACING_RULE
ENET
=STANDARD
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
FW_TP
TABLE_SPACING_RULE
501
3.81 MM
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
TABLE_PHYSICAL_RULE
FW_TP
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
201
0.2 MM
=STANDARD
=STANDARD
=STANDARD
=STANDARD
FW
FW
FW_SELF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
I2_FBCLK / XTAL
TABLE_SPACING_RULE
FW
0.50 MM
TABLE_SPACING_RULE
FW_SELF
TABLE_PHYSICAL_RULE
FW (FireWire Digital)
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
I2_FBCLK
CLOCK
CLOCK
FW
=STANDARD
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
XTAL
TABLE_PHYSICAL_ASSIGNMENT
I2C
TABLE_SPACING_RULE
I2_FBCLK
TABLE_SPACING_RULE
CLOCK
CLOCK
I2C
201
0.2 MM
=STANDARD
=STANDARD
=STANDARD
=STANDARD
XTAL
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
I2C
=STANDARD
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
MaxBus
TABLE_SPACING_RULE
TABLE_SPACING_RULE
MAXBUS
151
0.15 MM
=STANDARD
=STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
MAXBUS
=STANDARD
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
PCI
TABLE_SPACING_RULE
TABLE_SPACING_RULE
PCI
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
PCI
=STANDARD
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
RAM
TABLE_SPACING_RULE
TABLE_SPACING_RULE
RAM
201
0.2 MM
=STANDARD
=STANDARD
=STANDARD
=STANDARD
251
0.25 MM
2.5 MM
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_SPACING_RULE
RAM_DIFF
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
RAM
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_PHYSICAL_RULE
RAM_DIFF
UATA
TABLE_SPACING_RULE
TABLE_SPACING_RULE
UATA
151
0.15 MM
=STANDARD
=STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
UATA
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
Spacing & Physical Constraints
=50_OHM_SE
SYNC_MASTER=N/A
USB2
TABLE_SPACING_RULE
TABLE_SPACING_RULE
USB2
501
0.50 MM
SYNC_DATE=N/A
3.81 MM
=90_OHM_DIFF
=90_OHM_DIFF

=90_OHM_DIFF
TABLE_PHYSICAL_RULE

TABLE_PHYSICAL_RULE
USB2
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
110 115
SHT
OF
NONE
C
TABLE_SPACING_RULE
TABLE_SPACING_RULE
DVO
151
0.15 MM
=STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE
=STANDARD
DVO
TABLE_PHYSICAL_RULE
DVO
=STANDARD
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
TABLE_SPACING_RULE
TABLE_SPACING_RULE
TV
151
=75_OHM_SE
=75_OHM_SE
=75_OHM_SE
=75_OHM_SE
=75_OHM_SE
151
=TV
=TV
=TV
=TV
=TV
TABLE_SPACING_RULE
TV_CONN
TABLE_PHYSICAL_RULE
S-VIDEO
TABLE_PHYSICAL_RULE
TV
=75_OHM_SE
=75_OHM_SE
=75_OHM_SE
=75_OHM_SE
=TV
=TV
=TV
=TV
TABLE_PHYSICAL_RULE
TV_CONN
TABLE_SPACING_RULE
TABLE_SPACING_RULE
VGA
151
=75_OHM_SE
=75_OHM_SE
=75_OHM_SE
=75_OHM_SE
=75_OHM_SE
151
=VGA
=VGA
=VGA
=VGA
=VGA
TABLE_SPACING_RULE
VGA_CONN
TABLE_PHYSICAL_RULE
VGA
TABLE_PHYSICAL_RULE
VGA
=75_OHM_SE
=75_OHM_SE
=75_OHM_SE
=75_OHM_SE
=VGA
=VGA
=VGA
=VGA
TABLE_PHYSICAL_RULE
VGA_CONN
TABLE_SPACING_RULE
TABLE_SPACING_RULE
LVDS
151
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_PHYSICAL_RULE
=100_OHM_DIFF
LVDS
TABLE_PHYSICAL_RULE
LVDS
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_SPACING_RULE
TABLE_SPACING_RULE
TMDS
251
0.25 MM
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=TMDS
=TMDS
=TMDS
=TMDS
=TMDS
=TMDS
TABLE_SPACING_RULE
TMDS_CONN
TABLE_PHYSICAL_RULE
TMDS
TABLE_PHYSICAL_RULE
TMDS
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=TMDS
=TMDS
=TMDS
=TMDS
TABLE_PHYSICAL_RULE
TMDS_CONN
Spacing & Physical Constraints 2

SYNC_MASTER=N/A
TABLE_SPACING_RULE
THERM
251
0.25 MM
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_PHYSICAL_RULE
=100_OHM_DIFF

THERM
TABLE_PHYSICAL_RULE
THERM
SYNC_DATE=N/A
TABLE_SPACING_RULE
0.25 MM
=100_OHM_DIFF

=100_OHM_DIFF

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
111 115
SHT
OF
NONE
8
*** Signal Cross-Reference for the entire design ***
1V5RUN_EN
16A6<> 26C6<
1V8RUN_EN_L
16A4<> 26B4<>
1V8_1V5PWRON_EN_L 26D4<
1V20_REF
12C7< 14C8<
1V65_REF
13A5<
1_5V_BOOST
16C6<>
1_5V_BST
16C5<>
1_5V_DH
16C6<>
1_5V_DL
16B6<>
1_5V_FB
16B7<
1_5V_ILIM
16C5<>
1_5V_LX
1_8V_BOOST
1_8V_BST
1_8V_DH
1_8V_DL
16B5<>
16C4<>
16C4<>
16C3<>
16B3<>
1_8V_FB
16B4<
1_8V_ILIM
16C5<>
1_8V_LX
16B3<>
1_8V_PVDD_STD
51C1<
2V5PWRON_EN_L
26D4<
2V5RUN_EN_L
17A5<> 26C6<
3V3RUN_EN_L
15B3<> 26C5<
3V_BG
15C4<>
3V_BOOST
15C4<>
3V_BOOST_ESR
15D3<>
3V_ITH
15C4<>
3V_ITH_RC
15C3<
3V_PMU_VTAP
14B3<
3V_RSNS
15D2<
3V_RUNSS
15C4<
3V_SNSM
15C4<
3V_SNSP
15C4<
3V_SW
15C4<>
3V_TG
15D4<>
3V_VOSNS
15C4<>
5V3V3PWRON_EN_L 26D6<
5V3VPWRON_EN_L_RC 15B6<
5VRUNHD_EN_L
15B5<> 26D5<
5VRUN_EN_L
15A5<> 26D5<
5VTPAD_EN_L
26D4<
5V_BG
15C5<>
5V_BOOST
15C5<>
5V_BOOST_ESR
15D6<>
5V_ITH
5V_ITH_RC
5V_RSNS
5V_RUNSS
5V_SNSM
5V_SNSP
5V_SW
5V_TG
5V_VOSNS
1625_BG
1625_BST
1625_BST_ESR
1625_COMP
1625_DIV
1625_ENABLE
1625_ENABLE_L
15C5<>
15C6<
15D7<
15C5<
15C5<
15C5<
15C5<>
15C5<>
15C5<>
14C5<>
14C5<
14C5<>
13D2< 14C6<
14C8<
14D7<>
14D7<>
1625_FCB
1625_INTVCC
1625_RUNSS
1625_SGND
1625_TG
1625_VFB
14C6<
14C5<>
14C6<
14B7<>
14C5<>
14B5<>
1625_VIN
1625_VSW
1772_ACIN
1772_ACOK_L
1772_BST
1772_BST_ESR
1772_CCI
1772_CCS
1772_CCV
1772_CCV_RC
1772_CELLS
14C6<
14C4<>
13B5<
13B5<> 13C4<>
13B4<>
13C3<
13B5<>
13B5<
13B5<>
13B5<
13B4<
1772_CLS
1772_CSIN
1772_CSIP
1772_CSSN
1772_CSSP
1772_DCIN
1772_DHI
1772_DLO
1772_DLOV
1772_GND
1772_ICHG
1772_ICTL
1772_IINP
1772_LDO
1772_LX
1772_REF
13A4<
13B4<>
13B4<>
13C5<
13C5<
13B5<
13B4<>
13B4<>
13B4<>
13A5<>
13B5<>
13B5<>
13B5<
13C4<>
13B4<>
13B5<>
1772_VCTL
1778_BG
1778_BST
1778_BST_RC
1778_FCB
1778_GND
1778_ION
1778_ITH
1778_ITH_RC
1778_TG
1778_VFB
1778_VRNG
3707_FCB
3707_FSET
3707_INTVCC
3707_SGND
3707_STBYMD
13B5<
45C5<>
45C5<>
45C4<>
45C6<
45B6<>
45C5<
45C6<>
2B5> 45C7<
45C5<>
45C5<
2B5> 45C6<
15C5<
15C5<
15D5<>
15C7<>
15C5<>
=1V8_1V5PWRON_EN_L 16C8<> 26D3>

=1V8_1V5PWRON_PGOOD 16C6> 26B8<
=2V5PWRON_EN_L
17C7<> 26D3>
=2V5PWRON_PGOOD 17C4> 26B8<
=5V3V3PWRON_EN_L 15B6< 26D5>
=5V3VPWRON_PGOOD 15C4<> 26B8<
=5VPWRONTPAD_EN_L 15A8<> 26D3>
=ADT7467_THERM_L 11B3> 27C2<
=AGP_GPU_RESET_L 11C7> 44D4<
=AGP_VREF
11C7> 44B2<
=CLK33M_TBEN_SYNC 11D1> 21A5< 21D6>
=CPU0_MAX1717_AB_SEL 11A3> 36A7< 36C7<
=CPU0_VID_AB_SEL 11A3> 36D3<>
=CPU_HRESET_L
11B3> 34A8< 34C6< 34D4<
=ENET_COL_R
11A6> 66B3>
=ENET_CRS_R
11A6> 66B3>
=ENET_RXD_R<0>
66C3>
=ENET_RXD_R<7..0> 11A6>
=ENET_RXD_R<1>
66C3>
=ENET_RXD_R<2>
66C3>
=ENET_RXD_R<3>
66C3>
=ENET_RXD_R<4>
66C3>
=ENET_RXD_R<5>
=ENET_RXD_R<6>
=ENET_RXD_R<7>
=ENET_RX_DV_R
=ENET_RX_ER_R
66C3>
66C3>
66C3>
11A6> 66C3>
11A6> 66B3>
=ENET_TXD<0>
66C6<
=ENET_TXD<7..0> 11A6>
=ENET_TXD<1>
66C6<
=ENET_TXD<2>
66C6<
=ENET_TXD<3>
66C6<
=ENET_TXD<4>
66C6<
=ENET_TXD<5>
66C6<
=ENET_TXD<6>
66C6<
=ENET_TXD<7>
66C6<
=ENET_TX_EN
11A6> 66C6<
=ENET_TX_ER
11A6> 66B6<
=FTP_GND
7C5> 7C5> 7C7> 10D2>
=FTP_SLEEP_LED
7C5> 30B3>
=FWPWR_PWRON
18C8<> 26D3>
=GND_CHASSIS_BATTCHGR_HOLE 2C2<> 2C4>
=GND_CHASSIS_DVI1 2D4> 57D3<>
=GND_CHASSIS_DVI2 2D4> 57C3<>
=GND_CHASSIS_DVI3 2D4> 57C2<
=GND_CHASSIS_DVI4 2D4> 57B2<
=GND_CHASSIS_DVI_HOLE 2D2<> 2D4>
=GND_CHASSIS_ENET 2D4> 67B5<>
=GND_CHASSIS_FW_EMI 2D4> 70A1<
=GND_CHASSIS_FW_HOLE 2D2<> 2D4>
=GND_CHASSIS_FW_PORT1 2D4> 70C1<>
=GND_CHASSIS_FW_PORT2 2D4> 70A2<>
=GND_CHASSIS_INVERTER1 2D4> 56B3<
=GND_CHASSIS_INVERTER2 2C4> 56A2<
=GND_CHASSIS_INV_GND_CLIP 2C2<> 2D4>
=GND_CHASSIS_LCD1 2D4> 56C5<>
7
=GND_CHASSIS_LCD2 2D4> 56C6<
=GND_CHASSIS_LCD3 2D4> 56B6<
=GND_CHASSIS_LCD4 2D4> 56A5<>
=GND_CHASSIS_SLEEP_LED 2C4> 30A3<
=GND_CHASSIS_TV 2D4> 57A7<>
=GPUVCORE_PGOOD 26A8< 45C6>
=GPU_AGP_VREF
11C7> 44B4<
=I2C_ADT7467_SCL 8B1> 27C4<
=I2C_ADT7467_SDA 8B1> 27C4<>
=I2C_AUDIO_SCL
7A7> 8D1> 74C6<>
=I2C_AUDIO_SDA
7A7> 8D1> 74C6<>
=I2C_BATT_SCL
8B4> 12A5<
=I2C_BATT_SDA
8B4> 12A5<
=I2C_DS1775_SCL 7C5> 8B1> 30C5<>
=I2C_DS1775_SDA 7C5> 8B1> 30C5<>
=I2C_GPU_TMDS_SCL 8A5< 51B3<>
=I2C_GPU_TMDS_SDA 8A5< 51B3<>
=I2C_I2_NB_SCL
8C3< 22C2<
=I2C_I2_NB_SDA
8C3< 22C2<
=I2C_I2_SB_SCL
8D3< 22C2<
=I2C_I2_SB_SDA
8D3< 22B2<
=I2C_PMU_SCL
8C5< 25C5<>
=I2C_PMU_SDA
8C5< 25C5<>
=I2C_PMU_SMB_SCL 8B5< 25C5<>
=I2C_PMU_SMB_SDA 8B5< 25C5<>
=I2C_SI_M_SCL
8A4> 54B6<
=I2C_SI_M_SDA
8A4> 54B6<
=I2C_SI_S_SCL
8A4> 55B6<
=I2C_SI_S_SDA
8A4> 55B6<
=I2C_SODIMM_SCL 8C1> 40A6< 41A6<
=I2C_SODIMM_SDA 8C1> 40A6< 41A6<
=I2VCORE_PGOOD
20C4> 26B8<
=I2_AGP_FBCLK_IN 21C5> 43A5<
=I2_AGP_VREF
11C7> 43B5<
=I2_MAXBUS_FBCLK_IN 21D1> 32A6<
=I2_PCI_FBCLK_IN 21B5> 59A5<
=I2_STOPCPU_L
11B3> 22A5<
=I2_STOPXTAL_L
11B3> 22A5<
=JTAG_BBANGER_TCK 9D8< 25B5<>
=JTAG_BBANGER_TDI 9D8< 25B5<>
=JTAG_BBANGER_TMS 9D8< 25B5<>
=JTAG_BBANGER_TRST_L 9D8< 25C5<>
=JTAG_CPU0_TCK
9D5> 34D6<
=JTAG_CPU0_TDI
9D6> 34D6<
=JTAG_CPU0_TDO
9D6< 34D6>
=JTAG_CPU0_TMS
9D5> 34D6<
=JTAG_CPU0_TRST_L 9D5> 34D6<
=JTAG_I2_TCK
9B6> 22B5<
=JTAG_I2_TDI
9C6> 22B5<
=JTAG_I2_TDO
9C6< 22B2<
=JTAG_I2_TMS
9B6> 22B5<
=JTAG_I2_TRST_L 9B6> 22A5<
=JTAG_VESTA_TCK 9A6> 18A6<
=JTAG_VESTA_TDI 9A6> 18A6<
=JTAG_VESTA_TDO 9A6< 18A6>
=JTAG_VESTA_TMS 9A6> 18A6<
=JTAG_VESTA_TRST_L 9A6> 18A6<
=MAXBUS_CPU0_CLK 11D4> 33C1< 33D6>
=PCI_AIRPORT_GNT_L 11D1> 60C3<>
=PCI_AIRPORT_IDSEL 11C1> 60C7<
=PCI_AIRPORT_INT_L 11C1> 60B3<>
=PCI_AIRPORT_REQ_L 11D1> 60C5<>
=PCI_AIRPORT_RESET_L 11C1> 60C3<>
=PCI_CBUS_GNT_L 11C1> 61A7<
=PCI_CBUS_IDSEL 11C1> 61B8<
=PCI_CBUS_INT_L 11C1> 61A7<>
=PCI_CBUS_REQ_L 11C1> 61A7>
=PCI_CBUS_RESET_L 11C1> 61A7<
=PCI_CLK33M_AIRPORT 11D1> 60B3<> 60D6>
=PCI_CLK33M_CBUS 11C1> 61A7< 61D1>
=PCI_CLK33M_USB2 11C1> 62B5< 62D6>
=PCI_CLK33M_ZDBOUT_R<0> 11D4< 23B4> 23D6>
=PCI_CLK33M_ZDBOUT_R<1> 11C4< 23B4> 23D6>
=PCI_CLK33M_ZDBOUT_R<2> 11C4< 23B4> 23D6>
=PCI_CLK33M_ZDBOUT_R<3> 11B4< 23B4> 23D6>
=PCI_CLK33M_ZDB_IN 11D1> 23B5< 23D6>
=PCI_USB2_GNT_L 11C1> 62B5<
=PCI_USB2_IDSEL 11B1> 62B6<
=PCI_USB2_INT_L 11B1> 62B7<
=PCI_USB2_REQ_L 11C1> 62B5>
=PCI_USB2_RESET_L 11B1> 62A7<
=PP1V2_ENETFW
10D4> 66D2< 69C1< 69D5<
=PP1V2_VESTA
10D4> 18B7<
=PP1V2_VESTA_REG 10D6< 18C1<
=PP1V05R1V3_GPU_VCORE 10A6> 46D6<
=PP1V5R1V8_MAXBUS 10A1> 21C8< 32D1< 33A5< 33B8<
33C8< 34B5< 34B7< 34C4< 34C4< 34D4<
=PP1V5R1V8_PWRON_I2_MAXBUS 10A4> 32A5<
=PP1V5R1V8_RUN_I2_MAXBUS 10A1> 32B5<
=PP1V5R3V3_DVO_VREF 47C1> 54A2<
=PP1V5_AGP
10A6> 43A5< 43C1< 44B2< 44B7<
44C6< 47C2<
=PP1V5_GPU
10A1> 10A8<
=PP1V5_GPU_DVO
10A6> 47C2<
=PP1V5_GPU_PWRSEQ 10A6> 52C4<>
=PP1V5_GPU_VDD15 10A6> 46B5<>
=PP1V5_I2_AGP
10A4> 43C7<
=PP1V5_PWRON_I2PLL_LDO 10D3< 20B3<>
=PP1V5_PWRON_I2_PLL 10D1> 19C5<
=PP1V5_PWRON_I2_USBPLL 10D1> 72C7<
=PP1V5_PWRON_REG 10A6<> 16B8<>
=PP1V5_PWRON_RUNFET 10A4> 16A8<>
=PP1V5_RUN_RUNFET 10A3< 16A6<>
=PP1V8R2V5_GPU_FB_VIO 10A6> 47C8< 48A8<
=PP1V8_FB_VDD
10A6> 49D5< 49D8< 50D5< 50D8<
=PP1V8_FB_VDDQ
10A6> 49D5< 49D8< 50D5< 50D8<
=PP1V8_GPU
10A1> 10A8<
=PP1V8_GPU_AVDD 10A8< 53C2<
=PP1V8_GPU_DVO
10A6> 47C2<
=PP1V8_GPU_LVDS_PLL 47C2< 51D1>
=PP1V8_GPU_MEMVMODE 10A6> 48A6<
=PP1V8_GPU_PANEL_IO 10A6> 47B2<
=PP1V8_GPU_PWRSEQ 10A6> 52D4<>
=PP1V8_GPU_TPVDD 10A8< 53D4<
=PP1V8_PWRON_DDR2 10A4> 40B8< 40C3< 40D4< 40D6<
41C3< 41D4< 41D6<
=PP1V8_PWRON_I2_RAM 10A4> 38D3<
=PP1V8_PWRON_REG 10A6<> 16C1<>
=PP1V8_PWRON_RUNFET 10A4> 16B5<>
=PP1V8_RAM_I2_VREF 10A1> 38A6<
=PP1V8_RUN_RUNFET 10A3< 16A3<>
=PP1V8_RUN_TBEN_SYNC 10A1> 21B5<
=PP2V5R3V3_PWRON_I2_ENET 10B5< 65B6< 65C3< 65C7<
=PP2V5_ENET
10A4> 67C7<>
=PP2V5_ENETFW
10D4> 66D2< 69D1< 69D5<
=PP2V5_GPU
10B1> 10B8<
=PP2V5_GPU_A2VDD 10A6> 53B2<
=PP2V5_GPU_LVDS_IO 10B6> 47B1<
=PP2V5_GPU_PVDD 10B6> 51D3<
=PP2V5_GPU_PWRSEQ 10B6> 52D4<>
=PP2V5_PWRON_REG 10A6<> 17C2<
=PP2V5_PWRON_RUNFET 10A4> 17B5<>
=PP2V5_RUN_PCI1510 10B1> 61C8<
=PP2V5_RUN_RUNFET 10B3< 17B4<>
=PP2V5_VESTA
10D4> 18B2<
=PP2V5_VESTA_LDO 10D6< 18D1<>
=PP2V7R5V5_PWRON_I2VCORE 10B4> 20D7<
=PP2V8_GPU_LVDDR_LDO 10B8< 52B1<>
=PP2V8_GPU_LVDS_IO 10B6> 47A1<
=PP3V3_ADT7467
10B4> 27D5<
=PP3V3_AGP
10B6> 43D1< 44B4< 44C7<
=PP3V3_ALL_A29_DET 10C6> 12D3<>
=PP3V3_ALL_AC_DETECT 10C6> 12C7<>
=PP3V3_ALL_BATT0_DET 10B6> 12B7<
=PP3V3_ALL_BATT_CHGR 10C6> 13A6<> 13A8< 13C8<
=PP3V3_ALL_DEBUG 10B6> 24C3<>
=PP3V3_ALL_HALL_EFFECT 10C6> 30D3<
=PP3V3_ALL_LTC1625_SW 10C6> 14C7<>
=PP3V3_ALL_PBUS_ILIM 10C6> 13C3< 13D4<
=PP3V3_ALL_PMU
10C6> 24A7< 24D7< 25B6< 25C8<
25D5<
=PP3V3_ALL_PWRSEQ 10B6> 26B7<> 26D5<
=PP3V3_ALL_VREG 10C8< 14A2<
=PP3V3_AUDIO_MUTESEQ 10B5< 22B2< 22D7<
=PP3V3_BATT_IMON 10B6> 12A5<
=PP3V3_DDC_DVI
10B1> 57B4<> 57D2<>
=PP3V3_DDC_LCD
7B7> 10B1> 56C7<>
=PP3V3_ENET
10A5< 66B7<>
=PP3V3_ENETFW
10D4> 69D1<
=PP3V3_FW
10D4> 69A8< 69B2< 70A8<
=PP3V3_GPU
10B1> 10B8<
=PP3V3_GPU_CLOCKS 10B1> 52B8< 52C8<
=PP3V3_GPU_GPIOS 10B6> 51A7< 51B8< 53C4<
=PP3V3_GPU_PWRSEQ 10B6> 52D2<>
=PP3V3_GPU_VDDR3 10B6> 47D3<
=PP3V3_I2_PCISLOTEGPIOS 10B5< 22B7<
=PP3V3_PCI
10B1> 59D1<
=PP3V3_PCI_AIRPORT 10B1> 60C3<>
=PP3V3_PCI_ROM
10B5< 58B6< 58C5<>
=PP3V3_PCI_USB2 10B3< 62B6<
=PP3V3_PCI_ZDB
10B3< 23C5<
=PP3V3_PWRON_AUDIO_AVDD 10B4> 74B2<>
=PP3V3_PWRON_BT 10B4> 60C6<>
=PP3V3_PWRON_CPUVCORE_OFFSET 10B3> 36B7<
=PP3V3_PWRON_CPUVCORE_VID 10B4> 36C8< 36D6<
=PP3V3_PWRON_DS1775 10B4> 30D7<
=PP3V3_PWRON_I2_AGPPCI 10B5< 19A5<
=PP3V3_PWRON_I2_IO1 10B5< 19C5<
=PP3V3_PWRON_I2_IO2 10B5< 19B5<
=PP3V3_PWRON_I2_MAXBUS 10B4> 19B5<
=PP3V3_PWRON_I2_MISC 10B5< 22B6< 22C7<
=RP5610P2
=RP5610P3
=RP5610P4
=RP5611P1
=RP5611P2
=RP5611P3
=RP5611P4
6B5>
6B5>
6B5>
6B5>
6B5>
6B5>
6B5>
43C2<
43C2<
43C2<
43B2<
43C2<
43C2<
43C2<
=RP6720P1
=RP6720P2
=RP6720P3
=RP6720P4
=RP6720P5
=RP6720P6
6D4>
6D4>
6D4>
6D4>
6D4<
6D4<
54C8<
54B8<
54B8<
54B8<
54B7<
54B7<
AC_ENABLE_GATE
12D5<>
AC_ENABLE_L
12C5<>
AC_GTR_18V
13C3<>
ADAPTER_I_REG
13D3<>
ADT7467_ADR_ENABLE_L 27C2<>
AGP8X_DET_PU
44B6<
AGP_AD<0>
43D3< 44D6<>
AGP_AD<15..0>
43D6>
AGP_AD<1>
43D3< 44D6<>
AGP_AD<2>
43C3< 44C6<>
AGP_AD<3>
43C3< 44C6<>
=PP3V3_PWRON_INVERTER 10B4> 56B4<

=PP3V3_PWRON_JTAG_ASIC 9C8< 10B5<
=PP3V3_PWRON_LCD 10B4> 56C8<>
=PP3V3_PWRON_LEFT_ALS 7B5> 10B4> 31C3<>
=PP3V3_PWRON_LTC3412 10B4> 17D6<
=PP3V3_PWRON_MMM 10B4> 29C6<
=PP3V3_PWRON_MODEM 10B4> 30B6<>
=PP3V3_PWRON_PMU 10B4> 25B8<
=PP3V3_PWRON_PWRSEQ 10B5< 26C5< 26C7<>
=PP3V3_PWRON_REG 10B6<> 15D1<
=PP3V3_PWRON_RT_ALS 10B5< 28D5<
=PP3V3_PWRON_RUNFET 10B4> 15B2<>
=PP3V3_PWRON_TPS2211 10B4> 61D4<
=PP3V3_PWRON_USB2 10A4> 73B6< 73C6< 73D5<
=PP3V3_PWRON_VDDSPD 10B5< 40A6< 41A4< 41A6<
=PP3V3_PWRON_VGASYNC 10B4> 57C2< 57C2<
=RP6720P7
=RP6720P8
=RP6721P1
=RP6721P2
=RP6721P3
=RP6721P4
=RP6721P5
=RP6721P6
=RP6721P7
=RP6721P8
=RP6722P1
=RP6722P2
=RP6722P3
=RP6722P4
=RP6722P5
=RP6722P6
6D4<
6D4<
6D4>
6D4>
6D4>
6D4>
6D4<
6D4<
6D4<
6D4<
6C4>
6C4>
6C4>
6C4>
6C4<
6C4<
54B7<
54C7<
54B8<
54B8<
54B8<
54B8<
54B7<
54B7<
54B7<
54B7<
54A8<
54A8<
54A8<
54A8<
54A7<
54A7<
AGP_AD<4>
AGP_AD<5>
AGP_AD<6>
AGP_AD<7>
AGP_AD<8>
AGP_AD<9>
AGP_AD<10>
AGP_AD<11>
AGP_AD<12>
AGP_AD<13>
AGP_AD<14>
AGP_AD<15>
AGP_AD<16>
AGP_AD<31..16>
AGP_AD<17>
AGP_AD<18>
43C3<
43C3<
43C3<
43C3<
43C3<
43C3<
43C3<
43C3<
43C3<
43C3<
43C3<
43C3<
43C3<
43D6>
43C3<
43C3<
44C6<>
44C6<>
44C6<>
44C6<>
44C6<>
44C6<>
44C6<>
44C6<>
44C6<>
44C6<>
44C6<>
44C6<>
44C6<>
=PP3V3_RUN_AUDIO 7A7> 10B3< 74B6<>

=PP3V3_RUN_FANTACH 10B1> 27D2<
=PP3V3_RUN_FWPORTPWRSW 10B1> 18C8<
=PP3V3_RUN_HDD
10B1> 64B8< 64C7<
=PP3V3_RUN_KEYBRD_LED 10B1> 28B6<
=PP3V3_RUN_PCI1510_R 10B1> 61D7<
=RP6722P7
=RP6722P8
=RP6723P1
=RP6723P2
=RP6723P3
=RP6723P4
6C4<
6C4<
6C4>
6C4>
6C4>
6C4>
54A7<
54A7<
54A8<
54A8<
54A8<
54A8<
AGP_AD<19>
AGP_AD<20>
AGP_AD<21>
AGP_AD<22>
AGP_AD<23>
AGP_AD<24>
43C3<
43C3<
43B3<
43B3<
43B3<
43B3<
=PP3V3_RUN_PWRSEQ 10B3< 26B7<

=PP3V3_RUN_RUNFET 10B3< 15B1<>
=PP3V3_RUN_SI
10B1> 54C2< 54C3< 54C5< 55C3<
55D3< 55D3<
=PP3V3_VESTA
10D4> 18A2< 18A6< 18A8< 65C2<>
66C7< 67C7<>
=PP3V3_VESTA_1V2REG 10D4> 18C5<
=PP3V3_VESTA_2V5REG 10D4> 18D3<>
=PP3V3_VESTA_REG 10D6< 18D3<
=PP4V85_ALL_A29_DET 10C6> 12D4<
=PP4V85_ALL_VREG 10C8< 14B4<>
=PP5V_FAN1_PWR
7C5> 10C1> 31B4<>
=PP5V_FAN2_PWR
7C5> 10C1> 31B2<>
=PP5V_PWRON_AUDIO_AVDD 10C4> 74B2<>
=PP5V_PWRON_AUDIO_PVDD 10C4> 74B2<>
=PP5V_PWRON_CPUVCORE_PWRSEQ 10C3> 36C8<
=RP6723P5
=RP6723P6
=RP6723P7
=RP6723P8
=RP6821P1
=RP6821P2
=RP6821P3
=RP6821P4
=RP6821P5
=RP6821P6
=RP6821P7
6C4<
6C4<
6C4<
6C4<
6C4>
6C4>
6C4>
6C4>
6C4<
6C4<
6C4<
54A7<
54A7<
54A7<
54A7<
55B8<
55B8<
55B8<
55B8<
55B7<
55B7<
55B7<
=RP6821P8
=RP6822P1
=RP6822P2
=RP6822P3
=RP6822P4
=RP6822P5
=RP6822P6
=RP6822P7
=RP6822P8
=RP6823P1
=RP6823P2
=RP6823P3
=RP6823P4
=RP6823P5
=RP6823P6
=RP6823P7
=RP6823P8
=RP7250P1
=RP7250P2
=RP7250P3
=RP7250P4
=RP7251P1
6C4<
6C4>
6C4>
6C4>
6C4>
6C4<
6C4<
6C4<
6C4<
6C4>
6C4>
6B4>
6B4>
6B4<
6B4<
6C4<
6C4<
6B5>
6B5>
6B5>
6B5>
6B5>
55B7<
55B8<
55A8<
55A8<
55A8<
55A7<
55A7<
55A7<
55B7<
55A8<
55A8<
55A8<
55A8<
55A7<
55A7<
55A7<
55A7<
59D2<
59D2<
59D2<
59D2<
59C2<
=RP7251P2
=RP7251P3
=RP7251P4
=RP8150P1
=RP8150P2
=RP8150P3
=RP8150P4
=RP8150P5
=RP8150P6
=RP8150P7
=RP8150P8
=RP8151P1
=RP8151P2
=RP8151P3
=RP8151P4
=RP8151P5
=RP8151P6
=RP8151P7
=RP8151P8
=RP8152P1
=RP8152P2
=RP8152P3
=RP8152P4
=RP8152P5
=RP8152P6
=RP8152P7
=RP8152P8
=RP8153P1
=RP8153P2
=RP8153P3
=RP8153P4
=RP8153P5
=RP8153P6
=RP8153P7
=RP8153P8
=RP8154P1
=RP8154P2
=RP8154P3
=RP8154P4
=RP8154P5
=RP8154P6
=RP8154P7
=RP8154P8
=RP9100P1
=RP9100P2
=RP9100P3
=RP9100P4
=RP9100P5
=RP9100P6
=RP9100P7
=RP9100P8
=RP9101P1
=RP9101P2
=RP9101P3
=RP9101P4
=RP9101P5
=RP9101P6
=RP9101P7
=RP9101P8
=RP9210P5
=RP9210P6
=RP9210P7
=RP9210P8
=RP9211P5
=RP9211P6
=RP9211P7
6A5>
6A5>
6A5>
6C7>
6C7>
6C7>
6C7>
6C7<
6C7<
6C7<
6C7<
6C7>
6C7>
6C7>
6C7>
6C7<
6C7<
6C7<
6C7<
6C7>
6C7>
6C7>
6C7>
6C7<
6C7<
6C7<
6C7<
6C7>
6C7>
6C7>
6C7>
6C7<
6C7<
6C7<
6C7<
6C7>
6C7>
6B7>
6B7>
6B7<
6B7<
6C7<
6C7<
6A7>
6A7>
6A7>
6A7>
6A7<
6A7<
6A7<
6A7<
6A7>
6A7>
6A7>
6A7>
6A7<
6A7<
6A7<
6A7<
6B4<
6B4<
6B4<
6B4<
6B4<
6B4<
6B4<
59C2<
59C2<
59C2<
63D2<
63D2<
63D2<
63D2<
63D1<>
63D1<>
63D1<>
63D1<>
63D2<
63D2<
63D2<
63C2<
63C1<>
63D1<>
63D1<>
63D1<>
63C2<
63C2<
63C2<
63C2<
63C1<>
63C1<>
63C1<>
63C1<>
63C2<
63C2<
63C2<
63C2<
63C1<>
63C1<>
63C1<>
63C1<>
63C2<
63B2<
63B2<
63B2<
63B1>
63B1>
63B1>
63C1>
71C6<
71C6<
71C6<
71C6<
71C4<
71C4<
71C4<
71C4<
71C6<
71C6<
71C6<
71C6<
71C4<
71C4<
71C4<
71C4<
72A4<
72A4<
72A4<
72A4<
72A4<
72A4<
72A4<
AGP_AD<25>
AGP_AD<26>
AGP_AD<27>
AGP_AD<28>
AGP_AD<29>
AGP_AD<30>
AGP_AD<31>
AGP_AD_STB0_N
AGP_AD_STB0_P
AGP_AD_STB1_N
AGP_AD_STB1_P
AGP_ATI_RESET_L
AGP_BUSY_L
AGP_CBE_L<0>
AGP_CBE_L<1..0>
AGP_CBE_L<1>
AGP_CBE_L<2>
AGP_CBE_L<3..2>
AGP_CBE_L<3>
AGP_CLK66M_GPU
AGP_CLK66M_GPU_R
AGP_DEVSEL_L
AGP_FRAME_L
AGP_GNT_L
AGP_INT_L
AGP_IRDY_L
AGP_PAR
AGP_PIPE_L
AGP_RBF_L
AGP_REQ_L
AGP_SBA<0>
AGP_SBA<7..0>
AGP_SBA<1>
AGP_SBA<2>
AGP_SBA<3>
AGP_SBA<4>
AGP_SBA<5>
AGP_SBA<6>
AGP_SBA<7>
AGP_SB_STB_N
AGP_SB_STB_P
AGP_ST<0>
AGP_ST<3..0>
AGP_ST<1>
43B3< 44C6<>
43B3< 44C6<>
43B3< 44C6<>
43B3< 44B6<>
43B3< 44B6<>
43B3< 44B6<>
43B3< 44B6<>
43B2< 43C3< 43D6> 44B4<>
43B2< 43C3< 43D6> 44B4<>
43A2< 43B3< 43D6> 44B4<>
43B2< 43B3< 43D6> 44B4<>
44C4<
43D2< 43D5< 44B4>
43C3< 44C4<>
43D6>
43C3< 44C4<>
43B3< 44C4<>
43D6>
43B3< 44C4<>
11C7< 44C4< 44D6>
11C8< 43D3< 43D6>
6B6< 43C5< 43D6> 44C4<>
6B6< 43D5< 43D6> 44C4<>
6B6< 43C6> 43D3< 44C4<
22D5< 43C2< 44C4>
6B6< 43C5< 43C6> 44C4<>
43C6> 43D5< 44C4>
43B2< 43C5< 43C6>
6B6< 43C5< 43C6> 44B4>
6B6< 43C6> 43D5< 44C4<>
43C5< 44B6>
43D6>
43C5< 44B6>
43C5< 44B6>
43C5< 44B6>
43C5< 44B6>
43C5< 44B6>
43C5< 44B6>
43C5< 44B6>
43A2< 43C5< 43D6> 44B4<>
43B2< 43C5< 43D6> 44B4<>
43B3< 44B4<
43D6>
43B3< 44B4<
=PP5V_PWRON_CPUVCORE_VDD 10C4> 36C6<>

=PP5V_PWRON_GPUVCORE_PWRPLAY 10C3> 45B5<
=PP5V_PWRON_INVERTER 10B4> 56C4<>
=PP5V_PWRON_LEFT_USB 7B5> 10C4> 74C3<>
=PP5V_PWRON_LTC1625_EXTVCC 10C4> 14D7<>
=PP5V_PWRON_LTC1778_GPU_EXTVCC 10C3> 45D6<
=PP5V_PWRON_LTC3707_EXTVCC 10C4> 15D5<
=PP5V_PWRON_MAX1715_VDD 10C4> 16D5<>
=PP5V_PWRON_PMU_SUPPLY 10C4> 14B4<>
=PP5V_PWRON_PWRSEQ 10C4> 26D7<
=PP5V_PWRON_REG 10C6<> 15D8<
=PP5V_PWRON_RIGHT_USB 7B5> 10C4> 31C7<>
=PP5V_PWRON_RUNFET 10C4> 15B5<>
=PP5V_PWRON_SLEEPLED 10B4> 24B7<
=PP5V_PWRON_TPS2211 10C4> 61D4<
=PP5V_PWRON_TRACKPAD 10B4> 15B8<>
=PP5V_RUN_DVI_DDC 10C1> 57D4<
=PP5V_RUN_FANPWM 10C1> 27D2<
=PP5V_RUN_HDD
7B7> 10C1> 64B5<> 64B8<
=PP5V_RUN_HDDFET 10C3< 15B4<>
=PP5V_RUN_KEYBRD_LED 10C1> 28B5<
=PP5V_RUN_ODD
7B7> 10C1> 64C4<
=PP5V_RUN_PWRSEQ 10C1> 26A7< 26C8<
=PP5V_RUN_RUNFET 10C3< 15A4<>
=PP5V_SUPERCAP
14A4<
=PP5V_TPAD
10C1> 30D7<
=PP5V_TPAD_FET
10C3< 15A6<>
=PP12V8_LTC1625_VREG 10D8< 14C3<>
=PP12V8_PBUSB_HOLDUP_CAPS 10D6> 31D3<
=PP12V8_PBUS_PMU_SUPPLY 10D6> 14A7<>
=PP14VR24V_ALL_PBUS_A 10D8< 13D5<
=PP24V_ADAPTER_CONN 10C8< 31D6<>
=PP24V_ADAPTER_PMU_SUPPLY 10C6> 14A7<
=PP24V_ADAPTER_RAW 10C6> 12D8<>
=PP24V_PBUSA_HOLDUP_CAPS 10D6> 31D3<
=PPAVDD_CPU0
10C1> 35B6<
=PPBUS_DVI_PWRSW 10C6> 57A4<>
=PPBUS_FWPWRSW
10D6> 18D8<
=PPBUS_FW_FET
10D6< 18D5<>
=PPBUS_INVERTER 10D6> 56C3<
=PPBU_RUN_FW
10C1> 18D6<>
=PPFW_P3V3VESTA 10D4> 18D6<>
=PPFW_PHY_CPS
10D4> 69C5<
=PPFW_PORT1
10D4> 70D3<
=PPFW_PORT2
10D4> 70B4<
=PPI2C_GPU
8B5< 10B1>
=PPI2C_I2_NB
8C2< 10B5<
=PPI2C_I2_SB
8D2< 10B3<
=PPI2C_SYS0
8B5< 10C6>
=PPI2C_SYS1
8C5< 10B5<
=PPJTAG_CPU
9D8< 10A1>
=PPVBATT_BATT
10C6> 13D2<
=PPVBATT_BATTERY_PMU_SUPPLY 10C6> 14A7<
=PPVBATT_BATT_PBUSA 10D8< 13D2<>
=PPVBATT_BATT_PBUSB 10D8< 13D1<>
=PPVBATT_BATT_VSNS 10C8< 12B6<
=PPVBATT_ISNS_N 10C8< 12B4<>
=PPVCORE_CPU0
10C4> 35C4< 35C8< 35D4<
=PPVCORE_CPU_ADT7467 10C4> 27C4<
=PPVCORE_CPU_REG 10C6< 36C1<
=PPVCORE_GPU_REG 10A8<> 45C3<>
=PPVCORE_PWRON_I2 10A6> 19D6<
=PPVCORE_PWRON_I2_REG 10A8<> 20C2<
=PPVIN_ALL_BATT_CHGR 10D6> 13C2<>
=PPVIN_ALL_LTC1625 10D6> 14D3<>
=PPVIN_ALL_LTC3707 10D6> 15D5<>
=PPVIN_ALL_MAX1715 10D6> 16C3<> 16C7<> 16D5<
=PPVIN_BATT_CHRG_VSNS 10C6> 13A4<
=PPVIN_CPU0_AVDD 10B3< 37C7<
=PPVIN_CPUVCORE_MAX1717 10D6> 36D4<>
=PPVIN_GPU_LVDDR_LDO 10B6> 52B4<
=PPVIN_LTC1778_GPU 10D6> 45D5<>
=PPVIN_PWRON_I2PLLVDD 10A4> 20B6<>
=PPVIO_BU_BATT
7B5> 10D8< 31A6<>
=PPVIO_PCI_USB2 10B3< 62D5<
=PPVOUT_BATT_CHRG 13B1>
=PPVOUT_BU_BATT 7B5> 10D8< 31A6<>
=PPVOUT_CPU0_AVDD 10C3< 37C3<
=PPVREF_PMU
10B6> 25B5<
=RAM_VREF_A
40A6> 40D2< 40D6<
=RAM_VREF_B
40A6> 41D2< 41D6<
=ROM_PWD_L
11A4> 58B6<
=RP1150P1
6D7> 11D8<
=RP1150P2
=RP1150P3
=RP1150P4
=RP1150P5
=RP1150P6
=RP1150P7
=RP1150P8
=RP1151P1
=RP1151P2
=RP1151P3
=RP1151P4
=RP1151P5
=RP1151P6
=RP1151P7
=RP1151P8
=RP3510P1
=RP3510P2
=RP3510P3
=RP3510P4
=RP3511P1
=RP3511P2
=RP3511P3
=RP3511P4
=RP3512P1
=RP3512P2
=RP3512P3
=RP3512P4
6D7>
6D7>
6D7>
6D7<
6D7<
6D7<
6D7<
6D7>
6D7>
6D7>
6D7>
6D7<
6D7<
6D7<
6D7<
6B7>
6B7>
6B7>
6B7>
6B7>
6B7>
6B7>
6B7>
6B7>
6B7>
6B7>
6B7>
11D8<
11D8<
11D8<
11D7<
11D7<
11D7<
11D7<
11D8<
11C8<
11C8<
11C8<
11C7<
11C7<
11C7<
11D7<
32D2<
32D2<
32D2<
32D2<
32D2<
32C2<
32C2<
32C2<
32C2<
32C2<
32C2<
32C2<
=RP3513P2
=RP3513P3
=RP3513P4
=RP3514P1
=RP3514P2
=RP3514P3
6B7>
6B7>
6B7>
6A7>
6A7>
6A7>
32B2<
32B2<
32B2<
32B2<
32B2<
32B2<
=RP5610P1
6B5> 43B2<
AB_SEL_LOW
AC_DET_DIV
CBUS_BVD1_L
CBUS_BVD2_L
CBUS_CE1_L
CBUS_CE2_L
CBUS_DATA<0>
CBUS_DATA<1>
CBUS_DATA<2>
61A2<
61B2<
61C1<
61B2<
61A1<
61A1<
61A1<
CBUS_DATA<3>
CBUS_DATA<4>
CBUS_DATA<5>
CBUS_DATA<6>
CBUS_DATA<7>
CBUS_DATA<8>
61A4<> 61C1<
61A4<> 61C1<
61A4<> 61C1<
61A4<> 61C1<
61A4<> 61C1<
61A2< 61A4<>
FB_A_ADDR<9>
49B4< 49B7<
FB_A_ADDR<10>
49B4< 49B7<
FB_A_ADDR<11>
49B4< 49B7<
FB_A_ADDR_R<11..0> 48D4< 48D6>
FB_A_ADDR_R<12..0> 42D6>
FB_A_BA<0>
49A4< 49A7<
61A2< 61A4<>
61A2< 61A4<>
61A4<> 61C2<
61A4<> 61C2<
61A4<> 61C2<
61A4<> 61C2<
61A4<> 61C2<
61C2< 61C4<
61A2< 61C4<
61B2< 61B4<
61B2< 61C4>
61B2< 61C4>
61A7< 61A7<>
61A7< 61A7<>
61A7< 61A7<>
61A7< 61A7<>
FB_A_BA<1..0>
FB_A_BA<1>
FB_A_BA_R<1..0>
FB_A_BA_R<2..0>
FB_A_CAS_L
44C6<>
44C6<>
CBUS_DATA<9>
CBUS_DATA<10>
CBUS_DATA<11>
CBUS_DATA<12>
CBUS_DATA<13>
CBUS_DATA<14>
CBUS_DATA<15>
CBUS_DET_1_L
CBUS_DET_2_L
CBUS_INPACK_L
CBUS_IORD_L
CBUS_IOWR_L
CBUS_MFUNC1_PD
CBUS_MFUNC2_PD
CBUS_MFUNC3_PD
CBUS_MFUNC4_PD
44C6<>
44C6<>
44C6<>
44C6<>
44C6<>
44C6<>
CBUS_MFUNC5_PD
CBUS_MFUNC6_PD
CBUS_OE_L
CBUS_READY
CBUS_REG_L
CBUS_RESET_L
61A7<
61A7<
61B1<
61B1<
61B2<
61B2<
CBUS_SUSPEND_PU
CBUS_VCCD0_L
CBUS_VCCD1_L
CBUS_VPPD0
CBUS_VPPD1
61A7< 61B7<
61C5<>
61C5<>
61C5<>
61C5<>
AGP_ST<2>
43B3< 44B4<
AGP_STOP_L
6B6< 43C5< 43C6> 44C4<>
AGP_SUS_STAT_L_PU 44B4<>
AGP_TRDY_L
6B6< 43C5< 43C6> 44C4<>
AGP_VREF
11C8<
AGP_WBF_L
43B2< 43C5< 43C6> 44B4>
AIRPORT_CLKRUN_L_PD 60C4<>
ALS_0_OUT
7B5> 25A6> 31C3<>
ALS_1_OUT
25A6> 28D3<
ALS_GAIN_BOOST
7B5> 25A6> 28C5<> 31C3<>
ANALOG_AC_DET
12C3<
ATI_AGP_FBSKEW<0> 51B5<>
ATI_AGP_FBSKEW<1> 51B5<>
ATI_BUS_CFG<0>
51B5<>
ATI_BUS_CFG<1>
51B5<>
ATI_BUS_CFG<2>
51B5<>
ATI_CLK27M
51C3< 52C6< 52D6>
ATI_CLK27M_R
52C6< 52D6>
ATI_CLK27M_SS
51B5<> 52A5< 52D6>
ATI_CLK27M_SSIN 52A6< 52C5< 52D6>
ATI_CLK27M_SS_R 52A6<> 52D6>
ATI_DBI_HI_PU
44B6<>
ATI_DBI_LO_PU
44B6<>
ATI_MEMTYPE
51A7< 51B5<>
ATI_OSC_OE
52C7<
ATI_PVDD_BYP
51D2<>
ATI_R2SET
53B6<>
ATI_RSET
53B6<>
ATI_X1CLK_SKEW<0> 51B5<>
ATI_X1CLK_SKEW<1> 51B5<>
AUDIO_CODEC_RESET_L 7A7> 22C5< 74C4<>
AUDIO_EXT_MCLK_SEL 7A7> 22C5< 74B4<>
AUDIO_GPIO_11
7A7> 22C5< 74C3>
AUDIO_I2S_DTIB_SEL 7A7> 22C5< 74B4<>
AUDIO_LI_DET_L
7A7> 22D5< 74B6<>
AUDIO_LI_OPTICAL_PLUG_L 7A7> 22D5< 74C6<>
AUDIO_LO_DET_L
7A7> 22C5< 74B6<>
AUDIO_LO_MUTE
22C7<>
AUDIO_LO_MUTE_L 7A7> 22C6<> 74B4<>
AUDIO_LO_OPTICAL_PLUG_L 7A7> 22C5< 74B6<>
AUDIO_SPDIFRX_RESET_L 7A7> 22C5< 74C4<>
AUDIO_SPDIF_RXERR_INT 74B4<>
AUDIO_SPKR_MUTE 22B2<>
AUDIO_SPKR_MUTE_L 7A7> 22B1<> 74B4<>
BATT0_DET_L
12A7<>
BATTV_HIGH
13B7<>
BATTV_LOW
13B8<>
BATT_14PBUS_EN
13C1<>
BATT_14V_GATE
13C1<>
BATT_24PBUS_EN
13C2<>
BATT_24V_GATE
13C1<>
BATT_CLK
12A7<>
BATT_DATA
12A7<>
BATT_DIV
13A5<
BATT_ISNS
12A3< 25A3>
BATT_ISNS_R
12A4<>
BATT_LOW
13A6<>
BATT_LOW_L
13B6<>
BKFD_PROT_EN_L
13C8<>
BKFD_PROT_GATE
13D8<>
BRIGHT_PWM
7B7> 56B2<>
BRIGHT_PWM_F
56B3<>
CBUS_ADDR<0>
61B1< 61B4>
CBUS_ADDR<1>
61B1< 61B4>
CBUS_ADDR<2>
61B1< 61B4>
CBUS_ADDR<3>
61B1< 61B4>
CBUS_ADDR<4>
61B1< 61B4>
CBUS_ADDR<5>
61B1< 61B4>
CBUS_ADDR<6>
61B1< 61B4>
CBUS_ADDR<7>
61B1< 61B4>
CBUS_ADDR<8>
61B1< 61B4>
CBUS_ADDR<9>
61B1< 61B4>
CBUS_ADDR<10>
61B4> 61C1<
CBUS_ADDR<11>
61B1< 61B4>
CBUS_ADDR<12>
61B1< 61B4>
CBUS_ADDR<13>
61B1< 61B4>
CBUS_ADDR<14>
61B1< 61B4>
CBUS_ADDR<15>
61B1< 61B4>
CBUS_ADDR<16>
61B1< 61B4<
CBUS_ADDR<17>
61B2< 61B4>
CBUS_ADDR<18>
61B2< 61B4>
CBUS_ADDR<19>
61B2< 61B4>
=RP9211P8
6B4< 72A4<
=RP9212P5
6B4< 72A4<
=RP9212P6
6B4< 72A4<
=RP9212P7
6B4< 72A4<
=RP9212P8
6B4< 72A4<
=RP9300P5
6B4< 73B1<
=RP9300P6
6B4< 73B1<
=RP9300P7
6B4< 73B1<
=RP9300P8
6B4< 73B1<
=RP9301P5
6A4< 73B1<
=RP9301P6
6A4< 73B1<
=RP9301P7
6A4< 73B1<
=RP9301P8
6A4< 73B1<
=SI_TMDS_RESET_L 11C7> 54B6< 55B6<
=SLEEP_LED_CONN 11A3> 30B4<
=SLEEP_LED_IOUT 11A5< 24B6<
=SPI_I2_CLK
22A5<
=SPI_I2_MISO
22B2>
=SPI_I2_MOSI
22B5<
=SPI_I2_REQ
11A5< 22A7< 22C5<
=SYSCLK_TBEN_SYNC 11D4> 21A5< 21D6>
=TPS2211_SHDN_L 10B3< 61D5<
=VCORE_PGOOD
26B5< 36B4>
=VESTA_CLK25M_TX 11A6> 66C2>
=VESTA_CLK125M_GBE_REF 11A6> 66C2>
=VESTA_CLK125M_RX 11A6> 66C2>
=VESTA_ENERGYDET 11A6> 66B3>
=VESTA_MDC
11A6> 66B6<
=VESTA_MDIO
11A6> 66B6<>
A29_CLS_ADJ
13A5<>
A29_CURRENT_ADJ 13C4<>
A29_DETECT
12D1< 13A5<> 13C4<>
A29_DET_L
12C2<
A29_DET_REF
36A6<>
12C7<
CBUS_ADDR<20>
CBUS_ADDR<21>
CBUS_ADDR<22>
CBUS_ADDR<23>
CBUS_ADDR<24>
CBUS_ADDR<25>
CBUS_ADDR_16_R
12C2<
61B2< 61B4>
61B2< 61B4>
61A4> 61B2<
61A4> 61B2<
61A4> 61B2<
61A4> 61B2<
61B5<>
61C4<
61C4<
61C4>
61B4>
61A4<>
61A4<>
61A4<>
FB_A_ADDR<2>
FB_A_ADDR<3>
FB_A_ADDR<4>
FB_A_ADDR<5>
FB_A_ADDR<6>
FB_A_ADDR<7>
FB_A_ADDR<8>
61A7<>
61A7<>
61C4>
61C4<
61C4>
61C4>
CBUS_VS1
61B2< 61C4<>
CBUS_VS2
61B2< 61C4<>
CBUS_WAIT_L
61B2< 61B4<
CBUS_WE_L
61B1< 61C4>
CBUS_WP_L
61A1< 61B4<
CHARGE_DISABLE
13A7<>
CLKLVDS_L_N
7C7> 53A7> 53C1>
CLKLVDS_L_P
7C7> 53A7> 53C1>
CLKLVDS_U_N
7C7> 53B7> 53D1>
CLKLVDS_U_P
7C7> 53B7> 53D1>
COMM_DTR_L
24C2<>
COMM_RTS_L
24C2<>
COMP_DISABLE
57A4<>
COMP_ENABLE
57A3<>
COMP_RC
14C6<
CPU0_BMODE0_L
34C7< 34D4<
CPU0_BMODE1_L
34A8< 34D4<
CPU0_DFS2_L
34A8< 34D4<>
CPU0_DFS4_L
34A8< 34D4<>
CPU0_EXT_QUAL
34A6< 34D4<
CPU0_L1TSTCLK
34A6< 34D6<
CPU0_L2TSTCLK
34A8< 34D6<
CPU0_LVRAM_L
34A8< 34D4<>
CPU0_MAX1717_AB_SEL 11A4
CPU0_PLL_CFG<0> 34D1< 34D6<
56B5<>
56B5<>
56B5<>
56B5<>

CPU0_PLL_CFG<5> 34D1< 34D4<>
CPU0_PULLDOWN
33C3<>
CPU0_SMI_L
34A6< 34D4<
CPU0_SRESET_L
34A6< 34D4<
CPU0_TEMP
25A6>
CPU0_VID_AB_SEL 11A4
CPU1_TEMP
25A6>
CPUVCORE_VSENSE_R 36C2<>
CPU_AVDD_EN
26B5< 37C6<>
CPU_BVSEL<0>
34C6< 34D6<
CPU_BVSEL<1>
34B6< 34D4<>
CPU_CHKSTP_OUT_L 33B1<> 34B8<
CPU_LSSD_MODE_L 34B8< 34D6<
CPU_MCP_L
34A8< 34D4<
CPU_PMON_IN_L
34A8< 34D4<
CPU_VCORE_SNUB
36B3<
CURRENT_THRESHOLD 13C4<
CY25811_S0
52A6<
CY25811_S1
52A6<
DVI_DDC_CLK
57D2<>
DVI_DDC_CLK_UF
57B4<> 57C3<>
DVI_DDC_DATA
57C2<>
DVI_DDC_DATA_UF 57C3<>
DVI_HPD
57C2<>
DVI_HPD_DIV
57A4<
DVI_HPD_UF
57A5< 57C3<>
DVI_TURN_ON
57B4<>
DVI_TURN_ON_BASE 57B2<>
DVI_TURN_ON_ILIM 57B3<
ENETCONN_0_N
66B1<> 66D6> 67C6<>
ENETCONN_0_P
66B1<> 66D6> 67C6<>
ENETCONN_1_N
66B1<> 66D6> 67B6<>
ENETCONN_1_P
66B1<> 66D6> 67B6<>
ENETCONN_2_N
66B1<> 66D6> 67B6<>
ENETCONN_2_P
66B1<> 66D6> 67B6<>
ENETCONN_3_N
66B1<> 66D6> 67B6<>
ENETCONN_3_P
66B1<> 66D6> 67B6<>
ENET_CLK25M_TX
11A7< 65C5< 65D6>
ENET_CLK25M_TX_R 66C4<> 66D6>
ENET_CLK125M_GBE_REF 11A7< 65B5< 65D6>
ENET_CLK125M_GBE_REF_R 66C4<> 66D6>
ENET_CLK125M_GTX 66C6<
ENET_CLK125M_GTX_R 65B3< 65D6> 66C7<
ENET_CLK125M_RX 11A7< 65C5< 65D6>
ENET_CLK125M_RX_R 66C4<> 66D6>
ENET_COL
9B3> 11A7< 65B5< 65D6>
ENET_CRS
9B3> 11A7< 65B5< 65D6>
ENET_CTAP_EN_L
67C7<>
ENET_ENERGYDET
65B5<
ENET_MDC
9B3> 11A7< 65C3< 65D6>
ENET_MDI0
66A3<
ENET_MDI1
66A2<
ENET_MDI2
66A2<
ENET_MDI3
66A2<
ENET_MDIO
9B3> 11A7< 65C1<> 65D6>
ENET_RESET_L
11A8< 65B3<
ENET_RXD<0>
65B5<
ENET_RXD<3..0>
65D6>
ENET_RXD<7..0>
9B3> 11A7<
ENET_RXD<1>
65B5<
ENET_RXD<2>
65B5<
ENET_RXD<3>
65B5<
ENET_RXD<4>
65B5<
ENET_RXD<7..4>
65D6>
ENET_RXD<5>
65B5<
ENET_RXD<6>
ENET_RXD<7>
ENET_RX_DV
ENET_RX_ER
ENET_TXD<7..0>
ENET_TXD_R<0>
ENET_TXD_R<3..0>
ENET_TXD_R<7..0>
ENET_TXD_R<1>
ENET_TXD_R<2>
ENET_TXD_R<3>
ENET_TXD_R<4>
ENET_TXD_R<7..4>
ENET_TXD_R<5>
ENET_TXD_R<6>
ENET_TXD_R<7>
65B5<
65B5<
9B3> 11A7< 65B5< 65D6>
9B3> 11A7< 65B5< 65D6>
9B3> 11A7
65B3<
65D6>
11A8<
65B3<
65B3<
65B3<
65B3<
65D6>
65B3<
65B3<
65B3<
ENET_TX_EN
ENET_TX_EN_R
ENET_TX_ER
ENET_TX_ER_R
EXT_TMDS_CLK_CMF
EXT_TMDS_D0_CMF
EXT_TMDS_D1_CMF
EXT_TMDS_D2_CMF
FAN1_PWM
FAN1_TACH
FAN2_PWM
FAN2_TACH
FAN2558_ADJ_CPU0
FAN2558_EN_CPU0
FB_4_85V_BU
FB_A_ADDR<0>
FB_A_ADDR<11..0>
FB_A_ADDR<1>
9B3> 11A7
11A8< 65B3< 65D6>
9B3> 11A7
11A8< 65B3< 65D6>
54D2<
54D1<
54D2<
54C1<
7C5> 27C1<> 31B4<>
7C5> 27C1< 31B4<>
7C5> 27C1<> 31B2<>
7C5> 27C1< 31B2<>
37C5<>
37C5<>
14A5<
49B4< 49B7<
48D3> 49D1>
49B4< 49B7<
49B4<
49B4<
49B4<
49B4<
49B4<
49B4<
49B4<
49B7<
49B7<
49B7<
49B7<
49B7<
49B7<
49B7<
FB_B_CAS_L_R
FB_B_CKE
42B6> 48B2< 48B5>

48B1< 50A4< 50A7< 50D1>
1
FW_LINKON
FW_LPS
68C5< 68D6> 69C2>

9A3> 69B5< 71B4<
FB_B_CKE_R
42B6> 48B2< 48B5>
FB_B_CLKDDR_0_N 48B1< 50A7< 50D1>
FB_B_CLKDDR_0_N_R 42C6> 48B2< 48B5<>
FB_B_CLKDDR_0_P 48B1< 50A7< 50D1>
FB_B_CLKDDR_0_P_R 42C6> 48B2< 48B5<>
FB_B_CLKDDR_1_N 48A1< 50A4< 50D1>
FB_B_CLKDDR_1_N_R 42C6> 48A2< 48B5<>
FB_B_CLKDDR_1_P 48B1< 50A4< 50D1>
FB_B_CLKDDR_1_P_R 42C6> 48B2< 48B5<>
FB_B_CS_L
48B1< 50A4< 50A7< 50D1>
FB_B_CS_L_R
42B6> 48B2< 48B5>
FW_LPS_R
9B3> 68B3< 68D6> 71B6<
FW_LREQ
9A3> 69B5< 71B4<
FW_LREQ_R
9A3> 68B3< 68D6> 71B6<
FW_PINT
68B5< 68D6> 69C2>
FW_PORT1_AREF
70C2<>
FW_PORT1_TPA_N
70C5> 70C5<>
FW_PORT1_TPA_N_FL 70C2<> 70D6>
FW_PORT1_TPA_P
70C5> 70C5<>
FW_PORT1_TPA_P_FL 70C2<> 70D6>
FW_PORT1_TPB_N
70C5> 70D5<>
FW_PORT1_TPB_N_FL 70D2<> 70D6>
FB_A_CAS_L_R
42D6> 48B4< 48B6>
FB_A_CKE
48B3< 49A4< 49A7< 49D1>
FB_A_CKE_R
42D6> 48B4< 48B6>
FB_A_CLKDDR_0_N 48B3< 49A7< 49D1>
FB_A_CLKDDR_0_N_R 42D6> 48B4< 48B6<>
FB_A_CLKDDR_0_P 48B3< 49A7< 49D1>
FB_A_CLKDDR_0_P_R 42D6> 48B4< 48B6<>
FB_A_CLKDDR_1_N 48A3< 49A4< 49D1>
FB_A_CLKDDR_1_N_R 42D6> 48A4< 48B6<>
FB_A_CLKDDR_1_P 48B3< 49A4< 49D1>
FB_A_CLKDDR_1_P_R 42D6> 48B4< 48B6<>
FB_B_DDRCLK_0_RC
FB_B_DDRCLK_1_RC
FB_B_DQ<0>
FB_B_DQ<63..0>
FB_B_DQ<1>
FB_B_DQ<2>
FB_B_DQ<3>
FB_B_DQ<4>
FB_B_DQ<5>
FB_B_DQ<6>
FB_B_DQ<7>
FB_B_DQ<8>
FB_B_DQ<9>
FB_B_DQ<10>
FB_B_DQ<11>
FB_B_DQ<12>
50A7<
50A4<
50B5<>
48A1> 50C1>
50B5<>
50B5<>
50B5<>
50B5<>
50B5<>
50A5<>
50A5<>
50A5<>
50A5<>
50A5<>
50A5<>
50A5<>
FW_PORT1_TPB_P
70C5> 70D5<>
FW_PORT1_TPB_P_FL 70D2<> 70D6>
FW_PORT2_TPA_N
70A5<> 70C5>
FW_PORT2_TPA_N_FL 70A3<> 70D6>
FW_PORT2_TPA_P
70B5<> 70C5>
FW_PORT2_TPA_P_FL 70A3<> 70D6>
FW_PORT2_TPB_N
70A5<> 70C5>
FW_PORT2_TPB_N_FL 70A3<> 70D6>
FW_PORT2_TPB_P
70A5<> 70C5>
FW_PORT2_TPB_P_FL 70A3<> 70D6>
FW_POWERDOWN
22A7< 22C5<
FW_TPA0_C
70C7<
FW_TPA0_N
69B2<> 69D6> 70C7<
FW_TPA0_P
69B2<> 69D6> 70C7<
FW_TPA1_C
70C6<
FW_TPA1_N
69B2<> 69D6> 70C7<
FB_A_CS_L
FB_A_CS_L_R
FB_A_DDRCLK_0_RC
FB_A_DDRCLK_1_RC
FB_A_DQ<0>
FB_A_DQ<63..0>
48B3< 49A4< 49A7< 49D1>

42D6> 48B4< 48B6>
49A7<
49A4<
49A5<>
48A3> 49C1>
FB_B_DQ<13>
FB_B_DQ<14>
FB_B_DQ<15>
FB_B_DQ<16>
FB_B_DQ<17>
FB_B_DQ<18>
50A5<>
50A5<>
50A5<>
50A5<>
50A5<>
50A5<>
FW_TPA1_P
FW_TPA2_N
FW_TPA2_P
FW_TPB0_N
FW_TPB0_P
FW_TPB1_N
69B2<>
69B2<>
69B2<>
69B2<>
69B2<>
69B2<>
FB_A_DQ<1>
FB_A_DQ<2>
FB_A_DQ<3>
FB_A_DQ<4>
FB_A_DQ<5>
FB_A_DQ<6>
FB_A_DQ<7>
FB_A_DQ<8>
FB_A_DQ<9>
FB_A_DQ<10>
FB_A_DQ<11>
49A5<>
49A5<>
49A5<>
49A5<>
49A5<>
49A5<>
49A5<>
49A5<>
49A5<>
49A5<>
49A5<>
FB_B_DQ<19>
FB_B_DQ<20>
FB_B_DQ<21>
FB_B_DQ<22>
FB_B_DQ<23>
FB_B_DQ<24>
FB_B_DQ<25>
FB_B_DQ<26>
FB_B_DQ<27>
FB_B_DQ<28>
FB_B_DQ<29>
50A5<>
50A5<>
50A5<>
50A5<>
50A5<>
50B5<>
50B5<>
50B5<>
50B5<>
50B5<>
50B5<>
FW_TPB1_P
FW_TPB2_N
FW_TPB2_P
FW_TPB2_PD
FW_TPBIAS0
FW_TPBIAS1
FW_TPBIAS2
GAIN_SETTING2
GND_AUDIO_AGND
GND_AUDIO_PGND
GND_BATT_CONN
69B2<> 69D6> 70C7<

69B2<> 69D6> 70B7<>
69B2<> 69D6> 70B7<>
70B6<>
69B2> 70D7<
69B2> 70D7<
69B2> 70B7<
28C4<>
7A7> 74B6<>
7A7> 74B6<>
12A7<>
FB_A_DQ<12>
FB_A_DQ<13>
FB_A_DQ<14>
FB_A_DQ<15>
FB_A_DQ<16>
FB_A_DQ<17>
FB_A_DQ<18>
FB_A_DQ<19>
FB_A_DQ<20>
FB_A_DQ<21>
FB_A_DQ<22>
FB_A_DQ<23>
FB_A_DQ<24>
FB_A_DQ<25>
FB_A_DQ<26>
FB_A_DQ<27>
FB_A_DQ<28>
FB_A_DQ<29>
FB_A_DQ<30>
FB_A_DQ<31>
FB_A_DQ<32>
FB_A_DQ<33>
49A5<>
49A5<>
49A5<>
49A5<>
49B5<>
49B5<>
49A5<>
49B5<>
49A5<>
49B5<>
49B5<>
49B5<>
49B5<>
49B5<>
49B5<>
49B5<>
49B5<>
49B5<>
49B5<>
49B5<>
49A3<>
49B3<>
FB_B_DQ<30>
FB_B_DQ<31>
FB_B_DQ<32>
FB_B_DQ<33>
FB_B_DQ<34>
FB_B_DQ<35>
FB_B_DQ<36>
FB_B_DQ<37>
FB_B_DQ<38>
FB_B_DQ<39>
FB_B_DQ<40>
FB_B_DQ<41>
FB_B_DQ<42>
FB_B_DQ<43>
FB_B_DQ<44>
FB_B_DQ<45>
FB_B_DQ<46>
FB_B_DQ<47>
FB_B_DQ<48>
FB_B_DQ<49>
FB_B_DQ<50>
FB_B_DQ<51>
50B5<>
50B5<>
50B3<>
50B3<>
50B3<>
50B3<>
50B3<>
50B3<>
50A3<>
50A3<>
50A3<>
50A3<>
50A3<>
50A3<>
50A3<>
50A3<>
50A3<>
50A3<>
50B3<>
50B3<>
50B3<>
50B3<>
GND_GPU_TV1
GND_GPU_TV2
GND_I2VCORE
GND_INVERTER
GND_NEC_AVSS_R
57B8<>
57A8<>
20C4<>
7B7> 56B2<>
73A3<
GND_PMU_AVSS
GND_TV1
GND_TV2
GOV_RESET_L
GPUPVDD_EN
GPUVCORE_PGOOD
GPUVCORE_SHDN_L
GPUVDD15_EN
GPU_AGPTEST
GPU_AUXWIN_PU
GPU_DVI_DDC_CLK
25A3<> 25D3< 28D3< 29B3< 31B3<

57B7<>
57A7<>
11B4< 25C2<>
26A5< 51D3<>
26A7<
26B5<> 45C7<
26A5< 46B5<>
44B6<>
53B5<> 53C4<
51B3<> 57D1<>
GPU_DVI_DDC_DATA
GPU_DVI_HPD
GPU_DVOD<0>
GPU_DVOD<0..11>
GPU_DVOD<1>
GPU_DVOD<2>
51B3<> 57C1<>
51B3< 57C1<>
6C3> 54B6<
54D6>
6C3> 54B6<
6C3> 54B6<
FB_A_DQ<34>
FB_A_DQ<35>
FB_A_DQ<36>
FB_A_DQ<37>
FB_A_DQ<38>
FB_A_DQ<39>
FB_A_DQ<40>
FB_A_DQ<41>
FB_A_DQ<42>
FB_A_DQ<43>
FB_A_DQ<44>
49B3<>
49B3<>
49B3<>
49A3<>
49B3<>
49B3<>
49A3<>
49A3<>
49A3<>
49A3<>
49A3<>
FB_B_DQ<52>
FB_B_DQ<53>
FB_B_DQ<54>
FB_B_DQ<55>
FB_B_DQ<56>
FB_B_DQ<57>
FB_B_DQ<58>
FB_B_DQ<59>
FB_B_DQ<60>
FB_B_DQ<61>
FB_B_DQ<62>
50B3<>
50B3<>
50B3<>
50B3<>
50A3<>
50A3<>
50A3<>
50A3<>
50A3<>
50A3<>
50A3<>
FB_A_DQ<45>
FB_A_DQ<46>
FB_A_DQ<47>
FB_A_DQ<48>
FB_A_DQ<49>
FB_A_DQ<50>
FB_A_DQ<51>
FB_A_DQ<52>
FB_A_DQ<53>
FB_A_DQ<54>
FB_A_DQ<55>
FB_A_DQ<56>
FB_A_DQ<57>
FB_A_DQ<58>
FB_A_DQ<59>
FB_A_DQ<60>
FB_A_DQ<61>
FB_A_DQ<62>
FB_A_DQ<63>
FB_A_DQM<0>
FB_A_DQM<7..0>
FB_A_DQM<1>
FB_A_DQM<2>
FB_A_DQM<3>
FB_A_DQM<4>
FB_A_DQM<5>
FB_A_DQM<6>
FB_A_DQM<7>
FB_A_DQM_R<0>
FB_A_DQM_R<7..0>
FB_A_DQM_R<1>
FB_A_DQM_R<2>
FB_A_DQM_R<3>
FB_A_DQM_R<4>
FB_A_DQM_R<5>
FB_A_DQM_R<6>
FB_A_DQM_R<7>
FB_A_DQS<0>
FB_A_DQS<7..0>
FB_A_DQS<1>
FB_A_DQS<2>
FB_A_DQS<3>
FB_A_DQS<4>
FB_A_DQS<5>
FB_A_DQS<6>
FB_A_DQS<7>
FB_A_DQS_R<0>
FB_A_DQS_R<7..0>
FB_A_DQS_R<1>
FB_A_DQS_R<2>
FB_A_DQS_R<3>
FB_A_DQS_R<4>
FB_A_DQS_R<5>
FB_A_DQS_R<6>
FB_A_DQS_R<7>
49A3<>
49A3<>
49A3<>
49B3<>
49B3<>
49B3<>
49B3<>
49B3<>
49B3<>
49B3<>
49B3<>
49A3<>
49A3<>
49A3<>
49A3<>
49A3<>
49A3<>
49A3<>
49A3<>
49A7<
48A3> 49C1>
49A7<
49A7<
49A7<
49A4<
49A4<
49A4<
49A4<
42C6>
48A4< 48C6>
42C6>
42C6>
42C6>
42C6>
42C6>
42C6>
42C6>
49A7<>
48A3> 49C1>
49B7<>
49B7<>
49B7<>
49B4<>
49A4<>
49B4<>
49B4<>
42D6>
48A4< 48C6>
42D6>
42D6>
42D6>
42D6>
42D6>
42D6>
42D6>
FB_B_DQ<63>
FB_B_DQM<0>
FB_B_DQM<7..0>
FB_B_DQM<1>
FB_B_DQM<2>
FB_B_DQM<3>
FB_B_DQM<4>
FB_B_DQM<5>
FB_B_DQM<6>
FB_B_DQM<7>
FB_B_DQM_R<0>
50A3<>
50A7<
48A1> 50C1>
50A7<
50A7<
50A7<
50A4<
50A4<
50A4<
50A4<
42B6>
48C3>
49A4<
48C4<
42D6>
48B3<
49D1>
49A7<
48C6>
49A4< 49A7< 49C1>
69D6>
69D6>
69D6>
69D6>
69D6>
69D6>
70C7<
70B7<
70B7<
70C7<
70C7<
70C7<
FB_A_DQ_R<7..0> 42C6>
FB_A_DQ_R<63..0> 48A4< 48D8<
FB_A_DQ_R<15..8> 42C6>
FB_A_DQ_R<23..16> 42C6>
FB_A_DQ_R<31..24> 42C6>
FB_A_DQ_R<39..32> 42C6>
FB_A_DQ_R<47..40> 42C6>
FB_A_DQ_R<55..48> 42C6>
FB_A_DQ_R<63..56> 42C6>
FB_A_RAS_L
48B3< 49A4< 49A7< 49D1>
FB_A_RAS_L_R
42D6> 48B4< 48B6>
FB_A_WE_L
48B3< 49A4< 49A7< 49C1>
FB_A_WE_L_R
42D6> 48B4< 48B6>
FB_B_ADDR<0>
50B4< 50B7<
FB_B_ADDR<11..0> 48D1> 50D1>
FB_B_ADDR<1>
50B4< 50B7<
FB_B_ADDR<2>
50B4< 50B7<
FB_B_ADDR<3>
50B4< 50B7<
FB_B_ADDR<4>
50B4< 50B7<
FB_B_ADDR<5>
50B4< 50B7<
FB_B_ADDR<6>
50B4< 50B7<
FB_B_ADDR<7>
50B4< 50B7<
FB_B_ADDR<8>
50B4< 50B7<
FB_B_ADDR<9>
50B4< 50B7<
FB_B_ADDR<10>
50B4< 50B7<
FB_B_ADDR<11>
50B4< 50B7<
FB_B_ADDR_R<11..0> 48D2< 48D5>
FWPWR_ACIN
FWPWR_EN
FWPWR_EN_L
FWPWR_EN_L_DIV
FWPWR_PWRON
FWPWR_RUN
FW_CLK98M_LCLK
FW_CLK98M_LCLK_R
FW_CLK98M_PCLK
FW_CLK98M_PCLK_R
FW_CTL<0>
FW_CTL<1..0>
FW_CTL<1>
FW_CTL_R<0>
FW_CTL_R<1..0>
FW_CTL_R<1>
FW_D<0>
FW_D<7..0>
FW_D<1>
FW_D<2>
FW_D<3>
FW_D<4>
FW_D<5>
FW_D<6>
FW_D<7>
FW_D_R<0>
FW_D_R<7..0>
18B7<>
18C7<>
18C7<
18C7<>
26D4<
18C7<>
69C5< 69D6>
68B3< 68D6> 69C6<
68C5< 68D6> 69C1>
69C3<> 69D6>
69B6<> 71B4<
9B3>
69B6<> 71B4<
68B3< 71B6<
9B3> 68D6>
68B3< 71B6<
6A6> 69C5<>
9B3>
6A6> 69B5<>
6A6> 69B5<>
6A6> 69B5<>
6A6> 69B5<>
6A6> 69B5<>
6A6> 69B5<>
6A6> 69B5<>
6A8< 68C3<
9B3> 68D6>
GPU_DVOD<3>
6C3> 54B6<
GPU_DVOD<4>
6D3> 54B6<
GPU_DVOD<5>
6C3> 54B6<
GPU_DVOD<6>
6D3> 54B6<
GPU_DVOD<7>
6D3> 54B6<
GPU_DVOD<8>
6C3> 54A6<
GPU_DVOD<9>
6D3> 54A6<
GPU_DVOD<10>
6D3> 54A6<
GPU_DVOD<11>
6D3> 54A6<
GPU_DVOD<12>
6C3> 55B6<
GPU_DVOD<12..19> 55D6>
GPU_DVOD<13>
6C3> 55B6<
GPU_DVOD<14>
6C3> 55B6<
GPU_DVOD<15>
6C3> 55B6<
GPU_DVOD<16>
6D3> 55B6<
GPU_DVOD<17>
6C3> 55B6<
GPU_DVOD<18>
6B3> 55B6<
GPU_DVOD<19>
6C3> 55B6<
GPU_DVOD<20>
6C3> 55B6< 55D6>
GPU_DVOD<21>
6C3> 55B6<
GPU_DVOD<21..23> 55D6>
GPU_DVOD<22>
6C3> 55B6<
GPU_DVOD<23>
6B3> 55B6<
GPU_DVOD_R<0>
6C4< 53C7<>
GPU_DVOD_R<23..0> 53D1>
GPU_DVOD_R<1>
6C4< 53C7<>
GPU_DVOD_R<2>
6C4< 53C7<>
GPU_DVOD_R<3>
6C4< 53C7<>
GPU_DVOD_R<4>
6D4< 53C7<>
GPU_DVOD_R<5>
6C4< 53C7<>
GPU_DVOD_R<6>
6D4< 53C7<>
GPU_DVOD_R<7>
6D4< 53C7<>
GPU_DVOD_R<8>
6C4< 53C7<>
GPU_DVOD_R<9>
6D4< 53C7<>
GPU_DVOD_R<10>
6D4< 53C7<>
GPU_DVOD_R<11>
6D4< 53C7<>
GPU_DVOD_R<12>
6C4< 53C7<>
GPU_DVOD_R<13>
6C4< 53C7<>
GPU_DVOD_R<14>
6C4< 53C7<>
GPU_DVOD_R<15>
6C4< 53B7<>
GPU_DVOD_R<16>
6D4< 53B7<>
GPU_DVOD_R<17>
6C4< 53B7<>
GPU_DVOD_R<18>
2B5> 6B4< 53B7<>
GPU_DVOD_R<19>
6C4< 53B7<>
GPU_DVOD_R<20>
6C4< 53B7<>
GPU_DVOD_R<21>
6C4< 53B7<>
GPU_DVOD_R<22>
6C4< 53B7<>
GPU_DVOD_R<23>
6B4< 53B7<>
GPU_DVOVMODE
53C7<
GPU_DVO_CLKP
6C3> 54A6< 54C6> 55A6< 55C6>
GPU_DVO_CLKP_R
6C4< 53C7<> 53D1>
GPU_DVO_DE
6C3> 54A6< 54C6> 55B6< 55C6>
GPU_DVO_DE_R
6C4< 53C7<> 53D1>
GPU_DVO_HSYNC
6D3> 54A6< 54D6> 55B6<
GPU_DVO_HSYNC_R 6D4< 53C7<> 53D1>
GPU_DVO_VSYNC
6C3> 54A6< 54C6> 55A6< 55D6>
GPU_DVO_VSYNC_R 6C4< 53C7<> 53D1>
GPU_HSYNC_BUF
57B1<>
GPU_MEMTEST
48A5<>
GPU_MEMVMODE0
48A6<
GPU_MEMVMODE1
48A6<
GPU_MVREFD
48A7<
GPU_MVREFS
48A8<
GPU_RSTB_MSK
51B4<
GPU_SSIN_PD
51B4<
GPU_TESTEN
51B4<
GPU_TV_C
53B4< 53C1> 57A8<
GPU_TV_COMP
53B4<> 53C1> 57A8<
GPU_TV_Y
53B4<> 53C1> 57A8<
GPU_VCORE_HI
45B4<>
GPU_VCORE_HI_L
45A5< 51B8<>
GPU_VCORE_HI_L_RC 45A5<>
GPU_VCORE_SW
45C4<>
GPU_VGA_B
53C1> 53C4<> 57C8<
GPU_VGA_G
53C1> 53C4<> 57C8<
GPU_VGA_HSYNC
53B5<> 57B2<
GPU_VGA_R
53C1> 53C4<> 57B8<
GPU_VGA_VSYNC
53B5<> 57C2<
GPU_VREFG
51A5<
GPU_VSYNC_BUF
57C1<>
HIGH_GPU_VCORE_DIV 45B3<
HIGH_GPU_VCORE_L 45B3<>
HPD_4V_REF
57A4<
HPD_BASE
57A2<>
HPD_ON
57A3<>
HPD_ON_RC
57A3<
HPD_PWR_SNS_EN
51B5<> 57A4<>
HPD_PWR_SW
57A4<>
I2C_GPU_TMDS_SCL 8A5< 8D6>
I2C_GPU_TMDS_SDA 8A5< 8D6>
I2C_I2_NB_SCL
8C2< 8D6>
I2C_I2_NB_SDA
8C2< 8D6>
I2C_I2_SB_SCL
8D2< 8D6>
FB_B_ADDR_R<12..0> 42B6>
FB_B_BA<0>
50A4< 50A7<
FB_B_BA<1..0>
48C1> 50D1>
FB_B_BA<1>
50A4< 50A7<
FB_B_BA_R<1..0> 48C2< 48C5>
FB_B_BA_R<2..0> 42B6>
FB_B_CAS_L
48B1< 50A4< 50A7< 50C1>
FW_D_R<1>
FW_D_R<2>
FW_D_R<3>
FW_D_R<4>
FW_D_R<5>
FW_D_R<6>
6A8<
6A8<
6A8<
6A8<
6A8<
6A8<
I2C_I2_SB_SDA
I2C_PMU_SCL
I2C_PMU_SDA
I2C_PMU_SMB_SCL
I2C_PMU_SMB_SDA
I2C_VESTA_SCL
8D2< 8D6>
8C5< 8D6>
8C5< 8D6>
8B5< 8D6>
8B5< 8D6>
69B3<>
FW_D_R<7>
6A8< 68B3<
I2C_VESTA_SDA
69B3<>
FB_B_DQM_R<7..0> 48A2< 48C5>

FB_B_DQM_R<1>
42B6>
FB_B_DQM_R<2>
42B6>
FB_B_DQM_R<3>
42B6>
FB_B_DQM_R<4>
42B6>
FB_B_DQM_R<5>
42B6>
FB_B_DQM_R<6>
42B6>
FB_B_DQM_R<7>
42B6>
FB_B_DQS<0>
50B7<>
FB_B_DQS<7..0>
48A1> 50C1>
FB_B_DQS<1>
50B7<>
FB_B_DQS<2>
50A7<>
FB_B_DQS<3>
50B7<>
FB_B_DQS<4>
50B4<>
FB_B_DQS<5>
50A4<>
FB_B_DQS<6>
50B4<>
FB_B_DQS<7>
50B4<>
FB_B_DQS_R<0>
42B6>
FB_B_DQS_R<7..0> 48A2< 48C5>
FB_B_DQS_R<1>
42B6>
FB_B_DQS_R<2>
42B6>
FB_B_DQS_R<3>
42B6>
FB_B_DQS_R<4>
42B6>
FB_B_DQS_R<5>
42B6>
FB_B_DQS_R<6>
42B6>
FB_B_DQS_R<7>
42B6>
FB_B_DQ_R<7..0> 42B6>
FB_B_DQ_R<63..0> 48A2< 48D6<
FB_B_DQ_R<15..8> 42A6>
FB_B_DQ_R<23..16> 42A6>
FB_B_DQ_R<31..24> 42A6>
FB_B_DQ_R<39..32> 42A6>
FB_B_DQ_R<47..40> 42A6>
FB_B_DQ_R<55..48> 42A6>
FB_B_DQ_R<63..56> 42A6>
FB_B_RAS_L
48B1< 50A4< 50A7< 50D1>
FB_B_RAS_L_R
42B6> 48B2< 48B5>
FB_B_WE_L
48B1< 50A4< 50A7< 50C1>
FB_B_WE_L_R
42B6> 48B2< 48B5>
FB_C0_VREF
49C6<
FB_C1_VREF
49C4<
FB_D0_VREF
50C6<
FB_D1_VREF
50C4<
FP_PWR_EN_L
56C4<>
68C3<
68C3<
68B3<
68B3<
68B3<
68B3<
112
I2PLLVDD_ADJ
20A4<
I2PLLVDD_BYP
20A4<>
I2S0_BITCLK
6D6> 7A7> 74C6<>
I2S0_BITCLK_R
6D8< 22B2< 22D6>
I2S0_DEV_TO_SB_DTI 7A7> 22B5< 22D6> 74C4<>
I2S0_MCLK
6D6> 7A7> 74C4<>
I2S0_MCLK_R
6D8< 22B2< 22D6>
I2S0_SB_TO_DEV_DTO 6D6> 7A7> 74C4<>
I2S0_SB_TO_DEV_DTO_R 6D8< 22B2< 22D6>
I2S0_SYNC
6D6> 7A7> 74C6<>
I2S0_SYNC_R
6D8< 22B2< 22D6>
I2S1_BITCLK
6D6> 30B7<>
I2S1_BITCLK_R
6D8< 22B2< 22D6>
MAXBUS_CPU1_QREQ_L 32A2< 32D5<

MAXBUS_DATA<0>
32C3< 33D6<>
MAXBUS_DATA<0..40> 32D6>
MAXBUS_DATA<63..0> 9C3>
MAXBUS_DATA<1>
32C3< 33D6<>
MAXBUS_DATA<2>
32C3< 33D6<>
MAXBUS_DATA<3>
32C3< 33D6<>
MAXBUS_DATA<4>
MAXBUS_DATA<5>
MAXBUS_DATA<6>
MAXBUS_DATA<7>
MAXBUS_DATA<8>
MAXBUS_DATA<9>
32C3<
32C3<
32C3<
32C3<
32C3<
32C3<
33D6<>
33D6<>
33D6<>
33D6<>
33D6<>
33D6<>
I2S1_DEV_TO_SB_DTI 22B5< 22D6> 30B5<>

I2S1_MCLK
6D6> 30B7<>
I2S1_MCLK_R
6D8< 22B2< 22D6>
I2S1_SB_TO_DEV_DTO 6D6> 30A5<>
I2S1_SB_TO_DEV_DTO_R 6D8< 22B2< 22D6>
I2S1_SYNC
6D6> 30B5<>
I2S1_SYNC_R
6D8< 22B2< 22D6>
I2VCORE_ITH
20C5<>
I2VCORE_ITH_RC
20C6<
I2VCORE_MODE
20C5<>
I2VCORE_MODE_VDIV 20C5<
I2VCORE_RT
20C5<
I2VCORE_RUNSS
20C5<>
I2VCORE_SW
20C4<>
I2VCORE_VFB
20C5<>
I2_ACS_REF
32A5<
MAXBUS_DATA<10>
MAXBUS_DATA<11>
MAXBUS_DATA<12>
MAXBUS_DATA<13>
MAXBUS_DATA<14>
MAXBUS_DATA<15>
MAXBUS_DATA<16>
MAXBUS_DATA<17>
MAXBUS_DATA<18>
MAXBUS_DATA<19>
MAXBUS_DATA<20>
MAXBUS_DATA<21>
MAXBUS_DATA<22>
MAXBUS_DATA<23>
MAXBUS_DATA<24>
MAXBUS_DATA<25>
32C3<
32C3<
32C3<
32C3<
32C3<
32C3<
32C3<
32C3<
32C3<
32C3<
32C3<
32C3<
32C3<
32C3<
32C3<
32C3<
33D6<>
33D6<>
33D6<>
33D6<>
33D6<>
33D6<>
33D6<>
33D6<>
33D6<>
33D6<>
33D6<>
33C6<>
33C6<>
33C6<>
33C6<>
33C6<>
I2_AGP_FBCLK_IN 21C4< 21D6>

I2_AGP_FBCLK_MATCHED 21C3< 21D6>
I2_AGP_FBCLK_OUT 21C5< 43A2< 43D6>
I2_AGP_FBCLK_OUT_R 43A3< 43D6>
I2_AGP_PVTREF
43A5<
I2_AUDIO_LO_MUTE_L 22C5< 22C7<>
MAXBUS_DATA<26>
MAXBUS_DATA<27>
MAXBUS_DATA<28>
MAXBUS_DATA<29>
MAXBUS_DATA<30>
MAXBUS_DATA<31>
32B3<
32B3<
32B3<
32B3<
32B3<
32B3<
33C6<>
33C6<>
33C6<>
33C6<>
33C6<>
33C6<>
I2_AUDIO_SPKR_MUTE_L 22B2<> 22C5<

I2_CLK18M_XIN
22A5< 22D6>
I2_CLK18M_XOUT
22A6< 22D6>
I2_CLK18M_XOUT_R 22A5< 22D6>
I2_CLK30M_USB2_XIN 72B6< 72D6>
I2_CLK30M_USB2_XOUT 72B7< 72D6>
I2_CLK30M_USB2_XOUT_R 72B6< 72D6>
I2_ENET_MDIO
65C4<> 65D6>
I2_ENET_PVT
65B5<
I2_EXT_08
22D5<
I2_EXT_13
22C5<
MAXBUS_DATA<32>
MAXBUS_DATA<33>
MAXBUS_DATA<34>
MAXBUS_DATA<35>
MAXBUS_DATA<36>
MAXBUS_DATA<37>
MAXBUS_DATA<38>
MAXBUS_DATA<39>
MAXBUS_DATA<40>
MAXBUS_DATA<41>
MAXBUS_DATA<42>
32B3<
32B3<
32B3<
32B3<
32B3<
32B3<
32B3<
32B3<
32B3<
21B8<
21B8<
33C6<>
33C6<>
33C6<>
33C6<>
33C6<>
33C6<>
33C6<>
33C6<>
33C6<>
32B3< 32D6> 33C6<>
32B3< 32D6> 33C6<>
I2_EXT_14
22C5<
I2_FW_PVT
68C5<
I2_GPIO_11
22A6< 22C5<
I2_GPIO_EXT_02
11A5< 22A7< 22C5<
I2_MAXBUS_FBCLK_IN 21D3< 21D6>
I2_MAXBUS_FBCLK_MATCHED 21D4< 21D6>
I2_MAXBUS_FBCLK_OUT 21D6< 32A2< 32D6>
I2_MAXBUS_FBCLK_OUT_R 32A4< 32D6>
I2_MEM_VREF
38A5<
I2_PCI_FBCLK_IN 21B4< 21D6>
I2_PCI_FBCLK_MATCHED 21C3< 21D6>
I2_PCI_FBCLK_OUT 21C5< 59A2< 59D6>
I2_PCI_FBCLK_OUT_R 59A4< 59D6>
I2_SD_REF
38A5<
I2_TST_PLLEN
22B5<
I2_TST_TEI
22B5<
I2_UATA_VREF
63B5<
I2_USB2_VREF
72B5<
IAC_FB
13D4<
IAC_RC_COMP
13D4<
INV_ON_PWM
53B8<> 56B4<
JTAG_ASIC_TCK
9B8<
MAXBUS_DATA<43> 21B8< 32B3< 32D6>

MAXBUS_DATA<44> 21B8< 32B3< 32D6>
MAXBUS_DATA<45> 32B3< 33C6<>
MAXBUS_DATA<46> 32B3< 33C6<>
MAXBUS_DATA<47> 32B3< 33B6<>
MAXBUS_DATA<52> 32A3< 33B6<>
MAXBUS_DATA<54> 21B8< 32A3< 32D6>
MAXBUS_DATA<62> 21B8< 32A3< 32D6>
JTAG_ASIC_TMS
9B8<
JTAG_ASIC_TRST_L 9B8<
JTAG_CPU_TCK
9D7<
JTAG_CPU_TDI
9D7<
JTAG_CPU_TMS
9D7<
JTAG_CPU_TRST_L 9D7<
JTAG_I2_TDI
9C7<
JTAG_VESTA_TRST_L 9A8<
KBDLED_ANODE
7C5> 28A4< 30C5<>
KBDLED_RETURN
7C5> 28A4<> 30C5<>
LCD_DIGON_L
56C8<
LCD_PWREN_L
56C7<>
LTC1625_ITH
13D3<>
LTC3412_GND
17B5<>
LTC3412_ITH
17C5<>
LTC3412_ITH_RC
17C6<
LTC3412_RT
17C5<
LTC3412_RUNSS
2B5> 17C5<>
LTC3412_SW
17C4<>
LTC3412_SYNC
17C5<>
LTC3412_VFB
17C5<>
LTC3412_VFB_DIV 17C5<
LVDS_DDC_CLK
7B7> 51B3<> 56C7<>
LVDS_DDC_DATA
7B7> 51B3<> 56C7<>
LVDS_L0_N
7C7> 53A7> 53D1> 56C5<>
LVDS_L0_P
7C7> 53A7> 53D1> 56C5<>
LVDS_L1_N
7C7> 53A7> 53D1> 56C5<>
LVDS_L1_P
7C7> 53A7> 53D1> 56C5<>
LVDS_L2_N
7C7> 53A7> 53D1> 56B5<>
LVDS_L2_P
7C7> 53A7> 53D1> 56B5<>
LVDS_U0_N
7C7> 53B7> 53D1> 56B5<>
LVDS_U0_P
7C7> 53B7> 53D1> 56B5<>
LVDS_U1_N
7C7> 53B7> 53D1> 56B5<>
LVDS_U1_P
7C7> 53B7> 53D1> 56B5<>
LVDS_U2_N
7C7> 53B7> 53D1> 56B5<>
LVDS_U2_P
7C7> 53B7> 53D1> 56B5<>
MAX1715_EN_L_RC 16C7<>
MAX1715_GND
16B5<> 16C5<
MAX1715_ON
16D6<
MAX1715_REF
16B5<>
MAX1715_SKIP
16C4<
MAX1715_TON
16C5<
MAX4172_OUT
13D5<>
MAX8860_CC
52B3<>
MAX8860_FAULT_L 52B3<>
MAXBUS_AACK_L
6B8< 32D3< 32D6> 33C1<
MAXBUS_ADDR<0>
32C5< 33C3<>
MAXBUS_ADDR<31..0> 9C3> 32D6>
MAXBUS_ADDR<1>
32C5< 33C3<>
MAXBUS_ADDR<2>
32C5< 33C3<>
MAXBUS_ADDR<3>
32C5< 33C3<>
MAXBUS_ADDR<4>
32C5< 33C3<>
MAXBUS_ADDR<5>
32C5< 33C3<>
MAXBUS_ADDR<6>
32C5< 33C3<>
MAXBUS_ADDR<7>
32C5< 33C3<>
MAXBUS_ADDR<8>
32C5< 33C3<>
MAXBUS_ADDR<9>
32C5< 33C3<>
MAXBUS_ADDR<10> 32C5< 33C3<>
MAXBUS_ADDR<17> 32C5< 33B3<>
MAXBUS_DATA<63> 32A3< 32D6> 33B6<>

MAXBUS_DTI<0>
32A3< 33D4<
MAXBUS_DTI<2..0> 9C3> 32C6>
MAXBUS_DTI<1>
32A3< 33D4<
MAXBUS_DTI<2>
32A3< 33D4<
MAXBUS_EDTI
33A5< 33D4<
MAXBUS_GBL_L
9C3> 32B5< 32C6> 33C1<>
MAXBUS_SHD0_L
33A5< 33C1<>
MAXBUS_SHD1_L
33A5< 33C1<>
MAXBUS_TA_L
6B8< 32A3< 32D6> 33D4<
MAXBUS_TBEN
21B2< 33C1<
MAXBUS_TBEN_SYNC 21B2<>
MAXBUS_TBST_L
9C3> 32B5< 32C6> 33C1>
MAXBUS_TEA_L
6A8< 32A3< 32D6> 33D4<
MAXBUS_TSIZ<0>
32B5< 33C1>
MAXBUS_TSIZ<2..0> 9C3> 32C6>
MAXBUS_TSIZ<1>
32B5< 33C1>
MAXBUS_TSIZ<2>
32B5< 33C1>
MAXBUS_TS_L
6B8< 32D5< 32D6> 33C3<>
MAXBUS_TT<0>
32B5< 33C1<>
MAXBUS_TT<4..0> 9C3> 32C6>
MAXBUS_TT<1>
32B5< 33C1<>
MAXBUS_TT<2>
32B5< 33C1<>
MAXBUS_TT<3>
32B5< 33C1<>
MAXBUS_TT<4>
32B5< 33C1<>
MAXBUS_WT_L
9C3> 32B5< 32C6> 33C1>
MM3120_SW
28B4<>
MMM_ACC_PWRDOWN 25A7> 29C6<>
MMM_ACC_SELFTEST 25A7> 29C6<>
MMM_FFIRQ_L
22B6< 22C5< 25A7>
MMM_SIRQ_L
22B6< 22C5< 25A7>
MMM_X_AXIS
25A7> 29C3<> 29D6>
MMM_Y_AXIS
25A7> 29C3<> 29D6>
MMM_Z_AXIS
25A7> 29B3<> 29D6>
MODEM_RESET_L
22C5< 30B5<>
MODEM_RING2SYS_L 22B6< 22D5< 25C5<> 30A7<>
MUTE_CONTROL
22B1<> 22C6<>
NB_SUSPENDACK_L 22A2< 25C5<>
NB_SUSPENDREQ_L 22A5< 25A7< 25C5<>
NC_FW_TPA_N2
70B6>
NC_FW_TPA_P2
70B6>
NC_FW_TPBIAS2
70B6>
NC_MAXBUS_CPU1_QACK_L 11A4>
NC_MAXBUS_I2_TBEN 6B8<
NEC_CLK30M_XT1
73A5< 73D7>
NEC_CLK30M_XT2
73A5< 73D7>
NEC_CLK30M_XT2_R 73A5<> 73D7>
NEC_CRUN_L_PD
62A5<>
NEC_INTA_L
62B5<>
NEC_INTB_L
62B5<>
NEC_INTC_L
62B5<>
NEC_LEGC_PD
62A5<
NEC_NC1_PU
73A5<>
NEC_NC2_PU
73A5<>
NEC_PERR_L_PU
62B5<>
NEC_PME_L
62A5<>
NEC_RREF_PD
73A3<>
NEC_SERR_L_PU
62B5<>
NEC_VBBRST_L
62A5<
NEC_VCCRST_L
62A5<
OVER_18V_ADJ
13C3<>
PANEL_PWR_EN
53B8<> 56B4<> 56C8<
PCI1510_VR_EN_L 61C7<
PCI_AD<0>
59C3< 60B5<> 61C7<> 62D5<>
PCI_AD<16..0>
59D6>
PCI_AD<20..0>
58C5<>

MAXBUS_ADDR<25> 32B5< 33B3<>
MAXBUS_ARTRY_L
6A8< 32C6> 32D5< 33C1<>
MAXBUS_CI_L
9C3> 32B5< 32C6> 33C1>
MAXBUS_CLK_CPU0 11D5<
MAXBUS_CLK_CPU0_R 11D6< 32D3< 32D6>
MAXBUS_CLK_CPU1_R 11D6<
MAXBUS_CLK_TBEN_SYNC 11D5<
MAXBUS_CPU0_BG_L 6B8< 32C6> 32D3< 33C3<
MAXBUS_CPU0_BR_L 6B8< 32C6> 32D5< 33C3>
MAXBUS_CPU0_DBG_L 6B8< 32C6> 32D3< 33D4<
MAXBUS_CPU0_DRDY_L 6B8< 32C6> 32D5< 33D3<
MAXBUS_CPU0_DRDY_L_R 33D4<>
MAXBUS_CPU0_HIT_L 6B8< 32C6> 32D5< 33D4>
MAXBUS_CPU0_INT_L 6B8< 32D3< 34D4<
MAXBUS_CPU0_QACK_L 32D3< 33B1<
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
MAXBUS_CPU0_QREQ_L 32B2< 32D5< 33C1>

MAXBUS_CPU1_BG_L 6B8< 32C6> 32D3<
MAXBUS_CPU1_BR_L 6B8< 32C6> 32D5<
MAXBUS_CPU1_DBG_L 6A8< 32C6> 32D3<
MAXBUS_CPU1_DRDY_L 6B8< 32C6> 32D5<
MAXBUS_CPU1_HIT_L 6B8< 32C6> 32D5<
PCI_AD<23>
PCI_AD<24>
PCI_AD<31..24>
PCI_AD<25>
PCI_AD<26>
PCI_AD<27>
59B3< 60C3<>
59B3< 60C3<>
58C3<> 59D6>
59B3< 60C5<>
59B3< 60C5<>
59A3< 60C5<>
MAXBUS_CPU1_INT_L
PCI_AD<28>
59A3< 60C3<> 61B7<> 62B5<>
6B8< 32D3<
59C3<
59C3<
59C3<
59C3<
59C3<
59C3<
59B3<
59B3<
59B3<
59B3<
59B3<
59B3<
59B3<
59B3<
59B3<
59B3<
11C2<
62C5<>
PCI_AD<18>
59B3<
PCI_AD<19..18>
59D6>
PCI_AD<19>
59B3<
PCI_AD<20>
11C2<
62C5<>
PCI_AD<21>
11B2<
62C5<>
PCI_AD<22>
59B3<
PCI_AD<23..22>
59D6>
61B7<> 62B5<>
61B7<> 62B5<>
61B7<> 62B5<>
PP4V85_ALL
PP4V85_ALL_ESR
PP5V_INV_SW
7B7> 56C2<>
PP5V_INV_SW_F
56C3<>
PP5V_LTC1625_EXTVCC_SW 14D6<>
PP5V_MAX1715_VCC 16D5<
PP5V_PWRON
7C7> 10C5<>
RAM_DATA_A<28>
RAM_DATA_A<29>
RAM_DATA_A<30>
RAM_DATA_A<31>
RAM_DATA_A<32>
RAM_DATA_A<33>
RAM_DATA_A<34>
40C4<
40C6<
40C4<
40C4<
40B4<
40B4<
40B6<
61B7<> 62B5<>
PP5V_PWRON_AUDIO_AVDD 7A7> 74B3<>

PP5V_PWRON_AUDIO_PVDD 7A7> 74B3<>
PP5V_PWRON_REG
10C6<
PP5V_RUN
7C7> 10C2
PP5V_RUN_DDC
57B4<> 57D3<>
PP5V_RUN_DDC_FUSE 57D4<
RAM_DATA_A<35>
RAM_DATA_A<36>
RAM_DATA_A<37>
RAM_DATA_A<38>
RAM_DATA_A<39>
RAM_DATA_A<40>
PCI_CBUS_IDSEL
61B7<
PCI_CBUS_INT_L
11C2
PCI_CBUS_REQ_L
6B6< 11C2
PCI_CBUS_RESET_L 61A7<
PCI_CLK33M_AIRPORT 11D2<
PP5V_RUN_DDC_PULLUPS 57D2<>
PP5V_RUN_HDD
10C2
PP5V_RUN_ODD
64C3<>
PP5V_TPAD
10C2
PP5V_TPAD_F
7D5> 30D6<>
PCI_CLK33M_AIRPORT_R 11D3<
PCI_CLK33M_CBUS 11C2<
PCI_CLK33M_CBUS_R 11C3<
PCI_CLK33M_TBEN_SYNC 11D2<
PCI_CLK33M_TBEN_SYNC_R 11D3<
PCI_CLK33M_USB2 11C2<
PCI_CLK33M_USB2_R 11C3<
PCI_CLK33M_ZDB
11D2<
PCI_CLK33M_ZDB_R 11D3<
PCI_CLK_DELAY_ADJ 23B5<>
PCI_DEVSEL_L
59C5< 59D2< 59D6> 60B5<> 61A7<>
PCI_AD<29>
59A3< 60C5<>
PCI_AD<30>
59A3< 60C5<>
PCI_AD<31>
59A3< 60C3<>
PCI_AIRPORT_GNT_L 6B6< 11D2
PCI_AIRPORT_IDSEL 60C5<>
PCI_AIRPORT_INT_L 11C2
PCI_AIRPORT_REQ_L 6A6< 11D2
PCI_CBE_L<0>
59B3< 60B5<>
PCI_CBE_L<3..0> 59D6>
PCI_CBE_L<1>
59B3< 60B3<>
PCI_CBE_L<2>
59B3< 60B3<>
PCI_CBE_L<3>
59A3< 60C5<>
PCI_CBUS_GNT_L
6A6< 11C2
TP_CPU0_PMON_OUT_L 34D4>
TP_CPU0_SENSEGND1 35B6<
TP_CPU0_SENSEGND2 35B6<
TP_CPU0_SENSEVDD1 35B8<
TP_CPU0_SENSEVDD2 35B8<
TP_CPU0_TEMP_ANODE 34D4<>
TP_CPU0_TEMP_CATHODE 34D4<>
TP_ENET_ENERGYDET 11A7<
TP_EXTTMDS_RESET_L 11C8< 51B5<>
TP_GOV_RESET_L
11B3>
TP_I2_PENDINT
22A2<
TP_JTAG_CPU_TDO 9D5>
TP_JTAG_I2_TDO
9C5>
UATA_DSTROBE
UATA_DSTROBE_R
40B6<
40B6<
40B6<
40B4<
40B4<
40B4<
RAM_DQS_B_P<3>
41C4<
RAM_DQS_B_P<4>
41B6<
RAM_DQS_B_P<5>
41B4<
RAM_DQS_B_P<6>
41A6<
RAM_DQS_B_P<7>
41A4<
RAM_DQS_P_R<0>
38C6>
RAM_DQS_P_R<7..0> 38C3<> 39B6<
RAM_DQS_P_R<1>
38C6>
RAM_DQS_P_R<2>
38C6>
RAM_DQS_P_R<3>
38C6>
RAM_DQS_P_R<4>
38C6>
RAM_DQS_P_R<5>
38C6>
RAM_DQS_P_R<6>
38C6>
40A6<
40A6<
40B6<
40A4<
40A4<
40B4<
40B6<
40A4<
40A6<
40A4<
40A6<
40A6<
40A4<
40A4<
40A6<
40A6<
RAM_DQS_P_R<7>
RAM_ODT<0>
RAM_ODT<1..0>
RAM_ODT<1>
RAM_ODT_R<0>
RAM_ODT_R<1>
RAM_RAS_L
RAM_RAS_L_R
RAM_VREF
RAM_WE_L
RAM_WE_L_R
ROM_CS_L
ROM_OE_L
ROM_ONBOARD_CS_L
ROM_WE_L
ROM_WP_L
TP_JTAG_VESTA_TCK 9A5<>
TP_JTAG_VESTA_TDI 9A7<
TP_JTAG_VESTA_TDO 9A5>
TP_JTAG_VESTA_TMS 9A5<>
TP_LEFT_KYBRD_SCREW 2C3<>
PP12V8_ALL_PBUSB 7D7> 10D7<>

PP24V_ADAPTER
7D7> 10C7
PP24V_ADAPTER_ILIM_P 13D7<>
PP24V_ADAPTER_SW 12D4<> 13C6< 13D8<>
PP24V_ADAPT_PMU_ILIM 14A7<>
PP24V_ALL_PBUSA 7D7> 10D7
PPAVDD_CPU0
10C2
PPBUS_DVI_PWRSW 10D6<>
PPBUS_FWPWRSW_F 18D7<>
PPBUS_FW_FET_D
18D6<>
PPBUS_INVERTER
7B7> 56C2<>
RAM_DATA_A<41>
RAM_DATA_A<42>
RAM_DATA_A<43>
RAM_DATA_A<44>
RAM_DATA_A<45>
RAM_DATA_A<46>
RAM_DATA_A<47>
RAM_DATA_A<48>
RAM_DATA_A<49>
RAM_DATA_A<50>
RAM_DATA_A<51>
RAM_DATA_A<52>
RAM_DATA_A<53>
RAM_DATA_A<54>
RAM_DATA_A<55>
RAM_DATA_A<56>
TP_LVDS_L3_N
53A7>
TP_LVDS_L3_P
53A7>
TP_LVDS_U3_N
53B7>
TP_LVDS_U3_P
53B7>
TP_MAXBUS_CLK_CPU1_R 11D7< 32D3< 32D6>
TP_MAXBUS_CPU1_QACK_L 11A5< 32D3<
TP_MAXBUS_TBEN_I2 32A3<
TP_NEC_AMC
62A3<
TP_NEC_NANDTEST 62A3<
TP_NEC_NTEST1
62B3<
TP_NEC_SMC
2B5> 62B3<
USB2_I2_N<0>
11B7> 72C4< 72D6>
USB2_I2_N<1>
6B3> 72C4< 72D6>
USB2_I2_N<2>
11B7> 72B4< 72D6>
USB2_I2_N<3>
6B3> 72B4< 72D6>
USB2_I2_N<4>
11B7> 72B4< 72D6>
USB2_I2_N<5>
11B7> 72B4< 72D6>
USB2_I2_P<0>
11B7> 72C4< 72D6>
USB2_I2_P<1>
6B3> 72C4< 72D6>
USB2_I2_P<2>
11B7> 72C4< 72D6>
USB2_I2_P<3>
6B3> 72B4< 72D6>
USB2_I2_P<4>
11B7> 72B4< 72D6>
USB2_I2_P<5>
11B7> 72B4< 72D6>
USB2_I2_RIGHT_PORT_N 6B3> 11B8< 11C5<
USB2_I2_RIGHT_PORT_P 6B3> 11B8< 11C5<
USB2_LEFT_PORT_N 7B5> 11C7< 74C4<>
USB2_LEFT_PORT_P 7B5> 11D7< 74C4<>
62B5<>
6A6< 59C5< 59D6> 60C3<> 61B7<>
62B5<>
6B6< 59C5< 59D6> 60C5<> 61B7<>
62B5<>
59C5< 59D6> 60B5<> 61B7<> 62B5<>
PPFW_CABLE_POWER 10D5
PPFW_PORT1_VP
70D2<>
PPFW_PORT2_VP
70B3<>
PPFW_PORT2_VP_F 70B3<
PPVBATT_BATT
10C7
PPVBATT_BATTPOS_CONN 12B7<>
RAM_DATA_A<57>
RAM_DATA_A<58>
RAM_DATA_A<59>
RAM_DATA_A<60>
RAM_DATA_A<61>
RAM_DATA_A<62>
40A4<
40A4<
40A6<
40A4<
40A6<
40A4<
RT_ALS_OP_COMP
28D4<
RT_ALS_OP_IN
28D5<
RT_ALS_OUT_FB
28D4<>
RT_ALS_PHOTODIODE 28D5<>
SCCA_RXD
7B5> 22B6< 24C2<>
SCCA_TXD_L
7B5> 22B2< 24C1<>
TP_NEC_SMI_L
TP_NEC_SRCLK
TP_NEC_SRDATA
TP_NEC_SRMOD
TP_NEC_TEB
TP_NEC_TEST
USB2_NEC_LEFT_PORT_N 6B3> 11B6< 11C5<

USB2_NEC_LEFT_PORT_P 6B3> 11B6< 11D5<
USB2_NEC_N<0>
11B5> 73C2<> 73D7>
USB2_NEC_N<1>
11B5> 73C2<> 73D7>
USB2_NEC_N<2>
11B5> 73B2<> 73D7>
USB2_NEC_N<3>
11B5> 73B2<> 73D7>
61B7<> 61C7<
11A5< 11B2< 11C2< 11C2< 11C8<
25A7< 25C2<>
61B7> 61B7<
11D3< 59C3< 59C6>
11C3< 22D5< 59C2<
11D3< 59C5< 59C6>
11C3< 59C3< 59C6>
11C3< 22D5< 59C2<
11C3< 59C5< 59C6>
11C3< 22B7< 22C5<
PPVBATT_BATT_CHRG_VSNS 10C7
PPVBATT_BATT_PBUSA_FUSE 13B1< 13D2<>
PPVBATT_BATT_PBUSB_FUSE 13D1<>
PPVBATT_BATT_RAW 12B5<>
PPVBATT_ISNS_VINN 12A4<> 12D6>
PPVBATT_ISNS_VINP 12A5<> 12D6>
PPVCC_CBUS_SW
61B1< 61B2< 61D2<>
PPVCORE_CPU_ADT7467 10C4<>
PPVCORE_GPU_REG 10A8<
PPVCORE_PWRON_I2 10A7<>
PPVCORE_PWRON_I2_REG 10A8<
RAM_DATA_A<63>
40A6<
RAM_DATA_B<0>
41D4<
RAM_DATA_B<63..0> 39B5>
RAM_DATA_B<1>
41D6<
RAM_DATA_B<2>
41D6<
RAM_DATA_B<3>
41D4<
RAM_DATA_B<4>
41D4<
RAM_DATA_B<5>
41D4<
RAM_DATA_B<6>
41D6<
RAM_DATA_B<7>
41D6<
RAM_DATA_B<8>
41D6<
SI_HTPLG
SI_IDCK_N
SI_M_A1
SI_M_EXTSWING
SI_M_MSEN
SI_SYNC
SI_S_A1
SI_S_EXTSWING
SI_S_MSEN
SI_TMDS_CLKN
SI_TMDS_CLKP
54B6< 55B6<
54A4< 54A6< 55A6<
54B6<
54A3<
54B3<>
54B6<> 55B6<>
55B6<
55B4<
55B4<>
54B3< 54C6> 54D7<
2A4> 54B3< 54C6> 54D7<
TP_OPTICAL_DRIVE_SCREW
TP_PCI_CLK33M_ZDBOUT3
TP_PMU_AN_P0_0
11B1>
TP_PMU_AN_P0_1
11B1>
TP_PMU_AN_P0_2
11B1>
TP_PMU_AN_P0_3
11B1>
TP_PMU_AN_P0_4
11B1>
TP_PMU_AN_P0_5
11B1>
TP_PMU_AN_P0_6
25A8<
11B3< 22B7< 22C5<

11C3< 22A7< 22C5<
6B6< 59C5< 59D6> 60B5<> 61B7<>
62B5<>
6B6< 59C5< 59D6> 60B3<> 61A7<>
PPVCORE_RUN_CPU 7C7> 10C5<>

PPVCORE_RUN_GPU 7D7> 10A7<>
PPVIN_1778_VIN
45C5<
PPVIN_ALL_ADAPT_OR_BATT 14A6<>
PPVIN_CPU0_AVDD 37C6<
PPVIN_VESTA3V3
18D5<>
PPVOUT_1778_VCC 45C5<>
PPVOUT_BATT_CHRG_R 13B2<
PPVOUT_CPU0_AVDD_R 37C4<>
PPVOUT_VESTA1V2 18C4<
PPVPP_CBUS_SW
61B1< 61B2< 61D2<>
PWRON_REGS_PGOOD 26B7<
RAM_ADDR<0>
39D7< 40B4< 41B4<
RAM_ADDR<13..0> 39A6>
RAM_ADDR<1>
39D7< 40B6< 41B6<
RAM_ADDR<2>
39D7< 40B4< 41B4<
RAM_ADDR<3>
39D7< 40B6< 41B6<
RAM_ADDR<4>
39D7< 40B4< 41B4<
RAM_ADDR<5>
39D7< 40B6< 41B6<
RAM_ADDR<6>
39C7< 40C4< 41C4<
RAM_ADDR<7>
39C7< 40C4< 41C4<
RAM_ADDR<8>
39C7< 40C6< 41C6<
RAM_DATA_B<9>
RAM_DATA_B<10>
RAM_DATA_B<11>
RAM_DATA_B<12>
RAM_DATA_B<13>
RAM_DATA_B<14>
RAM_DATA_B<15>
RAM_DATA_B<16>
RAM_DATA_B<17>
RAM_DATA_B<18>
RAM_DATA_B<19>
RAM_DATA_B<20>
RAM_DATA_B<21>
RAM_DATA_B<22>
RAM_DATA_B<23>
RAM_DATA_B<24>
RAM_DATA_B<25>
RAM_DATA_B<26>
RAM_DATA_B<27>
RAM_DATA_B<28>
RAM_DATA_B<29>
RAM_DATA_B<30>
41D4<
41D6<
41D4<
41D4<
41D6<
41D6<
41D4<
41C6<
41D6<
41D4<
41C6<
41C4<
41C4<
41C6<
41C4<
41C4<
41C6<
41C6<
41C6<
41C4<
41C6<
41C4<
SI_TMDS_DN<0>
SI_TMDS_DN<1>
SI_TMDS_DN<2>
SI_TMDS_DN<3>
SI_TMDS_DN<4>
SI_TMDS_DN<5>
SI_TMDS_DP<0>
SI_TMDS_DP<1>
SI_TMDS_DP<2>
SI_TMDS_DP<3>
SI_TMDS_DP<4>
SI_TMDS_DP<5>
SI_TMDS_RESET_L
SI_VREF
SLEEP_LED_CONN
SLEEP_LED_DGND
2B4> 54B3< 54C6> 54D7<

2B4> 54B3< 54C6> 54D5<
2B4> 54B3< 54C6> 54D5<
55B4< 55C6> 55D2<
2B4> 55B4< 55C6> 55D2<
2B4> 55B4< 55C6> 55D2<
54B3< 54C6> 54D7<
54B3< 54C6> 54D5<
54B3< 54C6> 54D5<
2B4> 55B4< 55C6> 55D2<
55B4< 55C6> 55D2<
55B4< 55C2< 55C6>
11C8
54A3< 54A3< 55A4<
30B4<>
30B4<>
TP_PMU_AN_P0_7
25A8< 25C5<>
TP_PMU_AN_P10_0 25A8< 25B2<>
TP_PMU_AN_P10_1 25A8< 25B2<>
TP_PMU_AN_P10_2 25A8< 25B2<>
TP_PMU_AN_P10_3 25A7< 25B2<>
TP_PMU_AN_P10_4 25A7< 25B2<>
TP_PMU_AN_P10_5 11A1> 25A7< 25B2<>
TP_PMU_AN_P10_6 11B3> 25A7< 25B2<>
TP_PMU_AN_P10_7 25A4< 25B2<>
TP_PMU_P3_0
11A3> 25A5< 25B5<>
TP_PMU_P3_1
11A3> 25A5< 25B5<>
TP_PMU_P3_2
11A3> 25A5< 25B5<>
TP_PMU_P3_3
11A3> 25A5< 25B5<>
TP_PMU_P7_0
25A8< 25C2<>
TP_PMU_P7_1
25A8< 25C2<>
TP_PMU_P7_2
25A7< 25C2<>
TP_PMU_P7_4
11B1> 25A5< 25C2<>
TP_PMU_P7_5
11B3> 25A5< 25C2<>
TP_RT_KYBRD_SCREW 2C3<>
TP_USB2_PWREN<0> 2B5> 73B5>
TP_USB2_PWREN<1> 73B5>
PMU_CLK10M_XOUT_R 25B5<> 25D6>

PMU_CLK32K_XIN
25B3<> 25D6>
PMU_CLK32K_XOUT 25B1< 25D6>
PMU_CLK32K_XOUT_R 25B3<> 25D6>
PMU_CPU_CLK_EN
11B4< 25C5<>
PMU_CPU_HRESET_L 11B4< 25B5<>
PMU_CUSTOMER_RESET 24C7<>
PMU_INT_L
22B6< 22D5< 25B2<>
PMU_POWER_UP_L
25B5<> 25C7< 26D8<
PMU_RESET_L
24B2< 24C2<> 24D6<> 25B5<
PMU_SB_NMI_L
22B6< 22D5< 25B2<>
RAM_ADDR<9>
39C7< 40C6< 41C6<
RAM_ADDR<10>
39C7< 40B6< 41B6<
RAM_ADDR<11>
39C7< 40C4< 41C4<
RAM_ADDR<12>
39C7< 40C6< 41C6<
RAM_ADDR<13>
39C7< 40B4< 41B4<
RAM_ADDR_R<0>
39D8<
RAM_ADDR_R<13..0> 38D3> 38D6>
RAM_ADDR_R<1>
39D8<
RAM_ADDR_R<2>
39D8<
RAM_ADDR_R<3>
39D8<
RAM_ADDR_R<4>
39D8<
RAM_DATA_B<31>
RAM_DATA_B<32>
RAM_DATA_B<33>
RAM_DATA_B<34>
RAM_DATA_B<35>
RAM_DATA_B<36>
RAM_DATA_B<37>
RAM_DATA_B<38>
RAM_DATA_B<39>
RAM_DATA_B<40>
RAM_DATA_B<41>
41C4<
41B4<
41B4<
41B6<
41B6<
41B6<
41B6<
41B4<
41B4<
41B4<
41A6<
PMU_SYS_CLK_EN
11B4< 25C5<>
PP1V2_VESTA
10D5
PP1V2_VESTA_AVDDL 18B6<
PP1V2_VESTA_FAVDDL 69C2<
PP1V2_VESTA_PLLVDD1 66D4<
PP1V2_VESTA_PLLVDD2 69D4<
PP1V5R1V8_I2_MAXBUS 32B6<
PP1V5R3V3_GPU_VDDR4 47C3< 53C8< 53D8<
PP1V5_GPU
10A7<
PP1V5_GPU_AGP
47C3<
PP1V5_GPU_PSNECK 52C3<>
PP1V5_GPU_VDD15 46B2<
PP1V5_GPU_VDD15_F 46B4<>
PP1V5_PWRON
10A5<>
PP1V5_PWRON_I2PLL 10D2
PP1V5_PWRON_I2_PLL1AVDD 19C4<
PP1V5_PWRON_I2_PLL4AVDD 19B4<
PP1V5_PWRON_I2_PLL7AVDD 19A4<
PP1V5_PWRON_I2_PLL9AVDD 19A4<
PP1V5_PWRON_I2_PLLUSBAVDD 72C5<
PP1V5_PWRON_REG 10A6<
PP1V5_RUN
10A2
PP1V8R2V5_GPU_FB_VIO 47C6<
PP1V8_GPU
10A7<
PP1V8_GPU_A2VDDQ 53A2<
PP1V8_GPU_AVDD
53C2<
PP1V8_GPU_LVDS_PLL 47B2<
PP1V8_GPU_MEMPLL 51C3<
PP1V8_GPU_PANEL_IO 47B1< 53C4<
RAM_ADDR_R<5>
RAM_ADDR_R<6>
RAM_ADDR_R<7>
RAM_ADDR_R<8>
RAM_ADDR_R<9>
RAM_ADDR_R<10>
RAM_ADDR_R<11>
RAM_ADDR_R<12>
RAM_ADDR_R<13>
RAM_BA<0>
RAM_BA<2..0>
RAM_BA<1>
RAM_BA<2>
RAM_BA_R<0>
RAM_BA_R<2..0>
RAM_BA_R<1>
RAM_BA_R<2>
RAM_CAS_L
RAM_CAS_L_R
RAM_CKE<0>
RAM_CKE<3..0>
RAM_CKE<1>
RAM_CKE<2>
RAM_CKE<3>
RAM_CKE_R<0>
RAM_CKE_R<1..0>
RAM_CKE_R<3..0>
RAM_CKE_R<1>
RAM_CKE_R<2>
RAM_CKE_R<3..2>
RAM_CKE_R<3>
RAM_CLKDDR_0_N
RAM_CLKDDR_0_N_R
39D8<
39C8<
39C8<
39C8<
39C8<
39C8<
39C8<
39C8<
39C8<
39C7< 40B6< 41B6<
39A6>
39B7< 40B4< 41B4<
39B7< 40C6< 41C6<
39C8<
38C3> 38D6>
39B8<
39B8<
39A6> 39B7< 40B6< 41B6<
38B3> 38D6> 39B8<
39B4> 40C6<
39A6>
39B4> 40C4<
39B4> 41C6<
39B4> 41C4<
39B6<
38D6>
38B3>
39B6<
39B6<
38D6>
39B6<
39A6> 39D4> 40D4<
38A3> 38D6> 39D6<
PP1V8_GPU_PLL
51C3<
PP1V8_GPU_PSNECK 52D3<>
PP1V8_GPU_PVDD
26A6<> 51D2<>
PP1V8_GPU_TPVDD 53C5<
PP1V8_GPU_VDDDI 53B2<
PP1V8_GPU_VDD_MEM_CLK 47A4<
PP1V8_PWRON
7C7> 10A5<>
PP1V8_RUN
10A2
PP1VR1V3_GPU_VDDCI 46C2<
PP2V5R2V8_GPU_LVDS_IO 47B2<
PP2V5_ENET_CTAP 67C6<>
PP2V5_GPU
10B7<
PP2V5_GPU_A2VDD 53B2<
PP2V5_PWRON
7C7> 10A5<>
PP2V5_RUN
10B2
PP2V5_VESTA
10D5
PP2V5_VESTA_BIASVDD1 66D4<
PP2V5_VESTA_BIASVDD2 69D4<
PP2V5_VESTA_FAVDDM 69D2<
RAM_CLKDDR_0_P
RAM_CLKDDR_0_P_R
RAM_CLKDDR_1_N
RAM_CLKDDR_1_N_R
RAM_CLKDDR_1_P
RAM_CLKDDR_1_P_R
RAM_CLKDDR_2_N
RAM_CLKDDR_2_N_R
RAM_CLKDDR_2_P
RAM_CLKDDR_2_P_R
RAM_CLKDDR_3_N
RAM_CLKDDR_3_N_R
RAM_CLKDDR_3_P
RAM_CLKDDR_3_P_R
RAM_CS_L<0>
RAM_CS_L<3..0>
39A6> 39D4> 40D4<

38B3> 38D6> 39D6<
39A6> 39D4> 40A4<
38A3> 38D6> 39D6<
39A6> 39D4> 40A4<
38A3> 38D6> 39D6<
39A6> 39C4> 41D4<
38A3> 38D6> 39C6<
39A6> 39D4> 41D4<
38A3> 38D6> 39D6<
39A6> 39C4> 41A4<
38A3> 38D6> 39C6<
39A6> 39C4> 41A4<
38A3> 38D6> 39C6<
39C4> 40B4<
39A6>
RAM_CS_L<1>
RAM_CS_L<2>
RAM_CS_L<3>
RAM_CS_L_R<0>
RAM_CS_L_R<1..0>
RAM_CS_L_R<3..0>
39C4> 40B6<
39C4> 41B4<
39C4> 41B6<
39C6<
38D6>
38C3>
RAM_DATA_B<42>
41A6<
RAM_DATA_B<43>
41B6<
RAM_DATA_B<44>
41A4<
RAM_DATA_B<45>
41A4<
RAM_DATA_B<46>
41B4<
RAM_DATA_B<47>
41B6<
RAM_DATA_B<48>
41A4<
RAM_DATA_B<49>
41A6<
RAM_DATA_B<50>
41A4<
RAM_DATA_B<51>
41A6<
RAM_DATA_B<52>
41A6<
RAM_DATA_B<53>
41A4<
RAM_DATA_B<54>
41A4<
RAM_DATA_B<55>
41A6<
RAM_DATA_B<56>
41A6<
RAM_DATA_B<57>
41A4<
RAM_DATA_B<58>
41A4<
RAM_DATA_B<59>
41A6<
RAM_DATA_B<60>
41A4<
RAM_DATA_B<61>
41A6<
RAM_DATA_B<62>
41A4<
RAM_DATA_B<63>
41A6<
RAM_DATA_R<7..0> 38C6>
RAM_DATA_R<63..0> 38D6<> 39B6<
RAM_DATA_R<15..8> 38C6>
RAM_DATA_R<23..16> 38C6>
RAM_DATA_R<31..24> 38C6>
RAM_DATA_R<39..32> 38C6>
RAM_DATA_R<47..40> 38C6>
RAM_DATA_R<55..48> 38C6>
RAM_DATA_R<63..56> 38B6>
RAM_DQM<7..0>
39A6> 39B6
RAM_DQM_A<0>
40D4<
RAM_DQM_A<7..0> 39B5>
RAM_DQM_A<1>
40D4<
RAM_DQM_A<2>
40C4<
RAM_DQM_A<3>
40C6<
RAM_DQM_A<4>
40B4<
RAM_DQM_A<5>
40B6<
RAM_DQM_A<6>
40A4<
RAM_DQM_A<7>
40A6<
RAM_DQM_B<0>
41D4<
RAM_DQM_B<7..0> 39B5>
RAM_DQM_B<1>
41D4<
RAM_DQM_B<2>
41C4<
RAM_DQM_B<3>
41C6<
RAM_DQM_B<4>
41B4<
RAM_DQM_B<5>
41B6<
RAM_DQM_B<6>
41A4<
RAM_DQM_B<7>
41A6<
RAM_DQM_R<0>
38C6>
RAM_DQM_R<7..0> 38B3> 39B6<
RAM_DQM_R<1>
38C6>
RAM_DQM_R<2>
38C6>
RAM_DQM_R<3>
38C6>
PP2V5_VESTA_XTALVDD1 66D4<
PP2V5_VESTA_XTALVDD2 69C4<
PP2V8_GPU_LVDDR 10B7
PP3V3R5V_RUN_HDD_LOGIC 7B7> 64B7<>
PP3V3_ADT7467
27D3<
PP3V3_ALL
7C7> 10C7
PP3V3_ALL_ESR
14A2<
PP3V3_ALL_HALL_EFFECT_R 7C5> 30D5<>
PP3V3_ALL_PMU_AVCC 10B7< 25D3<
PP3V3_FW_ESD
70A6<> 70B5<> 70D5<>
PP3V3_FW_ESD_F
70A7<
PP3V3_GPU
10B7<
PP3V3_GPU_OSC
52C6<
PP3V3_GPU_SS
52B6<
PP3V3_GPU_VDDR3 47D3< 51B6<
PP3V3_LCD_CONN
7B7> 56C5<>
PP3V3_LCD_SW
56C6<>
PP3V3_PWRON
7C7> 10B5<>
PP3V3_PWRON_AUDIO_AVDD 7A7> 74B3<>
PP3V3_PWRON_DS1775_R 7D5> 30D6<>
PP3V3_PWRON_NEC_AVDD 73D4<
PP3V3_PWRON_REG 10B6<
PP3V3_RUN
10B2
PP3V3_RUN_PCI1510 61C8< 61D5<
PP3V3_SI_M_AVCC 54C4<
PP3V3_SI_M_PVCC 54C4<
RAM_CS_L_R<1>
39C6<
RAM_CS_L_R<2>
39C6<
RAM_CS_L_R<3..2> 38D6>
RAM_CS_L_R<3>
39C6<
RAM_DATA<63..0> 39A6> 39B6
RAM_DATA_A<0>
40D4<
RAM_DATA_A<63..0> 39B5>
RAM_DATA_A<1>
40D6<
RAM_DATA_A<2>
40D6<
RAM_DATA_A<3>
40D4<
RAM_DATA_A<4>
40D4<
RAM_DATA_A<5>
40D4<
RAM_DATA_A<6>
40D6<
RAM_DATA_A<7>
40D6<
RAM_DATA_A<8>
40D6<
RAM_DATA_A<9>
40D4<
RAM_DATA_A<10>
40D6<
RAM_DATA_A<11>
40D4<
RAM_DATA_A<12>
40D4<
RAM_DATA_A<13>
40D6<
RAM_DATA_A<14>
40D6<
RAM_DATA_A<15>
40D4<
RAM_DATA_A<16>
40C6<
RAM_DATA_A<17>
40D6<
RAM_DATA_A<18>
40D4<
RAM_DATA_A<19>
40C6<
RAM_DATA_A<20>
40C4<
RAM_DQM_R<4>
RAM_DQM_R<5>
RAM_DQM_R<6>
RAM_DQM_R<7>
RAM_DQS<7..0>
PP3V3_SI_M_VCC
54C5<
PP3V3_SI_S_AVCC 55C5<
PP3V3_SI_S_PVCC 55D5<
PP3V3_SI_S_VCC
55C5<
PP3V3_VESTA
10D5
PP3V3_VESTA_FAVDDH 69D2<
PP4V6_ALL_RAW
14B3<>
RAM_DATA_A<21>
RAM_DATA_A<22>
RAM_DATA_A<23>
RAM_DATA_A<24>
RAM_DATA_A<25>
RAM_DATA_A<26>
RAM_DATA_A<27>
PCI_FRAME_L
PCI_IRDY_L
PCI_PAR
33C6<>
33C6<>
PCI_PERR_L
PCI_RESET_L
PCI_SERR_L
PCI_SLOTA_GNT_L
PCI_SLOTA_INT_L
PCI_SLOTA_REQ_L
PCI_SLOTD_GNT_L
PCI_SLOTD_INT_L
PCI_SLOTD_REQ_L
PCI_SLOTE_GNT_L
PCI_SLOTE_INT_L
PCI_SLOTE_REQ_L
PCI_STOP_L
PCI_TRDY_L
33B6<>
33B6<>
60B5<> 61C7<> 62C5<>

60B3<> 61C7<> 62C5<>
60B5<> 61C7<> 62C5<>
60B3<> 61C7<> 62C5<>
60B5<> 61C7<> 62C5<>
60B5<> 61C7<> 62C5<>
60B5<> 61C7<> 62C5<>
60B5<> 61C7<> 62C5<>
60B5<> 61C7<> 62C5<>
60B3<> 61C7<> 62C5<>
60B3<> 61C7<> 62C5<>
60B5<> 61C7<> 62C5<>
60B3<> 61C7<> 62C5<>
60B3<> 61C7<> 62C5<>
60B3<> 61C7<> 62C5<>
60B5<> 61C7<> 62C5<>
59B3< 59D6> 60C3<> 61C7<>
60B5<> 61B7<> 62C5<>
60C5<> 61B7<> 62C5<>
59B3< 59D6> 60C3<> 61B7<>
59B3< 59D6> 60C5<> 61B7<>
60C5<> 61B7<> 62C5<>
61B7<> 62C5<>
61B7<> 62C5<>
61B7<> 62C5<>
61B7<> 62C5<>
61B7<> 62B5<>
61B7<> 62B5<>
61B7<> 62B5<>
61B7<> 62B5<>
62B5<>
PCI_USB2_GNT_L
11C2
PCI_USB2_IDSEL
62B5<
PCI_USB2_INT_L
11B2
PCI_USB2_REQ_L
11C2
PMU_BATT0_CHARGE 13A8<> 25C2<>
PMU_BATT1_CHARGE 25A4>
PMU_BATT1_DET_L 25A4>
PMU_BOOT_BUSY
24C1<> 25C2<>
PMU_BOOT_CNVSS
24C2<> 25B5<
PMU_BOOT_RP_L
24C1<> 25C2>
PMU_BOOT_RXD
PMU_BOOT_SCLK
PMU_BOOT_TXD
PMU_CHARGE_V
PMU_CLK10M_XIN
PMU_CLK10M_XOUT
24C1<> 25C2<>
24C2<> 25C2<>
24C1<> 25C2<>
11B4< 13B8<>
25B5< 25D6>
25A6< 25D6>
10C7
14A4<
38C6>
39B7< 40B4<
39A6>
39B7< 41B4<
38B3> 38D6> 39B8<
38B3> 38C6> 39B8<
39A6> 39B7< 40B4< 41B4<
38B3> 38D6> 39B8<
40A7<
39A6> 39B7< 40B6< 41B6<
38B3> 38D6> 39B8<
58B6< 59C3< 60B5<>
58B6< 59C3< 60B3<>
58B6< 60B5<>
58B6< 59C3< 60B3<>
58B5<
SLEEP_LED_I
24B6<
SLEEP_LED_IOUT
11A4
SLEEP_LED_L
24B7<
SLEEP_LED_SW_L
24B7<
SOFTMODEM_FC_RGDT 30A7<>
SPI_CHGR_TO_PMU_MISO 25A4>
SPI_PMU_CHGR_CLK 25A4>
SPI_PMU_CHGR_CS 25A4>
SPI_PMU_TO_CHGR_MOSI 25A4>
STOP_AGP_L
43D2< 43D3< 44B4<
SYS_ACIN
12C6<> 13C8<> 18B8< 25C2<>
SYS_ACIN_L
12C5<> 13C3<>
SYS_ACIN_L_RC
13C2<>
SYS_AC_DET
12C6<> 25C2<>
SYS_AC_DET_L
12C6<> 24D8<>
SYS_ADAPTER_ANALOG_AC_DET 7C5> 12D4< 74C6<>
SYS_BATT0_DET_L 12A5< 24C8<> 25C2<>
SYS_CHARGE_LED_L 7C5> 24A6< 74C6<>
SYS_COLD_RESET_L 25B7< 25C2<>
SYS_KBDLED
25C2<> 28A5<>
SYS_LED
24B8< 25C2<>
SYS_LID_OPEN
25C5<> 30C2<
SYS_LID_OPEN_F
7C5> 30C5<>
SYS_ONEWIRE
24A7< 25B2<>
SYS_OVERTEMP_L
7C5> 11B4< 25B7< 25C2<> 30C6<>
SYS_PME_L
22A2< 25B7< 25C2<> 62A7<
SYS_PMU_ANALOG_AC_DET 11B4< 12C2<
SYS_POWERUP
26D5<>
SYS_POWER_BUTTON_L 24B2< 24C8<> 25B7< 25C5<> 30C3<
36A3<> 57B1<>
SYS_POWER_BUTTON_L_F 7C5> 30C5<>
SYS_POWER_UP_L
26D6<>
SYS_PWRSEQ_1
11B2< 26D8<>
SYS_PWRSEQ_1_L
26D4<>
SYS_PWRSEQ_2
11B2< 26D8<>
SYS_PWRSEQ_2_L
26D6<>
SYS_PWRSEQ_3_L
11B2< 26C8<>
SYS_PWRSEQ_3_LS5 26C7<>
SYS_PWRSEQ_4
11B2< 26B8<>
SYS_PWRSEQ_5
11B2< 26B8<>
SYS_PWRSEQ_6_L
11B2< 26A8<>
SYS_PWRSEQ_6_LS5 26A7<>
SYS_PWRSEQ_FINAL 11A2< 26A8<>
SYS_PWRSEQ_TPAD_L 11B2< 26C5<
2B5> 62A5>
2B5> 62A3>
62A3<>
62A3<
62B3<
62A3<
2C3<>
11D4< 59C3< 59D6>
11D4< 59C3< 59D6>
11B2>
25C5<>
25C5<>
25C5<>
25C5<>
25C5<>
25C5<>
25C5<>

TP_USB2_PWREN<4> 73B5>
TP_VCORE_PGOOD
26B4>
TP_VESTA_2_5V_EN 18A3<
TP_VESTA_ACTLED_L 66A3>
TP_VESTA_AN_EN
66B3<>
TP_VESTA_DNC_B9 18A6<>
TP_VESTA_DNC_C9 18A6<>
TP_VESTA_DNC_E9 2B4> 18A6<>
TP_VESTA_EN_10B 66B6<
TP_VESTA_ER
66B6<
TP_VESTA_F1000
2B4> 66B6<
TP_VESTA_FDX
66B6<
TP_VESTA_FDXLED_L 66B3>
TP_VESTA_HUB
66B6<
TP_VESTA_LINKSPD1_L 66B3>
TP_VESTA_LINKSPD2_L 66B3>
TP_VESTA_MANMS
66B6<
TP_VESTA_PHYA<0> 2B4> 66B6<
TP_VESTA_PHYA<1> 66B6<
TP_VESTA_RBC0
66B3<>
TP_VESTA_RBC1
66B3<>
TP_VESTA_REGCTL1 18A3<
TP_VESTA_REGCTL2 18A3<
TP_VESTA_REGSEN1 18A3<
TP_VESTA_REGSEN2 2B4> 18A3<
TP_VESTA_REGSUP1 18A3<
TP_VESTA_REGSUP2 18A3<
TP_VESTA_RGMIIEN 66B6<
TP_VESTA_SPD0
2B4> 66B6<
TP_VESTA_TDBL<0> 69C2>
TP_VESTA_TEST<0> 66B6<
TP_VESTA_TEST<1> 66B6<
SYS_RESET_BUTTON_L 24B2< 25B7< 25C5<> 36A3<>

SYS_SLEEP
25A7< 25B5<>
SYS_WARM_RESET_L 22A2<> 22A5< 25A7< 25C2<> 62A7<
SYS_WATCHDOG
22A2< 25B5<>
TBEN_SYNC_CLR_L 21A4<>
TBEN_SYNC_F1
21B4<>
TBEN_SYNC_F2
21B3<>
THERM1_A_N
27B6< 27B8< 27D6>
THERM1_A_P
27B6< 27B8< 27D6>
THERM1_M_N
27C6< 27C8< 27D6>
THERM1_M_P
27C6< 27C8< 27D6>
THERM2_A_N
27A8< 27B6< 27D6>
THERM2_A_P
27B6< 27B8< 27D6>
THERM2_M_N
27B8< 27C6< 27D6>
THERM2_M_P
27C6< 27C8< 27D6>
THERM_D1_N
27B5< 27C4<> 27C5< 27D6>
THERM_D1_P
27B5< 27C4<> 27C5< 27D6>
THERM_D2_N
27B5< 27C4<> 27C5< 27D6>
THERM_D2_P
27B5< 27C4<> 27C5< 27D6>
TMDS_CLKN
54B1> 54D2< 54D5< 57C6<>
TMDS_CLKP
54B1> 54D3< 54D5< 57C6<>
TMDS_CONN_CLKN
57C4<> 57C5<> 57D6>
TMDS_CONN_CLKP
2B5> 57C4<> 57C5<> 57D6>
TMDS_CONN_DN<0> 57D4<> 57D5<> 57D6>
TMDS_CONN_DN<1> 57D3<> 57D5<> 57D6>
TMDS_CONN_DN<2> 57D3<> 57D5<> 57D6>
TMDS_CONN_DN<3> 57C3<> 57C5<> 57D6>
TMDS_CONN_DN<4> 57C3<> 57C5<> 57D6>
TP_VESTA_TEST_1394<0> 69B5<
TP_VESTA_TEST_1394<1> 69B5<
TP_VESTA_TVCO
66A6<>
TP_VESTA_TVCO_24 69B5<>
TP_VESTA_TXC_RXC_DELAY 66B3<>
TP_VESTA_XMTLED_L 66A3>
TV_C
53C1> 57A7<>
TV_COMP
53C1> 57A7<>
TV_Y
53C1> 57A7<>
UATA_CS0_L
6C6> 7B7> 63D6> 64B2<> 64B7<>
UATA_CS0_L_R
6C8< 63B3< 63D6>
UATA_CS1_L
7B7> 63B1> 63D6> 64B4<> 64B5<>
UATA_CS1_L_R
63B2< 63B3< 63D6>
UATA_DA<0>
6C6> 64B2<> 64B7<>
UATA_DA<2..0>
7B7> 63D6>
UATA_DA<1>
6B6> 64B2<> 64B7<>
UATA_DA<2>
6C6> 64B4<> 64B5<>
UATA_DASP_L
64B2<> 64B5<>
UATA_DA_R<0>
2B5> 6C8<
UATA_DA_R<2..0> 63B3> 63D6>
UATA_DA_R<1>
2B5> 6B8<
UATA_DA_R<2>
6C8<
UATA_DD<0>
6C6> 64B2<> 64C7<>
UATA_DD<15..0>
7B7> 63D6>
UATA_DD<1>
6B6> 64B2<> 64C7<>
UATA_DD<2>
6C6> 64B2<> 64C7<>
UATA_DD<3>
6C6> 64C2<> 64C7<>
UATA_DD<4>
6C6> 64C2<> 64C7<>
RAM_DQS_A_N<0>
39A5< 40D6<
RAM_DQS_A_N<1>
39A5< 40D6<
RAM_DQS_A_N<2>
39A5< 40C6<
RAM_DQS_A_N<3>
39B5< 40C4<
RAM_DQS_A_N<4>
39A5< 40B6<
RAM_DQS_A_N<5>
39A5< 40B4<
RAM_DQS_A_N<6>
39A5< 40A6<
RAM_DQS_A_N<7>
39A5< 40A4<
RAM_DQS_A_P<0>
40D6<
RAM_DQS_A_P<7..0> 39B5>
RAM_DQS_A_P<1>
40D6<
RAM_DQS_A_P<2>
40C6<
RAM_DQS_A_P<3>
40C4<
RAM_DQS_A_P<4>
40B6<
RAM_DQS_A_P<5>
40B4<
RAM_DQS_A_P<6>
40A6<
RAM_DQS_A_P<7>
40A4<
RAM_DQS_B_N<0>
39A5< 41D6<
RAM_DQS_B_N<1>
39B5< 41D6<
RAM_DQS_B_N<2>
39A5< 41C6<
RAM_DQS_B_N<3>
39A5< 41C4<
RAM_DQS_B_N<4>
39A5< 41B6<
TMDS_CONN_DN<5> 57B5<> 57C4<> 57D6>

TMDS_CONN_DP<0> 57D4<> 57D5<> 57D6>
TMDS_CONN_DP<1> 57D3<> 57D5<> 57D6>
TMDS_CONN_DP<2> 57C5<> 57D3<> 57D6>
TMDS_CONN_DP<3> 57C3<> 57C5<> 57D6>
TMDS_CONN_DP<4> 57C3<> 57C5<> 57D6>
TMDS_CONN_DP<5> 57B5<> 57C4<> 57D6>
TMDS_D3_CMF
55C1<
TMDS_D4_CMF
55C1<
TMDS_D5_CMF
55B1<
TMDS_DN<0>
54B1> 54D1< 54D5< 57D6<>
TMDS_DN<1>
54B1> 54D2< 54D4< 57D6<>
TMDS_DN<2>
54B1> 54C1< 54D4< 57D6<>
TMDS_DN<3>
55C1< 55C6> 55D1< 57C6<>
TMDS_DN<4>
55B1< 55C6> 55D1< 57C6<>
TMDS_DN<5>
55B1< 55C6> 55D1< 57B6<>
TMDS_DP<0>
54B1> 54D2< 54D5< 57D6<>
TMDS_DP<1>
54B1> 54D3< 54D4< 57D6<>
TMDS_DP<2>
54B1> 54C2< 54D4< 57C6<>
TMDS_DP<3>
55C2< 55C6> 55D1< 57C6<>
TMDS_DP<4>
55B2< 55C6> 55D1< 57C6<>
TMDS_DP<5>
55B2< 55C1< 55C6> 57B6<>
TPS2211_SHTDWN_L 61C5<
TP_AIRPORT_ALT_ANTENNA 60B3<>
TP_AIRPORT_PME_L 60C3<>
TP_ATI_GPIO8
51B5<>
TP_ATI_GPIO9
51B5<>
UATA_DD<5>
UATA_DD<6>
UATA_DD<7>
UATA_DD<8>
UATA_DD<9>
UATA_DD<10>
UATA_DD<11>
UATA_DD<12>
UATA_DD<13>
UATA_DD<14>
UATA_DD<15>
UATA_DD_R<0>
UATA_DD_R<6..0>
UATA_DD_R<15..0>
UATA_DD_R<1>
UATA_DD_R<2>
UATA_DD_R<3>
UATA_DD_R<4>
UATA_DD_R<5>
UATA_DD_R<6>
UATA_DD_R<7>
UATA_DD_R<8>
UATA_DD_R<15..8>
UATA_DD_R<9>
UATA_DD_R<10>
UATA_DD_R<11>
UATA_DD_R<12>
6C6> 64C2<>
6C6> 64C2<>
6C6> 64C2<>
6C6> 64C4<>
6C6> 64C4<>
6C6> 64C4<>
6C6> 64C4<>
6C6> 64C4<>
6C6> 64B4<>
6C6> 64B4<>
6C6> 64B4<>
2B5> 6C8<
63D6>
63C3>
6B8<
6C8<
6C8<
6C8<
6C8<
6C8<
6C8< 63D6>
2B5> 6C8<
63D6>
6C8<
2B5> 6C8<
6C8<
6C8<
40C4<
40C6<
40C4<
40C4<
40C6<
40C6<
RAM_DQS_B_N<5>
39A5< 41B4<
RAM_DQS_B_N<6>
39A5< 41A6<
RAM_DQS_B_N<7>
39A5< 41A4<
RAM_DQS_B_P<0>
41D6<
RAM_DQS_B_P<7..0> 39B5>
RAM_DQS_B_P<1>
41D6<
TP_ATI_GPIO10
51B5<>
TP_ATI_GPIO11
51B5<>
TP_ATI_GPIO12
51B5<>
TP_CPU0_CLKOUT
33C1>
TP_CPU0_HPR_N
34C4<>
TP_CPU0_OVDDSENSE1 33B8<
40C6<
RAM_DQS_B_P<2>
TP_CPU0_OVDDSENSE2
UATA_DD_R<13>
UATA_DD_R<14>
UATA_DD_R<15>
UATA_DMACK_L
UATA_DMACK_L_R
UATA_DMARQ
UATA_DMARQ_R
6C8<
6C8<
6C8<
7B7> 63B1> 63C6> 64B4<> 64B7<>
63B2< 63B3< 63D6>
7B7> 63B1< 63C6> 64B4<> 64B7<>
63B2< 63B5< 63D6>
38C6>
38C6>
38C6>
38C6>
39A6> 39B6
41C6<
33B8<
64C7<>
64C7<>
64C7<>
64C5<>
64C5<>
64C5<>
64C5<>
64C5<>
64C5<>
64C5<>
64C5<>
7B7> 63A1< 63C6> 64B2<> 64B5<>

63A2< 63B5< 63D6>
UATA_HSTROBE
7B7> 63B1> 63D6> 64B4<>
UATA_HSTROBE_R
63B2< 63B3< 63D6>
UATA_INTRQ
7B7> 63A1< 63C6> 64B2<>
UATA_INTRQ_R
63A2< 63B5< 63D6>
UATA_PDIAG
64B4<> 64B7<>
UATA_RESET_L
7B7> 63B1> 63C6> 64C2<>
UATA_RESET_L_R
63B2< 63B3< 63D6>
UATA_STOP
7B7> 63B1> 63D6> 64B2<>
UATA_STOP_R
63B2< 63B3< 63D6>
USB2_I2_LEFT_PORT_N 6B3> 11B8< 11C5<
USB2_I2_LEFT_PORT_P 6B3> 11B8< 11C5<
USB2_NEC_P<0>
11B5>
USB2_NEC_P<1>
11B5>
USB2_NEC_P<2>
11B5>
USB2_NEC_P<3>
11B5>
USB2_OC<0>
73B6<
USB2_OC<1>
73B6<
USB2_OC<2>
73B6<
USB2_OC<3>
73B6<
USB2_OC<4>
73B6<
64B7<>
64B5<>
64C7<>
64B5<>
73C2<> 73D7>
73C2<> 73D7>
73B2<> 73D7>
73B2<> 73D7>
6B3> 11B6< 11C5<
6B3> 11B6< 11C5<
USB2_RIGHT_PORT_N 7B5> 11C7< 31B7<>

USB2_RIGHT_PORT_P 7B5> 11C7< 31B7<>
USB_BT_N
11C5< 60B3<>
USB_BT_P
11D5< 60B3<>
USB_I2_BT_N
6B3> 11B8< 11C4<
USB_I2_BT_P
6B3> 11B8< 11C4<
USB_I2_TPAD_N
6B3> 11B8< 11C4<
USB_I2_TPAD_P
6B3> 11B8< 11C4<
USB_NEC_BT_N
2B4> 6A3> 11B6< 11C4<
USB_NEC_BT_P
6A3> 11B6< 11D4<
USB_NEC_N<0>
73C3<>
USB_NEC_N<1>
2B4> 73C3<>
USB_NEC_N<2>
2B4> 73B3<>
USB_NEC_N<3>
2B4> 73B3<>
USB_NEC_P<0>
2B4> 73C3<>
USB_NEC_P<1>
2B4> 73C3<>
USB_NEC_P<2>
73B3<>
USB_NEC_P<3>
73B3<>
USB_NEC_TPAD_N
6A3> 11B6< 11C4<
USB_NEC_TPAD_P
6A3> 11B6< 11C4<
USB_TPAD_N
7D5> 11C5< 30C6<>
USB_TPAD_P
7D5> 11C5< 30C6<>
VCORE_BOOST
36C4<>
VCORE_BST
36C5<>
VCORE_CC
36B6<>
VCORE_CPU0_SHDN_L 26B4<> 36C7<>
VCORE_DH
36B5<>
VCORE_DL
36B5<>
VCORE_FB
36B5<
VCORE_GND
36B5<>
VCORE_GNDA
36B5<>
VCORE_GNDDIV
36A4< 36B5<
VCORE_GNDDIV_TEST 36A3<>
VCORE_GNDSNS
36A2<> 36A4< 36D6>
VCORE_GNDSNS_TEST 36A3<>
VCORE_ILIM
36C6<>
VCORE_LX
36B5<>
VCORE_REF
36B6<>
VCORE_SEL_OFF_PU 36B6<>
VCORE_SEL_ON
36B6<>
VCORE_SNS
36A2<> 36D6>
VCORE_TIME
36B4<>
VCORE_TON
36B6<
VCORE_VCC
36C6<
VCORE_VID<0>
36A2<> 36B8<
VCORE_VID<1>
36A2<> 36B8< 36D1<>
VCORE_VID<2>
36A2<> 36B8< 36D1<>
VCORE_VID<3>
36A2<> 36B8< 36D1<>
VCORE_VID<4>
36A2<> 36B8< 36D1<>
VCORE_VID_A<1>
36C2< 36D3< 36D4<
VCORE_VID_A<2>
36C2< 36D3< 36D4<
VCORE_VID_A<3>
36C2< 36D3< 36D4<
VCORE_VID_A<4>
36C2< 36D3< 36D4<
VCORE_VID_B<1>
36D3< 36D3<
VCORE_VID_B<2>
36D3< 36D3<
VCORE_VID_B<3>
36D3< 36D3<
VCORE_VID_B<4>
36D3< 36D3<
VESTA1V2_ITH
18C3<>
VESTA1V2_ITH_RC 18C3<
VESTA1V2_MODE
18C4<>
VESTA1V2_RT
18C4<>
VESTA1V2_SGND
18B3<>
VESTA1V2_SW
18C3<>
VESTA1V2_VFB
18C3<>
VESTA2V5_NOISE
18D2<>
VESTA3V3_SW
18D4<>
VESTA_BILINGUAL_EN12_L 69A6< 69C5<
VESTA_CLK24M_XTALI 69B5< 69D6>
VESTA_CLK24M_XTALO 69A4< 69D6>
VESTA_CLK24M_XTALO_R 69B5<> 69D6>
VESTA_CLK25M_XTALI 66A6< 66D6>
VESTA_CLK25M_XTALO 66A5< 66D6>
VESTA_CLK25M_XTALO_R 66A6<> 66D6>
VESTA_CPS
69C5<>
VESTA_DS_ONLY_EN0 69A6< 69B5<
VESTA_ENET_LOWPWR 66B6<>
VESTA_LPWR_1394 69B5<
VESTA_PORT1_DISABLE_L 69A6< 69C5<
VESTA_PORT2_DISABLE_L 69A6< 69C5<
VESTA_PWR_CLASS_MSB 69A6< 69B5<
VESTA_RDAC1_PD
66A4<>
VESTA_RDAC2_PD
69B3<>
VESTA_RESET
18A7<> 66B8<
VESTA_RESET_L
18A6<>
VESTA_RESET_L_RC 18A7<>
VGA_B
53C1> 57C4<> 57C6<
VGA_G
53C1> 57C3<> 57C6<
VGA_HSYNC
57B1< 57C4<>
VGA_R
VGA_VSYNC
VIA_ACK_L
VIA_CLK
VIA_PMU_TO_SB
VIA_REQ_L
VIA_SB_TO_PMU
VID_MUX_OE_L
53C1> 57B6< 57C3<>

57C1< 57C3<>
22B5< 25B2<>
22B5< 25B2<>
22B5< 25B2<>
22B2< 25B2<> 25B7<
22B2< 25B2<>
36D3<>

SIZE
APPLE COMPUTER INC.
D
SCALE
DRAWING NUMBER
REV.
C
051-6929
113 115
SHT
NONE

OF
113
8
*** Part Cross-Reference for the entire design ***
CAP
73
CAP_P
74
CAP
74
CAP
74
CAP
74
CAP
74
CAP
74
DIODE_SCHOT 13
DIODE
13
DIODE
13
DIODE_SCHOT 14
DIODE_SCHOT 14
DIODE
14
Q1215
Q1220
Q1300
Q1301
Q1330
Q1340
Q1347
TRA_2N7002DW 12
TRA_2N7002 12
TRA_RLA130 13
TRA_IRF7811W 13
TRA_2N7002DW 13
TRA_2N7002DW 13
TRA_2N7002DW 13
R1345
R1346
R1347
R1348
R1351
R1352
R1353
RES
RES
RES
RES
RES
RES
RES
13
13
13
13
13
13
13
54
54
54
54
54
54
C9346
CA000
CA010
CA011
CA033
CA050
CA051
D1300
D1303
D1319
D1400
D1410
D1420
Q1348
Q1360
Q1384
Q1390
Q1392
Q1395
TRA_2N7002DW 13
TRA_IRF7416 13
TRA_2N7002DW 13
TRA_IRF7416 13
TRA_2N7002DW 13
TRA_SUD45P03 13
R1354
R1360
R1361
R1370
R1380
R1381
RES
RES
RES
RES
RES
RES
13
13
13
13
13
13
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
54
54
54
54
55
55
55
55
55
55
55
55
55
55
55
55
D1450
D1451
D1452
D1460
D1461
D1501
D1511
D1533
D1551
D1561
D1601
D1651
D1965
D1970
D1975
D2710
DIODE_SCHOT 14
DIODE
14
DIODE_SCHOT 14
DIODE_SCHOT 14
DIODE_SCHOT 14
DIODE_SCHOT 15
DIODE_SCHOT 15
DIODE
15
DIODE_SCHOT 15
DIODE_SCHOT 15
DIODE_SCHOT 16
DIODE_SCHOT 16
DIODE_SCHOT 18
DIO_MBRM140T3_SM 18
DIODE_SCHOT_3P2 18
DIODE
25
Q1400
Q1401
Q1430
Q1501
Q1502
TRA_RLA130 14
TRA_IRF7811W 14
TRA_FDG6324L 14
TRA_RLA130 15
TRA_IRF7811W 15
Q1533
Q1535
Q1551
Q1552
Q1580
Q1585
Q1590
Q1601
Q1602
Q1640
Q1651
TRA_2N7002 15
TRA_SI3443DV 15
TRA_RLA130 15
TRA_IRF7811W 15
TRA_SI3443DV 15
TRA_SI3443DV 15
TRA_SI3443DV 15
TRA_RLA130 16
TRA_IRF7805 16
TRA_2N7002 16
TRA_RLA130 16
R1382
R1383
R1384
R1385
R1386
R1387
R1390
R1391
R1392
R1395
R1396
R1401
R1402
R1410
R1415
R1416
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
13
13
13
13
13
13
13
13
13
13
13
14
14
14
14
14
C6839
C6900
C6901
C6910
C6911
C6920
CAP
CAP
CAP
CAP
CAP
CAP
55
56
56
56
56
56
D3354
D3900
D3901
D4610
D5800
D5823
ZENER_MMBZ15VDLT1 30
DIODE_3P_C 36
DIODE_SCHOT 36
DIODE_SCHOT 37
DIODE_SCHOT 45
DIODE_SCHOT 45
Q1652
Q1680
Q1685
Q1740
Q1780
Q1950
TRA_IRF7805 16
TRA_SI6467BDQ 16
TRA_SI3446DV 16
TRA_2N7002DW 17
TRA_SI6467BDQ 17
TRA_2N7002DW 18
R1420
R1421
R1422
R1425
R1427
R1430
RES
RES
RES
RES
RES
RES
14
14
14
14
14
14
47
47
47
47
47
47
47
47
47
47
47
C6921
C6950
C6951
C6952
C6953
C6954
C6955
C6999
C7010
C7011
C7013
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
56
56
56
56
56
56
56
56
57
57
57
Q1960
Q1965
Q2470
Q2480
Q2481
TRA_2N7002 18
TRA_NDS9407 18
TRA_2N7002DW 22
TRA_2N7002DW 22
TRA_2N7002DW 22
Q2600
Q2601
Q2680
Q2900
Q2910
Q2940
TRA_2N3906 24
TRA_2N7002 24
TRA_2N7002DW 24
TRA_2N7002DW 26
TRA_2N7002DW 26
TRA_2N7002DW 26
R1450
R1451
R1452
R1453
R1461
R1501
R1502
R1503
R1504
R1505
R1510
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
14
14
14
14
14
15
15
15
15
15
15
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
47
47
47
47
47
47
47
47
47
47
47
47
47
47
48
48
48
48
49
49
49
49
C7014
C7040
C7041
C7042
C7050
C7051
C7060
C7061
C7062
C7063
C7064
C7065
C7066
C7067
C7070
C7079
C7100
C7101
C7102
C7400
C7401
C7402
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
58
58
58
61
61
61
D7010 DIODE_SCHOT 57
D9090 ZENER
70
DP1390 DPAK3P
13
DP1620 DPAK3P
16
DP1960 DPAK3P
18
DP2680 DPAK3P
24
DP6590 DPAK3P
52
DP9010 DIODE_DUAL_6P 70
F1390 FUSE
13
F1395 FUSE
13
F1965 FUSE
18
F7010 FUSE
57
F9020 FUSE
70
FL7040 FILTER_LC 57
FL7041 FILTER_LC 57
FL7042 FILTER_LC 57
FL9010 FILTER_4P 70
FL9011 FILTER_4P 70
FL9020 FILTER_4P 70
FL9021 FILTER_4P 70
G6500 OSC
52
J1250 CON_M8RT_S_SM 12
J2690 CON_M16ST_D_SMA 24
J3300 CON_2RTSM_125 30
R1511
R1512
R1530
R1531
R1532
R1533
R1535
R1551
R1552
R1553
R1554
R1555
R1560
R1561
R1562
R1601
R1602
R1620
R1621
R1630
R1631
R1632
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
16
16
16
16
16
16
16
C6204
C6210
C6211
C6212
C6213
C6214
C6215
C6216
C6217
C6218
C6219
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
49
49
49
49
49
49
49
49
49
49
49
C7403
C7404
C7405
C7406
C7407
C7408
C7410
C7411
C7450
C7451
C7490
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
TRA_2N7002DW 26
TRA_2N7002 26
TRA_2N3904 27
TRA_2N3904 27
TRA_2N3904 27
TRA_2N3904 27
TRA_2N7002DW 28
TRA_HAT2168H 36
TRA_HAT2160H 36
TRA_HAT2160H 36
TRA_2N7002DW 36
TRA_SI7860DP 45
TRA_SI7892DP 45
TRA_2N7002DW 45
TRA_SI3446DV 46
TRA_SI3443DV 56
TRA_2N7002 56
TRA_FDG6324L 56
TRA_2N7002DW 57
TRA_2N7002DW 57
TRA_TP0610 57
TRA_2N7002DW 57
TRA_DUAL_MMDT3904 57
TRA_TP0610 57
TRA_2N7002DW 65 67
TRA_2N7002DW 66
TRA_SI6467BDQ 67
RES
8
RES
8
RES
8
RES
8
RES
8
RES
8
R1633
R1634
R1640
R1641
R1651
R1652
R1670
R1671
R1680
R1720
R1722
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
16
16
16
16
16
16
16
16
16
17
17
43
43
43
43
43
43
44
44
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
45
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
C6220
C6221
C6241
C6245
C6250
C6251
C6252
C6253
C6254
C6260
C6261
C6262
C6263
C6264
C6265
C6266
C6267
C6268
C6269
C6270
C6271
C6291
C6295
C6300
C6301
C6302
C6303
C6304
C6310
C6311
C6312
C6313
C6314
C6315
C6316
C6317
C6318
C6319
C6320
C6321
C6341
C6345
C6350
C6351
C6352
C6353
C6354
C6360
C6361
C6362
C6363
C6364
C6365
C6366
C6368
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
49
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
C7491
C7500
C8166
C8450
C8451
C8452
C8453
C8454
C8455
C8456
C8459
C8500
C8501
C8510
C8520
C8521
C8530
C8531
C8580
C8590
C8592
C8594
C8596
C8600
C8601
C8602
C8603
C8620
C8900
C8901
C8903
C8904
C8905
C8906
C8907
C8908
C8909
C8911
C8913
C8914
C8915
C8917
C8918
C8919
C8920
C8921
C9010
C9011
C9012
C9013
C9014
C9015
C9016
C9017
C9018
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
46
46
46
46
46
46
46
46
46
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
C6369
C6370
C6371
C6391
C6395
C6400
C6401
C6402
C6403
C6404
C6405
C6410
C6411
C6421
C6500
C6501
C6510
C6511
C6530
C6531
C6532
C6600
C6601
C6605
C6606
C6607
C6610
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
50
50
50
50
50
51
51
51
51
51
51
51
51
51
52
52
52
52
52
52
52
53
53
53
53
53
53
CAP
CAP
CAP
CAP
CAP
CAP
47
47
47
47
47
47
C6611
C6615
C6616
C6617
C6620
C6621
CAP
CAP
CAP
CAP
CAP
CAP
C6031 CAP
47
C6622 CAP
C1200
C1210
C1220
C1250
C1252
CAP
CAP
CAP
CAP
CAP
12
12
12
12
12
C1992
C1993
C1994
C1995
C2101
C2102
C2103
CAP
CAP
CAP
CAP
CAP
CAP
CAP
18
18
18
18
19
19
19
C3574
C3575
C3576
C3577
C3578
C3579
C3580
CAP
CAP
CAP
CAP
CAP
CAP
CAP
32
32
32
32
32
32
32
C4773
C4774
C4775
C4776
C4777
C4778
C4779
CAP
CAP
CAP
CAP
CAP
CAP
CAP
38
38
38
38
38
38
38
C6032
C6033
C6040
C6041
C6042
C6043
C6044
CAP
CAP
CAP
CAP
CAP
CAP
CAP
47
47
47
47
47
47
47
C6625
C6626
C6720
C6721
C6722
C6723
C6724
CAP
CAP
CAP
CAP
CAP
CAP
CAP
53
53
54
54
54
54
54
C1301
C1302
C1303
C1305
C1306
C1307
CAP
CAP
CAP
CAP
CAP
CAP
13
13
13
13
13
13
C2104
C2105
C2106
C2107
C2109
C2120
CAP
CAP
CAP
CAP
CAP
CAP
19
19
19
19
19
19
C3581
C3582
C3583
C3584
C3585
C3586
CAP
CAP
CAP
CAP
CAP
CAP
32
32
32
32
32
32
C4780
C4781
C4782
C4783
C4784
C4785
CAP
CAP
CAP
CAP
CAP
CAP
38
38
38
38
38
38
C6045
C6046
C6047
C6048
C6049
C6050
CAP
CAP
CAP
CAP
CAP
CAP
47
47
47
47
47
47
C6725
C6726
C6727
C6728
C6729
C6740
CAP
CAP
CAP
CAP
CAP
CAP
C1308
C1309
C1310
C1311
C1312
C1313
C1314
C1315
C1316
C1317
C1319
C1320
C1321
C1322
C1323
C1324
CAP
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
C2121
C2122
C2123
C2124
C2125
C2126
C2127
C2128
C2129
C2130
C2131
C2132
C2133
C2134
C2135
C2136
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
C3587
C3588
C3589
C3590
C3599
C3600
C3670
C3671
C3672
C3673
C3674
C3675
C3676
C3677
C3678
C3679
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
32
32
32
32
32
33
33
33
33
33
33
33
33
33
33
33
C4786
C4787
C4788
C4789
C4790
C4791
C4792
C4793
C4794
C4795
C4796
C4797
C5001
C5008
C5009
C5010
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
38
38
38
38
38
38
38
38
38
38
38
38
40
40
40
40
C6051
C6052
C6053
C6054
C6055
C6056
C6057
C6058
C6059
C6060
C6061
C6062
C6063
C6064
C6065
C6066
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
C6760
C6762
C6764
C6766
C6800
C6802
C6804
C6830
C6831
C6832
C6833
C6834
C6835
C6836
C6837
C6838
C1325
C1326
C1327
C1350
C1352
C1361
CAP
CAP
CAP
CAP
CAP
CAP
13
13
13
13
13
13
C2137
C2138
C2139
C2140
C2141
C2142
CAP
CAP
CAP
CAP
CAP
CAP
19
19
19
19
19
19
C3680
C3681
C3682
C3683
C3684
C3685
CAP
CAP
CAP
CAP
CAP
CAP
33
33
33
33
33
33
C5011
C5012
C5013
C5014
C5015
C5016
CAP
CAP
CAP
CAP
CAP
CAP
40
40
40
40
40
40
C6067
C6068
C6069
C6070
C6071
C6072
CAP
CAP
CAP
CAP
CAP
CAP
47
47
47
47
47
47
C1370
C1371
C1380
C1384
C1386
C1392
C1400
C1401
C1402
C1403
C1404
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
13
13
13
13
13
13
14
14
14
14
14
C2143
C2144
C2146
C2147
C2148
C2149
C2150
C2151
C2152
C2153
C2154
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
19
19
19
19
19
19
19
19
19
19
19
C3686
C3687
C3688
C3689
C3690
C3691
C3692
C3693
C3694
C3695
C3698
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
33
33
33
33
33
33
33
33
33
33
33
C5017
C5018
C5019
C5020
C5021
C5022
C5023
C5201
C5208
C5209
C5210
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
40
40
40
40
40
40
40
41
41
41
41
C6073
C6074
C6075
C6076
C6077
C6078
C6079
C6080
C6081
C6082
C6083
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
C1405
C1406
C1407
C1408
C1410
C1411
C1412
C1420
C1421
C1425
C1426
C1427
C1450
C1451
C1452
C1453
C1460
C1461
C1501
C1502
C1503
C1504
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
15
15
15
15
C2155
C2156
C2157
C2158
C2159
C2160
C2161
C2162
C2163
C2164
C2165
C2166
C2167
C2168
C2169
C2170
C2171
C2172
C2173
C2174
C2175
C2176
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
C3699
C3800
C3801
C3802
C3803
C3804
C3805
C3806
C3807
C3808
C3809
C3810
C3811
C3812
C3813
C3814
C3815
C3816
C3817
C3818
C3819
C3820
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
33
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
C5211
C5212
C5213
C5214
C5215
C5216
C5217
C5218
C5219
C5220
C5221
C5222
C5223
C5649
C5650
C5651
C5652
C5653
C5654
C5655
C5656
C5657
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
41
41
41
41
41
41
41
41
41
41
41
41
41
43
43
43
43
43
43
43
43
43
C6084
C6085
C6086
C6087
C6088
C6089
C6090
C6091
C6092
C6093
C6094
C6095
C6096
C6097
C6190
C6191
C6192
C6193
C6200
C6201
C6202
C6203
C1510
C1511
C1512
C1513
C1514
C1515
C1520
C1521
C1522
C1523
C1530
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
15
15
15
15
15
15
15
15
15
15
15
C2177
C2178
C2179
C2180
C2181
C2182
C2183
C2184
C2185
C2186
C2187
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
19
19
19
19
19
19
19
19
19
19
19
C3821
C3822
C3823
C3830
C3831
C3832
C3833
C3834
C3835
C3836
C3837
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
35
35
35
35
35
35
35
35
35
35
35
C5658
C5659
C5660
C5661
C5662
C5663
C5664
C5665
C5666
C5667
C5668
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
43
43
43
43
43
43
43
43
43
43
43
C1531
C1532
C1533
C1536
C1551
C1552
C1553
C1554
C1560
C1561
C1562
C1563
C1564
C1565
C1570
C1571
C1572
C1573
C1580
C1581
C1582
C1585
C1586
C1587
C1590
C1591
C1592
C1601
C1602
C1603
C1604
C1605
C1620
C1621
C1630
C1631
C1632
C1640
C1651
C1652
C1653
C1655
C1670
C1671
C1680
C1681
C1682
C1685
C1686
C1700
C1701
C1710
C1711
C1720
C1721
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP
CAP
CAP_P
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP_P
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
17
17
17
17
17
17
C2188
C2189
C2190
C2191
C2192
C2193
C2194
C2195
C2196
C2197
C2199
C2200
C2201
C2205
C2206
C2207
C2210
C2215
C2216
C2250
C2254
C2259
C2390
C2391
C2392
C2410
C2411
C2500
C2501
C2502
C2700
C2701
C2702
C2705
C2710
C2720
C2740
C2741
C2750
C2751
C3000
C3001
C3002
C3003
C3100
C3101
C3104
C3105
C3130
C3131
C3204
C3205
C3206
C3220
C3300
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
19
19
19
19
19
19
19
19
19
19
19
20
20
20
20
20
20
20
20
20
20
20
21
21
21
22
22
23
23
23
25
25
25
25
25
25
25
25
25
25
27
27
27
27
28
28
28
28
28
28
29
29
29
29
30
C3838
C3839
C3840
C3841
C3842
C3843
C3844
C3845
C3846
C3847
C3848
C3849
C3850
C3851
C3852
C3853
C3854
C3855
C3856
C3857
C3858
C3859
C3860
C3861
C3900
C3901
C3902
C3903
C3910
C3911
C3912
C3913
C3914
C3915
C3916
C3917
C3918
C3937
C3938
C3939
C3940
C3941
C3942
C3943
C3944
C3945
C3946
C3947
C3948
C3949
C3950
C3951
C3960
C3962
C3963
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP_P
CAP_P
CAP_P
CAP_P
CAP_P
CAP_P
CAP_P
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
C5669
C5670
C5671
C5672
C5673
C5674
C5731
C5732
C5801
C5802
C5803
C5804
C5805
C5810
C5811
C5820
C5822
C5823
C5824
C5825
C5830
C5831
C5882
C5885
C5900
C5901
C5902
C5903
C5904
C5905
C5906
C5907
C5908
C5909
C5910
C5911
C5912
C5913
C5914
C5915
C5916
C5917
C5918
C5919
C5920
C5921
C5922
C5923
C5924
C5950
C5951
C5952
C5953
C5954
C5955
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
C1722
C1730
C1780
C1781
C1900
C1901
C1902
C1903
C1908
C1910
C1911
C1912
C1913
C1920
C1921
C1922
C1923
C1924
C1925
C1930
C1931
C1940
C1941
C1942
C1943
C1950
C1965
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
17
17
17
17
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
C3320
C3350
C3352
C3353
C3354
C3355
C3400
C3430
C3450
C3460
C3550
C3551
C3552
C3553
C3554
C3555
C3556
C3557
C3558
C3559
C3560
C3561
C3562
C3563
C3564
C3565
C3566
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP_P
CAP_P
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
30
30
30
30
30
30
31
31
31
31
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
C3964
C3990
C4600
C4610
C4620
C4625
C4626
C4627
C4705
C4706
C4749
C4750
C4751
C4752
C4753
C4754
C4755
C4756
C4757
C4758
C4759
C4760
C4761
C4762
C4763
C4764
C4765
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
36
36
37
37
37
37
37
37
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
C5956
C5957
C5958
C5959
C5990
C5991
C5992
C5993
C5994
C6000
C6001
C6002
C6003
C6004
C6005
C6006
C6010
C6011
C6012
C6013
C6014
C6015
C6020
C6021
C6022
C6023
C6024
C1970
C1971
C1980
C1981
C1982
C1990
CAP
CAP_P
CAP
CAP
CAP
CAP
18
18
18
18
18
18
C3567
C3568
C3569
C3570
C3571
C3572
CAP
CAP
CAP
CAP
CAP
CAP
32
32
32
32
32
32
C4766
C4767
C4768
C4769
C4770
C4771
CAP
CAP
CAP
CAP
CAP
CAP
38
38
38
38
38
38
C6025
C6026
C6027
C6028
C6029
C6030
18
C3573 CAP
32
C4772 CAP
38
C1991 CAP
61
61
61
61
61
61
61
61
61
61
61
J3320
J3350
J3400
J3410
J3420
J3430
J3450
J3460
J3999
J5000
J6900
J6950
J7000
J7060
J7300
J7490
J8200
CON_M16ST_D_SMA 30
CON_M16ST_D_SMA 30
CON_M4RT_S_SM 31
CON_M16ST_D_SMA 31
CON_M3RT_S2MT_SM 31
CON_4RT_WRIB 31
CON_M4RT_S2MT_SM 31
CON_M4RT_S2MT_SM 31
CON_12
36
CON_F400RT_DDR2DIMM_SM1 40 41
CON_F30RT_S2MT_SM 56
CON_4RT_WRIB 56
CON_F30RT_T6MT_TH1 57
CON_F5RT_MINIDIN_TH 57
CON_F80ST_D4MT_SM 60
CON_M80ST_D4MT_SM 61
CON_M50SM_5MM 64
Q2941
Q2948
Q3001
Q3002
Q3003
Q3004
Q3103
Q3900
Q3902
Q3903
Q3940
Q5800
Q5801
Q5884
Q5950
Q6900
Q6901
Q6950
Q7011
Q7014
Q7075
Q7076
Q7080
Q7081
Q8420
Q8580
Q8620
R0820
R0821
R0830
R0831
R0840
R0841
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
61
62
63
65
65
65
65
65
65
65
65
66
66
66
66
66
66
66
66
66
66
66
66
67
67
67
67
67
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
70
70
70
70
70
70
70
70
70
J8250
J8600
J9010
J9020
JA000
L1250
L1251
L1252
L1253
L1254
L1300
L1400
L1501
L1551
L1601
L1651
L1700
L1900
L1970
L1990
L2200
L3130
L3300
L3350
L3354
L3355
L3900
L5800
L5950
L5990
L6000
L6010
L6011
L6020
L6040
L6041
L6043
L6048
L6050
L6095
L6403
L6410
L6500
L6510
L6600
L6610
L6615
L6620
L6625
L6720
L6723
L6726
L6830
L6833
L6836
CON_M50SM_5MM 64
CON_RJ45_10RT_S4MT_TH1 67
CON_F9RT_1394B_S6MT_SMA 70
CON_F6RT_S4MT_TH1 70
CON_M50SM_5MM 74
IND
12
IND
12
IND
12
IND
12
IND
12
IND
13
IND_3P
14
IND
15
IND
15
IND
16
IND
16
IND
17
IND
18
IND
18
IND
18
IND
20
IND
28
IND
30
IND
30
IND
30
IND
30
IND_3P
36
IND_3P
45
IND
46
IND
46
IND
47
IND
47
IND
47
IND
47
IND
47
IND
47
IND
47
IND
47
IND
47
IND
47
IND
51
IND
51
IND
52
IND
52
IND
53
IND
53
IND
53
IND
53
IND
53
IND
54
IND
54
IND
54
IND
55
IND
55
IND
55
R0842
R0843
R0850
R0851
R0950
R0980
R0981
R0982
R0983
R0984
R0985
R0990
R1015
R1018
R1025
R1033
R1110
R1111
R1120
R1130
R1135
R1136
R1137
R1140
R1160
R1161
R1162
R1163
R1164
R1165
R1166
R1167
R1170
R1171
R1172
R1173
R1174
R1175
R1176
R1177
R1185
R1201
R1202
R1203
R1204
R1205
R1206
R1207
R1208
R1209
R1210
R1215
R1216
R1221
R1222
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
8
8
8
8
9
9
9
9
9
9
9
9
10
10
10
10
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
12
12
12
12
12
12
12
12
12
12
12
12
12
12
R1723
R1724
R1730
R1731
R1732
R1733
R1950
R1951
R1952
R1960
R1961
R1963
R1965
R1966
R1990
R1991
R1992
R1993
R1994
R1995
R1996
R1997
R1998
R2101
R2102
R2103
R2104
R2105
R2106
R2107
R2109
R2204
R2205
R2207
R2208
R2209
R2210
R2211
R2212
R2255
R2256
R2300
R2301
R2302
R2303
R2304
R2305
R2306
R2307
R2308
R2309
R2310
R2311
R2340
R2350
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
17
17
17
17
17
17
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
19
19
19
19
19
19
19
19
20
20
20
20
20
20
20
20
20
20
21
21
21
21
21
21
21
21
21
21
21
21
21
21
C9019
C9020
C9021
C9022
C9023
C9024
C9025
C9026
C9050
C9054
C9060
C9064
C9090
C9091
C9092
C9220
C9221
C9250
C9251
C9320
C9321
C9322
C9323
C9324
C9325
C9326
C9327
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
72
72
72
72
73
73
73
73
73
73
73
73
L6900
L6950
L6952
L6953
L6955
L7000
L7001
L7002
L7003
L7004
L7005
L7006
L7010
L7060
L7061
L7062
L7064
L7066
L8510
L8520
L8530
L8900
L8901
L8902
L8906
L8909
L8913
IND
IND
IND
IND
IND
FILTER_4P
FILTER_4P
FILTER_4P
FILTER_4P
FILTER_4P
FILTER_4P
FILTER_4P
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
IND
R1223
R1224
R1225
R1226
R1227
R1228
R1250
R1251
R1252
R1255
R1256
R1300
R1301
R1302
R1303
R1304
R1305
R1317
R1318
R1319
R1320
R1321
R1322
R1323
R1324
R1325
R1328
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
12
12
12
12
12
12
12
12
12
12
12
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
R2352
R2360
R2365
R2367
R2380
R2385
R2387
R2392
R2400
R2401
R2410
R2411
R2451
R2452
R2455
R2460
R2461
R2462
R2463
R2464
R2470
R2471
R2472
R2480
R2481
R2482
R2490
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
21
21
21
21
21
21
21
21
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
53
53
53
53
53
53
C9328
C9329
C9330
C9335
C9336
C9337
CAP
CAP
CAP
CAP
CAP
CAP
73
73
73
73
73
73
R1329
R1330
R1340
R1341
R1342
R1343
RES
RES
RES
RES
RES
RES
13
13
13
13
13
13
R2600
R2601
R2602
R2610
R2680
R2690
RES
RES
RES
RES
RES
RES
24
24
24
24
24
24
53
C9345 CAP
73
L9010 IND
70
L9020 IND
70
L9090 IND
70
L9335 IND
73
PD3100 PHOTODIODE_2P 28
Q1208 TRA_2N7002DW 12
Q1210 TRA_IRF7416 12
R1344 RES
13
R2691 RES
24
56
56
56
56
56
57
57
57
57
57
57
57
57
57
57
57
57
57
66
66
66
69
69
69
69
69
69
114
R2692
R2695
R2696
R2705
R2710
R2715
R2730
RES
RES
RES
RES
RES
RES
RES
24
24
24
25
25
25
25
R4701
R4710
R4810
R4811
R4850
R4851
R4855
RES
RES
RES
RES
RES
RES
RES
38
38
39
39
39
39
39
R6999
R7010
R7011
R7012
R7013
R7014
R7020
RES
RES
RES
RES
RES
RES
RES
56
57
57
57
57
57
57
RP4871
RP4872
RP4873
RP4875
RP4876
RP4877
RP4878
RPAK2P
RPAK4P
RPAK4P
RPAK2P
RPAK2P
RPAK4P
RPAK4P
39
39
39
39
39
39
39
R2740
R2741
R2750
R2751
R2760
R2761
RES
RES
RES
RES
RES
RES
25
25
25
25
25
25
R4856
R4860
R4861
R4865
R4866
R5001
RES
RES
RES
RES
RES
RES
39
39
39
39
39
40
R7021
R7022
R7030
R7031
R7040
R7041
RES
RES
RES
RES
RES
RES
57
57
57
57
57
57
RP5610
RP5611
RP6100
RP6101
RP6102
RP6108
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK2P
43
43
48
48
48
48
R2765
R2766
R2767
R2768
R2770
R2771
R2772
R2773
R2774
R2900
R2901
R2902
R2903
R2910
R2911
R2912
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
25
25
25
25
25
25
25
25
25
26
26
26
26
26
26
26
R5002
R5600
R5605
R5610
R5611
R5612
R5613
R5614
R5615
R5616
R5617
R5618
R5619
R5620
R5700
R5720
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
40
43
43
43
43
43
43
43
43
43
43
43
43
43
44
44
R7042
R7050
R7051
R7070
R7071
R7072
R7073
R7075
R7076
R7077
R7078
R7079
R7080
R7081
R7082
R7083
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
57
RP6109
RP6150
RP6151
RP6152
RP6158
RP6159
RP6707
RP6708
RP6709
RP6710
RP6720
RP6721
RP6722
RP6723
RP6811
RP6812
RPAK2P
RPAK4P
RPAK4P
RPAK4P
RPAK2P
RPAK2P
RPAK2P
RPAK2P
RPAK2P
RPAK2P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK2P
RPAK2P
48
48
48
48
48
48
54
54
54
54
54
54
54
54
55
55
R2913
R2920
R2921
R2922
R2929
R2930
RES
RES
RES
RES
RES
RES
26
26
26
26
26
26
R5721
R5722
R5725
R5726
R5730
R5731
RES
RES
RES
RES
RES
RES
44
44
44
44
44
44
R7150
R7151
R7152
R7205
R7252
R7253
RES
RES
RES
RES
RES
RES
58
58
58
59
59
59
RP6813
RP6821
RP6822
RP6823
RP7250
RP7251
RPAK2P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
55
55
55
55
59
59
R2935
R2936
R2940
R2941
R2943
R2948
R2949
R2951
R2958
R2965
R2966
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
26
26
26
26
26
26
26
26
26
26
26
R5820
R5821
R5822
R5823
R5826
R5827
R5828
R5829
R5830
R5880
R5881
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
45
45
45
45
45
45
45
45
45
45
45
R7254
R7300
R7305
R7400
R7410
R7411
R7412
R7420
R7421
R7422
R7423
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
59
60
60
61
61
61
61
61
61
61
61
RP7410
RP7510
RP8150
RP8151
RP8152
RP8153
RP8154
RP9100
RP9101
RP9210
RP9211
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
61
62
63
63
63
63
63
71
71
72
72
R2967
R2969
R3000
R3001
R3002
R3003
R3004
R3005
R3010
R3011
R3012
R3013
R3020
R3021
R3022
R3023
R3100
R3101
R3102
R3103
R3104
R3105
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
26
26
27
27
27
27
27
27
27
27
27
27
27
27
27
27
28
28
28
28
28
28
R5882
R5883
R5884
R5885
R6103
R6104
R6105
R6106
R6107
R6108
R6109
R6153
R6154
R6155
R6156
R6157
R6158
R6159
R6190
R6191
R6192
R6193
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
45
45
45
45
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
R7424
R7430
R7450
R7500
R7501
R7502
R7503
R7504
R7510
R7511
R7512
R8100
R8151
R8160
R8161
R8162
R8163
R8164
R8165
R8166
R8167
R8200
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
61
61
61
62
62
62
62
62
62
62
62
63
63
63
63
63
63
63
63
63
63
64
RP9212
RP9300
RP9301
RP9310
SH0200
RPAK4P
72
RPAK4P
73
RPAK4P
73
RPAK4P
73
SHLD_3P_EMI 2
R3130
R3131
R3132
R3220
R3300
R3301
R3320
R3321
R3352
R3353
R3355
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
28
28
28
29
30
30
30
30
30
30
30
R6194
R6196
R6197
R6198
R6199
R6240
R6241
R6245
R6246
R6290
R6291
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
48
48
48
48
48
49
49
49
49
49
49
R8201
R8202
R8203
R8210
R8211
R8212
R8255
R8400
R8405
R8410
R8420
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
R3500
R3505
R3506
R3513
R3514
R3550
R3551
R3600
R3601
R3610
R3611
R3620
R3702
R3703
R3704
R3705
R3706
R3707
R3720
R3721
R3722
R3723
R3724
R3725
R3726
R3727
R3728
R3729
R3730
R3731
R3752
R3753
R3756
R3757
R3758
R3759
R3761
R3765
R3766
R3767
R3769
R3771
R3772
R3900
R3901
R3910
R3940
R3941
R3942
R3943
R3944
R3945
R3946
R3950
R3951
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
32
32
32
32
32
32
32
33
33
33
33
33
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
36
36
36
36
36
36
36
36
36
36
36
36
R6295
R6296
R6340
R6341
R6345
R6346
R6390
R6391
R6395
R6396
R6400
R6420
R6421
R6422
R6423
R6450
R6451
R6452
R6453
R6454
R6455
R6456
R6457
R6458
R6459
R6460
R6461
R6462
R6463
R6470
R6490
R6498
R6499
R6500
R6501
R6502
R6503
R6510
R6511
R6512
R6513
R6514
R6530
R6640
R6641
R6642
R6650
R6651
R6660
R6661
R6662
R6670
R6671
R6672
R6680
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
49
49
50
50
50
50
50
50
50
50
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
51
52
52
52
52
52
52
52
52
52
52
53
53
53
53
53
53
53
53
53
53
53
53
R8421
R8501
R8509
R8560
R8561
R8562
R8569
R8580
R8590
R8591
R8592
R8593
R8594
R8595
R8596
R8597
R8620
R8621
R8800
R8902
R8903
R8904
R8905
R8906
R8909
R8911
R8912
R8914
R8915
R8916
R8921
R8931
R8933
R8935
R8998
R8999
R9011
R9050
R9051
R9052
R9053
R9054
R9060
R9061
R9062
R9063
R9064
R9070
R9090
R9099
R9100
R9101
R9102
R9103
R9200
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
R3960
R3961
R3962
R3963
R3964
R3965
R3970
R3971
R3972
R3973
R3974
R3975
R3976
R3977
R3980
R3981
R3982
R3983
R3984
R3985
R3986
R3987
R3988
R3989
R3990
R3998
R3999
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
R6681
R6690
R6730
R6731
R6732
R6733
R6734
R6740
R6741
R6742
R6752
R6754
R6760
R6761
R6762
R6763
R6764
R6765
R6766
R6767
R6800
R6801
R6802
R6803
R6804
R6805
R6880
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
53
53
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
55
55
55
55
55
55
55
R9220 RES
R9221 RES
R9250 RES
R9300 RES
R9301 RES
R9302 RES
R9303 RES
R9304 RES
R9305 RES
R9306 RES
R9307 RES
R9310 RES
R9335 RES
R9338 RES
R9339 RES
R9340 RES
R9341 RES
R9345 RES
RP0990 RPAK4P
RP1150 RPAK4P
RP1151 RPAK4P
RP2450 RPAK4P
RP3510 RPAK4P
RP3511 RPAK4P
RP3512 RPAK4P
RP3513 RPAK4P
RP3514 RPAK4P
R4600
R4610
R4611
R4620
R4621
R4625
RES
RES
RES
RES
RES
RES
37
37
37
37
37
37
R6881
R6882
R6900
R6901
R6910
R6911
RES
RES
RES
RES
RES
RES
55
55
56
56
56
56
RP3990
RP4800
RP4801
RP4802
RP4803
RP4804
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
RPAK4P
36
39
39
39
39
39
R4700 RES
38
R6950 RES
56
RP4870 RPAK2P
39
U1200
U1220
U1250
U1300
U1350
U1370
U1380
U1400
U1420
U1450
U1460
COMPARATOR_LMC7211
COMPARATOR_LMC7211
INA138
12
MAX1772
13
COMPARATOR_LMC7211
AMP_MAX4172 13
OPAMP_LMC7111 13
LTC1625
14
COMPARATOR_LMC7211
VREG_LP2951 14
VREG_LP2951 14
12
12
64
64
64
64
64
64
64
65
65
65
65
U1500
U1600
U1700
U1970
U1980
U1990
U2100
U2200
U2250
U2390
U2391
U2392
U2500
U2700
U3000
U3100
U3130
LTC3707
15
MAX1715
16
LTC3412
17
VREG_LM2594 18
VREG_MM1572FN 18
LTC3411
18
I2
19 22 32 38 43 59 63 65 68 72
LTC3412
20
VREG_LT1962 20
SN74AUC1G74 21
SN74AUC1G74 21
SN74AUC1G74 21
CLK_DR_CDCVF2505 23
M30280F8 25
ADT7467
27
OPAMP_MAX4236EUTT 28
MM3120
28
65
66
66
66
66
66
66
66
66
66
66
66
66
66
66
66
67
67
68
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
69
70
70
70
70
70
70
70
70
70
70
70
70
70
70
71
71
71
71
72
U3220 KXM52
29
U3600 A8
33 34 35
U3900 MAX1717
36
U3990 PI3B3257 36
U4600 FAN2558
37
U5700 M11P
44 46 47 48 51 53
U5800 LTC1778
45
U6200 SDRAM_DDR_K4D553235F 49
U6400 VREG_MM1571J 51
U6510 CLK_GEN_CY25811 52
U6530 MAX8860
52
U6700 SIL1178CS48 54
U6800 SIL1178CS48 55
U6953 NC7S32
56
U7050 741G32
57
U7051 741G32
57
U7070 COMPARATOR_LMC7211 57
U7100 FEPR_1MX8 58
U7400 PCI1510GGU 61
U7450 PWR_CNTRL_TPS2211 61
U7500 UPD720101_FBGA_SPLIT 62 73
U8500 BCM5462
18 66 69
XW1012 SHORT
10
XW1013 SHORT
10
XW1015 SHORT
10
XW1017 SHORT
10
XW1018 SHORT
10
XW1019 SHORT
10
XW1025 SHORT
10
XW1033 SHORT
10
XW1050 SHORT
10
XW1251 SHORT
12
XW1252 SHORT
12
XW1300 SHORT
13
XW1400 SHORT
14
XW1500 SHORT
15
XW1600 SHORT
16
XW1700 SHORT
17
XW1990 SHORT
18
XW2200 SHORT
20
XW2700 SHORT
25
XW2970 SHORT
26
XW3900 SHORT
36
XW3901 SHORT
36
XW3910 SHORT
36
XW3911 SHORT
36
XW5800 SHORT
45
XW6590 SHORT
52
XW6591 SHORT
52
XW6592 SHORT
52
XW6593 SHORT
52
XW7060 SHORT
57
72
72
72
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
9
11
11
22
32
32
32
32
32
XW7061 SHORT
XW9070 SHORT
XW9071 SHORT
XWA000 SHORT
XWA001 SHORT
XWA033 SHORT
XWA050 SHORT
XWA051 SHORT
Y2410 CRYSTAL
Y2740 CRYSTAL
Y2750 CRYSTAL
Y8500 CRYSTAL
Y8920 CRYSTAL
Y9220 CRYSTAL
Y9345 CRYSTAL
ZT0200 HOLE_VIA
ZT0201 HOLE_VIA
ZT0202 HOLE_VIA
ZT0203 HOLE_VIA
ZT0210 HOLE_VIA
ZT0211 HOLE_VIA
ZT0212 HOLE_VIA
ZT0221 HOLE_VIA
ZT0222 HOLE_VIA
ZT0223 HOLE_VIA
13
14
57
70
70
74
74
74
74
74
22
25
25
66
69
72
73
2
2
2
2
2
2
2
2
2
2
115

PowerBookG415High Res

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PowerBookG415High Res

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8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

DDR2 SO-DIMM Slot B

DIMENSIONS ARE IN MILLIMETERS

Apple Computer Inc.

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

LBL,P/N LABEL,PCB,28MM X 6MM

LBL,P/N LABEL,PCB,28MM X 6MM

THIRD ANGLE PROJECTION

CHASSIS GND CONNECTIONS

"1MM" area defined around BGAs to

"BGA_P2MM" rule ensures these critical

Layer-specific rules for 60-ohm single-ended impedance

Layer-specific rules for 100-ohm differential impedance

Layer-specific rules for 90-ohm differential impedance

Layer-specific rules for 50-ohm single-ended impedance

BOARD STACK-UP AND CONSTRUCTION

SEE BOARD FILE FOR DETAILED INFORMATION

Layer-specific rules for 110-ohm differential impedance

Portable-specific Override Rules

SIGNAL (1/2 OZ + COPPER PLATING)

GROUND (1/2 OZ)

SIGNAL (1/2 OZ)

SIGNAL (1/2 OZ)

GROUND (1/2 OZ)

CUT POWER PLANE (1 OZ)

CUT POWER PLANE (1 OZ)

GROUND (1/2 OZ)

SIGNAL (1/2 OZ)

SIGNAL (1/2 OZ)

GROUND (1/2 OZ)

SIGNAL (1/2 OZ + COPPER PLATING)

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

IC,GDDR SDRAM,2MX32X4,300MHZ, LF FBGA144

IC,GDDR SDRAM,2MX32X4,300MHZ, LF FBGA144

v1.4 is alt to v1.3

APPLE COMPUTER INC.

DDR2 SDRAM DIMM 1

DDR2 SDRAM DIMM 0

System Block Diagram

NOTICE OF PROPRIETARY PROPERTY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE COMPUTER INC.

POWER SYSTEM ARCHITECTURE

NO AC: BATTERY VOLTAGE

TURNS ON OUTPUT @ 2.4V

TURNS CONTROL TO RUN/SS

INTERNAL ZENER CLAMP TO 6V

14V CHARGES BACKUP BATTERY

HOLDS BOTH RUN/SS AT GND

& BOOST OUTPUT

WHEN ONLY BATTERY IS CONNECTED

AND PREVENTS +PBUS AND +24V_PBUS FROM DROPPING BELOW 6V

WHEN ONLY BATTERY IS CONNECTED

Power Block Diagram

NOTICE OF PROPRIETARY PROPERTY