Faculty of Electrical and Electronic Engineering MEE 10701 : Experiment 02 Inverter Schematic

Number of Pages Edition Revision Number Effective Date Amendment Date

1 1 1

COURSE DESCRIPTION SUBJECT TOPIC : MEE10701 : Inverter Schematic And Simulation

EXPERIMENT A : NMOS Transistor Layout 1.0 AIM 1.1

To draw a CMOS inverter circuit using Tanner Tools and simulate it.

2.0

OBJECTIVES 2.1 To understand the basic command of Tanner Tools. 2.2 To use S-Edit to draw a schematic diagram of CMOS inverter. 2.3 To do a simulation using T-Spice to verify the output of an inverter. THEORY 3.1 S-Edit (Schematic Entry Tool) & T-SPICE (Analog Simulation Tool)

3.0

S-edit is a schematic entry tool that is used to document circuits that can be driven forward into a layout of an integrated circuit. It also provides the ability to perform SPICE simulations of the circuits using a simulation engine called TSPICE. T-SPICE can be setup and invoked from within S-edit. The user interface provided by S-Edit is similar to that of many other CAD and schematic design software packages. There are three important sections of the S-Edit User Interface: toolbar sidebar drawing area 4.0 EQUIPMENT 4.1 Computer with Tanner Tools installed. 5.0 PROCEDURE 5.1 Setting the Directory Structure & Libraries 1. Create a directory for all of the Tanner EDA projects. Create a directory structure named ..\Tanner_workfile

Faculty of Electrical and Electronic Engineering MEE 10701 : Experiment 02 Inverter Schematic

Number of Pages Edition Revision Number Effective Date Amendment Date

2 1 1

2. The name of the directory can be anything, but the exact location of that directory must be known. 5.2 Starting a New Design & Setting the Libraries 1. Start S-Edit Start All Programs Tanner EDA Tanner Tools v13 S-Edit v13.0 2. Start a New Design Using the pull down menus, create a new design: File New New Design A dialog will appear asking for a design name and location. When the name is given, S-edit will create a folder of that name in the directory that is provided that will contain all of the design files. Give a descriptive name to the Design name that represents each simulation that will be running later. For this experiment, enter the name first_simulation and browse to ..\Tanner_workfile directory. Then click OK

3. Create a new Cell A cell is a design element. A cell can contain multiple views such as schematics and symbols. Cells can be instantiated in other cells. When performing a simulation, a typically cell is always call the cell TOP. When testing a circuit, for example an inverter, the inverter will have its own cell that contains a schematic of the devices and a symbol. The inverter cell is instantiated in the TOP cell that contains ideal elements such as voltage sources and probes that are only used for simulation (will be done in Experiment B). This will allow cells separation that is actually going to be implemented on the die versus cells that are only used for simulation. Using the pull down menus, create a new cell view: Cell New View: Enter the cell name TOP. Ensure the design name is first_simulation and click OK. The interface and view names can be leaved as view0. Click save button to save the file.

Faculty of Electrical and Electronic Engineering MEE 10701 : Experiment 02 Inverter Schematic

Number of Pages Edition Revision Number Effective Date Amendment Date

3 1 1

A blank schematic page will appear.

4. Enter the symbol libraries: First, include a library which contains the symbols for all basic circuit elements such as resistors, NMOS, capacitors, etc On the left side of the S-Edit screen under a Libraries window, click on the Add button. Browse to ..\Libraries\All\All.tanner (This is the sub-directory where the tanner is installed) and click OK

Faculty of Electrical and Electronic Engineering MEE 10701 : Experiment 02 Inverter Schematic

Number of Pages Edition Revision Number Effective Date Amendment Date

4 1 1

A set of libraries will appear:

5. Setup the SPICE Models for the Generic_025 kit. The libraries that are just added have symbols for NMOS and PMOS transistors. However, all non-linear components such as MOS transistors require a model to describe their behaviour. If an NMOS symbol is entered in the schematic, SPICE do not know what to do since each NMOS transistor fabricated in a different technology behave differently. In this experiment, a transistor technology called Generic_025 will be used, which represents a standard, 0.25um CMOS process. Hence, setup the SPICE models for this process in S-edit. Once this is done, when an NMOS or PMOS transistor symbol is entered, then that symbol will be associated with the 0.25um model. Using the pull down menus, setup the SPICE models: Setup SPICE Simulation

In the dialog that appears, highlight General on the left. On the right, click in the Library Files field. This is where to specify any SPICE models that will be used in the simulations. Browse & select ..\Users\admin\Documents\TannerEDA\TannerTools v13.0\Libraries\Models\Generic_025.lib. Add tt at the end to enable the simulation.

Faculty of Electrical and Electronic Engineering MEE 10701 : Experiment 02 Inverter Schematic

Number of Pages Edition Revision Number Effective Date Amendment Date

5 1 1

On the right, click in the SPICE File Name field. This is where to specify the name and location of the SPICE Netlist output. Browse to the design directory (..\Tanner_workfile\first_simulation) and enter the filename TOP.sp. On the right, click in the Simulations Results File Name field. This is where the results of the simulation will be written. This file is what the waveform viewer will look for when to plot the results. Browse to the design directory (..\Tanner_workfile\first_simulation) and enter the filename TOP.out. Before exiting this window, select an analysis type. The details of the analysis will be setup later, but for now, just check the DC Sweep Analysis and click OK to close the setup window. 5.3 Enter the Schematic to simulate an Inverter

1. Draw the circuit as shown in Figure 1. In this experiment, a CMOS inverter will be created and its transient response will be simulated.

Figure 1: An inverter

Faculty of Electrical and Electronic Engineering MEE 10701 : Experiment 02 Inverter Schematic

Number of Pages Edition Revision Number Effective Date Amendment Date

6 1 1

2. Enter the NMOS transistor On the left, click on Devices in the upper window. This will display all of the symbols available in this group. All of the components that can be implemented on a CMOS integrated circuit can be seen here. On the bottom left window, click once on NMOS. The symbol of the NMOS transistor will be shown in the symbol viewer window at the bottom. To place the NMOS, click on the Instance button. Two things will happen when this button is clicked. First, a dialog will appear that will allow to setup the parameters for the NMOS. Second, the symbol will attach to the mouse. Place the NMOS in the schematic, the properties will be setup later. This is an easier way to enter the device. Click in the schematic window to drop an instance of the NMOS. Hit the Esc button to end the insert-mode. The NMOS is now in the schematic.

A note on zooming: - [Home] = zoom fit - the scroll wheel also zooms in/out

- [-] = zoom out - [=] = zoom in

To setup the NMOS, click on the NMOS symbol. The properties of the device will be seen on the left. Setup the following: Model : enter NMOS. This model is found in the Generic_025 library that is added before. Name: NMOS_1. The SPICE designation for MOS transistors is to have the name start with an M. S-edit automatically appends an M to the name; the final name will be MNMOS_1 in the TOP.sp file. But it is good practice to name all MOS transistors with Ms.

Faculty of Electrical and Electronic Engineering MEE 10701 : Experiment 02 Inverter Schematic

Number of Pages Edition Revision Number Effective Date Amendment Date

7 1 1

W: Width - Set to 2.5u. This is the default. L: Length - Set to 0.25u. This is the default. Do the same thing for PMOS transistor. 3. Enter a voltage source symbols for VDD and also for the input voltage (Vin) Enter a SPICE_Elements: VoltageSource. Position the symbol in the schematic drawing window. This is a generic voltage source symbol that can be configured as a DC, TRAN, PWL, etc. in its properties dialog. Click on the voltage source symbol and enter the following: MasterInterface: DC (this is the default but this can be changed to something else.) Name: VDD (it is a good idea to use descriptive names) V: This is where to set the DC voltage (i.e., 4V, 5V etc.)

A note on zooming: Hold down ALT-M to move a component. While holding these buttons down, click and drag the components. To rotate, click on the device and click the [r] button. Do the same for the input voltage, but choose Pulse at the MasterInterface and set the properties as follows: Name = Vin MasterInterface = Pulse Period = 200ns PulseWidth = 95ns VHigh = 5v VLow = 0v RiseTime = 5ns FallTime = 5ns

Faculty of Electrical and Electronic Engineering MEE 10701 : Experiment 02 Inverter Schematic

Number of Pages Edition Revision Number Effective Date Amendment Date

8 1 1

4. Enter Grounds Using the same process as above, enter three grounds from Misc: Gnd

5. Enter Wires Wires can be entered by clicking on the wire icon at the top. Enter wires by clicking on a symbol node and then dragging. Enter corners by clicking once where to turn the wire.

Faculty of Electrical and Electronic Engineering MEE 10701 : Experiment 02 Inverter Schematic

Number of Pages Edition Revision Number Effective Date Amendment Date

9 1 1

Net Label icon at the top can be used to label nets. Labeling a net/wire is a good practice to easily identify a node. This will be useful when plotting the graph. Complete the schematic drawing as shown in Figure 1 and save it before simulating it. For the schematic, label the wire for Vin and Vout. 6. Export a SPICE Netlist Exporting a SPICE Netlist is a good idea in order to verify that the circuit is entered in the schematic correctly. Also, this Netlist will be used later when performing a Layout versus Schematic (LVS) check. Export a Netlist at the Inverter schematic cell level so that a Netlist of just the inverter exists for LVS. When the simulation of this inverter is conducted, a TOP level schematic that will have a Netlist containing ideal voltage sources will be created. This Netlist cannot be used for LVS since it contains components that will not be fabricated. With the schematic open, use the pull down menus to perform : File Export Export SPICE.

Browse to the design directory and give the file name TOP.spc. Then click Export. Open the file TOP.spc with any text editor. Analyse this SPICE netlist, and state what can be deduced from this file. Print this file and submit in the laboratory report.

Faculty of Electrical and Electronic Engineering MEE 10701 : Experiment 02 Inverter Schematic

Number of Pages Edition Revision Number Effective Date Amendment Date

10 1 1

7. Plotting Waveform. There are 2 ways to put the marker on what to be plotted/to be observed. Choose either one. First way is by placing PrintVoltage from SPICE_Commands as shown.

Faculty of Electrical and Electronic Engineering MEE 10701 : Experiment 02 Inverter Schematic

Number of Pages Edition Revision Number Effective Date Amendment Date

11 1 1

Another way is by adding SPICE command, under Pull down menu: Setup SPICE Simulation Additional SPICE Commands.

In the second method, the SPICE command to be included will be typed in. In this example, it is to plot (.print) the transient analysis (TRAN) of the input voltage (Vin) and output voltage (Vout).

5.4 Simulate the Design 1. First, check the design using the pull down menus: Tools Design Checks (any warnings/errors will be shown at the bottom)

a) Design check

b) Simulate design

2. Simulate the design: Click on the Green Arrow to start the simulator, either using the pull down menu (Fig. a) or simply by clicking the Green Arrow (Fig. b). The T-Spice window will appear. If everything is OK (no error), the waveform viewer will also appear. If everything worked, the waveform viewer will show the input and output waveforms. Observe the waveforms and discuss the finding. Print and include the obtained waveform in the laboratory report.

Faculty of Electrical and Electronic Engineering MEE 10701 : Experiment 02 Inverter Schematic

Number of Pages Edition Revision Number Effective Date Amendment Date

12 1 1

3. View the Netlist: In the T-Spice window, right click on the file at the bottom and select Show Netlist. This will bring up the TOP.sp Netlist that was created and used by the spice engine. This is a good place to look when there are errors. This is the text based description of the circuit as entered in S-edit.

Analyse this netlist file (TOP.sp) and compare it with the Netlist file in step 5.3(6) (TOP.spc). Discuss the finding. 4. View the Waveform If the windows viewer did NOT automatically appear, click on the file in the Tspice window and select Show Waveform 5. View the Output file The output file can be viewed by using any text editor. It is kept in the file filename.out and can be found in the working directory.

In this example it is TOP.out as specified in the setup earlier (Setup

Faculty of Electrical and Electronic Engineering MEE 10701 : Experiment 02 Inverter Schematic

Number of Pages Edition Revision Number Effective Date Amendment Date

13 1 1

SPICE Simulation : under Simulation Results File Name).

Open the output file and discuss what is in the file. Please include this output file in the laboratory report. This experiment is one way of simulating a circuit schematic (in this example it is an inverter) without using a symbol. In the next experiment, is another way of simulating a circuit (inverter) which employs symbol creation. EXPERIMENT B : Inverter Simulation Method 2 6 AIM 6.1 To draw an inverter and simulate it using Tanner Tools. OBJECTIVES 7.1 To use S-Edit to draw a CMOS inverter schematic and drawing its symbol. 7.2 To simulate the schematic by instancing a cell to the TOP cell. THEORY In this experiment, a new CMOS inverter circuit will be created and simulated. The design contains a symbol and then will be instantiated in another schematic to simulate the circuit. Symbols are handled by adding another view to a design. When performing a simulation, a typically cell is always call the cell TOP. When testing a circuit, for this experiment it is an inverter, the inverter will have its own cell (invert) that contains a schematic of the devices and a symbol. The inverter cell is instantiated in the TOP cell that contains ideal elements such as voltage sources and probes that are only used for simulation. This will allow cells separation that is actually going to be implemented on the die versus cells that are only used for simulation. 9 EQUIPMENT 9.1 Computer with Tanner Tools installed.

10 PROCEDURE 10.1 Start a New Design, Setup Libraries, Setup Simulation and Model 1. Start S-Edit (Note: These steps are similar to Step in section 5.2 in Experiment A) Create a new design called Inverter in the Tanner_workfile sub-directory (..\Tanner_workfile) File New New Design Create a new cell using the pull down menu: Cell New View and enter cell name TOP and View Type = schematic. (Note: Check that the design name must be Inverter)

Faculty of Electrical and Electronic Engineering MEE 10701 : Experiment 02 Inverter Schematic

Number of Pages Edition Revision Number Effective Date Amendment Date

14 1 1

Add the library to the library list on the left (..\Libraries\All\All.tanner) Setup the simulation using Pull Down Menus: Setup SPICE Simulation. Highlight the General Tab of the Setup SPICE window and set the following: SPICE File Name: ..\Tanner_workfile\Inverter\TOP.sp Library Files: ..\Libraries\Models\Generic_025.lib tt Simulation Results File Name: ..\Tanner_workfile\Inverter \TOP.out Check the Transient/Fourier Analysis box on the left and set the following: Stop Time = 100ns Maximum Time Step = 2ns Click OK 2. Create a new cell called invert with View Type = schematic. This new cell schematic (invert:schematic) will contain an NMOS and PMOS wired as an inverter as shown in the following figure. Draw the schematic and add Ports for the Input, Output, VDD, and VSS.

3. Create the Inverter Symbol Symbols can either be created manually by creating a new symbol view or automatically by S-edit. For the automatic symbol generation, this will create a new symbol view from the schematic, create the ports for the symbol, and make a symbol shape. Although the shape of the symbol is rarely what is wanted ultimately, it will do a lot of the work for the designer. With the invert:schematic view open, use the pull down menus to create the symbol view: Cell Update Symbol A new window will come up with a square symbol and 4 ports with the same names that are entered in the invert:schematic view (i.e., In, Out, Vdd, Vss).

Faculty of Electrical and Electronic Engineering MEE 10701 : Experiment 02 Inverter Schematic

Number of Pages Edition Revision Number Effective Date Amendment Date

15 1 1

Edit the shapes using the tool as shown, until a symbol that looks like an inverter is created.

Tools to edit/create symbol

Then add a symbol view to this design. The symbol will contain the inverter shape and the corresponding pins for Input, Output, Vdd, and Vss. Save the cell.

A note on drawing: The Path icon will put you into a mode where you can draw lines that are not wires. The Circle icon will allow you to enter the inversion bubble. The ports can be moved by holding down alt-m The ports can be rotated by selecting and pressing the r button

Faculty of Electrical and Electronic Engineering MEE 10701 : Experiment 02 Inverter Schematic

Number of Pages Edition Revision Number Effective Date Amendment Date

16 1 1

10.2

Create the TOP schematic to test the Inverter

1. Instantiate the invert in the TOP schematic Open the TOP schematic view using the pull-down menus: Cell Open View: Cell Name: TOP View Type: schematic In the library windows on the left of the window, highlight the Inverter library. In the lower left window, two cells TOP and invert will be seen. Click on invert, the inverter symbol will show up in the symbol viewer (invert:symbol), or the schematic of the inverter circuit in schematic viewer (invert:schmetic) Click on the Instance button and place the inverter symbol in the TOP schematic. 2. Draw the following circuit (Figure 2) in order to power and simulate the inverter. Enter the Pulse Voltage Source. All voltage sources are the same component in the SPICE_Elements library. The default is DC, but this can be changed to any other type of source in the properties dialog. Name = Vin MasterInterface = Pulse Period = 40ns PulseWidth = 20ns VHigh = 5v VLow = 0v RiseTime = 10ps FallTime = 10ps Enter a Load capacitor from the Devices library. Name = Cap_Load C =50fF Enter a DC Source for VDD. Name = VDD MasterInterface = DC V = 5v Enter the grounds from the Misc library. Enter wire connections and name them Vin and Vout. Enter a voltage probe for both Vin and Vout. Save the cell.

Faculty of Electrical and Electronic Engineering MEE 10701 : Experiment 02 Inverter Schematic

Number of Pages Edition Revision Number Effective Date Amendment Date

17 1 1

Figure 2 10.3 Simulate the Design 1. First, check the design using the pull down menus: Tools Design Checks (any warnings or errors will be shown at thecommand window) 2. Simulate the design: Click on the Green Arrow to start the simulator: The TSpice window will appear. If everything is OK, the waveform viewer will also appear. If everything worked, the waveform viewer will show the input and the output waveforms. Print this graph and discuss the result obtained. 3. Open the Netlist file TOP.sp and compare this file with the Netlist file (also TOP.sp) in experiment A. Discuss the findings.

Laboratory Report The laboratory report must include: 1. Print out of the complete schematic diagram of the inverter drawn in Step 5.3(15) of Experiment A. 2. Print out of the Netlist file (TOP.spc) created in Step 5.3(6) of Experiment A. 3. Print out of the graphs obtained in Step 5.4(2) of Experiment A. 4. Print out of the Netlist file from T-Spice (TOP.sp), of Step 5.4(3) in Experiment A. 5. Print out of the output file (TOP.out) created in Step 5.4(5) of Experiment A. 6. Print out of the cell invert in schematic form (Step 10.1(2)) and in symbol form (Step 10.1(3) from Experiment B. 7. Print out of the cell TOP (Step 10.2(2)) from Experiment B. 8. Print out of the graphs in Step 10.3(2) of Experiment B. 9. Print out of the following files: TOP.sp and TOP.out of Experiment B 10. Analysis and discussion from the observation made on the result and concise conclusion of the experiment. All the files created in Experiment A (1 folder) and Experiment B (another folder) must be submitted by e-mail to sitihawa@uthm.edu.my