OptiX PTN 910 Hardware Description

OptiX PTN 910 Packet Transport Platform of PTN Series V100R002C00
Hardware Description
Issue Date 04 2010-08-28
HUAWEI TECHNOLOGIES CO., LTD.
Copyright Huawei Technologies Co., Ltd. 2010. All rights reserved. No part of this document may be reproduced or transmitted in any form or by any means without prior written consent of Huawei Technologies Co., Ltd.
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and other Huawei trademarks are trademarks of Huawei Technologies Co., Ltd. All other trademarks and trade names mentioned in this document are the property of their respective holders.
Notice
The purchased products, services and features are stipulated by the contract made between Huawei and the customer. All or part of the products, services and features described in this document may not be within the purchase scope or the usage scope. Unless otherwise specified in the contract, all statements, information, and recommendations in this document are provided "AS IS" without warranties, guarantees or representations of any kind, either express or implied. The information in this document is subject to change without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents, but all statements, information, and recommendations in this document do not constitute the warranty of any kind, express or implied.
Huawei Technologies Co., Ltd.

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Issue 04 (2010-08-28)
Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd.
OptiX PTN 910 Hardware Description
About This Document
About This Document

Related Versions
The following table lists the product versions related to this document. Product Name OptiX PTN 910 Huawei iManager U2000 Version V100R002C00 V100R002C00
Intended Audience
This document describes the equipment structure, chassis structure, and board classification. This document also describes each board of these classes in details. This document helps you get the detailed information about the equipment hardware. This document is intended for:
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Network planning engineers Hardware installation engineers System maintenance engineers
Symbol Conventions
The symbols that may be found in this document are defined as follows. Symbol Description
DANGER
Indicates a hazard with a high level of risk, which if not avoided, will result in death or serious injury. Indicates a hazard with a medium or low level of risk, which if not avoided, could result in minor or moderate injury.
WARNING
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iii
About This Document
Symbol
Description
CAUTION
NOTE
Indicates a potentially hazardous situation, which if not avoided, could result in equipment damage, data loss, performance degradation, or unexpected results. Provides additional information to emphasize or supplement important points of the main text. Indicates a tip that may help you solve a problem or save time.
TIP
GUI Conventions
The GUI conventions that may be found in this document are defined as follows. Convention Boldface > Description Buttons, menus, parameters, tabs, window, and dialog titles are in boldface. For example, click OK. Multi-level menus are in boldface and separated by the ">" signs. For example, choose File > Create > Folder.
Change History
Updates between document versions are cumulative. Therefore, the latest document version contains all updates made to previous versions.
Changes in Issue 04 (2010-08-28) Based on Product Version (V100R002C00)

This document is the fourth release of the V100R002C00 version. Compared with issue 03 (2010-05-20), this document updates the following contents: Chasis Updates the description of the installation scenarios. Boards Fixes the known bugs of the FE/GE interface specifications . Others Updates the description of the safety labels.

This document is the third release of the V100R002C00 version. Compared with issue 02 (2010-03-30), this document updates the following contents:
iv Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd. Issue 04 (2010-08-28)
About This Document
Boards Updates the description of the functions of the CXPA/CXPB, and CXPG/CXPH. Others
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Updates and optimizes the description of indicators. Fixes the known bugs.

This document is the second release of the V100R002C00 version. Compared with issue 01 (2009-12-30), this document updates the following contents: Others Fixes the known bugs.

This document is the first release of the V100R002C00 version. Compared with the V100R001C01 version, this document updates the following contents: This document is used to be Chapter 9 of the OptiX PTN 910 Product Description. For the V100R002C00 version, this part is separated as an independent document. Boards
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Updates the diagram showing the inter-board relation of boards. Adds the description of single-fiber bidirectional optical modules in the contents describing the front panels of the CXPG/CXPH, EG2, EF8F, and CD1 and technical specifications of these boards. Deletes the description of the IFE2 board.
Filler Panel Adds the description of the functions and features of the filler panel. Pluggable Optical Modules Adds the description of the pluggable optical modules used by the equipment. Fibers and Cables Adds the description of various fibers and cables used by the equipment. Others
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Updates and optimizes the description of indicators. Adds the table providing the board weight and power consumption. Adds the description of board configuration parameters.
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Contents
Contents
About This Document...................................................................................................................iii 1 Chassis..........................................................................................................................................1-1 2 Boards...........................................................................................................................................2-1
2.1 Overview of Boards........................................................................................................................................2-3 2.2 CXPA/CXPB...................................................................................................................................................2-5 2.2.1 Version Description................................................................................................................................2-6 2.2.2 Functions and Features...........................................................................................................................2-6 2.2.3 Working Principle and Signal Flow.......................................................................................................2-9 2.2.4 Front Panel...........................................................................................................................................2-11 2.2.5 Valid Slots............................................................................................................................................2-18 2.2.6 Board Configuration Reference...........................................................................................................2-18 2.2.7 Technical Specifications......................................................................................................................2-18 2.3 CXPG/CXPH................................................................................................................................................2-19 2.3.1 Version Description..............................................................................................................................2-20 2.3.2 Functions and Features.........................................................................................................................2-20 2.3.3 Working Principle and Signal Flow.....................................................................................................2-22 2.3.4 Front Panel...........................................................................................................................................2-24 2.3.5 Valid Slots............................................................................................................................................2-31 2.3.6 Board Configuration Reference...........................................................................................................2-31 2.3.7 Technical Specifications......................................................................................................................2-31 2.4 EF8T..............................................................................................................................................................2-34 2.4.1 Version Description..............................................................................................................................2-34 2.4.2 Functions and Features.........................................................................................................................2-34 2.4.3 Working Principle and Signal Flow.....................................................................................................2-35 2.4.4 Front Panel...........................................................................................................................................2-36 2.4.5 Valid Slots............................................................................................................................................2-38 2.4.6 Board Configuration Reference...........................................................................................................2-38 2.4.7 Technical Specifications......................................................................................................................2-38 2.5 EF8F..............................................................................................................................................................2-39 2.5.1 Version Description..............................................................................................................................2-39 2.5.2 Functions and Features.........................................................................................................................2-39 2.5.3 Working Principle and Signal Flow.....................................................................................................2-40 Issue 04 (2010-08-28) Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd. vii
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OptiX PTN 910 Hardware Description 2.5.4 Front Panel...........................................................................................................................................2-41 2.5.5 Valid Slots............................................................................................................................................2-43 2.5.6 Board Configuration Reference...........................................................................................................2-43 2.5.7 Technical Specifications......................................................................................................................2-43
2.6 EG2................................................................................................................................................................2-44 2.6.1 Version Description..............................................................................................................................2-45 2.6.2 Functions and Features.........................................................................................................................2-45 2.6.3 Working Principle and Signal Flow.....................................................................................................2-46 2.6.4 Front Panel...........................................................................................................................................2-47 2.6.5 Valid Slots............................................................................................................................................2-48 2.6.6 Board Configuration Reference...........................................................................................................2-48 2.6.7 Technical Specifications......................................................................................................................2-48 2.7 ML1/ML1A...................................................................................................................................................2-50 2.7.1 Version Description..............................................................................................................................2-51 2.7.2 Functions and Features.........................................................................................................................2-51 2.7.3 Working Principle and Signal Flow.....................................................................................................2-53 2.7.4 Front Panel...........................................................................................................................................2-54 2.7.5 Valid Slots............................................................................................................................................2-56 2.7.6 Board Configuration Reference...........................................................................................................2-57 2.7.7 Technical Specifications......................................................................................................................2-57 2.8 CD1...............................................................................................................................................................2-57 2.8.1 Version Description..............................................................................................................................2-58 2.8.2 Functions and Features.........................................................................................................................2-58 2.8.3 Working Principle and Signal Flow.....................................................................................................2-61 2.8.4 Front Panel...........................................................................................................................................2-63 2.8.5 Valid Slots............................................................................................................................................2-64 2.8.6 Board Configuration Reference...........................................................................................................2-64 2.8.7 Technical Specifications......................................................................................................................2-65 2.9 ADS2A/ADS2B............................................................................................................................................2-66 2.9.1 Version Description..............................................................................................................................2-67 2.9.2 Functions and Features.........................................................................................................................2-67 2.9.3 Working Principle and Signal Flow.....................................................................................................2-68 2.9.4 Front Panel...........................................................................................................................................2-69 2.9.5 Valid Slots............................................................................................................................................2-70 2.9.6 Board Configuration Reference...........................................................................................................2-70 2.9.7 Technical Specifications......................................................................................................................2-71 2.10 SHD4...........................................................................................................................................................2-71 2.10.1 Version Description............................................................................................................................2-72 2.10.2 Functions and Features.......................................................................................................................2-72 2.10.3 Working Principle and Signal Flow...................................................................................................2-73 2.10.4 Front Panel.........................................................................................................................................2-74 2.10.5 Valid Slots..........................................................................................................................................2-75 viii Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd. 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2.10.6 Board Configuration Reference.........................................................................................................2-75 2.10.7 Technical Specifications....................................................................................................................2-76 2.11 SHD4I..........................................................................................................................................................2-76 2.11.1 Version Description............................................................................................................................2-76 2.11.2 Functions and Features.......................................................................................................................2-77 2.11.3 Working Principle and Signal Flow...................................................................................................2-77 2.11.4 Front Panel.........................................................................................................................................2-80 2.11.5 Valid Slots..........................................................................................................................................2-81 2.11.6 Board Configuration Reference.........................................................................................................2-81 2.11.7 Technical Specifications....................................................................................................................2-81 2.12 PIU..............................................................................................................................................................2-82 2.12.1 Version Description............................................................................................................................2-82 2.12.2 Functions and Features.......................................................................................................................2-82 2.12.3 Working Principle and Signal Flow...................................................................................................2-83 2.12.4 Front Panel.........................................................................................................................................2-83 2.12.5 Valid Slots..........................................................................................................................................2-85 2.12.6 Technical Specifications....................................................................................................................2-85 2.13 FAN.............................................................................................................................................................2-85 2.13.1 Version Description............................................................................................................................2-86 2.13.2 Functions and Features.......................................................................................................................2-86 2.13.3 Working Principle and Signal Flow...................................................................................................2-86 2.13.4 Front Panel.........................................................................................................................................2-87 2.13.5 Valid Slots..........................................................................................................................................2-88 2.13.6 Technical Specifications....................................................................................................................2-88
3 Filler Panel...................................................................................................................................3-1
3.1 Functions and Features....................................................................................................................................3-2 3.2 Appearance and Valid Slots............................................................................................................................3-2
4 Pluggable Optical Modules......................................................................................................4-1

4.1 Appearance and Application...........................................................................................................................4-2 4.2 Optical Module Labels....................................................................................................................................4-2
5 Fibers and Cables.......................................................................................................................5-1

5.1 Fibers...............................................................................................................................................................5-2 5.1.1 Fiber Types.............................................................................................................................................5-2 5.1.2 Fiber Connectors....................................................................................................................................5-2 5.2 -48 V Power Supply Cable..............................................................................................................................5-4 5.3 Protection Grounding Cables..........................................................................................................................5-5 5.4 Service Cables.................................................................................................................................................5-6 5.4.1 Ethernet Cables...................................................................................................................................... 5-6 5.4.2 75-Ohm 16 x E1 Cables.........................................................................................................................5-8 5.4.3 120-Ohm 16 x E1 Cables.....................................................................................................................5-11 5.4.4 xDSL Cables........................................................................................................................................5-14 Issue 04 (2010-08-28) Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd. ix
Contents
5.5 Management Cables......................................................................................................................................5-16 5.6 Clock Cables.................................................................................................................................................5-18 5.6.1 External Clock Cables..........................................................................................................................5-18 5.6.2 Clock Bridging Cable...........................................................................................................................5-20 5.7 Alarm Input/Output Cables...........................................................................................................................5-21
A Safety Labels.............................................................................................................................A-1 B Indicators....................................................................................................................................B-1 C Power Consumption and Weight..........................................................................................C-1 D Board Configuration Parameters..........................................................................................D-1 E Glossary.......................................................................................................................................E-1
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Figures
Figures
Figure 1-1 Appearance of the OptiX PTN 910.................................................................................................... 1-1 Figure 1-2 Slot allocation of the OptiX PTN 910................................................................................................1-1 Figure 2-1 Board relations of the OptiX PTN 910...............................................................................................2-5 Figure 2-2 Block diagram for the working principle of the CXPA/CXPB..........................................................2-9 Figure 2-3 Front panels of the CXPA and CXPB..............................................................................................2-11 Figure 2-4 Block diagram for the working principle of the CXPG/CXPH........................................................2-23 Figure 2-5 Appearances of the front panel of the CXPG and CXPH.................................................................2-24 Figure 2-6 Block diagram for the functions of the EF8T...................................................................................2-35 Figure 2-7 Font panel of the EF8T.....................................................................................................................2-37 Figure 2-8 Block diagram for the functions of the EF8F...................................................................................2-40 Figure 2-9 Font panel of the EF8F.....................................................................................................................2-41 Figure 2-10 Block diagram for the functions of the EG2...................................................................................2-46 Figure 2-11 Font panel of the EG2.....................................................................................................................2-47 Figure 2-12 Block diagram for the working principle of the ML1/ML1A........................................................2-53 Figure 2-13 Front panel of the ML1...................................................................................................................2-54 Figure 2-14 Front panel of the ML1A................................................................................................................2-55 Figure 2-15 Block diagram for the working principle of the CD1.....................................................................2-61 Figure 2-16 Appearance of the front panel of the CD1......................................................................................2-63 Figure 2-17 Block diagram for the working principle of the ADS2..................................................................2-68 Figure 2-18 Appearance of the front panel of the ADS2A................................................................................2-69 Figure 2-19 Appearance of the front panel of the ADS2B.................................................................................2-69 Figure 2-20 Block diagram for the working principle of the SHD4..................................................................2-73 Figure 2-21 Appearance of the front panel of the SHD4...................................................................................2-74 Figure 2-22 Block diagram for the working principle of the SHD4I.................................................................2-78 Figure 2-23 Appearance of the front panel of the SHD4I..................................................................................2-80 Figure 2-24 Block diagram for the working principle of the PIU......................................................................2-83 Figure 2-25 Appearance of the front panel of the PIU.......................................................................................2-84 Figure 2-26 Block diagram for the working principle of the FAN....................................................................2-86 Figure 2-27 Appearance of the front panel.........................................................................................................2-87 Figure 3-1 Appearance of a filler panel................................................................................................................3-2 Figure 4-1 Appearance of the eSFP optical module.............................................................................................4-2 Figure 4-2 Optical module label...........................................................................................................................4-2 Figure 5-1 LC/PC fiber connector........................................................................................................................5-3 Issue 04 (2010-08-28) Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd. xi
Figures
OptiX PTN 910 Hardware Description Figure 5-2 FC/PC fiber connector........................................................................................................................5-3 Figure 5-3 SC/PC fiber connector........................................................................................................................5-4 Figure 5-4 Appearance of the power cable...........................................................................................................5-5 Figure 5-5 Appearance of the protection grounding cable...................................................................................5-5 Figure 5-6 Appearance of the network cable.......................................................................................................5-7
Figure 5-7 RJ-45 connector..................................................................................................................................5-7 Figure 5-8 Structure of the network cable............................................................................................................5-7 Figure 5-9 Appearance of the 75-ohm 16 x E1 cable...........................................................................................5-9 Figure 5-10 Structure of the 75-ohm 16 x E1 cable.............................................................................................5-9 Figure 5-11 Appearance of the 120-ohm 16 x E1 cable.....................................................................................5-12 Figure 5-12 Structure of the 120-ohm 16 x E1 cable.........................................................................................5-12 Figure 5-13 Structure of the telephone wire.......................................................................................................5-15 Figure 5-14 RJ-45 connector..............................................................................................................................5-16 Figure 5-15 Structure of the RJ-45 Connector...................................................................................................5-18 Figure 5-16 Structure of the clock bridging cable..............................................................................................5-20 Figure 5-17 Structure of the alarm input/output cable.......................................................................................5-22 Figure A-1 Label position...................................................................................................................................A-2
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Tables
Tables
Table 2-1 Boards supported by the OptiX PTN 910 and their valid slots............................................................2-3 Table 2-2 Functions and Features of the CXPA/CXPB.......................................................................................2-6 Table 2-3 Types and usage of the interfaces on the CXPA/CXPB....................................................................2-12 Table 2-4 Pins of the ETH/OAM interface........................................................................................................2-13 Table 2-5 Pins of the CLK1/TOD1 and CLK2/TOD2 interface........................................................................2-14 Table 2-6 Pins of the EXT/F1 interface..............................................................................................................2-15 Table 2-7 Pins of the PHONE interface.............................................................................................................2-16 Table 2-8 Pins of the ALMI/ALMO interface....................................................................................................2-16 Table 2-9 Pins of the FE1-FE4 interfaces..........................................................................................................2-16 Table 2-10 Pins of the Anea 96 interface...........................................................................................................2-17 Table 2-11 Specifications of FE electrical interfaces.........................................................................................2-18 Table 2-12 Specifications of E1 interfaces.........................................................................................................2-19 Table 2-13 Functions and features of the CXPG/CXPH....................................................................................2-20 Table 2-14 Interfaces on the CXPG/CXPH........................................................................................................2-25 Table 2-15 Pins of the ETH/OAM interface......................................................................................................2-26 Table 2-16 Pins of the CLK1/TOD1 and CLK2/TOD2 interfaces.....................................................................2-27 Table 2-17 Pins of the PHONE interface...........................................................................................................2-28 Table 2-18 Pins of the FE1 interface to FE4 interface.......................................................................................2-28 Table 2-19 Pins of the GE optical interfaces......................................................................................................2-29 Table 2-20 Pins of the Anea 96 interface...........................................................................................................2-29 Table 2-21 Specifications of the FE electrical interface.....................................................................................2-31 Table 2-22 Technical specifications of the GE optical interface........................................................................2-31 Table 2-23 Wavelength allocation of 1000BASE-CWDM optical interfaces and related optical module code .............................................................................................................................................................................2-33 Table 2-24 Wavelength allocation of 1000BASE-BX optical interfaces and related optical module code.......2-33 Table 2-25 Specifications of the E1 interface.....................................................................................................2-33 Table 2-26 Functions and features of the EF8T.................................................................................................2-34 Table 2-27 Types and usage of interfaces on the EF8T.....................................................................................2-37 Table 2-28 Pins of the RJ-45 connector of the EF8T.........................................................................................2-38 Table 2-29 Specifications of interfaces on the EF8T.........................................................................................2-38 Table 2-30 Functions and features of the EF8F.................................................................................................2-39 Table 2-31 Interfaces of the EF8F......................................................................................................................2-42 Table 2-32 Performance specifications of the FE optical interface....................................................................2-43 Table 2-33 Wavelength allocation of 100BASE-BX optical interfaces and related optical module code.........2-44 Issue 04 (2010-08-28) Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd. xiii
Tables
OptiX PTN 910 Hardware Description Table 2-34 Functions and Features of the EG2..................................................................................................2-45 Table 2-35 Types and usage of optical interfaces on the EG2...........................................................................2-48 Table 2-36 Technical specifications of the GE optical interface........................................................................2-49 Table 2-37 Wavelength allocation of 1000BASE-CWDM optical interfaces and related optical module code .............................................................................................................................................................................2-50 Table 2-38 Wavelength allocation of 1000BASE-BX optical interfaces and related optical module code.......2-50 Table 2-39 Functions and features of the ML1/ML1A...................................................................................... 2-51 Table 2-40 Type and usage of the interface on the front panel of the ML1.......................................................2-55 Table 2-41 Pins of the Anea 96 interface...........................................................................................................2-55 Table 2-42 Specifications of the interfaces on the ML1/ML1A.........................................................................2-57 Table 2-43 Functions and features of the CD1...................................................................................................2-58 Table 2-44 Interfaces on the CD1.......................................................................................................................2-64 Table 2-45 Technical specifications of the STM-1 optical interface................................................................. 2-65 Table 2-46 Wavelength allocation of single-fiber bidirectional interface optical interface and related optical module code..................................................................................................................................................................... 2-66 Table 2-47 Functions and Features of the ADS2............................................................................................... 2-67 Table 2-48 Types and usage of the interfaces on the ADS2...............................................................................2-70 Table 2-49 Pins of the ADSL1 and ADSL2 interface on the ADS2..................................................................2-70 Table 2-50 Performance specifications of the ADS2A......................................................................................2-71 Table 2-51 Performance specifications of the ADS2B...................................................................................... 2-71 Table 2-52 Functions and Features of the SHD4............................................................................................... 2-72 Table 2-53 Types and usage of the interfaces on the SHD4...............................................................................2-75 Table 2-54 Pins of the SHDSL1 - SHDSL4 interfaces on the SHD4.................................................................2-75 Table 2-55 Performance specifications of the SHD4.........................................................................................2-76 Table 2-56 Functions and Features of the SHD4I..............................................................................................2-77 Table 2-57 Types and usage of the interfaces on the SHD4I.............................................................................2-80 Table 2-58 Pins of the SHDSL1 - SHDSL4 interfaces on the SHD4I...............................................................2-81 Table 2-59 Specifications of the interfaces of the SHD4I..................................................................................2-81 Table 2-60 Functions and features of the PIU....................................................................................................2-82 Table 2-61 Types and usage of the interfaces on the PIU..................................................................................2-84 Table 2-62 Technical specifications of the PIU................................................................................................. 2-85 Table 2-63 Technical specifications of the FAN................................................................................................2-88 Table 4-1 Boards where the eSFP optical module is applicable..........................................................................4-2 Table 4-2 Codes and types of optical modules.....................................................................................................4-3 Table 5-1 Types of Fiber......................................................................................................................................5-2 Table 5-2 Usage and types of fiber connectors....................................................................................................5-3 Table 5-3 Technical specifications of the power cable........................................................................................5-5 Table 5-4 Technical specifications of the power cable and protection grounding cable......................................5-6 Table 5-5 Pin assignment of the network cable connector...................................................................................5-8 Table 5-6 Technical specifications of the network cable.....................................................................................5-8 Table 5-7 Pin assignment of the 75-ohm E1 cable connector............................................................................5-10 Table 5-8 Technical specifications of the 75-ohm 16 x E1 cable.......................................................................5-11 Table 5-9 Pin assignment of the 120-ohm E1 cable connector..........................................................................5-12
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Tables
Table 5-10 Technical specifications of the 120-ohm 16 x E1 cable...................................................................5-14 Table 5-11 Pin assignment of the ADSL cable connector (RJ-11)....................................................................5-15 Table 5-12 Pin assignment of the G.SHDSL cable connector...........................................................................5-15 Table 5-13 Technical specifications of the xDSL cable.....................................................................................5-16 Table 5-14 Pin assignment of the RJ-45 connector (ETH/OAM)......................................................................5-17 Table 5-15 Pin assignment of the RJ-45 connector (EXT/F1)...........................................................................5-17 Table 5-16 Technical specifications of the Ethernet cable.................................................................................5-18 Table 5-17 Pin assignment of the RJ-45 connector (external clock mode)........................................................5-19 Table 5-18 Pin assignment of the RJ-45 connector (external time mode).........................................................5-19 Table 5-19 Technical specifications of the external clock cable........................................................................5-20 Table 5-20 Pin assignment of the clock bridging cable connector.....................................................................5-20 Table 5-21 Technical specifications of the clock bridging cable.......................................................................5-21 Table 5-22 Pin assignment of the alarm input/output cable connector..............................................................5-22 Table 5-23 Technical specifications of the alarm input/output cable.................................................................5-22 Table A-1 Label description................................................................................................................................A-1 Table B-1 Start status indicator combination.......................................................................................................B-7 Table C-1 Power consumption and weight..........................................................................................................C-1 Table D-1 Mapping relation between the service type and C2 byte....................................................................D-2 Table D-2 Mapping relation between the service type and V5 byte................................................................... D-2
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1 Chassis
1
The OptiX PTN 910 is case-shaped for easy deployment. Figure 1-1 shows the appearance of the OptiX PTN 910 equipment. Figure 1-1 Appearance of the OptiX PTN 910
Chassis
The dimensions of the OptiX PTN 910 are 442 mm (width) x 220 mm (depth) x 1 U (height, 1 U = 44.45 mm). The OptiX PTN 910 can be installed in the following scenarios:
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ETSI cabinet (300 mm deep) ETSI cabinet (600 mm deep) 19 inch cabinet (450 mm deep) 19 inch cabinet (600 mm deep) Indoor Mini Box (IMB) network box APM30/OMB outdoor cabinet Open rack
The PTN equipment can be installed indoors or outdoors. The installation must satisfy the requirement of running environment for equipment. To better satisfy the requirement, you can install the equipment in an IMB network cabinet or an APM30/OMB outdoor cabinet. Use the GIE4805S external AC power supply system to provide power to the IMB network box or outdoor cabinet. Figure 1-2 shows the slot allocation of the OptiX PTN 910. Figure 1-2 Slot allocation of the OptiX PTN 910
SLOT SLOT 6 5 SLOT 3 SLOT 1 and SLOT 2 SLOT 4
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1-1
1 Chassis
1-2
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2 Boards
2
About This Chapter
2.1 Overview of Boards Boards are the key hardware components of the equipment.
Boards
Boards of the OptiX PTN 910 include system control, cross-connect and protocol processing board, interface boards, power supply board, and fan board.
2.2 CXPA/CXPB This section describes the CXPA/CXPB, which is the system control, cross-connect and protocol processing board, with regard to the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.3 CXPG/CXPH This section describes the CXPG/CXPH, which integrates the control, cross-connect, and protocol processing units, in terms of the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.4 EF8T This section describes the EF8T, which is an interface board with eight FE electrical interfaces, with regard to the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.5 EF8F This section describes the EF8F, which is an interface board with eight FE optical interfaces, with regard to the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.6 EG2 This section describes the EG2, which is an interface board with two GE optical interfaces, with regard to the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.7 ML1/ML1A This section describes the ML1/ML1A, which is a 16 x E1 electrical interface board, with regard to the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.8 CD1
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2 Boards
This section describes the CD1, which is a 1 x channelized STM-1 service processing board, in terms of the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.9 ADS2A/ADS2B This section describes the ADS2A/ADS2B, a 2-channel ADSL service interface board, in terms of the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.10 SHD4 This section describes the SHD4, a 4-channel G.SHDSL service interface board, in terms of the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.11 SHD4I This section describes the SHD4I, a 4-channel SHDSL service interface board that supports the IMA mode, in terms of the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.12 PIU This section describes the PIU, a power input unit, in terms of the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.13 FAN This section describes the FAN, a fan board, in terms of the version, functions, features, working principle, front panel, valid slots, and technical specifications.
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2.1 Overview of Boards

Boards are the key hardware components of the equipment.
Board Description and Valid Slots

Table 2-1 shows the boards supported by the OptiX PTN 910 and their valid slots. Table 2-1 Boards supported by the OptiX PTN 910 and their valid slots Board Name CXPA Board Description System control, switching and timing board, with 4 x FE service interfaces and 16 x E1 interfaces (matching 75-ohm E1) System control, switching and timing board, with 4 x FE service interfaces and 16 x E1 interfaces (matching 120ohm E1) System control, switching and timing board, with 4 x FE service interfaces, 2 x GE service interfaces, and 16 x E1 interfaces (matching 75ohm E1) System control, switching and timing board, with 4 x FE service interfaces, 2 x GE service interfaces, and 16 x E1 interfaces (matching 120ohm E1) 8 x FE service interface board (electric interface) 8 x FE service interface board (optical interface) 2 x GE service interface board 16 x E1 service interface board (75 ohms) 16 x E1 service interface board (120 ohms) Valid Slot Slot 1 and slot 2
CXPB
Slot 1 and slot 2
CXPG
Slot 1 and slot 2
CXPH
Slot 1 and slot 2
EF8T EF8F EG2 ML1 ML1A
Slot 3, slot 4 Slot 3, slot 4 Slot 3, slot 4 Slot 3, slot 4 Slot 3, slot 4
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2 Boards
Board Name CD1 ADS2A/ADS2B SHD4
Board Description 1 x channelized STM-1 service interface board 2 x ADSL2+ interface board 4 x G.SHDSL interface board (supporting the ATM mode and EFM mode)
Valid Slot Slot 3, slot 4 Slot 3, slot 4 Slot 3, slot 4
SHD4I
4 x G.SHDSL interface board (supporting the IMA mode)
Slot 3, slot 4
PIU FAN
NOTE
Power board Fan board
Slot 5 Slot 6
l The CXPA and CXPB each house two slots. Slot 1 and slot 2 house one CXPA or CXPB. l The CXPG and CXPH each house two slots. Slot 1 and slot 2 house one CXPG or CXPH. l The second port of the CD1 can be used for only the LMSP protection. l The ADS2A supports the Annex A mode. The ADS2B supports the Annex B mode.
Board Relations
The OptiX PTN 910 uses different boards to achieve various functions. Figure 2-1 shows board relations of the OptiX PTN 910.
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Figure 2-1 Board relations of the OptiX PTN 910

1.Orderwire interface 2.NM network interface 3.Alarm interface 4.Synchronous data interface 5.NE serial interface 6.Clock interface 7.Time interface 8.Concatenation interface Network side Control and management module
EF8F EF8T EG2 GE GE GE E1
User side
FE FE GE E1 Channelized STM-1 EF8F EF8T EG2 ML1/ML1A CD1 FE E1 GE
Service processing and forwarding module
ML1/ML1A
ADS2 SHD4/ SHD4I CD1
ADSL2+ G.SHDSL Channelized STM-1 FE E1
Clock module CXPA/CXPB/CXPG/CXPH
GE
-48 V DC/-60 V DC -48 V DC/-60 V DC
Power module PIU
Heat dissipation module FAN
NOTE
Only the CXPA/CXPB supports the NM cascading interface, transparent data interface, and alarm interface. The GE signal can be accessed from the front panel of only the CXPG/CXPH.
2.2 CXPA/CXPB
This section describes the CXPA/CXPB, which is the system control, cross-connect and protocol processing board, with regard to the version, functions, features, working principle, front panel, valid slots, and technical specifications.
NOTE
The matched impedance of the E1 service interface on the CXPA is 75 ohms and the matched impedance of the E1 interface on the CXPB is 120 ohms. The CXPA and CXPB have the same functions and features, except for the impedance of the E1 service interfaces.
2.2.1 Version Description The functional version of the CXPA/CXPB is TNC1. 2.2.2 Functions and Features The CXPA/CXPB accesses and processes 4 x FE electrical signals and 16 x E1 signals, grooms services, performs the system control, processes the system clock, and provides auxiliary interfaces.
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2.2.3 Working Principle and Signal Flow The CXPA/CXPB consists of the control module, auxiliary interface module, service grooming and processing module, clock module, and power supply module. 2.2.4 Front Panel On the front panel of the CXPA/CXPB, there are indicators, buttons, and interfaces. 2.2.5 Valid Slots Two slots house one CXPA/CXPB. The CXPA/CXPB can be housed in slot 1 and slot 2. 2.2.6 Board Configuration Reference You can use the U2000 to set parameters for the CXPA/CXPB. 2.2.7 Technical Specifications The technical specifications of the CXPA/CXPB include the interface specifications, board dimensions, weight, and power consumption.
2.2.1 Version Description

The functional version of the CXPA/CXPB is TNC1.
2.2.2 Functions and Features

The CXPA/CXPB accesses and processes 4 x FE electrical signals and 16 x E1 signals, grooms services, performs the system control, processes the system clock, and provides auxiliary interfaces. Table 2-2 lists the functions and features of the CXPA/CXPB. Table 2-2 Functions and Features of the CXPA/CXPB Function and Feature Basic function Description Cross-connect capacity Line Rate I/O Capability using the CXPA/CXPB 6.5 Gbit/s 4.43 Gbit/s
Accesses and processes 4 x FE electrical signals and 16 x E1 signals. In the case of the E1 services, the IMA, CES, and ML-PPP protocols are supported. Supports the inband DCN. By default, the DCN function is enabled at all the ports. In addition, this function can be disabled or enabled manually. Fractional E1 Supports the CES services and IMA services at 64 kbit/s level.
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Function and Feature Auxiliary interface function
Description Provides one NM serial port or NM network port to communicate with the NMS so that the NMS can manage and query the equipment. Provides two interfaces for inputting and outputting the external clock/time to obtain the external clock/time information. Provides one alarm input/output interface for three alarm inputs and one alarm output. Provides one extended network port or 64 kbit/s synchronous data port. The extended network port is used to realize the cascading of Huawei equipment. The 64 kbit/s synchronous data port, which is compliant with ITU-T G.703, is used to transparently transmit other NM data. Provides one orderwire interface.The orderwire interface is reserved for later use.
Interface function
Type of the loopback at the FE port Automatic loopback release at the port
PHY-layer inloop MAC-layer outloop Supported Supported Supported 8
LAG
Intra-board LAG Inter-board LAG
ATM/IMA
Number of supported IMA groups /supported ATM E1 services Maximum number of E1 links or 64kbit/s level serial ports in each IMA group
16
Dynamically enables or disables the IMA group, restarts the IMA group protocol, and dynamically adds or deletes the IMA group members. Supported traffic type CBR UBR UBR+ rt-VBR nrt-VBR Number of supported ATM connections (VPC and VCC included) Number of supported ATM services 64 256 remote connections 128 local connections
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Function and Feature
Description Encapsulates the ATM VPC/VCC services to the PWE3 in the N-to-1 (N32) or 1-to-1 format. Encapsulates the ATM cells to the PW in the concatenation and non-concatenation modes. The number of PW connections that support the cell concatenation is 64, and the maximum number of concatenated cells is 31. ATM OAM on the UNI side and NNI side Supports the CC test. Supports the LB test. 16 CESoPSN SAToP Supports the timeslot compression function. Provides the idle 64 kbit/s timeslot suppression function for the CES services in the CESoPSN mode to save the transmission bandwidth. Supported clock mode Retiming mode Self-adaptation mode The jitter compensation buffer time of the CES service can be set. The jitter buffer time ranges from 0.375 ms to 16 ms, and the step value is 0.125 ms. The packet loading time of the CES service can be set. The encapsulation buffer time ranges from 0.125 ms to 3 ms, and the step value is 0.125 ms.
CES
Number of supported CES services Supported emulation mode
ML-PPP
Number of supported MLPPP groups Maximum number of links supported by each ML-PPP group Functions as the NNI interface.
7 16
PRBS APS
Supports the PRBS function in framed or unframed mode of an E1 port in the receive/transmit direction. Supports MPLS Tunnel APS. Supports 1:1 PW APS with dual-ended switching.
MPLS Tunnel OAM PW OAM BFD
Supported Supported Supports BFD with a period of 3.3 ms, 10 ms, 20 ms, 50 ms, 100 ms, or 1 s.
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Function and Feature Black list and white list of MAC addresses Clock
Description Supported Synchronous Ethernet SSM protocol IEEE 1588V2 protocol 1588 ACR clock Supported Supported by the FE ports Supported Supported
2.2.3 Working Principle and Signal Flow

The CXPA/CXPB consists of the control module, auxiliary interface module, service grooming and processing module, clock module, and power supply module. Figure 2-2 shows the block diagram for the working principle of the CXPA/CXPB. Figure 2-2 Block diagram for the working principle of the CXPA/CXPB
Backplane
2-channel external time/ clock input/output interface NM network interface/ serial interface Extended network interface/ transparent data interface Alarm input/output interface Orderwire interface External time/ clock signals Clock signals
Clock module
Working clock signals
Interface boards Each module on the board
Auxiliary interface module
NM network interface/serial interface signals Extended network interface signals Alarm input/output signals
Time/clock signals
Orderwire signals
Transparent data signals Management bus
Control module
Interface boards
Management bus
4 x FE electrical signals 16 x E1 signals
Service grooming and processing module
Service bus
Interface boards
3.3 V Working power
Interface boards FAN PIU PIU
Each module on the board
Power supply module
12 V -48 V/-60 V -48 V/-60 V
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Control Module
This module performs the following functions:
l l l
Configures and monitors the CXPA/CXPB and the entire system. Enables the communication through the NM serial interface and NM Ethernet interface. Enables the communication based on the extended Ethernet interface.
Service Grooming and Processing Module

l l l l l l
Accesses and processes 4 x FE electrical signals. Accesses and processes 16 x E1 signals. Processes the services accessed by the interface boards. Supports the CES, ML-PPP, and IMA protocols for E1 services. Grooms services with 6.5 Gbit/s switching capacity in the full-duplex mode. Supports 4.43 Gbit/s line rate I/O capability of the system.
Auxiliary Interface Module

l l
Provides two interfaces for input and output of the external clock/time. Provides one NM serial interface or NM Ethernet interface for communication with the NMS, management and queries of the equipment. Provides one alarm input/output interface to input three channels of alarms and output one channel of alarms. Provides one orderwire interface. Provides one extended network port or 64 kbit/s synchronous data port. The extended network port is used to realize the cascading of Huawei equipment. The 64 kbit/s synchronous data port, which is compliant with ITU-T G.703, is used to transparently transmit other NM data.
NOTE
l l
The orderwire interface is reserved for later use.
Clock Module
l
Provides the system clock signals and processes the clock signals from the service boards and the external clock/time interfaces. Provides the working clock for each module on the CXPA/CXPB. Supports the synchronous Ethernet and the SSM protocol. Supports the IEEE 1588V2 protocol.
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2-10

l
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Supports the 1588 ACR clock.
Power Supply Module

l l l l
Accesses two - 48 V DC or - 60 V DC power supplies. Supplies working power for each module on the CXPA/CXPB. Supplies 12 V power for the FAN board. Supplies 3.3 V power for other boards.
2.2.4 Front Panel

On the front panel of the CXPA/CXPB, there are indicators, buttons, and interfaces.
Appearance of the Front Panel

Figure 2-3 shows the appearance of the front panel of the CXPA/CXPB. Figure 2-3 Front panels of the CXPA and CXPB
Indicator
The following indicators are present on the front panel of the CXPA/CXPB:
l l l l l l l l l
STAT indicator, red, green, or orange, which indicates the working status PROG indicator, red or green, which indicates the running status of the program SYNC indicator, red or green, which indicates the clock synchronization status SRV indicator, red, green, or orange, which indicates the service status CRIT indicator, red, which indicates critical alarms MAJ indicator, orange, which indicates major alarms MIN indicator, yellow, which indicates minor alarms LINK indicator, green, which indicates the port connection status ACT indicator, yellow, which indicates the data transceiving status of the port
NOTE
The LINK and ACT indicators, which are present above ETH/OAM, EXT/F1, and FE service interface, indicate the connection status of the Ethernet interface.
For details on meanings of indicators, see B Indicators.

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Button
The following buttons are present on the front panel of the CXPA/CXPB:
l
RST button, which is used for warm reset of the board. When you press the RST button and then release it, the board is reset (warm). CF RCV button, which is used to restore the configuration data from the CF card. When you press the CF RCV button for 5 seconds, the equipment automatically restores the configuration data from the CF card. LAMP button, which is used to test the indicators. When you press the LAMP button, except the LINK indicators on the ADS2A/ADS2B and the FE service port indicators on the EF8T/EF8F/CXPA/CXPB all the board indicators on the NE are on.
Interface
Table 2-3 lists the types and usage of the interfaces on the CXPA/CXPB. Table 2-3 Types and usage of the interfaces on the CXPA/CXPB Interface on the Front Panel ETH/ OAM Interface Type Usage Pin Correspondi ng Cable
RJ-45
10M/100M interface for NM network port or NM serial port
For details, see Table 2-4.
For details, see 5.5 Management Cables. For details, see 5.6 Clock Cables.
CLK1/ TOD1 CLK2/ TOD2 EXT/F1
RJ-45 RJ-45 RJ-45
External clock/time input/ output interface External clock/time input/ output interface 10Base-T/100Base-TX extended Ethernet interface or 64 kbit/s synchronous data interface Orderwire interface
For details, see 5.5 Management Cables. For details, see 5.5 Management Cables. For details, see 5.7 Alarm Input/Output Cables. For details, see 5.4.1 Ethernet Cables.
PHONE
RJ-45
ALMI/ ALMO
RJ-45
3 x alarm inputs and 1 x alarm output interface
FE1 - FE4
RJ-45
Input/output interface for FE electrical signals
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Interface on the Front Panel E1 (1 - 16)
Interface Type
Usage
Pin
Correspondi ng Cable
Anea 96
E1 service input/output interface
For details, see Table 2-10
For details, see 5.4.2 75-Ohm 16 x E1 Cablesand 5.4.3 120Ohm 16 x E1 Cables.
NOTE The FE1 to FE4 interfaces, ETH/OAM interface and EXT/F1 interface support auto-adaptation to a straight-through network cable or a crossover network cable. The matched impedance of the E1 service interface on the CXPA is 75 ohms and the matched impedance of the E1 interface on the CXPB is 120 ohms. The PHONE interface is reserved for later use.
Table 2-4 Pins of the ETH/OAM interface Front View Pin 1 2

87654321
Usage Transmit positive of the NM interface Transmit negative of the NM interface Receive positive of the NM interface Grounding end of the NM serial interface Receive end of the NM serial interface Receive negative of the NM interface Undefined Transmit end of the NM serial interface
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Table 2-5 Pins of the CLK1/TOD1 and CLK2/TOD2 interface Front View Pin Usage External Clock External Time Input (1PPS + Time Information) External Time Output (1PPS + Time Informatio n) Unspecified Unspecified Unspecified External Time Input (DCLS) External Time Output (DCLS)
87654321
Negative receive end of external clock Positive receive end of external clock Unspecified
Unspecified
Unspecified
Unspecified
Unspecified
Unspecified
Negative input for the 1pps signal (RS422 level)
Negative output for the 1pps signal (RS422 level)
Negative input for the DCLS time signal (RS422 level)
Negative output for the DCLS time signal (RS422 level) Grounding end
Negative transmit end of external clock Positive transmit end of external clock Unspecified
Grounding end
Grounding end
Grounding end
Grounding end
Grounding end
Grounding end
Grounding end
Positive input for the 1pps signal (RS422 level)
Positive output for the 1pps signal (RS422 level)
Positive input for the DCLS time signal (RS422 level)
Positive output for the DCLS time signal (RS422 level)
Unspecified
Negative input for time information (RS422 level)
Negative output for time information (RS422 level)
Unspecified
Unspecified
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Front View
Pin
Usage External Clock External Time Input (1PPS + Time Information) External Time Output (1PPS + Time Informatio n) Positive output for time information (RS422 level) Unspecified Unspecified External Time Input (DCLS) External Time Output (DCLS)
Unspecified
Positive input for time information (RS422 level)
NOTE The CLK1/TOD1 and CLK2/TOD2 interfaces can be configured so that they can work in one of the preceding five working modes.
Table 2-6 Pins of the EXT/F1 interface Front View Pin 1 2

87654321
Usage Transmit positive of the extended Ethernet interface Transmit negative of the extended Ethernet interface Receive positive of the extended Ethernet interface Transmit positive of the 64 kbit/s synchronous data interface Transmit negative of the 64 kbit/s synchronous data interface Receive negative of the extended Ethernet interface Receive positive of the 64 kbit/s synchronous data interface Receive negative of the 64 kbit/s synchronous data interface
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Table 2-7 Pins of the PHONE interface Front View Pin 1-3 4
87654321
Purpose Undefined RING TIP Undefined
5 6-8
Table 2-8 Pins of the ALMI/ALMO interface Front View Pin 1 2

87654321
Usage Alarm input 1 Grounding end for alarm input 1 Alarm input 2 Alarm input 3 Grounding end for alarm input 3 Grounding end for alarm input 2 Alarm output positive Alarm output negative
3 4 5 6 7 8
Table 2-9 Pins of the FE1-FE4 interfaces Front View Pin 1 2

87654321
Usage Positive of twisted pair 1 Negative of twisted pair 1 Positive of twisted pair 2 Undefined Undefined Negative of twisted pair 2 Undefined Undefined
3 4 5 6 7 8
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Table 2-10 Pins of the Anea 96 interface Front View Connector Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 49 50 51 52 53 R x 15 R x 14 R x 13 R x 12 R x 11 R x 10 Rx9 Rx8 Rx7 Rx6 Rx5 Rx4 Rx3 Rx2 Usage Rx1 Connector Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 73 74 75 76 77 T x 15 T x 14 T x 13 T x 12 T x 11 T x 10 Tx9 Tx8 Tx7 Tx6 Tx5 Tx4 Tx3 Tx2 Usage Tx1
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Front View
Connector Pin 54 55 56
Usage
Connector Pin 78
Usage
R x 16
79 80
T x 16
2.2.5 Valid Slots

Two slots house one CXPA/CXPB. The CXPA/CXPB can be housed in slot 1 and slot 2.
2.2.6 Board Configuration Reference

You can use the U2000 to set parameters for the CXPA/CXPB. You can use the U2000 to set the following parameter for the CXPA/CXPB:
l l l l l
Ethernet interface PDH interface Environment monitor interface External time interface Phase-locked source output by External clock
For details on the parameters, see D Board Configuration Parameters.
2.2.7 Technical Specifications

The technical specifications of the CXPA/CXPB include the interface specifications, board dimensions, weight, and power consumption.
Interface Specifications
The interface specifications of the CXPA/CXPB are as follows:
l l
For specifications of FE electrical interfaces, see Table 2-11. For specifications of E1 interfaces, see Table 2-12.
Table 2-11 Specifications of FE electrical interfaces Item Electrical interface rate RJ-45 electrical interface specification Specification 100 Mbit/s The specifications of the RJ-45 electrical interfaces comply with the following regulations:
l
IEEE 802.3 and enterprise regulations
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Table 2-12 Specifications of E1 interfaces Item Nominal bit rate (kbit/s) Interface impedance Specification Requirement 2048 75 ohms (CXPA) 120 ohms (CXPB) Interface code Pulse waveform at the output interface Attenuation tolerance of the input interface at the point with a frequency of 1024 kHz (dB) Anti-interference capability of the input interface Input jitter tolerance Output jitter HDB3 Complies with ITU-T G.703 0 to 6
Complies with ITU-T G.703 Complies with ITU-T G.823 Complies with ITU-T G.823
Other Specifications
Other specifications of the CXPA/CXPB are as follows:
l l l
Board dimensions (mm): 20.32 (H) x 226.00 (D) x 388.40 (W) Weight (kg): 1.25 Power consumption (W): 43.9
2.3 CXPG/CXPH
This section describes the CXPG/CXPH, which integrates the control, cross-connect, and protocol processing units, in terms of the version, functions, features, working principle, front panel, valid slots, and technical specifications.
NOTE
The matched impedance of the E1 service interface on the CXPG is 75 ohms and that on the CXPH is 120 ohms. The CXPG and CXPH have the same functions and features, except for the impedance of the interfaces.
2.3.1 Version Description The functional version of the CXPG/CXPH is TNC1. 2.3.2 Functions and Features The CXPG/CXPH accesses and processes 4 x FE electrical signals, 2 x GE optical signals, and 16 x E1 signals, grooms services, performs the system control, processes the system clock, and provides auxiliary interfaces. 2.3.3 Working Principle and Signal Flow The CXPG/CXPH consists of the auxiliary interface module, control and communication module, service grooming and processing module, clock module, and power supply module.
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2.3.4 Front Panel On the front panel of the CXPG/CXPH, there are indicators, buttons, and interfaces. 2.3.5 Valid Slots Two slots house one CXPG/CXPH. The CXPG/CXPH can be housed in slots 1 and 2. 2.3.6 Board Configuration Reference The CXPG/CXPH can be configured through the U2000. 2.3.7 Technical Specifications The technical specifications of the CXPG cover the interface specifications, board dimensions, weight, and power consumption.

The functional version of the CXPG/CXPH is TNC1.

The CXPG/CXPH accesses and processes 4 x FE electrical signals, 2 x GE optical signals, and 16 x E1 signals, grooms services, performs the system control, processes the system clock, and provides auxiliary interfaces. Table 2-13 lists the functions and features of the CXPG/CXPH. Table 2-13 Functions and features of the CXPG/CXPH Function and Feature Basic function Description Cross-connect capacity Line Rate I/O Capability using the CXPG/CXPH 6.5 Gbit/s 6.43 Gbit/s
Accesses and processes 4 x FE electrical signals, 2 x GE optical signals, and 16 x E1 signals. Supports the inband DCN. By default, the DCN function is enabled at all the ports. In addition, this function can be disabled or enabled manually. Fractional E1 Auxiliary interface function Supports the CES services and IMA services at 64 kibt/s level. Provides one NM serial port or NM network port to communicate with the NMS so that the NMS can manage and query the equipment. Provides two interfaces for inputting and outputting the external clock/time to obtain the external clock/time information. Provides one orderwire interface. The orderwire interface is reserved for later use. Interface function Type of the loopback at the GE port PHY-layer inloop and outloop MAC-layer outloop
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Description Type of the loopback at the FE port Automatic loopback release at the port PHY-layer inloop MAC-layer outloop Supported Supported Supported 8 8 16
LAG
ATM/IMA
Number of supported ATM E1 services Number of supported IMA groups Maximum number of E1 links or 64kbit/s serial ports in each IMA group
Dynamically enables or disables the IMA group, restarts the IMA group protocol, and dynamically adds or deletes the IMA group members. Supported traffic type CBR UBR UBR+ rt-VBR nrt-VBR Number of supported ATM connections Number of supported ATM services 256 remote connections 128 local connections 64
Encapsulates ATM VPC/VCC service to the PWE3 in the Nto-1 (N32) or 1-to-1 format. Encapsulates the ATM cells to the PW in the concatenation and non-concatenation modes. The number of PW connections that support the cell concatenation is 64, and the maximum number of concatenated cells is 31. ATM OAM on the UNI side and NNI side CES Number of supported CES services Supported emulation mode Supports the CC test. Supports the LB test. 16 CESoPSN SAToP
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Description Supports the timeslot compression function. Provides the idle 64 kbit/s timeslot suppression function for the CES services in the CESoPSN mode to save the transmission bandwidth. Supported clock mode Retiming mode Self-adaptation mode The jitter compensation buffer time of the CES service can be set. The jitter buffer time ranges from 0.375 ms to 16 ms, and the step value is 0.125 ms. The packet loading time of the CES service can be set. The encapsulation buffer time ranges from 0.125 ms to 3 ms, and the step value is 0.125 ms.
ML-PPP
Number of supported MLPPP groups Maximum number of links supported by each ML-PPP group Functions as the NNI interface.
7 16
PRBS APS
Supports the PRBS function in framed or unframed mode of an E1 port in the receive/transmit direction. Supports MPLS Tunnel APS. Supports 1:1 PW APS with dual-ended switching.
MPLS Tunnel OAM PW OAM BFD Black list and white list of MAC addresses Clock
Supported Supported Supports BFD with a period of 3.3 ms, 10 ms, 20 ms, 50 ms, 100 ms, or 1s. Supported Synchronous Ethernet SSM protocol IEEE 1588V2 protocol 1588 ACR clock Supported Supported Supported Supported

The CXPG/CXPH consists of the auxiliary interface module, control and communication module, service grooming and processing module, clock module, and power supply module. Figure 2-4 shows the block diagram for the working principle of the CXPG/CXPH.
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Figure 2-4 Block diagram for the working principle of the CXPG/CXPH
Two external time/clock input/output interfaces NMS network port or NMS serial port Orderwire interface
Backplane Auxiliary interface module

Two external time/clock signals Clock signal
Clock signal
Clock module
Interface boards
Orderwire signal
NMS signal
Control and communication module

Management bus
Management bus
Interface boards
2 x GE signals 4 x FE electrical signals 16 x E1 signals
Service grooming and processing module
Service bus
Interface boards
3.3 V
Working power supply
Power supply module
12 V -48 V/-60 V -48 V/-60 V
Interface boards FAN PIU PIU
Auxiliary Interface Module

l l
Provides two interfaces for inputting and outputting the external clock/time. Provides one NM serial port or NM network port for communicating with the NMS, managing the equipment, and querying the equipment. Provides one orderwire interface.
NOTE
The orderwire interface is reserved for later use.
Control and Communication Module

l l
Configures and monitors the CXPG/CXPH and the entire system. Enables the communication through the NM serial port or NM network port.
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Service Grooming and Processing Module

l l l l l l l
Accesses and processes 2 x GE optical signals. Accesses and processes 4 x FE electrical signals. Accesses and processes 16 x E1 signals. Processes the service signals accessed by the interface boards. Supports the CES, ML-PPP, and IMA protocols for E1 services. Grooms services with 6.5 Gbit/s switching capacity in the full-duplex mode. Supports 6.43 Gbit/s line rate I/O capability of the system.
Clock Module
l
Provides the system clock signals and processes the clock signals from the service boards and the external clock/time interfaces. Provides the working clock for each module on the CXPG/CXPH. Supports the synchronous Ethernet and the SSM protocol. Supports the IEEE 1588V2 protocol. Supports the 1588 ACR clock.
l l l l
Power Supply Module

l l l l
Accesses two -48 V or -60 V DC power supplies. Supplies working power for each module on the CXPG/CXPH. Supplies 12 V power for the FAN board. Supplies 3.3 V power for the interface board.
2.3.4 Front Panel

On the front panel of the CXPG/CXPH, there are indicators, buttons, and interfaces.

Figure 2-5 shows the appearance of the front panel of the CXPG/CXPH. Figure 2-5 Appearances of the front panel of the CXPG and CXPH
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Indicators
The following indicators are present on the front panel of the CXPG/CXPH:
l l l l l l l l l l
STAT indicator, red, green, or orange, which indicates the working status PROG indicator, red or green, which indicates the running status of the program SYNC indicator, red or green, which indicates the clock synchronization status SRV indicator, red, green, or orange, which indicates the service status L/A1 and L/A2 indicators, orange or green, which indicate the connection status of the port CRIT indicator, red, which indicates critical alarms MAJ indicator, orange, which indicates major alarms MIN indicator, yellow, which indicates minor alarms LINK indicator, green, which indicates the port connection status ACT indicator, yellow, which indicates the data transceiving status of the port
NOTE
Above the ETH/OAM and four FE service interfaces, five pairs of LINK and ACT indicators are present, which indicate the connection status of the Ethernet interface.
For details on indications of indicators, see B Indicators.
Buttons
The following buttons are present on the front panel of the CXPG/CXPH:
l
RST button, which is used for warm reset of the board. When you press the RST button and then release it, the board is reset (warm). CF RCV button, which is used to restore the configuration data from the CF card. When you hold down the CF RCV button for five seconds, the equipment automatically restores the configuration data from the CF card. LAMP button, which is used to test the indicators. When you press the LAMP button, except the LINK indicators on the ADS2A/ADS2B, the FE service port indicators on the EF8T/EF8F/CXPG/CXPH, and the L/A indicators on the CXPG/CXPH, all the board indicators on the NE are on.
Interfaces
Table 2-14 lists the types and usage of the interfaces on the CXPG/CXPH. Table 2-14 Interfaces on the CXPG/CXPH Interface Name ETH/ OAM Interfac e Type RJ-45 Usage 10M/100M interface for NM network port or NM serial port Pin For details, see Table 2-15. Correspondin g Cable For details, see 5.5 Management Cables.
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Interface Name CLK1/ TOD1 CLK2/ TOD2 PHONE
Interfac e Type RJ-45
Usage External time/clock input/ output interface
Pin For details, see Table 2-16.
Correspondin g Cable For details, see 5.6 Clock Cables.
RJ-45
Orderwire interface
For details, see 5.5 Management Cables. For details, see 5.4.1 Ethernet Cables. For details, see 5.1.1 Fiber Types. For details, see 5.4.2 75-Ohm 16 x E1 Cablesand 5.4.3 120-Ohm 16 x E1 Cables.
FE1 to FE4 OUT1 IN1, OUT2 IN2 E1 (1 to 16)
RJ-45
Input/output interface for FE electrical signals Input/output interface for GE optical signals
For details, see Table 2-18. For details, see Table 2-19.
LC
Anea 96
E1 service input/output interface
NOTE The FE1 to FE4 interfaces and ETH/OAM interface support auto-adaptation to a straight-through network cable or a crossover network cable. The matched impedance of the E1 service interface on the CXPG is 75 ohms and the matched impedance of the E1 interface on the CXPH is 120 ohms. The PHONE interface is reserved for later use.
Table 2-15 lists the pins of the ETH/OAM interface. Table 2-15 Pins of the ETH/OAM interface Front View Pin 1 2
87654321
Usage Transmit positive of the NM network port Transmit negative of the NM network port Receive positive of the NM network port Grounding end of the NM serial port Receive end of the NM serial port Receive negative of the NM network port
3 4 5 6
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Front View
Pin 7 8
Usage Unspecified Transmit end of the NM serial port
Table 2-16 lists the pins of the CLK1/TOD1 and CLK2/TOD2 interfaces. Table 2-16 Pins of the CLK1/TOD1 and CLK2/TOD2 interfaces Front View Pi n Working Mode Externa l Clock External Time Input (1PPS + Time Informatio n) 1 Receive negative of the CLK Receive positive of the CLK Unspeci fied Unspecified External Time Output (1PPS + Time Information) External Time Input (DCLS) External Time Output (DCLS)
Unspecified
Unspecified
Unspecified
87654321
Unspecified
Unspecified
Unspecified
Unspecified
Input negative for the 1PPS signal (RS422 level)
Output negative for the 1PPS signal (RS422 level) Grounding end
Input negative for the DCLS time signal (RS422 level) Grounding end
Output negative for the DCLS time signal (RS422 level) Grounding end
Transmi t negative of the CLK Transmi t positive of the CLK Unspeci fied
Grounding end
Grounding end
Grounding end
Grounding end
Grounding end
Input positive Output positive for the 1PPS for the 1PPS signal signal (RS422 level) (RS422 level)
Input positive for the DCLS time signal (RS422 level)
Output positive for the DCLS time signal (RS422 level)
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Front View
Pi n
Working Mode Externa l Clock External Time Input (1PPS + Time Informatio n) External Time Output (1PPS + Time Information) External Time Input (DCLS) External Time Output (DCLS)
Unspeci fied
Input negative for the time information (RS422 level)
Output negative for the time information (RS422 level)
Unspecified
Unspecified
Unspeci fied
Input positive Output positive for the time for the time information information (RS422 level) (RS422 level)
Unspecified
Unspecified
NOTE
The CLK1/TOD1 and CLK2/TOD2 interfaces can be configured so that they can work in one of the preceding five working modes.
Table 2-17 lists the pins of the PHONE interface. Table 2-17 Pins of the PHONE interface Front View Pin 1 to 3 4
87654321
Usage Unspecified RING TIP Unspecified
5 6 to 8
Table 2-18 lists the pins of the FE1 interface to FE4 interface. Table 2-18 Pins of the FE1 interface to FE4 interface Front View Pin 1 2
87654321
Usage Positive of twisted pair 1 Negative of twisted pair 1 Positive of twisted pair 2
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Front View
Pin 4 5 6 7 8
Usage Undefined Undefined Negative of twisted pair 2 Undefined Undefined
Table 2-19 list the pins of the OUT1 IN1 and OUT2 IN2 interfaces. Table 2-19 Pins of the GE optical interfaces Interface on the Front Panel Optical interface IN1 to IN2 Interface Type LC Usage When a two-fiber bidirectional optical module is used, this interface is used as an input interface for the GE optical signal. When a single-fiber bidirectional optical module is used, this interface is not used. OUT1 to OUT2 LC When a two-fiber bidirectional optical module is used, this interface is used as an output interface for the GE optical signal. When a single-fiber bidirectional optical module is used, this interface is used as an input/output interface for the GE optical signal.
NOTE The SFP interface should be used with an optical module.
l When a two-fiber bidirectional optical module is used, two LC interfaces are provided on the left and
right sides of the optical module. Each interface uses one fiber, which is used to transmit or receive service signals.
l When a single-fiber bidirectional optical module is used, only one LC interface is provided on the left
side of the optical module. This optical interface uses only one fiber, which is used to transmit and receive service signals at the same time.
Table 2-20 Pins of the Anea 96 interface Front View Connector Pin 1 2 3 Rx2 Usage Rx1 Connector Pin 25 26 27 Tx2 Usage Tx1
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Front View
Connector Pin 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 49 50 51 52 53 54 55 56
Usage
Connector Pin 28
Usage
Rx3
29 30
Tx3
Rx4
31 32
Tx4
Rx5
33 34
Tx5
Rx6
35 36
Tx6
Rx7
37 38
Tx7
Rx8
39 40
Tx8
Rx9
41 42
Tx9
R x 10
43 44
T x 10
R x 11
45 46
T x 11
R x 12
47 48
T x 12
R x 13
73 74
T x 13
R x 14
75 76
T x 14
R x 15
77 78
T x 15
R x 16
79 80
T x 16
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2.3.5 Valid Slots

Two slots house one CXPG/CXPH. The CXPG/CXPH can be housed in slots 1 and 2.

The CXPG/CXPH can be configured through the U2000. You can use the U2000 to set the following parameters for the CXPG/CXPH:
l l l l
Ethernet interface PDH interface External time interface Phase-locked source output by External clock

The technical specifications of the CXPG cover the interface specifications, board dimensions, weight, and power consumption.
Interface Specifications
The interface specifications of the CXPG are as follows:
l l l
For the specifications of the FE electrical interface, see Table 2-21. For the specifications of the GE optical interface, see Table 2-22. For the specifications of the E1 interface, see Table 2-25.
Table 2-21 Specifications of the FE electrical interface Item Specification Requirement FE electrical interface Interface rate RJ-45 electrical interface specification 100 Mbit/s. Complies with IEEE 802.3 and enterprise regulations.
Table 2-22 Technical specifications of the GE optical interface Item Optical interface type Specification Two-fiber bidirectional interface Single-fiber bidirectional interface
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Item
Specification 1000BASESX (0.5 km) 1000BASELX (10 km) Single-mode 1270 to 1360 1000BASEVX (40 km) Single-mode 1260 to 1360 1000BASEZX (80 km) Single-mode 1500 to 1580 1000BASECWDM (80 km) Single-mode For details, see wavelength allocation of 1000BASECWDM optical interfaces and related optical module code. 0 to 5 1000BASEBX (10 km) Single-mode For details, see wavelength allocation of 1000BASEBX optical interfaces and related optical module code. -9 to -3
Fiber type Working wavelength range (nm)
Multi-mode 770 to 860
Mean launched optical power (dBm) Receiver sensitivity (dBm) Minimum overload (dBm) Minimum extinction ratio (dB) Optical module code
-9.5 to 0
-11 to -3
-5 to 0
-2 to 5
-17
-19
-22
-22
-28
-19.5
-3
-3
-3
-9
-3
8.2
34060286
34060473 34060290
34060298
34060360 34060324
For details, see wavelength allocation of 1000BASECWDM optical interfaces and related optical module code.
For details, see wavelength allocation of 1000BASEBX optical interfaces and related optical module code.
NOTE For details of the optical module, see 4.2 Optical Module Labels.
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Table 2-23 Wavelength allocation of 1000BASE-CWDM optical interfaces and related optical module code SN 1 2 3 4 Optical module code 34060483 34060481 34060479 34060482 Wavelength (nm) 1464.5 to 1477.5 1484.5 to 1497.5 1504.5 to 1517.5 1524.5 to 1537.5 SN 5 6 7 8 Optical module code 34060478 34060476 34060477 34060480 Wavelength (nm) 1544.5 to 1557.5 1564.5 to 1577.5 1584.5 to 1597.5 1604.5 to 1617.5
Table 2-24 Wavelength allocation of 1000BASE-BX optical interfaces and related optical module code Item Optical module code Transmitter wavelength (nm) Receiver wavelength (nm) Local 34060470 1260 to 1360 1480 to 1500 Remote 34060475 1480 to 1500 1260 to 1360
Table 2-25 Specifications of the E1 interface Item Nominal bit rate (kbit/s) Interface impedance Specification Requirement 2048 75 ohms (CXPG) 120 ohms (CXPH) Interface code Pulse waveform at the output interface Attenuation tolerance of the input interface at the point with a frequency of 1024 kHz (dB) Anti-interference capability of the input interface Input jitter tolerance Output jitter HDB3 Complies with ITU-T G.703 0 to 6
Other Specifications
Board dimensions (mm): 20.3 (H) x 226.0 (D) x 388.4 (W) Board weight (kg): 1.32
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Power consumption (W): 46.8
2.4 EF8T
This section describes the EF8T, which is an interface board with eight FE electrical interfaces, with regard to the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.4.1 Version Description The functional version of the EF8T is TND1. 2.4.2 Functions and Features The EF8T mainly accesses 8 x FE electrical signals, and processes the services with the CXPA/ CXPB/CXPG/CXPH. 2.4.3 Working Principle and Signal Flow The EF8T mainly consists of the access and convergence module, control driver module, clock module, and power supply module. 2.4.4 Front Panel On the front panel of the EF8T, there are indicators and interfaces. 2.4.5 Valid Slots The EF8T can be housed in any of slots 3 - 4 in the slot area. 2.4.6 Board Configuration Reference You can use the U2000 to set parameters for the EF8T. 2.4.7 Technical Specifications The technical specifications of the EF8T include the interface specifications, board dimensions, weight, and power consumption.

The functional version of the EF8T is TND1.

The EF8T mainly accesses 8 x FE electrical signals, and processes the services with the CXPA/ CXPB/CXPG/CXPH. Table 2-26 lists the functions and features of the EF8T. Table 2-26 Functions and features of the EF8T Function and Feature Basic function Description Supports eight FE electrical interfaces. Accesses 8 x FE electrical signals, and processes the services with the CXPA/CXPB/CXPG/ CXPH. Supports the inband DCN. By default, the DCN function is enabled at the first four ports. In addition, this function can be disabled or enabled manually.
2 Boards
Description Supports the hot swappable function. Detects the temperature and voltage of the board.
Interface function
Type of the loopback at the port
PHY-layer inloop MAC-layer outloop
Automatic loopback release at the port LAG Intra-board LAG Inter-board LAG Black list and white list of MAC addresses Clock Supported Synchronous Ethernet SSM protocol IEEE 1588V2 protocol 1588 ACR clock
Supported Supported Supported
Supported Supported Supported Supported

The EF8T mainly consists of the access and convergence module, control driver module, clock module, and power supply module. Figure 2-6 shows the block diagram for the functions of the EF8T. Figure 2-6 Block diagram for the functions of the EF8T
Backplane
8 x FE electrical signals
Access and convergence module
Service bus
Control driver module
Management bus Service bus
CXP CXP
Clock signals Clock signals
Clock module
Clock signals
CXP
3.3 V 1.2 V
Power supply module
-48 V/-60 V -48 V/-60 V
PIU PIU
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NOTE
As shown in Figure 2-6, the CXP on the backplane indicates the system control, cross-connect and protocol processing board. For OptiX PTN 910, the CXP indicates the CXPA/CXPB/CXPG/CXPH.
Access and Convergence Module

l l l l
Accesses 8 x FE electrical signals. Buffers FE signals to avoid packet loss. Provides flow control frames to control the number of packets. Processes the IEEE 1588V2 packets.
Control Driver Module

l
Detects the system status through the management bus.

Detects any fault of the system control board. Detects whether board is loosened from the slot. Detects the voltage and temperature.
Realizes the hot swappable function of the board.
Clock Module
l l l l
Provides the working clock for each module on the board. Supports the synchronous Ethernet and the SSM protocol. Supports the IEEE 1588V2 protocol. Supports the 1588 ACR clock.
Power Supply Module

l l
Accesses two -48 V DC or -60 V DC power supplies. Supplies 3.3 V and 1.2 V power for the EF8T.
2.4.4 Front Panel

On the front panel of the EF8T, there are indicators and interfaces.

Figure 2-7 shows the appearance of the front panel of the EF8T.
2 Boards
Figure 2-7 Font panel of the EF8T
Indicator
The following indicators are present on the front panel of the EF8T:
l l l l
STAT indicator, red, green, or orange, which indicates the working status SRV indicator, red, green, or orange, which indicates the service status LINK indicator, green, which indicates the connection status of the port ACT indicator, yellow, which indicates the data transceiving status of the port
NOTE
There are eight LINK indicators and eight ACT indicators. One LINK indicator and one ACT indicator are present above each FE service interface.
Interface
Table 2-27 lists the types and usage of the interfaces on the EF8T. Table 2-27 Types and usage of interfaces on the EF8T Interface on the Front Panel FE1 - FE8 Interface Type RJ-45 Usage Pin Correspondin g Cable For details, see 5.4.1 Ethernet Cables.
Input/output interfaces for FE electrical signals
NOTE The FE1 to FE8 interfaces support auto-adaptation to a straight-through network cable or a crossover network cable.
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Table 2-28 Pins of the RJ-45 connector of the EF8T Front View Pin 1 2
87654321
Usage Positive of twisted pair 1 Negative of twisted pair 1 Positive of twisted pair 2 Unspecified Unspecified Negative of twisted pair 2 Unspecified Unspecified
3 4 5 6 7 8
2.4.5 Valid Slots

The EF8T can be housed in any of slots 3 - 4 in the slot area.

You can use the U2000 to set parameters for the EF8T. You can use the U2000 to set the following parameter for the EF8T: Ethernet interface For details on the parameters, see D Board Configuration Parameters.

The technical specifications of the EF8T include the interface specifications, board dimensions, weight, and power consumption. Table 2-29 lists the specifications of the electrical interfaces of the EF8T. Table 2-29 Specifications of interfaces on the EF8T Item FE electrical signal interface rate RJ-45 electrical interface specification Specification 100 Mbit/s Complies with IEEE 802.3 and enterprise regulations.
2 Boards
2.5 EF8F
This section describes the EF8F, which is an interface board with eight FE optical interfaces, with regard to the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.5.1 Version Description The functional version of the EF8F is TND1. 2.5.2 Functions and Features The EF8F mainly accesses 8 x FE optical signals, and processes the services with the CXPA/ CXPB/CXPG/CXPH. 2.5.3 Working Principle and Signal Flow The EF8F mainly consists of the access and convergence module, control driver module, clock module, and power supply module. 2.5.4 Front Panel On the front panel of the EF8F, there are indicators and interfaces. 2.5.5 Valid Slots The EF8F can be housed in any of slots 3 - 4 in the slot area. 2.5.6 Board Configuration Reference You can use the U2000 to set parameters for the EF8F. 2.5.7 Technical Specifications The technical specifications of the EF8F include the interface specifications, board dimensions, weight, and power consumption.

The functional version of the EF8F is TND1.

The EF8F mainly accesses 8 x FE optical signals, and processes the services with the CXPA/ CXPB/CXPG/CXPH. Table 2-30 lists the functions and features of the EF8F. Table 2-30 Functions and features of the EF8F Function and Feature Basic function Description Supports eight FE optical interfaces. Accesses 8 x FE optical signals, and processes the services with the CXPA/CXPB/ CXPG/CXPH. Supports the inband DCN. By default, the DCN function is enabled at the first four ports. In addition, this function can be disabled or enabled manually. Supports the hot swappable function.
2 Boards
Description Detects the temperature and voltage of the board.
Interface function
Type of the loopback at the port Automatic loopback release at the port
PHY-layer inloop MAC-layer outloop Supported Supported Supported
LAG
Black list and white list of MAC addresses Clock
Supported Synchronous Ethernet SSM protocol IEEE 1588V2 protocol 1588 ACR clock Supported Supported Supported Supported

The EF8F mainly consists of the access and convergence module, control driver module, clock module, and power supply module. Figure 2-8 shows the block diagram for the functions of the EF8F. Figure 2-8 Block diagram for the functions of the EF8F
Backplane
8 x FE optical signals
Access and convergence module
Service bus
CXP CXP
Clock signals
Clock signals
Clock module
Clock signals
CXP
Each module on the board Each module on the board
3.3 V 1.2 V
Power supply module
-48 V/-60 V -48 V/-60 V
PIU PIU
NOTE
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Access and Convergence Module

l l l l
Accesses 8 x FE optical signals. Buffers FE signals to avoid packet loss. Provides flow control frames to control the number of packets. Processes the IEEE 1588V2 packets.
Control Driver Module

l
Detects the system status through the management control bus.

Checks whether any fault occurs on the system control board. Detects whether board is loosened from the slot. Detects the voltage and temperature.
Clock Module
l l l l
Provides the working clock for each module on the EF8F. Supports the synchronous Ethernet and the SSM protocol. Supports the IEEE 1588V2 protocol. Supports the 1588 ACR clock.
Power Supply Module

l l
Accesses two - 48 V DC or - 60 V DC power supplies. Supplies 3.3 V and 1.2 V power for the EF8F.
2.5.4 Front Panel

On the front panel of the EF8F, there are indicators and interfaces.

Figure 2-9 shows the appearance of the front panel of the EF8F. Figure 2-9 Font panel of the EF8F
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Indicators
The following indicators are present on the front panel of the EF8F:
l l l
STAT indicator, red, green, or orange, which indicates the working status SRV indicator, red, green, or orange, which indicates the service status LINK1 to LINK8 indicators, green, which indicate the connection status of the port
Interfaces
Eight SFP interfaces are present on the EF8F. Table 2-31 lists the types and usage of the interfaces. Table 2-31 Interfaces of the EF8F Interface on the Front Panel IN1 - IN8 Interface Type Usage Corresponding Fiber
LC
When a two-fiber bidirectional optical module is used, this interface is used as an input interface for the FE optical signal. When a single-fiber bidirectional optical module is used, this interface is not used.
For details, see 5.1.1 Fiber Types.
OUT1 OUT8
LC
When a two-fiber bidirectional optical module is used, this interface is used as an output interface for the FE optical signal. When a single-fiber bidirectional optical module is used, this interface is used as an input/output interface for the FE optical signal.

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2.5.5 Valid Slots

The EF8F can be housed in any of slots 3 - 4 in the slot area.

You can use the U2000 to set parameters for the EF8F. You can use the U2000 to set the following parameter for the EF8F: Ethernet interface For details on the parameters, see D Board Configuration Parameters.

The technical specifications of the EF8F include the interface specifications, board dimensions, weight, and power consumption. Table 2-32 lists the specifications of the optical interfaces of the EF8F. Table 2-32 Performance specifications of the FE optical interface Item Optical interface type Specification Two-fiber bidirectional interface 100BASE-FX (15 km) Fiber type Working wavelength range (nm) Single-mode 1261 to 1360 100BASE-FX (40 km) Single-mode 1263 to 1360 100BASE-FX (80 km) Single-mode 1480 to 1580 Single-fiber bidirectional interface 100BASE-BX (10 km) Single-mode For details, see wavelength allocation of 100BASE-BX optical interfaces and related optical module code. -15 to -8 100BASE-BX (40 km) Single-mode For details, see wavelength allocation of 100BASE-BX optical interfaces and related optical module code. -5 to 0
Mean launched optical power (dBm) Receiver sensitivity (dBm) Minimum overload (dBm) Minimum extinction ratio (dB)
-15 to -8
-5 to 0
-5 to 0
-28
-34
-34
-28.2
-30
-8 8.2
-10 10
-10 10
-8 6.6
-10 10
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Item Optical module code
Specification 34060276 34060307 34060281 34060308 34060282 34060309 For details, see wavelength allocation of 100BASE-BX optical interfaces and related optical module code. For details, see wavelength allocation of 100BASE-BX optical interfaces and related optical module code.
Table 2-33 Wavelength allocation of 100BASE-BX optical interfaces and related optical module code Item Optical module code (10 km) Optical module code (40 km) Transmitter wavelength (nm) Receiver wavelength (nm) 1260 to 1360 1480 to 1580 1480 to 1580 1260 to 1360 34060328 34060329 Local 34060363 Remote 34060364
2.6 EG2
This section describes the EG2, which is an interface board with two GE optical interfaces, with regard to the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.6.1 Version Description The functional version of the EG2 is TND1. 2.6.2 Functions and Features The EG2 mainly accesses 2 x GE signals, and processes the services with the CXPA/CXPB/ CXPG/CXPH. 2.6.3 Working Principle and Signal Flow The EG2 mainly consists of the interface conversion module, control driving module, clock module, and power supply module. 2.6.4 Front Panel
2 Boards
On the front panel of the EG2, there are indicators and interfaces. 2.6.5 Valid Slots The EG2 can be housed in any of slots 3 to 4 in the slot area. 2.6.6 Board Configuration Reference You can use the U2000 to set parameters for the EG2. 2.6.7 Technical Specifications The technical specifications of the EG2 include the interface specifications, board dimensions, weight, and power consumption.

The functional version of the EG2 is TND1.

The EG2 mainly accesses 2 x GE signals, and processes the services with the CXPA/CXPB/ CXPG/CXPH. Table 2-34 lists the functions and features of the EG2. Table 2-34 Functions and Features of the EG2 Function and Feature Basic function Description Supports two GE optical interfaces. Accesses 2 x GE signals, and processes the services with the CXPA/CXPB/CXPG/ CXPH. Supports the inband DCN. By default, the DCN function is enabled at the two ports. In addition, this function can be disabled or enabled manually. Supports the hot swappable function. Detects the temperature and voltage of the board. Interface function Type of the loopback at the port PHY-layer inloop and outloop MAC-layer outloop Automatic loopback release at the port LAG Intra-board LAG Inter-board LAG Black list and white list of MAC addresses Clock Supported Synchronous Ethernet SSM protocol Supported Supported Supported Supported Supported
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Description IEEE 1588V2 protocol 1588 ACR clock Supported Supported

The EG2 mainly consists of the interface conversion module, control driving module, clock module, and power supply module. Figure 2-10 shows the block diagram for the functions of the EG2. Figure 2-10 Block diagram for the functions of the EG2
Backplane
2 x GE signals
Interface conversion module
Service bus
CXP CXP
Clock signals
Clock signals
Clock module
Clock signals
CXP
Each module on the board Each module on the board
3.3 V 1.2 V
Power supply module
-48 V/-60 V -48 V/-60 V
PIU PIU
NOTE
Interface Conversion Module

l l
Accesses 2 x GE services in two directions. Supports ESFP optical interfaces and GE colored optical interfaces. Select a proper optical interface for single-mode or multi-mode transmission over a specified distance.
Control Driving Module


l
2 Boards
Detects the system status through the management bus.

Detects any fault of the system control board. Detects whether board is loosened from the slot. Detects the voltage and temperature.
Clock module
l l l l
Provides the working clock for each module on the EG2. Supports the synchronous Ethernet and the SSM protocol. Supports the IEEE 1588V2 protocol. Supports the 1588 ACR clock.
Power Supply Module

l l
Accesses two -48 V DC or -60 V DC power supplies. Supplies 3.3 V or 1.2 V power for each module on the EG2.
2.6.4 Front Panel

On the front panel of the EG2, there are indicators and interfaces.

Figure 2-11 shows the appearance of the front panel of the EG2. Figure 2-11 Font panel of the EG2
Indicators
The following indicators are present on the front panel of the EG2.
l l l l
STAT indicator, red, green, or orange, which indicates the working status SRV indicator, red, green, or orange, which indicates the service status LINK1 to LINK2 indicators, green, which indicate the connection status of the port ACT1 to ACT2 indicators, yellow, which indicate the data transceiving status of the port

2 Boards
Interfaces
Two SFP interfaces are present on the EFG2. Table 2-35 lists the types and usage of the interfaces on the EG2. Table 2-35 Types and usage of optical interfaces on the EG2 Interface on the Front Panel Optical interfac e IN1, IN2 Interf ace Type LC Usage Correspond ing Fiber For details, see 5.1.1 Fiber Types.
When a two-fiber bidirectional optical module is used, this interface is used as an input interface for the GE optical signal. When a single-fiber bidirectional optical module is used, this interface is not used.
OUT1, OUT2
LC
When a two-fiber bidirectional optical module is used, this interface is used as an output interface for the GE optical signal. When a single-fiber bidirectional optical module is used, this interface is used as an input/output interface for the GE optical signal.

2.6.5 Valid Slots

The EG2 can be housed in any of slots 3 to 4 in the slot area.

You can use the U2000 to set parameters for the EG2. You can use the U2000 to set the following parameter for the EG2: Ethernet interface For details on the parameters, see D Board Configuration Parameters.

The technical specifications of the EG2 include the interface specifications, board dimensions, weight, and power consumption.
2 Boards
Table 2-36 list the specifications of the interfaces on the EG2. Table 2-36 Technical specifications of the GE optical interface Item Optical interface type Specification Two-fiber bidirectional interface Single-fiber bidirectional interface 1000BASEZX (80 km) Single-mode 1500 to 1580 1000BASECWDM (80 km) Single-mode For details, see wavelength allocation of 1000BASECWDM optical interfaces and related optical module code. 0 to 5 1000BASEBX (10 km) Single-mode For details, see wavelength allocation of 1000BASEBX optical interfaces and related optical module code. -9 to -3
1000BASESX (0.5 km) Fiber type Working wavelength range (nm) Multi-mode 770 to 860
1000BASELX (10 km) Single-mode 1270 to 1360
1000BASEVX (40 km) Single-mode 1260 to 1360
-9.5 to 0
-11 to -3
-5 to 0
-2 to 5
-17
-19
-22
-22
-28
-19.5
-3
-3
-3
-9
-3
8.2
34060286
34060473 34060290
34060298
34060360 34060324
For details, see wavelength allocation of 1000BASECWDM optical interfaces and related optical module code.
For details, see wavelength allocation of 1000BASEBX optical interfaces and related optical module code.
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Table 2-37 Wavelength allocation of 1000BASE-CWDM optical interfaces and related optical module code SN 1 2 3 4 Optical module code 34060483 34060481 34060479 34060482 Wavelength (nm) 1464.5 to 1477.5 1484.5 to 1497.5 1504.5 to 1517.5 1524.5 to 1537.5 SN 5 6 7 8 Optical module code 34060478 34060476 34060477 34060480 Wavelength (nm) 1544.5 to 1557.5 1564.5 to 1577.5 1584.5 to 1597.5 1604.5 to 1617.5
Table 2-38 Wavelength allocation of 1000BASE-BX optical interfaces and related optical module code Item Optical module code Transmitter wavelength (nm) Receiver wavelength (nm) Local 34060470 1260 to 1360 1480 to 1500 Remote 34060475 1480 to 1500 1260 to 1360
2.7 ML1/ML1A
This section describes the ML1/ML1A, which is a 16 x E1 electrical interface board, with regard to the version, functions, features, working principle, front panel, valid slots, and technical specifications.
NOTE
The ML1 and ML1A have the same functions and features except for the matched impedance (ML1: 75 ohms E1; ML1A: 120 ohms E1).
2.7.1 Version Description The functional version of the ML1/ML1A is TND1. 2.7.2 Functions and Features The ML1 is a 75-ohm E1 board and the ML1A is a 120-ohm E1 board. The ML1/ML1A can access a maximum of 16 x E1 signals, supports flexible configuration of different services on each port, and is hot swappable. 2.7.3 Working Principle and Signal Flow The ML1/ML1A mainly consists of the control module, line-side processing module, systemside processing module, backplane interface module, clock module, and power supply module. 2.7.4 Front Panel On the front panel of the ML1/ML1A, there are indicators and interfaces.
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2.7.5 Valid Slots The ML1/ML1A can be housed in any of slots 3 - 4. 2.7.6 Board Configuration Reference You can use the U2000 to set parameters for the ML1/ML1A. 2.7.7 Technical Specifications The technical specifications of the TND1ML1/TND1ML1A include the interface specifications, dimensions, weight, and power consumption.

The functional version of the ML1/ML1A is TND1.

The ML1 is a 75-ohm E1 board and the ML1A is a 120-ohm E1 board. The ML1/ML1A can access a maximum of 16 x E1 signals, supports flexible configuration of different services on each port, and is hot swappable. Table 2-39 lists functions and features of the ML1/ML1A . Table 2-39 Functions and features of the ML1/ML1A Function and Feature Basic functions Remarks Accesses and processes 16 x E1 signals and supports the ATM E1, IMA, CES, and ML-PPP protocols. Supports the in-band DCN. By default, the DCN function is enabled at the first and the sixteenth E1 ports. In addition, this function can be disabled or enabled manually. Fractional E1 PRBS ATM/IMA Supports the CES services and IMA services at 64 kbit/s level. Supports the PRBS function in framed or unframed mode of an E1 port in the receive/transmit direction. Number of supported IMA groups /supported ATM E1 services Maximum number of E1 links or 64 kbit/s level serial ports in each IMA group 16 8
Dynamically enables or disables the IMA group, restarts the IMA group protocol, and dynamically adds or deletes the IMA group members.
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Remarks Supported traffic types CBR UBR UBR+ rt-VBR nrt-VBR Number of supported ATM connections (VPC and VCC included) Number of supported ATM services 64 256 remote connections 128 local connections
Encapsulates ATM VPC/VCC service to the PWE3 in the Nto-1 (N32) or 1-to-1 format. Encapsulates the ATM cells to the PW in the concatenation and non-concatenation modes. The number of PW connections that support the cell concatenation is 64, and the maximum number of concatenated cells is 31. ATM OAM on the UNI side and NNI side CES Number of supported CES services Supported emulation mode Supports the CC test. Supports the LB test. 16 CESoPSN SAToP Supports the timeslot compression function. Provides the idle 64 kbit/s timeslot suppression function for the CES services in the CESoPSN mode to save the transmission bandwidth. Supported clock modes Retiming mode Self-adaptation mode The jitter compensation buffer time of the CES service can be set. The jitter buffer time ranges from 0.375 ms to 16 ms, and the step value is 0.125 ms. The packet loading time of the CES service can be set. The encapsulation buffer time ranges from 0.125 ms to 3 ms, and the step value is 0.125 ms. ML-PPP Number of supported MLPPP groups Maximum number of links supported by each ML-PPP group 7 16
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Remarks Functions as the NNI interface.

The ML1/ML1A mainly consists of the control module, line-side processing module, systemside processing module, backplane interface module, clock module, and power supply module. Figure 2-12shows the block diagram for the working principle of the ML1/ML1A. Figure 2-12 Block diagram for the working principle of the ML1/ML1A
Backplane
1.2 V 1.26 V To each module 2.5 V 3.3 V -48 V/-60 V
Power supply module
-48 V/-60 V 3.3 V
16 x E1 signals
Line-side processing module
Service bus
System-side processing module
Service bus
Backplane interface module
Service bus
CXP
Management bus Management bus
Control module
Serial management bus
CXP
To each module
Clock signals
Clock module
Clock signals
CXP
NOTE
In Transmit Direction
The ML1/ML1A first distributes the signals in Ethernet packets from the backplane to different protocol processing chips according to the service types. The system-side processing module decapsulates the concatenated services and buffers the services in queues. Then, this module schedules the egress queues according to the service types, processes and converts the services, and finally sends the services to the line-side processing module. The line-side processing module performs coding, dejitter, pulse shaping, and line driving for the services, and finally sends the services to E1 interfaces.
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In Receive Direction
The line processing module performs impedance match, signal equalization, signal level conversion, clock data recovery, dejitter, and decoding for the accessed E1 signals. Then, the signals are sent into the system-side processing module, which frames the signals, encapsulates the IMA, CES, and ML-PPP services in PWE3, and schedules PWs. Finally, this module sends the signals in Ethernet packets to the backplane interface module.
Line-Side Processing Module

In the receive channel, this module performs impedance match, signal equalization, electrical level conversion, clock data recovery, dejitter, and decoding to signals. In the transmit channel, this module performs encoding, dejitter, pulse shaping, and line driving to signals.
System-Side Processing Module

This module frames 16 x E1 signals, runs the CES, IMA, and ML-PPP protocols, and performs PWE3 encapsulation.
Backplane Interface Module

The service bus receives or transmits service signals.
Control Module
This module controls the reading and writing on the chip, resets the chip, and detects faults in the chip.When used with the CXPA/CXPB/CXPG/CXPH, this module controls the board.
Clock Module
This module provides various clock signals for the board to operate normally, detects clocks, and selects the line recovery clock.
Power Supply Module

This module converts the -48 V DC/-60 V DC voltage to DC voltages required by each module on the board. In addition, this module supplies 3.3 V power to the ML1/ML1A through the backplane.
2.7.4 Front Panel

On the front panel of the ML1/ML1A, there are indicators and interfaces.

Figure 2-13 shows the appearance of the front panel of the ML1. Figure 2-13 Front panel of the ML1
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Figure 2-14 shows the appearance of the front panel of the ML1A. Figure 2-14 Front panel of the ML1A
Indicators
The following indicators are present on the front panel of the ML1/ML1A:
l l
STAT indicator, red, green, or orange, which indicates the working status SRV indicator, red, green, or orange, which indicates the service status
Interfaces
There is one Anea 96 interface on the front panel of the ML1/ML1A. Table 2-40 lists the type and usage of the interface. For cables corresponding to the interfaces, see 5.4.2 75-Ohm 16 x E1 Cablesand 5.4.3 120-Ohm 16 x E1 Cables. Table 2-40 Type and usage of the interface on the front panel of the ML1 Interface on the Front Panel 1 - 16 Interface Type Usage ML1 75-ohm interface, which is used to transmit or receive the first to sixteenth channels of E1 services. ML1A 120-ohm interface, which is used to transmit or receive the first to sixteenth channels of E1 services.
Anea 96
Table 2-41 lists the pins of the Anea 96 interface. Table 2-41 Pins of the Anea 96 interface Front View Connector Pin 1 2 3 4 5
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Usage Rx1
Connector Pin 25 26
Usage Tx1
Rx2
27 28
Tx2
Rx3
29
Tx3
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Front View
Connector Pin 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 49 50 51 52 53 54 55 56
Usage
Connector Pin 30
Usage
Rx4
31 32
Tx4
Rx5
33 34
Tx5
Rx6
35 36
Tx6
Rx7
37 38
Tx7
Rx8
39 40
Tx8
Rx9
41 42
Tx9
R x 10
43 44
T x 10
R x 11
45 46
T x 11
R x 12
47 48
T x 12
R x 13
73 74
T x 13
R x 14
75 76
T x 14
R x 15
77 78
T x 15
R x 16
79 80
T x 16
2.7.5 Valid Slots

The ML1/ML1A can be housed in any of slots 3 - 4.
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You can use the U2000 to set parameters for the ML1/ML1A. You can use the U2000 to set the following parameters for the ML1/ML1A:
l l
PDH interface Spare timeslot recovery value

The technical specifications of the TND1ML1/TND1ML1A include the interface specifications, dimensions, weight, and power consumption. Table 2-42 lists the specifications of the interfaces on the ML1/ML1A. Table 2-42 Specifications of the interfaces on the ML1/ML1A Item Nominal bit rate (kbit/s) Interface impedance Specification Requirement 2048 75 ohms (ML1) 120 ohms (ML1A) Interface code Pulse waveform at the output interface Attenuation tolerance of the input interface at the point with a frequency of 1024 kHz (dB) Anti-interference capability of the input interface Input jitter tolerance Output jitter HDB3 Complies with ITU-T G.703 0 to 6
2.8 CD1
This section describes the CD1, which is a 1 x channelized STM-1 service processing board, in terms of the version, functions, features, working principle, front panel, valid slots, and technical specifications.
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2.8.1 Version Description The functional version of the CD1 is TND1. 2.8.2 Functions and Features The CD1 accesses 1 x channelized STM-1 services, and supports the intra-board LMSP protection.. When used with the CXPA/CXPB/CXPG/CXPH, the CD1 processes the service signals. The CD1 supports the IMA, CES, and ML-PPP protocols, and the service type can be flexibly configured. 2.8.3 Working Principle and Signal Flow The CD1 consists of the SDH processing module, line processing module, data processing module, management module, clock module, and power supply module. 2.8.4 Front Panel On the front panel of the CD1, there are indicators and interfaces. 2.8.5 Valid Slots The CD1 can be housed in any of the two slots, that is, slots 3 and 4. 2.8.6 Board Configuration Reference You can use the U2000 to configure parameters for the CD1. 2.8.7 Technical Specifications The technical specifications of the CD1 cover the interface specifications, board dimensions, weight, and power consumption.

The functional version of the CD1 is TND1.

The CD1 accesses 1 x channelized STM-1 services, and supports the intra-board LMSP protection.. When used with the CXPA/CXPB/CXPG/CXPH, the CD1 processes the service signals. The CD1 supports the IMA, CES, and ML-PPP protocols, and the service type can be flexibly configured. Table 2-43 lists functions and features of the CD1. Table 2-43 Functions and features of the CD1 Function and Feature Basic function Fractional E1 Interface function Remarks Service interfaces on the front panel Supports two channelized STM-1 optical interfacesa.
Supports the CES services and IMA services at 64 kibt/s level. Automatic shutdown function of the laser at the port Supported
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Remarks Type of the loopback at the port Inloop at an STM-1 port Outloop at an STM-1 port Inloop in a VC-12 channel Outloop in a VC-12 channel Automatic loopback release at the port Supported
All the VC-12 timeslots of each CD1 interface support the DCN function. By default, the DCN function of only the first, seventeenth, thirty-third, and forty-ninth VC-12 timeslots of each optical interface can be enabled. Manually enables or disables the DCN function of the VC-12 timeslots of the optical interface on the CD1. PRBS ATM/IMA Supports the PRBS function in unframed mode of a VC-12 channel in the receive/transmit direction. Number of supported ATM E1 services Number of supported IMA groups Maximum number of VC-12 timeslots or serial ports in each IMA group 32 32 63
Dynamically enables or disables the IMA group, restarts the IMA group protocol, and dynamically adds or deletes the IMA group members. Supported traffic type CBR UBR UBR+ rt-VBR nrt-VBR Number of supported ATM connections (VPC and VCC included) Number of supported ATM services 64 256 remote connections 128 local connections
Encapsulates ATM VPC/VCC service to the PWE3 in the N-to-1 (N 32) or 1-to-1 format.
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Remarks Encapsulates the ATM cells to the PW in the concatenation and nonconcatenation modes. The number of PW connections that support the cell concatenation is 64, and the maximum number of concatenated cells is 31. ATM OAM on the UNI sideand NNI side Supports the CC test Supports the LB test. 63 CESoPSN SAToP Supports the timeslot compression function. Provides the idle 64 kbit/ s timeslot suppression function for the CES services in the CESoPSN mode to save the transmission bandwidth. Supported clock mode Retiming mode Self-adaptation mode The jitter compensation buffer time of the CES service can be set. The jitter buffer time ranges from 0.375 ms to 16 ms, and the step value is 0.125 ms. The packet loading time of the CES service can be set. The encapsulation buffer time ranges from 0.125 ms to 3 ms, and the step value is 0.125 ms.
CES
Number of supported CES servicesb Supported emulation mode
ML-PPP
Number of supported MLPPP groups Maximum number of links supported by each ML-PPP group
7 16
Functions as the NNI interface. LMSP protection Extraction and insertion of the S1 byte SSM protocol Supports the 1+1 LMSP and 1:1 LMSP protection schemes. Supported
Supported
NOTE a: The second channelized STM-1 interface on the front panel cannot be used to carry services, and it can be used for only the intra-board LMSP protection. b: The CD1 board does not support the intra-board CES local services.
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The CD1 consists of the SDH processing module, line processing module, data processing module, management module, clock module, and power supply module. Figure 2-15 shows the block diagram for working principle of the CD1. Figure 2-15 Block diagram for the working principle of the CD1
Channelized STM-1 Stand-by channelized STM-1
Backplane SDH processing module

Service signal
Line processing module
Service signal
Data processing module
Service signal
CXP
Management bus
Management bus
Management bus Management bus
Management module
CXP
Line clocks Line clocks
Clock module
CXP CXP
System clocks
3.3V . . . 1.2V
NOTE
. . .
Power supply module
-48V/-60V -48V/-60V
PIU PIU
Receive Direction
In the receive direction, the SDH processing module accesses 1 x channelized STM-1 services through the interface on the front panel. This module decapsulates the VC-12 timeslots from the STM-1 signals, recovers the E1 signals, processes the overhead bytes, pointers, and alarm signals, and sends the processed signals to the line processing module. Then, the line processing module rearranges the E1 frames, processes the rearranged signals according to the service type, and sends the signals to the data processing module for PWE3 encapsulation and PW scheduling. Finally, the signals are sent to the CXPA/CXPB/CXPG/CXPH through the interface on the backplane.
Transmit Direction
In the transmit direction, the data processing module receives the signals from the CXPA/ CXPB/CXPG/CXPH, identifies the signals, performs the PWE3 decapsulation, and then sends the signals to the line processing module. The line processing module processes various signals, schedules queues, and sends the processed signals to the SDH processing module. The SDH processing module maps the E1 signals to the VC-12 timeslots, multiplexes the VC-12 timeslots to the STM-1 signals, adds the overhead bytes and pointers, processes the alarm signals, and sends out the STM-1 signals through the interface on the front panel.
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SDH Processing Module

l
In the receive direction, this module accesses 1 x channelized STM-1 signals, decapsulates the VC-12 timeslots from the STM-1 signals, obtains the E1 signals by demapping the VC-12 timeslots, and processes the overhead bytes, pointers, and alarm signals. In the transmit direction, this module receives the E1 signals from the line processing module, maps the signals to the VC-12 timeslots, multiplexes the VC-12 timeslots to STM-1 signals, adds the overhead bytes and pointers, processes the alarm signals, and sends out the 1 x channelized STM-1 signals through the interface on the backplane. When the service fails, this module realizes the LMSP protection. Thus, the service is switched. This module extracts and recovers the line clocks.
Line Processing Module

l
In the receive direction, this module receives the signals from the SDH processing module, rearranges the frames of the E1 signals, performs processing for various services such as setup and deletion of the IMA link, creation of the ML-PPP group, extraction of protocol packets in the ML-PPP services, and suppression of timeslots of the CES services. Then, the processed signals are sent to the data processing module. In the transmit direction, this module receives the signals from the data processing module, processes various services, and sends the processed signals to the SDH processing module.
Data Processing Module

l
In the receive direction, this module obtains the corresponding PW channel information of each E1 service, performs the PWE3 encapsulation and PW scheduling, and sends the processed signals to the CXPA/CXPB/CXPG/CXPH through the interface on the backplane. In the transmit direction, this module receives the signals from the CXPA/CXPB/CXPG/ CXPH, identifies different service types, and performs the PWE3 decapsulation and service scheduling. In the case of the ATM E1 or IMA services, this module performs the VP/VC switching for the ATM cells, and processes the concatenated cells during the PWE3 encapsulation or decapsulation.
Management Module
When used with the CXPA/CXPB/CXPG/CXPH, this module manages and controls each module on the CD1.
Clock Module
l
Processes the line clocks.

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Accesses and processes the system clock from the CXPA/CXPB/CXPG/CXPH, and provides the working clock to each module on the CD1. Supports the SSM protocol.
Power Supply Module

l l
Accesses two -48 V/-60 V DC power supplies. Supplies the working power for each module on the CD1.
2.8.4 Front Panel

On the front panel of the CD1, there are indicators and interfaces.

Figure 2-16 shows the appearance of the front panel of the CD1. Figure 2-16 Appearance of the front panel of the CD1
Indicators
The following indicators are present on the front panel of the CD1:
l l l
STAT indicator, red, green, or orange, which indicates the working status SRV indicator, red, green, or orange, which indicates the service status LOS1 and LOS2 indicators, red, green, or orange, which indicate the port status
Interfaces
Table 2-44 lists the amount, types, and usage of the interfaces on the CD1.
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Table 2-44 Interfaces on the CD1 Interface on the Front Panel IN1 to IN2 Interface Type LC Usage Corresponding Fiber For details, see 5.1.1 Fiber Types.
When a two-fiber bidirectional optical module is used, this interface is used as an input interface for the STM-1 optical signal. When a single-fiber bidirectional optical module is used, this interface is not used.
OUT1 to OUT2
LC
When a two-fiber bidirectional optical module is used, this interface is used as an output interface for the STM-1 optical signal. When a single-fiber bidirectional optical module is used, this interface is used as an input/output interface for the STM-1 optical signal.

2.8.5 Valid Slots

The CD1 can be housed in any of the two slots, that is, slots 3 and 4.

You can use the U2000 to configure parameters for the CD1. You can use the U2000 to configure the following parameters for the CD1.
l l l l l l l l
J0 J1 J2 C2 V5 SDH interface Automatic laser shutdown Spare timeslot recovery value

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The technical specifications of the CD1 cover the interface specifications, board dimensions, weight, and power consumption. Table 2-45 lists the specifications of interfaces on the CD1. Table 2-45 Technical specifications of the STM-1 optical interface Item Nominal bit rate (kbit/s) Optical interface type Specification 155520 Two-fiber bidirectional interface S-1.1 (15 km) Fiber type Working wavelength range (nm) Single-mode 1261 to 1360 L-1.1 (40 km) Single-mode 1263 to 1360 L-1.2 (80 km) Single-mode 1480 to 1580 Single-fiber bidirectional interface S-1.1 (15 km) Single-mode For details, see wavelength allocation of single-fiber bidirectional optical interface and related optical module code. -15 to -8 L-1.1 (40 km) Single-mode For details, see wavelength allocation of single-fiber bidirectional optical interface and related optical module code. -5 to 0
-15 to -8
-5 to 0
-5 to 0
-28
-34
-34
-28.2
-30
-8 8.2
-10 10
-10 10
-8 6.6
-10 10
34060276 34060307
34060281 34060308
34060282 34060309
For details, see wavelength allocation of single-fiber bidirectional optical interface and related optical module code.
For details, see wavelength allocation of single-fiber bidirectional optical interface and related optical module code.
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Item
Specification
Table 2-46 Wavelength allocation of single-fiber bidirectional interface optical interface and related optical module code Item Optical module code (15 km) Optical module code (40 km) Transmitter wavelength (nm) Receiver wavelength (nm) 1260 to 1360 1480 to 1580 1480 to 1580 1260 to 1360 34060328 34060329 Local 34060363 Remote 34060364
Board dimensions (mm): 20.32 (H) x 225.75 (D) x 193.80 (W) Board weight (kg): 0.52 Power consumption (W): 16.4
2.9 ADS2A/ADS2B
This section describes the ADS2A/ADS2B, a 2-channel ADSL service interface board, in terms of the version, functions, features, working principle, front panel, valid slots, and technical specifications.
NOTE
The ADS2A and ADS2B have the same functions, except for supporting different modes. The ADS2A supports the Annex A mode and the ADS2B supports the Annex B mode. The following refers the ADS2A and ADS2B uniformly as ADS2.
2.9.1 Version Description The functional version of the ADS2 is TND1. 2.9.2 Functions and Features Used with the CXPA/CXPB/CXPG/CXPH, the ADS2 can process the asymmetrical digital subscriber line (ADSL) services. 2.9.3 Working Principle and Signal Flow The ADS2 mainly consists of the service access module, interface converting module, clock module, and power supply module. 2.9.4 Front Panel On the front panel of the ADS2, there are indicators and interfaces. 2.9.5 Valid Slots
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The ADS2 can be housed in any of slots 3 - 4. 2.9.6 Board Configuration Reference You can use the U2000 to configure parameters for the ADS2. 2.9.7 Technical Specifications The technical specifications of the ADS2A/ADS2B cover the performance specifications, board dimensions, weight, and power consumption.

The functional version of the ADS2 is TND1.

Used with the CXPA/CXPB/CXPG/CXPH, the ADS2 can process the asymmetrical digital subscriber line (ADSL) services. Table 2-47 lists the functions and features of the ADS2. Table 2-47 Functions and Features of the ADS2 Function and Feature Basic Function Description Provides two ADSL interfaces and accesses 2 x ADSL signals. Supports PVC pair setting for ports (eight PVC for each port). Detects the temperature and voltage of the board. Supports the hot swappable function. Application scenario The ADS2 is applied in the offload scenario. On the access side, the OptiX PTN 910 performs ATM PWE3 emulation for the HSDPA service flow. Then, the emulated service is encapsulated in the tunnel required by the WMS network. Finally, the ADS2 performs ATM adaptation for the service. When entering the ADSL network, the encapsulated service is transported to the opposite equipment, then decapsulated, and finally transported to the RNC node. ITU-T G.994 ITU-T G.992.1 (G.dmt), Annex A, B ITU-T G.992.2 (G.lite), Annex A, B ANSI T1.413 ITU-T G.992.3 (ADSL2), Annex A, B ITU-T G.992.5 (ADSL2+), Annex A, B
Compliant norms
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The ADS2 mainly consists of the service access module, interface converting module, clock module, and power supply module. Figure 2-17 shows the block diagram for the working principle of the ADS2. Figure 2-17 Block diagram for the working principle of the ADS2
Backplane To each module Clock signals Clock module Clock signals CXP
Service bus Two-channel ADSL signals

ADSL transceiver Line driver
Management bus
Logic control module
Parallel/serial converting module
Service bus
CXP
Serial management bus Status signal
CXP CXP
Service access module
Interface converting and control module
1.2 V 2.5 V 3.3 V 5V
-48V/-60V
Power supply module
PIU PIU
-48V/-60V
NOTE
In the Transmit Direction

The CXPA/CXPB/CXPG/CXPH sends the service signals to the ADS2. The parallel/serial converting module converts and sends the signals to the logic control unit, which processes the signals. The ADSL transceiver unit of the service access module adapts the service signals into the ADSL service. Then, the line driver amplifies the ADSL service and outputs it through the interface.
In the Receive Direction

The ADSL interface accesses the ADSL signals. Then, the ADSL transceiver unit of the service access module stripes the ATM AAL5 adaptation layer from the ADSL signals and outputs service signals. The logic control module processes the signals, and then sends the signals to the backplane through the parallel/serial converting module.
Service Access Module

l
The ADSL transceiver unit strips the ATM AAL5 adaptation layer from the ADSL service accessed from the interface and then outputs the service.
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l
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The ADSL transceiver unit performs ATM AAL5 adaptation and encapsulation for the service sent by the interface converting and control module and finally outputs the ADSL service. The line driver unit amplifies the signals to be transmitted.
Interface Converting and Control Module

This module performs parallel/serial conversion for transporting the service between the system control board and the local board. The system control board controls and manages the board through the serial management bus. In addition, the logic control unit detects alarms and reports them to the CXPA/CXPB/CXPG/ CXPH through the serial management bus.
Clock Module
The clock module provides working clock signals to each module.
Power Supply Module

This module provides DC voltages required by each module on the board.
2.9.4 Front Panel

On the front panel of the ADS2, there are indicators and interfaces.

Figure 2-18 and Figure 2-19 show the appearance of the front panel of the ADS2. Figure 2-18 Appearance of the front panel of the ADS2A
Figure 2-19 Appearance of the front panel of the ADS2B
Indicators
l
STAT indicator, red, green, or orange, which indicates the working status
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l l
STAT indicator, red, green, or orange, which indicates the working status LINK1 and LINK2 indicators, green, which indicate the port connection status.
Interfaces
Table 2-48 lists the types of the interfaces on the ADS2 and their respective usage. Table 2-48 Types and usage of the interfaces on the ADS2 Interface on the Front Panel ADSL1, ADSL2 Interface Type RJ-11 Usage Accesses two channels of ADSL services. Corresponding Cable For details, see 5.4.4 xDSL Cables.
Table 2-49 lists the pins of the ADSL1 and ADSL2 interfaces. Table 2-49 Pins of the ADSL1 and ADSL2 interface on the ADS2 Front View Pin No. 1 2 3 Usage Unspecified Unspecified RING TIP Unspecified Unspecified
6543 21
4 5 6
2.9.5 Valid Slots

The ADS2 can be housed in any of slots 3 - 4.

You can use the U2000 to configure parameters for the ADS2. You can use the U2000 to configure the following parameters for the ADS2. ADSL Interface For details on the parameters, see D Board Configuration Parameters.
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The technical specifications of the ADS2A/ADS2B cover the performance specifications, board dimensions, weight, and power consumption. Table 2-50 and Table 2-51 list the performance specifications of the ADS2A/ADS2B. Table 2-50 Performance specifications of the ADS2A Interface ADSL standard ADSL2 ADSL2+ Max. Upstream Rate 0.896 Mbit/s 1.2 Mbit/s 1.2 Mbit/s Max. Downstream Rate 8 Mbit/s 15 Mbit/s 24 Mbit/s Transmission Distance 5.5 km 5.5 km 5.5 km
Table 2-51 Performance specifications of the ADS2B Interface ADSL standard ADSL2 ADSL2+ Max. Upstream Rate 0.896 Mbit/s 1.2 Mbit/s 1.2 Mbit/s Max. Downstream Rate 8 Mbit/s 15 Mbit/s 24 Mbit/s Transmission Distance 4 km 4 km 4 km
Board dimensions (mm): 20.32 (H) x 225.75 (D) x 193.80 (W) Weight (kg): 0.54 ADS2A Power consumption (W): 10.5 ADS2B Power consumption (W): 10.4
2.10 SHD4
This section describes the SHD4, a 4-channel G.SHDSL service interface board, in terms of the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.10.1 Version Description The functional version of the SHD4 is TND1. 2.10.2 Functions and Features Used with the CXPA/CXPB/CXPG/CXPH, the SHD4 can process the G.991.2 single-pair highspeed digital subscriber line (G.SHDSL) service. 2.10.3 Working Principle and Signal Flow
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The SHD4 mainly consists of the service access module, interface converting module, clock module, and power supply module. 2.10.4 Front Panel On the front panel of the SHD4, there are indicators, and interfaces. 2.10.5 Valid Slots The SHD4 can be housed in any of slots 3 - 4. 2.10.6 Board Configuration Reference You can use the U2000 to configure parameters for the SDH4. 2.10.7 Technical Specifications The technical specifications of the SHD4 cover the performance specifications, board dimensions, weight, and power consumption.

The functional version of the SHD4 is TND1.

Used with the CXPA/CXPB/CXPG/CXPH, the SHD4 can process the G.991.2 single-pair highspeed digital subscriber line (G.SHDSL) service. Table 2-52 lists the functions and features of the SHD4. Table 2-52 Functions and Features of the SHD4 Function and Feature Basic function Description Provides four G.SHDSL interfaces and accesses 4 x G.SHDSL signals. Supports the ATM mode and the EFM mode. The outgoing lines of the four G.SHDSL interfaces support the M-Pair binding of lines. In addition, M can be 1, 2, 3, or 4. Supports the G.SHDSL load sharing protection. Supports the hot swappable function. Clock Application scenario Supplies the G.SHDSL line clock for CXPA/CXPB/CXPG/ CXPH as system clock. The SHD4 is applied in the offload scenario. On the access side, the OptiX PTN 910 performs ATM PWE3 emulation for the HSDPA service flow. Then, the emulated service is encapsulated in the tunnel required by the WMS network. Finally, the SHD4 performs ATM adaptation for the service. When entering the xDSL network, the encapsulated service is transported to the opposite equipment, then decapsulated, and finally transported to the RNC node. ETSI SDSL (ETSI TS 101 524 V 1.2.1)
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Description ETSI SDSL.bis (ETSI TS 101 524 V 1.2.2) ITU G.shdsl (ITU-T G.991.2) ITU G.shdls.bis (ITU-T G.991.2 (2004)) ITU G.hs (ITU-T G.994.1) IEEE 802.3ah clause 61

The SHD4 mainly consists of the service access module, interface converting module, clock module, and power supply module. Figure 2-20 shows the block diagram for the working principle of the SHD4. Figure 2-20 Block diagram for the working principle of the SHD4
Backplane Each module of the board Clock signals
Clock module
Clock signals
CXP
4 x G.SHDSL signals
Signal voltage and performs protection module
Service bus Service encapsulation and bundling Management bus module
Logic control unit
Parallel/serial converting module Serial management bus Status signal
Service bus
CXP
CXP CXP
To each module
1.2 V 1.5 V 3.3 V Power supply module
-48V/-60V
PIU
-48V/-60V
PIU
NOTE

The CXPA/CXPB/CXPG/CXPH sends the service signals to the parallel/serial converting module and then to the logic control unit, which processes the service signals. Finally, the service encapsulation and bundling module decapsulates the service signals and outputs the G.SHDSL service.
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The service board accesses the G.SHDSL signals and the service access module transforms the signal voltage and performs protection for the signals. Then, the service encapsulation and bundling module encapsulates and bundles the signals, adjusts the signal rate, frames the signals, and then sends the signals to the logic control module, which processes the service signals. Finally, the parallel/serial converting module converts and sends the service signals to the CXPA/CXPB/CXPG/CXPH.

l
The service access module transforms the signal voltage and performs protection for the access signals. Then, the service encapsulation and bundling module bundles four channels of G.SHDSL signals, strips the ATM AAL5 adaptation layer, and finally outputs the service signals. The interface converting and control module sends the service to the service encapsulation and bundling module, which then performs ATM AAL5 adaptation and encapsulation, and finally outputs the G.SHDSL service.

This module performs parallel/serial conversion for transporting the service between the system control board and the local board. The system control board controls and manages the board through the serial management bus. In addition, the logic control unit detects alarms and reports them to the CXPA/CXPB/CXPG/ CXPH through the serial management bus.
Clock Module
The clock module provides working clock for each module on the SHD4.
Power Supply Module

This module provides DC voltages required by each module on the board.
2.10.4 Front Panel

On the front panel of the SHD4, there are indicators, and interfaces.

Figure 2-21 shows the appearance of the front panel of the SHD4. Figure 2-21 Appearance of the front panel of the SHD4
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Indicators
l l l
STAT indicator, red, green, or orange, which indicates the working status SRV indicator, red, green, or orange, which indicates the service status LINK1/LINK2/LINK3/LINK4 indicators, green, which indicate the port connection status.
Interfaces
Table 2-53 lists the types of the interfaces on the SHD4 and their respective usage. Table 2-53 Types and usage of the interfaces on the SHD4 Interface Interface on the Type Front Panel SHDSL1 SHDSL4 RJ-11 Usage Corresponding Cable For details, see 5.4.4 xDSL Cables.
Accesses the first 4 x G.SHDSL services.
Table 2-54 lists the pins of theSHDSL1 - SHDSL4 interfaces. Table 2-54 Pins of the SHDSL1 - SHDSL4 interfaces on the SHD4 Front View Pin No. 1 2 3 Usage Unspecified Unspecified TIP RING Unspecified Unspecified
6543 21
4 5 6
2.10.5 Valid Slots

The SHD4 can be housed in any of slots 3 - 4.

You can use the U2000 to configure parameters for the SDH4. You can use the U2000 to configure the following parameters for the SHD4. G.SHDSL Interface For details on the parameters, see D Board Configuration Parameters.
2 Boards

The technical specifications of the SHD4 cover the performance specifications, board dimensions, weight, and power consumption. Table 2-55 lists the performance specifications of the SHD4. Table 2-55 Performance specifications of the SHD4 Interface Max. Upstream Rate 5.7 Mbit/s Max. Downstream Rate 5.7 Mbit/s Max. Four-Line Bundling Rate 23 Mbit/s Max. Transmission Distance 5.25 km
G.SHDSL
2.11 SHD4I
This section describes the SHD4I, a 4-channel SHDSL service interface board that supports the IMA mode, in terms of the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.11.1 Version Description The functional version of the SHD4I is TND1. 2.11.2 Functions and Features The SHD4I can access four channels of G.SHDSL signals encapsulated in the IMA format when it is used with the CXPA/CXPB/CXPG/CXPH. 2.11.3 Working Principle and Signal Flow The SHD4I mainly consists of the service access module, interface converting and control module, IMA processing module, clock module, and power supply module. 2.11.4 Front Panel On the front panel of the SHD4I, there are indicators and interfaces. 2.11.5 Valid Slots The SHD4I can be housed in slot 3 or slot 4. 2.11.6 Board Configuration Reference You can use the U2000 to configure parameters for the SHD4I. 2.11.7 Technical Specifications The technical specifications of the SHD4I cover the interface specifications, board dimensions, weight, and power consumption.

The functional version of the SHD4I is TND1.
2 Boards

The SHD4I can access four channels of G.SHDSL signals encapsulated in the IMA format when it is used with the CXPA/CXPB/CXPG/CXPH. Table 2-56 lists the functions and features of the SHD4I. Table 2-56 Functions and Features of the SHD4I Function and Feature Basic Function Description Provides four G.SHDSL interfaces to access four channels of G.SHDSL signals. Accesses the service signals encapsulated in the IMA format and supports one IMA group. Provides the G.SHDSL load sharing protection in the IMA encapsulation mode. Supports the network timing recovery (NTR) function. Supports the hot-swap function. Compliant norms ETSI SDSL (ETSI TS 101 524 V 1.2.1) ETSI SDSL.bis (ETSI TS 101 524 V 1.2.2) ITU G.shdsl (ITU-T G.991.2) ITU G.shdls.bis (ITU-T G.991.2 (2004)) ITU G.hs (ITU-T G.994.1)

The SHD4I mainly consists of the service access module, interface converting and control module, IMA processing module, clock module, and power supply module. Figure 2-22 shows the block diagram for the working principle of the SHD4I.
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Figure 2-22 Block diagram for the working principle of the SHD4I
Management and control bus Backplane Service signals CXP
IMA processing module
IMA service signals ATM cells
4 x G.SHDSL signals
IMA service signals Management and control bus
Serial management bus
CXP
Status signal bus
CXP
4 x NTR clock signals
To each module on the SHD4I
Working clock signals
Clock module
Clock signals
CXP
To each module on the SHD4I
3.3 V 1.8 V 1.5 V 1.2 V
-48 V/-60 V
PIU
Power supply module
-48 V/-60 V
PIU
NOTE

The RJ-11 interfaces access the G.SHDSL signals to the service access module. Then, the service access module works with the IMA processing module to multiplexes the service signals, and sends the ATM cells to the interface converting and control module. The interface converting and control module decapsulates the ATM frames, converts the parallel signals to serial signals, converges the serial signals to one channel service signal, and finally sends the service signal to the backplane.

The interface converting and control module receives the service signal from the backplane, converts the serial signal to parallel signal, encapsulates the signals in the ATM frame format, and then sends the ATM frames to the service access module. The service access module processes the ATM cells and work with the IMA processing module to inversely multiplexes the ATM signals as IMA signals. Finally, the service access module sends the packets to the G.SHDSL interfaces.

This module accesses the service packets in different modes according to the encapsulation mode of the G.SHDSL interfaces. In addition, this module has the thunder protection function.
l
In the receive direction, this module converts the serial packets to parallel packets, and sends the parallel packets to the interface converting and control module. In the transmit direction, this module receives the IMA service signals from the interface converting and control module, converts the serial IMA service signals to parallel IMA
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service signals, and finally sends the parallel IMA service signals to the G.SHDSL interfaces.
l
In addition, this module extracts the NTR clock signals from the G.SHDSL service signals received and sends the clock signals to the clock module.

This module converges the G.SHDSL service signals to one channel service signal and works with the CXPA/CXPB/CXPG/CXPH to manage and control the SHD4I.
l
In the receive direction, this module receives the IMA service signals from the service access module, converts the IMA service signals, and sends the service signals to the IMA processing module, which multiplexes the service signals . Then, this module receives the ATM cells from the IMA processing module, decapsulates the ATM frames, converts the parallel signals to serial signals, converges the signals to one channel service signal, and finally sends the service signal to the backplane. In the transmit direction, this module receives the service signal from the backplane, converts the serial signal to parallel signal, encapsulates the service signal into ATM frames, and sends the ATM cells to the IMA processing module, which inversely multiplexes the ATM signals. Then, this module receives IMA signals from the IMA processing module and finally sends the IMA signals to the service access module. In addition, this module works with the CXPA/CXPB/CXPG/CXPH to manage and control each module on the SHD4I.
IMA Processing Module

l
In the receive direction, this module receives the IMA service signals from the interface converting and control module, multiplexes the service signals as ATM signals, and finally sends the ATM signals to the interface converting and control module, which converges the signals. In the transmit direction, this module receives the service signals from the backplane after the interface converting and control module processes the service signals. Then, this module inversely multiplexes the ATM signals and sends the IMA service signals to the interface converting and control module.
Clock Module
l
Selects a clock source from the four channels of NTR clock signals and uploads the clock signals to the CXPA/CXPB/CXPG/CXPH. Provides working clock signals for each module on the SHD4I board.
Power Supply Module

This module provides the following DC voltages for the modules on the SHD4I board:
l l l
3.3 V 1.8 V 1.5 V

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l
1.2 V
2.11.4 Front Panel

On the front panel of the SHD4I, there are indicators and interfaces.

Figure 2-23 shows the appearance of the front panel of the SHD4I. Figure 2-23 Appearance of the front panel of the SHD4I
Indicator
The following indicators are present on the front panel of the SHD4I:
l l l
STAT indicator, red, green, or orange, which indicates the working status SRV indicator, red, green, or orange, which indicates the service status LINK1, LINK2, LINK3 and LINK4 indicators, green, which indicate the port connection status.
Interface
Table 2-57 lists the types of the interfaces on the SHD4I and their respective usage. Table 2-57 Types and usage of the interfaces on the SHD4I Interface on the Front Panel SHDSL1SHDSL4 Interface Type RJ-11 Usage Input and output G.SHDSL signals. Corresponding Cable For details, see 5.4.4 xDSL Cables.
Table 2-58 lists the pins of the SHDSL1-SHDSL4 interfaces.
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Table 2-58 Pins of the SHDSL1 - SHDSL4 interfaces on the SHD4I Front View Pin No. 1 2 3 4
6 5 4 3 2 1
Usage Unspecified Unspecified TIP RING Unspecified Unspecified
5 6
2.11.5 Valid Slots

The SHD4I can be housed in slot 3 or slot 4.

You can use the U2000 to configure parameters for the SHD4I. You can use the U2000 to configure the following parameters for the SHD4I. G.SHDSL Interface For details on the parameters, see D Board Configuration Parameters.

The technical specifications of the SHD4I cover the interface specifications, board dimensions, weight, and power consumption. Table 2-59 lists the specifications of the interfaces of the SHD4I. Table 2-59 Specifications of the interfaces of the SHD4I Interface Max. Upstream Rate (Mbit/s) 2.3 Max. Downstream Rate (Mbit/s) 2.3 Max. Rate of Four Bundled Interfaces (Mbit/s) 9.2 Max. Transmission Distance (km) 5.25
G.SHDSL
Board dimensions (mm): 20.32 (H) x 225.75 (D) x 193.82 (W) Board weight (kg): 0.60 Power consumption (W): 7.5
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2.12 PIU
This section describes the PIU, a power input unit, in terms of the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.12.1 Version Description The functional version of the PIU is TNC1. 2.12.2 Functions and Features The PIU, a power access board, supports the functions and features such as power access, power protection, lightning protection detection, and information reporting. 2.12.3 Working Principle and Signal Flow The PIU mainly consists of the lighting protection and failure detection module, communication unit module, and board in-position module. 2.12.4 Front Panel On the front panel of the PIU, there are indicators and power supply interfaces. 2.12.5 Valid Slots The PIU can be housed in slot 5 in the chassis. 2.12.6 Technical Specifications The technical specifications of the PIU cover the board dimensions, weight, power consumption, and input voltage.

The functional version of the PIU is TNC1.

The PIU, a power access board, supports the functions and features such as power access, power protection, lightning protection detection, and information reporting. Table 2-60 lists functions and features of the PIU. Table 2-60 Functions and features of the PIU Function and Feature Power access Power protection Description One PIU accesses two -48 V DC (or -60 V DC) power supplies for the equipment. The PIU protects the power supply against overcurrent and short circuit. In this way, the overcurrent is prevented from shocking boards and components on them. The PIU protects the equipment against lightning and reports an alarm if the protection fails. The two DC power supplies back up each other.
Lightning protection Power backup
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The PIU mainly consists of the lighting protection and failure detection module, communication unit module, and board in-position module. Figure 2-24 shows the block diagram for the working principle of the PIU. Figure 2-24 Block diagram for the working principle of the PIU
Backplane -48 V/-60 V Lightning protection and failure detection module
Each board
-48 V/-60 V
Lightning protection and failure detection module
Lightning protection failure alarm signals Communication
Lightning protection failure alarm signals Inter-board communication bus
Each board
CXP
Board in-position module
Board in-position signals
CXP
NOTE
In Figure 2-24, the CXP on the backplane indicates the system control, cross-connect and protocol processing board. For OptiX PTN 910, the CXP indicates the CXPA/CXPB/CXPG/CXPH.
Lighting Protection and Failure Detection Module

This module protects the equipment against lightning and detects the failure of the anti-lightning circuit. If the lightning protection fails, the PIU reports the alarm signals to the CXPA/CXPB/ CXPG/CXPH.
Communication Unit Module

This module has the function of reporting the board manufacturing information, PCB version information, and alarm signals about the lightning protection failure.
Board In-Position Module

This module reports the board in-position signals to the CXPA/CXPB/CXPG/CXPH.
2.12.4 Front Panel

On the front panel of the PIU, there are indicators and power supply interfaces.

Figure 2-25 shows the appearance of the front panel of the PIU.
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Figure 2-25 Appearance of the front panel of the PIU
Indicators
The following indicator is present on the front panel of the PIU. PWRA/PWRB, green, which indicates the power supply status. When PWRA/PWRB is on and green, it indicates that power is accessed. For details on indications of indicators, see B Indicators.
Interfaces
The PIU accesses two power supplies. Table 2-61 lists the types of the interfaces on the PIU and their respective usage. For cable corresponding to the interfaces, see 5.2 -48 V Power Supply Cable. Table 2-61 Types and usage of the interfaces on the PIU Interface on the Front Panel NEG1(-) RTN1(+) NEG2(-) RTN2(+) Usage -48 V power input interface BGND power input interface -48 V power input interface BGND power input interface
Label
Operation warning label: indicates the following precaution, which should be taken for removal or insertion of the PIU board.
2 Boards
CAUTION
Multiple power supplies are accessed for the equipment. When powering off the equipment, make sure that these power supplies are disabled. Do not remove or insert the board with power on.
2.12.5 Valid Slots

The PIU can be housed in slot 5 in the chassis.

The technical specifications of the PIU cover the board dimensions, weight, power consumption, and input voltage. Table 2-62 lists the technical specifications of the PIU. Table 2-62 Technical specifications of the PIU Item Board dimensions (mm) Weight (kg) Power consumption (W) Input voltage (V) Technical Specification 41.4 (H) x 224.8 (D) x 21.0 (W) 0.12 0.5 -38.4 to -72.0
2.13 FAN
This section describes the FAN, a fan board, in terms of the version, functions, features, working principle, front panel, valid slots, and technical specifications. 2.13.1 Version Description The functional version of the FAN is TNC1. 2.13.2 Functions and Features The FAN is used to adjust the fan rotating speed, detect and report status of fans. 2.13.3 Working Principle and Signal Flow The FAN mainly consists of the start-delay module, communication unit module, intelligent fan speed adjustment module, and board in-position module. 2.13.4 Front Panel On the front panel of the FAN, there are indicators, anti-static wrist strap jack, handle, and labels. 2.13.5 Valid Slots The FAN can be housed in slot 6 in the chassis. 2.13.6 Technical Specifications
2 Boards
The technical specifications of the FAN cover the board dimensions, weight, power consumption, and input voltage.

The functional version of the FAN is TNC1.

The FAN is used to adjust the fan rotating speed, detect and report status of fans. The functions and features of the FAN are as follows:
l l
Accesses one 12 V power supply for driving three fans that each consumes 6 W power. Provides start-delay for the power supply of the fans and protects fans against overcurrent. Intelligently adjusts the rotating speed of fans to ensure proper heat dissipation of the system. Reports information about the fan rotating speed, environment temperature, alarms, version number, and board in-position information. Provides alarm indicators.

The FAN mainly consists of the start-delay module, communication unit module, intelligent fan speed adjustment module, and board in-position module. Figure 2-26shows the block diagram for the working principle of the FAN. Figure 2-26 Block diagram for the working principle of the FAN
Fans x 3 12 V 12 V 12 V Backplane 12V CXP
Start-delay module 12 V power shut signals Communication unit module
Inter-board communication bus CXP
Fan-speed reporting module PWM signals PWM driver module Intelligent fan speed adjustment module Board in-position module
Fan-speed signals CXP
CXP
Fan in-position signals CXP
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NOTE
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In the block diagram, the CXP on the backplane indicates the system control, cross-connect and protocol processing board. For OptiX PTN 910, the CXP indicates the CXPA/CXPB/CXPG/CXPH.
Start-delay Module
This module has the function of provides start-delay to the power supply for fans and protects fans against overcurrent.
Communication Unit Module

This module reports the board manufacturing information, PCB version, and environment temperature information. In addition, this module provides 12 V power shut signals to the startdelay module.
Intelligent Fan Speed Adjustment Module

This module reports information about the fan rotating speed to the CXPA/CXPB/CXPG/ CXPH and adjusts the fan rotating speed according to the three pulse-width modulation (PWM) signals received from the CXPA/CXPB/CXPG/CXPH. The PWM signal of one fan is isolated from that of another.
Board In-Position Module

This module reports the board in-position signals to the CXPA/CXPB/CXPG/CXPH.
2.13.4 Front Panel

On the front panel of the FAN, there are indicators, anti-static wrist strap jack, handle, and labels.

Figure 2-27 shows the appearance of the front panel of the FAN. Figure 2-27 Appearance of the front panel
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Indicators
The following indicators are present on the front panel of the FAN: FAN indicator, red or green, which indicates status of fans. For details on indications of indicators, see B Indicators.
Anti-Static Wrist Strap Jack

The anti-static wrist strap should be connected to this jack for proper grounding of the human body.
Handle
The handle is used for pushing the FAN into or pulling the FAN out of the chassis during board replacement.
Label
The following labels are present on the front panel of the FAN:
l l
ESD protection label, which indicates that the equipment is static-sensitive. Fan warning label, which says that do not touch the fan leaves before the fan stops rotating.
2.13.5 Valid Slots

The FAN can be housed in slot 6 in the chassis.

The technical specifications of the FAN cover the board dimensions, weight, power consumption, and input voltage. Table 2-63 lists the technical specifications of the FAN. Table 2-63 Technical specifications of the FAN Item Board dimensions (mm) Weight (kg) Power consumption (W) Working voltage (V) Technical Specification 42.0 (H) x 217.6 (D) x 28.5 (W) 0.20 2.3 W 12 V DC power
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3
About This Chapter
A filler panel is used to cover any idle slot in a chassis. 3.2 Appearance and Valid Slots There is no indicator or interface on a filler panel.
Filler Panel
3.1 Functions and Features A filler panel can be used to perform electromagnetic shielding, keep out foreign substances, and ensure proper ventilation.
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3 Filler Panel
3.1 Functions and Features

A filler panel can be used to perform electromagnetic shielding, keep out foreign substances, and ensure proper ventilation. Main functions of a filler panel are as follows:
l
Performs electromagnetic shielding and ensures that the chassis meets the requirement of electromagnetic radiation. Prevents foreign substances from getting into the chassis. Prevents internal voltage from being exposed. Ensures proper ventilation of cooling current inside the chassis.
l l l
3.2 Appearance and Valid Slots

There is no indicator or interface on a filler panel.
Appearance
Figure 3-1 shows the appearance of a filler panel. Figure 3-1 Appearance of a filler panel
Valid Slots
A filler panel can be housed in any of slots 3-4 of a chassis.
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4 Pluggable Optical Modules
4
About This Chapter
Pluggable Optical Modules
Optical interface boards for the OptiX PTN 910 use the enhanced small form-factor pluggable (eSFP) optical module. The eSFP optical module, which is a protocol-independent optical transceiver applicable to optical communication, implements O/E and E/O conversion for signals, and supports query of information such as the transceiver performance and manufacturer. 4.1 Appearance and Application The eSFP optical module can be inserted in GE, FE, and STM-1 optical interfaces. 4.2 Optical Module Labels Optical module labels, attached on back of the optical modules, are used to distinguish different types of optical modules.
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4.1 Appearance and Application

The eSFP optical module can be inserted in GE, FE, and STM-1 optical interfaces.
Appearance
Figure 4-1 shows the appearance of the eSFP optical module. Figure 4-1 Appearance of the eSFP optical module
Application
Table 4-1 lists the boards where the eSFP optical module is applicable. Table 4-1 Boards where the eSFP optical module is applicable Board Type GE optical interface board FE optical interface board STM-1 optical interface board Board Name EG2, CXPG/CXPH EF8F CD1
4.2 Optical Module Labels

Optical module labels, attached on back of the optical modules, are used to distinguish different types of optical modules. Figure 4-2 shows the optical module labels. Figure 4-2 Optical module label
1.25G-80km-1550nm 34060360 Optical module code
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As shown in Table 4-2, different types of optical modules have different codes. Table 4-2 Codes and types of optical modules Optical Module Code 34060286 Optical Interface Type 1000BASESX (0.5 km) 34060473 1000BASELX (10 km) 34060290 1000BASELX (10 km) 34060298 1000BASEVX (40 km) 34060360 1000BASEZX (80 km) 34060324 1000BASEZX (80 km) 34060483 1000BASECWDM (80 km) 34060481 1000BASECWDM (80 km) 34060479 1000BASECWDM (80 km) 34060482 1000BASECWDM (80 km) 34060478 1000BASECWDM (80 km) Optical Transceiver, eSFP, 1550 nm, 1.25 Gbit/s, LC (-40 to 85), Singlemode, 80 km Optical transceiver, eSFP, 1471 nm, 100 Mbit/s to 2.67 Gbit/s, LC, Singlemode, 80 km Optical transceiver, eSFP, 1491 nm, 100 Mbit/s to 2.67 Gbit/s, LC, Singlemode, 80 km Optical transceiver, eSFP, 1511 nm, 100 Mbit/s to 2.67 Gbit/s, LC, Singlemode, 80 km Optical transceiver, eSFP, 1531 nm, 100 Mbit/s to 2.67 Gbit/s, LC, Singlemode, 80 km Optical transceiver, eSFP, 1551 nm, 100 Mbit/s to 2.67 Gbit/s, LC, Singlemode, 80 km CXPG/ CXPH EG2 Optical Transceiver, eSFP, 1550 nm, 1.25 Gbit/s, LC, Single-mode, 80 km Optical Transceiver, eSFP, 1310 nm, 1.25 Gbit/s, LC ( - 40 to 85), Singlemode, 10 km Optical Transceiver, eSFP, 1310 nm, 1.25 Gbit/s, LC, Single-mode, 40 km Optical Module Basic Information Optical Transceiver, eSFP, 850 nm, 2.125 Gbit/s (Multi rate), LC, Multimode, 0.5 km Optical transceiver, eSFP, 1310 nm, 1.25 Gbit/s, LC, Single-mode, 10 km Mapping Board CXPG/ CXPH EG2
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Optical Module Code 34060476
Optical Interface Type 1000BASECWDM (80 km)
Optical Module Basic Information Optical transceiver, eSFP, 1571 nm, 100 Mbit/s to 2.67 Gbit/s, LC, Singlemode, 80 km Optical transceiver, eSFP, 1591 nm, 100 Mbit/s to 2.67 Gbit/s, LC, Singlemode, 80 km Optical transceiver, eSFP, 1611 nm, 100 Mbit/s to 2.67 Gbit/s, LC, Singlemode, 80 km Optical Transceiver, eSFP, 1310 nm, STM1, LC, Single-mode, 15 km
Mapping Board
34060477
1000BASECWDM (80 km)
34060480
1000BASECWDM (80 km)
34060276
100BASE-FX /S-1.1 (15 km)
EF8F CD1
34060307
100BASE-FX /S-1.1 (15 km)
Optical Transceiver, eSFP, 1310 nm, STM1, LC, Single-mode, 15 km
34060281
100BASE-FX /L-1.1 (40 km)
34060308
100BASE-FX /L-1.1 (40 km)
Optical Transceiver, eSFP, 1310 nm, STM1 LC, Single-mode, 40 km
34060282
100BASE-FX /L-1.2 (80 km)
34060309
100BASE-FX /L-1.2 (80 km)
34060475
1000BASEBX (10 km)
Optical Transceiver, eSFP, Tx 1490 nm/Rx 1310 nm, 1.25 Gbit/s, LC, Single-mode, 10 km Optical Transceiver, eSFP, Tx 1310 nm/Rx 1490 nm, 1.25 Gbit/s, LC, Single-mode, 10 km
CXPG/ CXPH EG2
34060470
1000BASEBX (10 km)
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Optical Module Code 34060364
Optical Interface Type 100BASE-BX (10 km) /S-1.1 (15 km)
Optical Module Basic Information Optical Transceiver, eSFP, Tx 1550 nm/Rx 1310 nm, STM1, LC, Singlemode, 15 km
Mapping Board EF8F CD1
34060363
100BASE-BX (10 km) /S-1.1 (15 km)
Optical Transceiver, eSFP, Tx 1310 nm/Rx 1550 nm, STM1, LC, Singlemode, 15 km
34060329
100BASE-BX (40 km) /L-1.1 (40 km)
34060328
100BASE-BX (40 km) /L-1.1 (40 km)
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About This Chapter
Fibers and Cables
This chapter describes various fibers and cables used on the equipment, including fibers, power cables, grounding cables, service cables, management cables, clock cables, and alarm cables. 5.1 Fibers This section describes the types of fibers and fiber connectors. 5.2 -48 V Power Supply Cable The OptiX PTN 910 uses 1 U DC connectors to receive external power. 5.3 Protection Grounding Cables Protection grounding cables are used to ground the OptiX PTN 910. 5.4 Service Cables The service cables include Ethernet cables, 75-ohm 16 x E1 cables, 120-ohm 16 x E1 cables, and telephone wires. 5.5 Management Cables On the OptiX PTN 910, Ethernet cables are used to input and output NM signals. 5.6 Clock Cables The clock cables used on the OptiX PTN 910 include external clock cables and 120-to-75-ohm clock cables. 5.7 Alarm Input/Output Cables On the OptiX PTN 910, the RJ-45 connectors are used to input the alarm signals from the external equipment and output the local alarm signals to the equipment that monitors all the alarms.
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5.1 Fibers
This section describes the types of fibers and fiber connectors. 5.1.1 Fiber Types Single-mode fibers or multi-mode fibers can be used on the OptiX PTN 910. 5.1.2 Fiber Connectors The fiber connectors of the LC/PC, FC/PC, and SC/PC types are applicable to the OptiX PTN 910.
5.1.1 Fiber Types

Single-mode fibers or multi-mode fibers can be used on the OptiX PTN 910. Table 5-1 lists the types of fibers used on the OptiX PTN 910. Table 5-1 Types of Fiber Usage To interconnect optical interfaces on the OptiX PTN equipment To interconnect the local equipment with the ODF To interconnect the local equipment with other equipment Connect or 1 LC/PC Connect or 2 LC/PC Fiber 2 mm singlemode fiber 2 mm multimode fiber LC/PC FC/PC 2 mm singlemode fiber 2 mm multimode fiber LC/PC SC/PC 2 mm singlemode fiber 2 mm multimode fiber Available Length 0.5 m, 1.5 m, 3 m, 6 m, 10 m, 15 m, 20 m, 30 m 3 m, 5 m, 10 m, 20 m, 30 m 0.8 m, 2.7 m, 5 m, 7 m, 10 m, 15 m, 20 m, 25 m, 30 m, 50 m 10 m, 20 m, 30 m 3 m, 5 m, 10 m, 15 m, 20 m, 25 m, 30 m, 50 m 10 m, 20 m
Select proper fiber connectors and fibers of proper length according to the site survey.
5.1.2 Fiber Connectors

The fiber connectors of the LC/PC, FC/PC, and SC/PC types are applicable to the OptiX PTN 910. Table 5-2 lists the types and usage of the fiber connectors applicable to the equipment.
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Table 5-2 Usage and types of fiber connectors Type LC/PC FC/PC SC/PC Description Plug-in square fiber connector/ protruding polished Round fiber connector/protruding polished Square fiber connector/protruding polished Usage Used at the optical interfaces on all the boards on the OptiX PTN equipment Used at the client-side ODF or the optical interfaces on other equipment
LC/PC Fiber Connector

Figure 5-1 shows the appearance of the LC/PC fiber connector. Figure 5-1 LC/PC fiber connector
Only axial operations instead of rotation is required to insert or remove the LC/PC fiber connector. To insert or remove an LC/PC fiber connector, do as follows:
l l
To insert the fiber jumper into the LC/PC connector, align the head of the fiber jumper with the optical interface and then push the fiber jumper with proper force into the connector. To remove the LC/PC fiber jumper, press the clip first, push the fiber connector inward slightly, and then pull out the connector.
FC/PC Fiber Connector

Figure 5-2 shows the appearance of the FC/PC fiber connector. Figure 5-2 FC/PC fiber connector
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To insert or remove an FC/PC fiber connector, do as follows:

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To insert the fiber jumper into the FC/PC connector, align the head of the fiber jumper with the optical interface on the optical interface board carefully, to avoid any damage to the internal ceramic pipe. After inserting the fiber jumper to the bottom of the optical interface, clockwise rotate the external screw to tighten the fiber jumper into the optical interface. To remove the fiber jumper, first anticlockwise rotate the external screw of the optical interface. When the screw is loosened, remove the fiber jumper with proper force from the optical interface.
SC/PC Fiber Connector

Figure 5-3 shows the appearance of the SC/PC fiber connector. Figure 5-3 SC/PC fiber connector
To insert or remove an SC/PC fiber connector, do as follows.

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To insert the fiber jumper into the SC/PC connector, align the head of the fiber jumper with the optical interface and then push the fiber jumper with proper force into the connector. To remove the fiber jumper, press the clip first, push the fiber connector inward slightly, and then pull out the connector.
5.2 -48 V Power Supply Cable

The OptiX PTN 910 uses 1 U DC connectors to receive external power. Power cables need to be produced on site. The power cables are made of 1U DC connectors, single cord end terminals, and wires. Figure 5-4 shows the appearance of a power cable. The technical specifications of the power cable are listed in Table 5-3.
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Figure 5-4 Appearance of the power cable
Single cord end terminal
1U DC connector
Power cable
Table 5-3 Technical specifications of the power cable Item 2.5 mm2 power cable and terminal Wire Related Parameter Electronic/Electric wire, 450 V/ 750V, H07Z, K, 2.5 mm2, blue/ black green, fire resistant cable with low smoke and no halogen Terminal Related Parameter Bare crimp terminal, single cord end terminal, 2.5 mm2, 12.5 A, tin plating, 8 mm deep, blue
NOTE
In the case of the OptiX PTN 910 equipment, there are following limitations on mapping relations between the cable length and the cross-sectional area. If the cross-sectional area is 2.5 mm2, the maximum cable length is 50 m.
5.3 Protection Grounding Cables

Protection grounding cables are used to ground the OptiX PTN 910. Protection grounding cables are made of wires and OT terminals. Figure 5-5 shows the appearance of a protection grouding cable. The technical specifications of the protection grounding cable are listed in Table 5-4. Figure 5-5 Appearance of the protection grounding cable
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Table 5-4 Technical specifications of the power cable and protection grounding cable Wire Related Parameter Electronic/Electric wire, 450 V/750 V, H07Z, K, 2.5 mm2, yellow green, fire resistant cable with low smoke and no halogen Terminal Related Parameter Bare crimp terminal, OT, 2.5 mm2, M4, tin plating, pre-insulated ring terminal, 16-14AWG, blue
NOTE
In the case of the OptiX PTN 910 equipment, there are following limitations on mapping relations between the cable length and the cross-sectional area. If the cross-sectional area is 2.5 mm2, the maximum cable length is 50 m.
5.4 Service Cables

The service cables include Ethernet cables, 75-ohm 16 x E1 cables, 120-ohm 16 x E1 cables, and telephone wires. 5.4.1 Ethernet Cables On the OptiX PTN 910, Ethernet cables are used to input and output Ethernet service signals. 5.4.2 75-Ohm 16 x E1 Cables On the OptiX PTN 910, Anea96 connectors are used to input and output 75-ohm E1 signals. 5.4.3 120-Ohm 16 x E1 Cables On the OptiX PTN 910, Anea96 connectors are used to input and output 120-ohm E1 signals. 5.4.4 xDSL Cables On the OptiX PTN 910, the telephone wires with RJ-11 connectors are used to input and output ADSL and G.SHDSL service signals.
5.4.1 Ethernet Cables

On the OptiX PTN 910, Ethernet cables are used to input and output Ethernet service signals. Ethernet cables are also referred to as network cables and can be classified into straight through network cables and crossover network cables according to the connection sequence of the copper cores in the cables. The Ethernet service interfaces on the equipment are adaptive to the straight through network cables and crossover network cables. Hence, you can connect either type of the network cables to the Ethernet service interfaces as required. Ethernet cables need to be made on site.
Structure
Figure 5-6 shows the appearance of the network cable.
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Figure 5-6 Appearance of the network cable
RJ-45 connectors are used at both ends of a network cable. Figure 5-7 shows an RJ-45 connector and Figure 5-8 shows the structure of the network cable. Figure 5-7 RJ-45 connector
PIN#8 PIN#1
Figure 5-8 Structure of the network cable

RJ-45 network interface connector
Label 1
Main Ethernet cable Label 2 label 8 1
8 1 X1
X2
NOTE
For a crossover cable, pins 1 and 2 of the RJ-45 connector at one end must be cross-connected to pins 3 and 6 of the RJ-45 connector at the other end respectively.
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Pin Assignment
Table 5-5 lists the pin assignment of the network cable connector. Table 5-5 Pin assignment of the network cable connector Straight Through Cable Conne ctor X1 Pin X1.1 X1.2 X1.3 X1.6 X1.4 X1.5 X1.7 X1.8 Connec tor X2 Pin X2.1 X2.2 X2.3 X2.6 X2.4 X2.5 X2.7 X2.8 Color Relatio n Twisted pair Crossover Cable Connec tor X1 Pin X1.1 X1.2 Twisted pair X1.3 X1.6 Twisted pair X1.4 X1.5 X1.7 X1.8 Conne ctor X2 Pin X2.3 X2.6 X2.1 X2.2 X2.4 X2.5 X2.7 X2.8 Color Relatio n Twisted pair
Whiteorange Orange Whitegreen Green Blue Whiteblue Whitebrown Brown
Whiteorange Orange Whitegreen Green Blue White-blue Whitebrown Brown
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Technical Specifications
Table 5-6 lists the technical specifications of the network cable. For the technical specifications of connector X1/X2, see Figure 5-8 and Figure 5-6. Table 5-6 Technical specifications of the network cable Item Connector X1/X2 Cable type Number of cores Specification Network Interface Connector, 8-Bit 8PIN, Shielded, Crystal Model Connector Twisted-Pair Cable, 100ohm,Category 5e, 0.52mm, 24AWG, 8Cores, 4Pairs, PANTONE 430U Eight
5.4.2 75-Ohm 16 x E1 Cables

On the OptiX PTN 910, Anea96 connectors are used to input and output 75-ohm E1 signals.
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At one end of the 75-ohm 16 x E1 cable, the Anea96 connector is used to connect the 75-ohm E1 electrical interface on the board; the other end is connected to the digital distribution frame (DDF). Make the connector as required on site.
Structure
Figure 5-9 shows the appearance of the 75-ohm 16 x E1 cable and Figure 5-10 shows the structure of the cable. Figure 5-9 Appearance of the 75-ohm 16 x E1 cable
Figure 5-10 Structure of the 75-ohm 16 x E1 cable
Main label 1 W
X1
A View A Pos.96 Cable Connector, Anea, 96PIN, Female Connector
Pos .1
Pin Assignment
Table 5-7 lists the pin assignment of the 75-ohm 16 x E1 cable connector.
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Table 5-7 Pin assignment of the 75-ohm E1 cable connector Connecto r Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 49 50 51 52 Cable Core Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring 27 R13 25 R12 23 R11 21 R10 19 R9 17 R8 15 R7 13 R6 11 R5 9 R4 7 R3 5 R2 3 R1 Serial No. 1 R0 Remarks Connecto r Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 73 74 75 76 Cable Core Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring Tip Ring 28 T13 26 T12 24 T11 22 T10 20 T9 18 T8 16 T7 14 T6 12 T5 10 T4 8 T3 6 T2 4 T1 Serial No. 2 T0 Remarks
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Connecto r Pin 53 54 55 56 Shell
Cable Core Tip Ring Tip Ring 31 Serial No. 29
Remarks
Connecto r Pin 77 78
Cable Core Tip Ring Tip Ring 32 Serial No. 30
Remarks
R14
T14
R15
79 80
T15
External braid shielding layer
Table 5-8 Technical specifications of the 75-ohm 16 x E1 cable Item Cable Connector Cable type Diameter of the shielding layer diameter of the internal insulation layer diameter of the internal conductor Number of cores Available length Specification Trunk Cable, 75ohm, 16E1, 1.6mm,Anea 96FI,SYFVZP75-1.1/0.26*32(S), +45deg Cable Connector, Anea, 96PIN, Suite Of Female Connector And Shielding Case, IDC Type, For 28-30 AWG Solid Wire, 1 A Coaxial Cable, SYFVZP-MC 75-1-1*32, 75 ohm, 12.40 mm, 1.1 mm, 0.26 mm, Pantone Warm Gray 1U, Only for OEM 12.4 mm - 1.6 mm - 0.26 mm
32 5 m, 10 m, 15 m, 20 m, 25 m, 30 m, 35 m, 40 m, 45 m, 50 m
5.4.3 120-Ohm 16 x E1 Cables

On the OptiX PTN 910, Anea96 connectors are used to input and output 120-ohm E1 signals. At one end of the a 120-ohm 16 x E1 cable, the Anea96 connector is used to connect the 120ohm E1 electrical interface on the board; the other end is connected to the DDF. Make the connector as required on site.
Structure
Figure 5-11 shows the appearance of the 120-ohm 16 x E1 cable and Figure 5-12 shows the structure of the cable.
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Figure 5-11 Appearance of the 120-ohm 16 x E1 cable
Figure 5-12 Structure of the 120-ohm 16 x E1 cable
Main label 1 W
X1
A View A Pos.96 Cable Connector, Anea, 96PIN, Female Connector
Pos .1
Pin assignment
Table 5-9 lists the pin assignment of the 120-ohm 16 x E1 cable connector. Table 5-9 Pin assignment of the 120-ohm E1 cable connector Connecto r Pin Cable Core White Blue White Relations hip Twisted pair Twisted pair R0 Remarks Connecto r Pin Cable Core White Orange White Relations hip Twisted pair Twisted pair T0 Remarks
1 2 3
25 26
R1
27
T1
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Connecto r Pin
Cable Core Green White Grey Red Orange Red Brown Black Blue Black Green Black Grey White Blue White Green White Grey Red Orange Red Brown Black Blue Black Green Black Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Relations hip
Remarks
Connecto r Pin
Cable Core Brown Red Blue Red Green Red Grey Black Orange Black Brown Yellow Blue White Orange White Brown Red Blue Red Green Red Grey Black Orange Black Brown Yellow Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Twisted pair Relations hip
Remarks
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 49 50 51 52 53 54 55
28 R2 29 30 R3 31 32 R4 33 34 R5 35 36 R6 37 38 R7 39 40 R8 41 42 R9 43 44 R10 45 46 R11 47 48 R12 73 74 R13 75 76 R14 77 78 R15 79
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
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Connecto r Pin
Cable Core Grey Relations hip
Remarks
Connecto r Pin
Cable Core Blue Relations hip
Remarks
56 Shell
80
External braid shielding layer
Table 5-10 Technical specifications of the 120-ohm 16 x E1 cable Item Cable Connector Cable type Core diameter of the inner conductor Number of cores Available length Specification Trunk Cable, 120 ohm, 16E1, 0.4 mm, Anea 96F, 120CC32P0.4P430U(S), +45deg Cable Connector, Anea, 96PIN, Suite Of Female Connector And Shielding Case, IDC Type, For 24-26 AWG Solid Wire - 1 A Twisted-Pair Cable, 120 ohm, SEYVP, 0.4 mm, 26AWG, 32Pairs, Pantone 430U 0.4 mm 32 twisted pairs 5 m, 10 m, 15 m, 20 m, 25 m, 30 m, 35 m, 40 m, 45 m, 50 m
5.4.4 xDSL Cables

On the OptiX PTN 910, the telephone wires with RJ-11 connectors are used to input and output ADSL and G.SHDSL service signals. The connectors at both ends of the telephone wire are RJ-11 connectors.
Structure
Figure 5-13 shows the structure of the telephone wire used as an xDSL cable.
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Figure 5-13 Structure of the telephone wire
1 6 1 X1 W
Main label 6 1 X2 15 m
1. Telephone wire RJ-11 crystal connector
Pin Assignment
Table 5-11 lists the pin assignment of the ADSL cable connector and Table 5-11 lists the pin assignment of the G.SHDSL cable connector. Table 5-11 Pin assignment of the ADSL cable connector (RJ-11) Connector X1 X1.1 X1.2 X1.3 X1.4 X1.5 X1.6 Connector X2 X2.1 X2.2 X2.3 X2.4 X2.5 X2.6 Description Unspecified Unspecified Ring Tip Unspecified Unspecified
Table 5-12 Pin assignment of the G.SHDSL cable connector Connector X1 X1.1 X1.2 X1.3 X1.4 X1.5 X1.6 Connector X2 X2.1 X2.2 X2.3 X2.4 X2.5 X2.6 Description Unspecified Unspecified Tip Ring Unspecified Unspecified
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Table 5-13 lists the technical specifications of the xDSL cable (telephone wire). Table 5-13 Technical specifications of the xDSL cable Item RJ-11 Connector X1/ X2 Cable Number of cores Available length Specification Network Interface Connector, 6-Bit 4PIN, Crystal Model Connector, Matching 26-28AWG Electronic and Power Cable, 150 V,UL20251, 28AWG, Black, 1 A, 2 Cores Telephone Cable 2 15 m
5.5 Management Cables

On the OptiX PTN 910, Ethernet cables are used to input and output NM signals. The management cables for the OptiX PTN 910 include Ethernet cables and orderwire telephone wires.
l
Ethernet cables are classified into straight through cables and crossover cables, and are used for communication between the equipment and the NMS computer. Both the NM interface and 64 kbit/s data-synchronization interface on the equipment are adaptive to a straight through cable or a crossover cable.
Ethernet Cables
Figure 5-14 shows an RJ-45 connector used at the end of the Ethernet cable. When the cable is connected to the ETH/OAM interface, the pin assignment of the RJ-45 connector is as listed in Table 5-14; when the cable is connected to the EXT/F1 interface, the pin assignment of the RJ-45 connector is as listed in Table 5-15. Table 5-16 lists the technical specifications of the Ethernet cable. Figure 5-14 RJ-45 connector
PIN#8 PIN#1
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Table 5-14 Pin assignment of the RJ-45 connector (ETH/OAM) Connecto r Pin 1 2 3 6 4 5 7 8 Color White-orange Orange White-green Green Blue White-blue White-brown Brown Twisted pair Twisted pair Twisted pair Relation Twisted pair Usage Transmit positive of the NM interface Transmit negative of the NM interface Receive positive of the NM interface Receive negative of the NM interface Grounding end of the NM serial interface Receive end of the NM serial interface Unspecified Transmit end of the NM serial interface
Table 5-15 Pin assignment of the RJ-45 connector (EXT/F1) Connector Pin 1 2 3 6 4 5 7 8 Color White-orange Orange White-green Green Blue White-blue White-brown Brown Twisted pair Twisted pair Twisted pair Relation Twisted pair Usage Transmit positive of the extended Ethernet interface Transmit negative of the extended Ethernet interface Receive positive of the extended Ethernet interface Receive negative of the extended Ethernet interface Transmit positive of the 64 kbit/s synchronous data interface Transmit negative of the 64 kbit/s synchronous data interface Receive positive of the 64 kbit/s synchronous data interface Receive negative of the 64 kbit/s synchronous data interface
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Table 5-16 Technical specifications of the Ethernet cable Item Connector Cable type Number of cores Specification Network Interface Connector, 8-Bit 8PIN, Shielded, Crystal Model Connector Twisted-Pair Cable, 100ohm,Category 5e, 0.52mm, 24AWG, 8Cores, 4Pairs, PANTONE 430U Eight
5.6 Clock Cables

The clock cables used on the OptiX PTN 910 include external clock cables and 120-to-75-ohm clock cables. 5.6.1 External Clock Cables On the OptiX PTN 910, the external clock cables with RJ-45 connectors are used to input and output the external clock or time signals. 5.6.2 Clock Bridging Cable On the OptiX PTN 910, the 120-to-75-ohm clock cable is used as the clock bridging cable.
5.6.1 External Clock Cables

On the OptiX PTN 910, the external clock cables with RJ-45 connectors are used to input and output the external clock or time signals. The external clock cables can be connected to the CLK1/TOD1 and CLK2/TOD2 interfaces on the OptiX PTN 910.
Structure
Figure 5-15 shows the structure of the RJ-45 connector used on the external clock cable. Figure 5-15 Structure of the RJ-45 Connector
PIN#8 PIN#1
Pin Assignment
The external clock cables must be made on the equipment installation site. When the CLK1/ TOD1 and CLK2/TOD2 interfaces are used as external clock interfaces, the pin assignment of
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the RJ-45 connector is as listed in Table 5-17; when the CLK1/TOD1 and CLK2/TOD2 interfaces are used as external time interfaces, the pin assignment of the RJ-45 connector is as listed in Table 5-18. Table 5-17 Pin assignment of the RJ-45 connector (external clock mode) Connector Pin 1 2 3 6 4 5 7 8 Color White-orange Orange White-green Green Blue White-blue White- brown Brown Twisted pair Twisted pair Twisted pair Relation Twisted pair Description Receive negative of CLK Receive positive of CLK Unspecified Unspecified Transmit negative of CLK Transmit positive of CLK Unspecified Unspecified
Table 5-18 Pin assignment of the RJ-45 connector (external time mode) Connecto r Pin Color Relation Description 1PPS + Time Information Mode White-orange Orange White-green Green Blue White-blue White-brown Brown Twisted pair Twisted pair Twisted pair Twisted pair Unspecified Unspecified Negative of 1PPS signals Positive of 1PPS signals Grounding terminal Grounding terminal Negative of time information Positive of time information DCLS Mode Unspecified Unspecified Negative of DCLS signals Positive of DCLS signals Grounding terminal Grounding terminal Unspecified Unspecified
1 2 3 6 4 5 7 8
Table 5-19 lists the technical specifications of the external clock cable.
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Table 5-19 Technical specifications of the external clock cable Item Connector Cable type Number of cores Specification Network Interface Connector, 8-Bit 8PIN, Crystal Model Connector Twisted-Pair Cable, 100 ohm, Category 5e, 0.52 mm, 24AWG, 8 Cores, 4 Pairs, PANTONE 430U Eight
5.6.2 Clock Bridging Cable

On the OptiX PTN 910, the 120-to-75-ohm clock cable is used as the clock bridging cable.
Structure
Figure 5-16 shows the structure of the 120-to-75-ohm clock bridging cable. Figure 5-16 Structure of the clock bridging cable
120-ohm or 75ohm conversion connector
W1
Heat-shrink tube
View A
Label
RJ-45 connector
A
Main label
Heat-shrink tube
W5
8 1
Heat-shrink tube
W2 W3
X1
W4
30 m
Pin Assignment
Table 5-20 lists the pin assignment of the clock bridging cable connector. Table 5-20 Pin assignment of the clock bridging cable connector 120-Ohm Cable Connector Pin X1.1 X1.2 X1.4 X1.5
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75-Ohm Cable Color Orange White Blue White Twisted pair W2 Relation Twisted pair Core No. W1
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120-Ohm Cable Connector Pin X1.3 X1.6 X1.7 X1.8 Color Green White White Brown Twisted pair Relation Twisted pair
75-Ohm Cable Core No. W3
W4
Table 5-21 lists the technical specifications of the clock bridging cable. Table 5-21 Technical specifications of the clock bridging cable Item Cable Connector X1 type 120-ohm cable type 75-ohm cable type Cable length Specification Single Cable, 120 ohm To 75 ohm Clock Cable, 30 m, MP8-II, 120CC4P0.4P430U(S)+4*SYV75-2/0.34(S) Network Interface Connector,8-Bit 8PIN, Crystal Model Connector Twisted-Pair Cable, 120 ohm, SEYVP, 0.4 mm, 26AWG, 4Pairs, Pantone 430U Coaxial Cable, SYV-75-2-2(4.0Z)-1/0.34 mm, OD3.9 mm, Double-Layer Copper Braid Shielded 30 m
5.7 Alarm Input/Output Cables

On the OptiX PTN 910, the RJ-45 connectors are used to input the alarm signals from the external equipment and output the local alarm signals to the equipment that monitors all the alarms. At one end of the alarm input/output cable, the RJ-45 connector is used to connect to the ALMI/ ALMO interface on the equipment; at the other end, a connector (made as required on site) is used to connect to the external equipment or the equipment that monitors all the alarms.
Structure
Figure 5-17 shows the structure of the alarm input/output cable.
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Figure 5-17 Structure of the alarm input/output cable
RJ-45 Connector
Main label W
8 1 X1
Pin Assignment
Table 5-22 lists the pin assignment of the alarm input/output alarm cable connector. Table 5-22 Pin assignment of the alarm input/output cable connector Connector Pin 1 2 3 6 4 5 7 8 Color White-orange Orange White-green Green Blue White-blue White- brown Brown Twisted pair Twisted pair Twisted pair Relation Twisted pair Description Alarm input 1 Ground for alarm input 1 Alarm input 2 Ground for alarm input 2 Alarm input 3 Ground for alarm input 3 Alarm output positive Alarm output negative
Table 5-23 lists the technical specifications of the alarm input/output cable. Table 5-23 Technical specifications of the alarm input/output cable Item Connector X1
5-22
Specification Network Interface Connector, 8-Bit 8PIN, Crystal Model Connector

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Item Cable type
Specification Twisted-Pair Cable, 100 ohm, Category 5e, 0.52 mm, 24AWG, 8 Cores, 4 Pairs, PANTONE 430U
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A Safety Labels
A
Label Description
There are labels on the chassis and boards. See Table A-1. Table A-1 Label description Figure Type ESD protection label
Safety Labels
The equipment has various safety labels. This section describes the suggestions and locations of these safety labels.
Description The label suggests the electrostaticsensitive equipment. The label indicates the position of the grounding terminal. When the equipment is installed in a 19-inch cabinet, it is recommended that you use the grounding terminal specified in this label. The label indicates the position of the general grounding terminal. When the equipment is installed in a cabinet rather than a 19-inch cabinet, it is recommended that you use the grounding terminal specified in this label. The label suggests that do not touch the fan leaves when the fan is rotating. The label indicates the precaution that should be taken for operations on the PIU board. For details, see Label
Chassis grounding label
Chassis grounding label
Fan warning label
Operation warning label

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A Safety Labels
Figure
/QUALIFICATION CARD
Type Qualification label
Description The equipment is qualified.
HUAWEI
HUAWEI TECHNOLOGIES CO.,LTD.
MADE IN CHINA
Product nameplate label

OptiX PTN 910
POWER RATING: -48-60V;3.2A
The label suggests the product name and certification.
Class 1 Laser Product
N14036
HUAWEI TECHNOLGIES CO.,LTD.
MADE IN CHINA
Label Position
Figure A-1 shows positions of labels on the chassis. Figure A-1 Label position
OptiX PTN 910
POWER RATING: -48 -60V;3.2A
Class 1 Laser Product
/QUALIFICATION CARD
N14036
HUAWEI
HUAW EI TECHNOLOGIES CO.,LTD.
MADE IN CHINA
H U A W E I TE C H N O LG I E S C O . , LTD .
MADE IN CHINA
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B Indicators
B
Index of Indicators
For boards and their indicators, see Boards and Their Indicators. For board status indicators, see:
l l l l l l
Indicators
This section describes the names of various indicators and their indications.
Description of the Board Status Indicator (STAT) Description of the Program Running Indicator (PROG) Description of the Synchronization Status Indicator (SYNC) Description of the Service Status Indicator (SRV) Description of the Power Supply Status Indicator (PWRA/PWRB) Description of the Fan Status Indicator (FAN)
For service port status indicators, see:

l l
Description of the Service Port Transmitting/Receiving Status Indicator (ACT) Description of the Port Status Indicator of the CXPA/CXPB/CXPG/CXPH/EF8T (LINK) Description of the Port Connection and Data Transmitting/Receiving Status Indicators of the CXPG/CXPH (L/A) Description of the EF8F/EG2 Port Connection Status Indicator (LINK) Description of the CD1 Port Status Indicator (LOS1/LOS2) Description of the Port Status Indicators of the ADS2 (LINK1 and LINK2) Description of the Port Status Indicators of the SHD4/SHD4I (LINK1, LINK2, LINK3, and LINK4)
l l l l
For system alarm indicators, see:

l l l
Description of the Critical Alarm Indicator (CRIT) Description of the Major Alarm Indicator (MAJ) Description of the Minor Alarm Indicator (MIN)
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B Indicators
For combination of indicators in different start statuses on the system control board, see Description of the Start Status Indicator Combination on the System Control Board.
Boards and Their Indicators

Board CXPA/CXPB CXPG/CXPH EF8T EF8F EG2 ML1/ML1A CD1 ADS2A/ASD2B SHD4 SHD4I PIU FAN Indicator STAT, PROG, SYNC, SRV, CRIT, MAJ, MIN, LINK, ACT STAT, PROG, SYNC, SRV, CRIT, MAJ, MIN, L/A1, L/A2, LINK, ACT STAT, SRV, LINK, ACT STAT, SRV, LINK1 - LINK8 STAT, SRV, LINK1, LINK2, ACT1, ACT2 STAT, SRV STAT, SRV, LOS1, LOS2 STAT, SRV, LINK1, LINK2 STAT, SRV, LINK1, LINK2, LINK3, LINK4 STAT, SRV, LINK1, LINK2, LINK3, LINK4 PWRA, PWRB FAN
Description of the Board Status Indicator (STAT)

Status On (green) On (red) On (orange) Off Indication The board is working normally. The board hardware is faulty. The interface board is not loaded with the logic.
l l
No power is input. The board is not running.
Description of the Program Running Indicator (PROG)

Status On (green) Indication
l l
The board software is being initialized. The board software is normally initialized, and the board software is running normally.
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B-2
B Indicators
Status On (red)
Indication
l l l
The memory self-check fails. The board software or the logic file is lost. Loading of the board software fails.
On for 100 ms and off for 100 ms alternately (green) On for 300 ms and off for 300 ms alternately (green) On for 100 ms and off for 100 ms alternatively (red) Off
Loading of the board software is in process. The BIOS is guiding the upper-layer software. The BIOS self-check fails. No power is input.
Description of the Synchronization Status Indicator (SYNC)

l
The clock works in free-run mode and the system clock priority list is not set. By default, the system clock priority list contains only internal sources. The clock works in locked mode and is tracing a clock source other than the internal sources in the priority list. The system clock is working in time synchronization mode, and the PTP time and system clock are in the tracing state. The system clock priority list is set. All the clock sources, however, are lost except for the internal clock sources. The clock works in holdover mode or free-run mode. The system clock is working in time synchronization mode, but no synchronization source is available. The system clock and PTP time are working in holdover or free-run mode.
On (red)
Description of the Service Status Indicator (SRV)

Status On (green) Indication Services are running normally and no service-related alarm occurs (including the situation where the board is activated but not configured with services). A critical or major service-related alarm occurs. A minor or remote service-related alarm occurs.
On (red) On (orange)
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B-3
B Indicators
Status Off
Indication
l l
No power is input. The board is not running.
Description of the Power Supply Status Indicator (PWRA/PWRB)

Status On (green) Off Indication Power is accessed.
l l
No power is accessed. The power supply poles are inversely connected.
Description of the Fan Status Indicator (FAN)

Status On (green) On (red) Off Indication The fans are working normally. The fans are working abnormally.
l l
The fans are not powered. No fan is installed.
Description of the Service Port Transmitting/Receiving Status Indicator (ACT)

Status Blinking (orange) Off Indication The data interface is transmitting or receiving data. The data interface is not transmitting or receiving data.
Description of the Port Status Indicator of the CXPA/CXPB/CXPG/CXPH/EF8T (LINK)

Status On (green) Off Indication The physical port connection is normal. physical port connection fails.
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B Indicators
Description of the Port Connection and Data Transmitting/Receiving Status Indicators of the CXPG/CXPH (L/A)
Status On (green) Blinking (orange) Off Indication The connection at the physical port is normal. The connection at the physical port is normal, and data is received or transmitted at the port. The physical connection fails.
Description of the EF8F/EG2 Port Connection Status Indicator (LINK)

Status On (green) Off Indication The physical connection of the port is normal. The physical connection of the port is faulty.
Description of the CD1 Port Status Indicator (LOS1/LOS2)

Status On (green) On (red) Off Indication The signal at the port is normal. The signal at the port is lost. The optical module is offline.
Description of the Port Status Indicators of the ADS2 (LINK1 and LINK2)
Status On (green) On for 300 ms and off for 300 ms alternately (green) On for 100 ms and off for 100 ms alternately (green) Off Indication Physical connections at the service port are normal and links are activated.
l l
The board software is normally initialized No service is accessed.
Service connections are being activated. Cables at the service port are not connected.
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B Indicators
Description of the Port Status Indicators of the SHD4/SHD4I (LINK1, LINK2, LINK3, and LINK4)
l
Physical connections at the service port are normal and links are activated. The board software is being initialized.
On for 300 ms and off for 300 ms alternately (green)
Service connections are being activated.
Description of the Critical Alarm Indicator (CRIT)

Status On (red) Off Indication Critical alarms are generated in the equipment. No critical alarms are generated in the equipment.
Description of the Major Alarm Indicator (MAJ)

Status On (orange) Off Indication Major alarms are generated in the equipment. No major alarms are generated in the equipment.
Description of the Minor Alarm Indicator (MIN)

Status On (yellow) Off Indication Minor alarms are generated in the equipment. No minor alarms are generated in the equipment.
Description of the Start Status Indicator Combination on the System Control Board
From power on to normal running, the system control board goes through various status. Table B-1 shows the indicator combination corresponding to these statuses.
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B Indicators
Table B-1 Start status indicator combination SN Status Indicator STAT 1 2 3 4 5 The system control board is not powered on. The BIOS is being started. The BIOS is started, and guides and loads the board software. The upper-layer software is being initialized. The upper-layer software initialization is complete, but the system control board is not running. The system control board is running. Off Off Off Green Green PROG Off Green Blinking (green) Green Green SRV Off Off Off Off Off
Green
Green
Always ona
NOTE a: When the system control board is running, the SRV indicator may be in red, orange, or green. When services are normal, the indicator is green. For other statuses of the indicator, see Description of the Service Status Indicator (SRV).
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B-7
C Power Consumption and Weight
C
Board CXPA/CXPB CXPG/CXPH EF8T EF8F EG2 ML1/ML1A CD1
Power Consumption and Weight
This chapter lists the power consumption and weight of each board used for the OptiX PTN 910. Table C-1 lists the power consumption and weight of boards. Table C-1 Power consumption and weight Weight (kg) 1.25 1.32 0.53 0.55 0.52 0.56 0.52 0.54 Power Consumption (W) 43.9 46.8 9 12.8 5.9 13.1 16.4 10.5(ADS2A) 10.4(ADS2B) SHD4 SHD4I PIU FAN 0.60 0.60 0.12 0.2 7.4 7.5 0.5 2.3
ADS2A/ADS2B
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C-1
D Board Configuration Parameters
D
l
Board Configuration Parameters
You can use the U2000 to configure each parameter of the interface boards, cross-connect and system control board.
Parameters of the Interface Board

The configurable parameters of the interface boards are the Ethernet interface, PDH interface, ADSL interface, G.SHDSL interface, SDH interface, path configuration, J0, J1, J2, C2, V5, automatic laser shutdown (ALS), and spare timeslot recovery value. The attributes of an Ethernet interface cover the general attributes, Layer 2 attributes, Layer 3 attributes, advanced attributes and flow control. To configure an Ethernet interface, configure the physical parameters, link layer parameters, network layer parameters and flow control schemes. The attributes of a PDH interface cover the general attributes, Layer 3 attributes and advanced attributes. To configure an E1 interface, configure the physical parameters, network layer parameters, signal frame format, clock mode and loopback scheme. The attributes of an ADSL interface cover the general attributes, VPI/VCI of the interface, and enabling status of the tunnel at the virtual interface The attributes of a G.SHDSL interface cover the general attributes, the interface mode (ATM mode,,IMA mode and EFM mode included). The attributes of an SDH interface cover the general attributes, Layer 2 attributes, Layer 3 attributes and advanced attributes. To configure an SDH interface, configure the physical parameters, link layer parameters and network layer parameters. The attributes of the path configuration cover the VC12 frame format and frame mode of a channelized SDH interface. The J0 byte is continually transmitted to carry section access point identifiers, according to which the receive end verifies the constant connection to the intended transmit end. It is recommended to set the J0 byte to "0". The J1 byte is the path tracing byte. The transmit end successively transmits the higher order access point identifiers, according to which the receive end verifies the constant connection to the intended transmit end. When detecting mismatch of the J1 bytes, the receive end inserts the HP_TIM alarm in the corresponding path. The J2 byte is a VC-12 path tracing byte. The transmit end successively transmits the lower order access point identifiers based on the negotiation of the two ends. According to these
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access point identifiers, the receive end verifies the constant connection to the intended transmit end in this path.
l
The C2 byte is the signal label byte, which indicates the multiplexing structure of the VC frames and the payload property. The received C2 should be consistent with the transmitted C2. If the C2 bytes are mismatched, the local end inserts the HP_SLM alarm in the corresponding VC-4 path. Table D-1 lists the mapping relation between the service type and setting of the C2. Table D-1 Mapping relation between the service type and C2 byte Input Service Type TUG structure ATM mapping HDLC, PPP framed signal mapping Unequipped C2 Byte (in Hex) 02 13 16 00
As a path status and signal identification byte, the V5 byte detects the bit error and indicates the remote fault and failure in the lower order path. Table D-2 lists the mapping relation between the service type and V5 byte. Table D-2 Mapping relation between the service type and V5 byte Input Service Type Asynchronization Unequipped or supervisory unequipped V5 Byte (in Hex) 02 00
l l
To configure the ALS is to set the parameters of the optical interface. To ensure the valid utilization of the path, the spare timeslots are eliminated when the signals are encapsulated into the network. In this way, the TDM frame is partially stuffed. To recover the TDM frame at the service sink, the spare timeslots eliminated during encapsulation are added again.
Parameters of the Cross-Connect and System Control Board

The configurable parameters of the cross-connect and system control board board are the environment monitor interface, the external time interface and the phase-locked source output by external clock. You can set the relay control mode and enable or disable the major alarm relay and critical alarm relay to configure the environment monitor interface. You can set the basic Attribute, BMC, and Cable Transmitting Distance to configure the external time interface. You can set the output mode, output timeslot, output threshold, failure condition and failure action of the 2M phase-locked source external clock
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For details, see OptiX PTN 910 Configuration Guide and the U2000 Online Help.
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D-3
E Glossary
E
A
Administrator Alarm alarm cable APS Asynchronous Transfer Mode The cable for generation of visual or audio alarms. See Automatic Protection Switching
Glossary
A user who has authority to access all the Management Domains of the EMLCore product. He has access to the whole network and to all the management functionalities. A message reported when a fault is detected by a device or by the network management system during the process of polling devices. Each alarm corresponds to a recovery alarm. After a recovery alarm is received, the status of the corresponding alarm changes to cleared.
A data transfer technology based on cell, in which packets allocation relies on channel demand. It supports fast packet switching to achieve efficient utilization of network resources. The size of a cell is 53 bytes, which consist of 48-byte payload and 5-byte header. See Asynchronous Transfer Mode Automatic Protection Switching (APS) is the capability of a transmission system to detect a failure on a working facility and to switch to a standby facility to recover the traffic.
ATM Automatic Protection Switching
B
backup A periodic operation performed on the data stored in the database for the purposes of database recovery in case that the database is faulty. The backup also refers to data synchronization between active and standby boards. A range of transmission frequencies that a transmission line or channel can carry in a network. In fact, it is the difference between the highest and lowest frequencies the transmission line or channel. The greater the bandwidth, the faster the data transfer rate. See Bit Error Rate The binding strap is 12.7 mm wide, with one hook side (made of transparent polypropylene material) and one mat side (made of black nylon material).
bandwidth
BER binding strap
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E-1
E Glossary
bit error Bit Error Rate breaker bundling
An incompatibility between a bit in a transmitted digital signal and the corresponding bit in the received digital signal. Bit error rate. Ratio of received bits that contain errors. BER is an important index used to measure the communications quality of a network. A breaker is a device that connects/disconnects power to a circuit. An optional multiplexing operation, whereby more than one user message may be carried in the same SCTP packet.
C
Cable distribution plate A component which is used to arrange the cables in order. cable tie CE CES Circuit Emulation Service The tape used to bind the cables. See Customer Edge See Circuit Emulation Service A function with which the E1/T1 data can be transmitted through ATM networks. At the transmission end, the interface module packs timeslot data into ATM cells. These ATM cells are sent to the reception end through the ATM network. At the reception end, the interface module re-assigns the data in these ATM cells to E1/T1 timeslots. The CES technology guarantees that the data in E1/T1 timeslots can be recovered to the original sequence at the reception end. A device that sends requests, receives responses, and obtains services from the server. A part of BGP/MPLS IP VPN model. It provides interfaces for direct connection to the Service Provider (SP) network. A CE can be a router, switch, or host.
client Customer Edge
D
Data Communication Network DCN DDF diamond-shaped nut Digital Distribution Frame A communication network used in a TMN or between TMNs to support the Data Communication Function (DCF). See Data Communication Network See Digital Distribution Frame A type of nut that is used to fasten the wiring frame to the cabinet. A type of equipment used between the transmission equipment and the exchange with transmission rate of 2 to 155 Mbit/s to provide the functions such as cables connection, cable patching, and test of loops that transmitting digital signals.
E
E-AGGR E-LAN ejector lever Ethernet-Aggregation See Ethernet LAN A lever for removing circuit boards from an electronic chassis.
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E Glossary
electromagnetic compatibility
Electromagnetic compatibility is the condition which prevails when telecommunications equipment is performing its individually designed function in a common electromagnetic environment without causing or suffering unacceptable degradation due to unintentional electromagnetic interference to or from other equipment in the same environment. [NTIA]
ElectroStatic Discharge The sudden and momentary electric current that flows between two objects at different electrical potentials caused by direct contact or induced by an electrostatic field. EMC ESD Ethernet See electromagnetic compatibility See ElectroStatic Discharge A technology complemented in LAN. It adopts Carrier Sense Multiple Access/Collision Detection. The speed of an Ethernet interface can be 10 Mbit/s, 100 Mbit/s, 1000 Mbit/ s or 10000 Mbit/s. The Ethernet network features high reliability and easy maintaining.. Ethernet LAN. A L2VPN service type that is provided for the user Ethernet in different domains over the PSN network. For the user Ethernet, the entire PSN network serves as a Layer 2 switch. See European Telecommunications Standards Institute A standards-setting body in Europe. Also the standards body responsible for GSM.
Ethernet LAN
ETSI European Telecommunications Standards Institute
F
fault A failure to implement the function while the specified operations are performed. A fault does not involve the failure caused by preventive maintenance, insufficiency of external resources and intentional settings. A frame, starting with a header, is a string of bytes with a specified length. Frame length is represented by the sampling circle or the total number of bytes sampled during a circle. A header comprises one or a number of bytes with pre-specified values. In other words, a header is a code segment that reflects the distribution (diagram) of the elements prespecified by the sending and receiving parties.
frame
G
GE Gigabit Ethernet See Gigabit Ethernet GE adopts the IEEE 802.3z. GE is compatible with 10 Mbit/s and 100 Mbit/s Ethernet.It runs at 1000Mbit/s. Gigabit Ethernet uses a private medium, and it does not support coaxial cables or other cables. It also supports the channels in the bandwidth mode. If Gigabit Ethernet is, however, deployed to be the private bandwidth system with a bridge (switch) or a router as the center, it gives full play to the performance and the bandwidth. In the network structure, Gigabit Ethernet uses full duplex links that are private, causing the length of the links to be sufficient for backbone applications in a building and campus. Components to guide, position, and support plug-in boards.
guide rail
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E-3
E Glossary
H
hot standby A mechanism of ensuring device running security. The environment variables and storage information of each running device are synchronized to the standby device. When the faults occur on the running device, the standby device can take over the services in the faulty device in automatic or manual way to ensure the normal running of the entire system. See hot standby
HSB
I
IEC IEEE IMA Institute of Electrical and Electronics Engineers International Electrotechnical Commission International Telecommunication Union Telecommunication Standardization Sector Internet Protocol See International Electrotechnical Commission See Institute of Electrical and Electronics Engineers See Inverse Multiplexing over ATM A society of engineering and electronics professionals based in the United States but boasting membership from numerous other countries. The IEEE focuses on electrical, electronics, computer engineering, and science-related matters. The International Electrotechnical Commission (IEC) is an international and nongovernmental standards organization dealing with electrical and electronical standards. An organization that coordinates standards for telecommunications on behalf of the International Telecommunication Union (ITU). It is based in Geneva, Switzerland. Prior to 1992, the ITU-T was known as the International Telegraph and Telephone Consultative Committee (CCITT, from the French name "Comit| consultatif international t|l|phonique et t|l|graphique"). The TCP/IP standard protocol that defines the IP packet as the unit of information sent across an internet and provides the basis for connectionless, best-effort packet delivery service. IP includes the ICMP control and error message protocol as an integral part. The entire protocol suite is often referred to as TCP/IP because TCP and IP are the two fundamental protocols. IP is standardized in RFC 791. Inverse Multiplexing over ATM. The ATM inverse multiplexing technique involves inverse multiplexing and de-multiplexing of ATM cells in a cyclical fashion among links grouped to form a higher bandwidth logical link whose rate is approximately the sum of the link rates. This is referred to as an IMA group. See Internet Protocol See International Telecommunication Union - Telecommunication Standardization Sector
Inverse Multiplexing over ATM
IP ITU-T
L
L3VPN Layer3 Virtual Private Network Label Switching Router The Label Switching Router (LSR) is the basic element of MPLS network. All LSRs support the MPLS protocol. The LSR is composed of two parts: control unit and forwarding unit. The former is responsible for allocating the label, selecting the route, creating the label forwarding table, creating and removing the label switch path; the latter forwards the labels according to groups received in the label forwarding table.
E-4 Huawei Proprietary and Confidential Copyright Huawei Technologies Co., Ltd. Issue 04 (2010-08-28)
E Glossary
LAN Laser
See Local Area Network A component that generates directional optical waves of narrow wavelengths. The laser light has better coherence than ordinary light. The fiber system takes the semi-conductor laser as the light source. See Loopback A network communications channel consisting of a circuit or transmission path and all related equipment between a sender and a receiver. A link is used to connect signaling points (SPs) and signaling transfer points (STPs) and transmit signaling messages. Linear Multiplex Section Protection A network formed by the computers and workstations within the coverage of a few square kilometers or within a single building. It features high speed and low error rate. Ethernet, FDDI, and Token Ring are three technologies used to implement a LAN. Current LANs are generally based on switched Ethernet or Wi-Fi technology and running at 1,000 Mbit/ s (that is, 1 Gbit/s). A troubleshooting technique that returns a transmitted signal to its source so that the signal or message can be analyzed for errors. The subrack close to the bottom of the cabinet when a cabinet contains several subracks. See Label Switching Router
LB link
LMSP Local Area Network
Loopback Lower subrack LSR
M
Maintenance Point Merge Point Maintenance Point (MP) is one of either a MEP or a MIP. Merge Point. The LSR where one or more backup tunnels rejoin the path of the protected LSP downstream of the potential failure. The same LSR may be both an MP and a PLR simultaneously. See Merge Point See Maintenance Point See Multi-Protocol Label Switch A technology that uses short tags of fixed length to encapsulate packets in different link layers, and provides connection-oriented switching for the network layer on the basis of IP routing and control protocols. It improves the cost performance and expandability of networks, and is beneficial to routing.
MP MP MPLS Multi-Protocol Label Switch
N
N63E cabinet NE network element A cabinet which is 600 mm in width and 300 mm in depth, compliant with the standards of the ETSI. See network element A network element (NE) contains both the hardware and the software running on it. One NE is at least equipped with one system control board which manages and monitors the entire network element. The NE software runs on the system control board. This is an internal interface within a network linking two or more elements.
Network to Network Interface

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E-5
E Glossary
NNI
See Network to Network Interface
O
OAM ODF Operation, Administration and Maintenanc See Operation, Administration and Maintenanc See Optical Distribution Frame Operation, Administration and Maintenance. A group of network support functions that monitor and sustain segment operation, activities that are concerned with, but not limited to, failure detection, notification, location, and repairs that are intended to eliminate faults and keep a segment in an operational state and support activities required to provide the services of a subscriber access network to users/subscribers. A frame which is used to transfer and spool fibers.
Optical Distribution Frame
P
packet 1. A sequence of binary digits including data and call control signals that is switched as a composite whole. The data, call control signals, and possibly error control information, are arra nged in a specific format. 2. A short block of data of fixed length and destination information. It is the information transmission unit of the packet switching network. The maximum length of the information packet reaches 8000 bit. The information packet can be tranfered from one metwork to another network. 3. Data packets and local packets. Logical grouping of information that includes a header containing control information and (usually) user data. Packets are most often used to refer to network layer units of data. A MAN and WAN technology that provides point-to-point data connections. The POS interface uses SDH/SONET as the physical layer protocol, and supports the transport of packet data (such as IP packets) in MAN and WAN. See Printed Circuit Board See Power Distribution Unit Protocol Data Unit
Packet over SDH/ SONET PCB PDU PDU
Point-to-Point Protocol A protocol on the data link layer, provides point-to-point transmission and encapsulates data packets on the network layer. It is located in layer 2 of the IP protocol stack. POS Power Distribution Unit PPP Printed Circuit Board See Packet over SDH/SONET The power distribution unit performs AC or DC power distribution. See Point-to-Point Protocol A board used to mechanically support and electrically connect electronic components using conductive pathways, tracks, or traces, etched from copper sheets laminated onto a non-conductive substrate. An emulated connection between two PEs for transmitting frames. The PW is established and maintained by PEs through signaling protocols. The status information of a PW is maintained by the two end PEs of a PW. Packet Transport Network
Pseudo wire
PTN
E-6
E Glossary
PW
See Pseudo wire
R
Radio Network Controller RNC route A device used in the RNS to control the usage and integrity of radio resources. See Radio Network Controller A route is the path that network traffic takes from its source to its destination. In a TCP/ IP network, each IP packet is routed independently. Routes can change dynamically.
S
SDH signal cable Synchronous Digital Hierarchy See Synchronous Digital Hierarchy Common signal cables cover the E1cable, network cable, and other non-subscriber signal cable. SDH is a transmission scheme that follows ITU-T G.707, G.708, and G.709. It defines the transmission features of digital signals such as frame structure, multiplexing mode, transmission rate level, and interface code. SDH is an important part of ISDN and BISDN. It interleaves the bytes of low-speed signals to multiplex the signals to high-speed counterparts, and the line coding of scrambling is only used only for signals. SDH is suitable for the fiber communication system with high speed and a large capacity since it uses synchronous multiplexing and flexible mapping structure.
T
T63 cabinet TPS Tributary Protection Switch Tunnel A cabinet which is 600 mm in width and 300 mm in depth, compliant with the standards of the ETSI. See Tributary Protection Switch Tributary protection switching, a function provided by the equipment, is intended to protect N tributary processing boards through a standby tributary processing board. A channel on the packet switching network that transmits service traffic between PEs. In VPN, a tunnel is an information transmission channel between two entities. The tunnel ensures secure and transparent transmission of VPN information. In most cases, a tunnel is an MPLS tunnel.
U
Upload Upper subrack upward cabling An operation to report some or all configuration data of an NE to the T2000. The configuration data then covers the configuration data stored at the T2000 side. The subrack close to the top of the cabinet when a cabinet contains several subracks. Cables or fibres connect the cabinet with other equipment from the top of the cabinet.
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E-7
E Glossary
V
Virtual Local Area Network VLAN A logical grouping of two or more nodes which are not necessarily on the same physical network segment but which share the same IP network number. This is often associated with switched Ethernet. See Virtual Local Area Network
E-8
Issue 04 (2010-08-28)

OptiX PTN 910 Hardware Description - (V100R002C00 04)

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Network planning engineers Hardware installation engineers System maintenance engineers

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About This Document