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This document discusses algorithmic state machines (ASMs) and their use in VHDL coding for sequential logic synthesis. It begins with an overview of ASM charts and their elements, such as state boxes, decision boxes, and conditional output boxes. It then provides examples of ASM charts modeling Moore and Mealy finite state machines. The document concludes with an example of an ASM chart for a control unit that arbitrates between three request signals to grant access.
This document discusses algorithmic state machines (ASMs) and their use in VHDL coding for sequential logic synthesis. It begins with an overview of ASM charts and their elements, such as state boxes, decision boxes, and conditional output boxes. It then provides examples of ASM charts modeling Moore and Mealy finite state machines. The document concludes with an example of an ASM chart for a control unit that arbitrates between three request signals to grant access.
This document discusses algorithmic state machines (ASMs) and their use in VHDL coding for sequential logic synthesis. It begins with an overview of ASM charts and their elements, such as state boxes, decision boxes, and conditional output boxes. It then provides examples of ASM charts modeling Moore and Mealy finite state machines. The document concludes with an example of an ASM chart for a control unit that arbitrates between three request signals to grant access.
George Mason University ECE 448 FPGA and ASIC Design with VHDL
VHDL Coding for Synthesis
ECE 448 Lecture 11 Algorithmic State Machines 2 ECE 448 FPGA and ASIC Design with VHDL Required reading S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 8.10, Algorithmic State Machine (ASM) Charts S. Lee, Advanced Digital Logic Design, Chapter 3.3, More Advanced VHDL Concepts (handout) 3 ECE 448 FPGA and ASIC Design with VHDL Variables vs. Signals (1) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all;
ENTITY test_delay IS PORT( clk : IN STD_LOGIC; in1, in2 : IN STD_LOGIC; var1_out, var2_out : OUT STD_LOGIC; sig1_out : BUFFER STD_LOGIC; sig2_out : OUT STD_LOGIC ); END test_delay; 4 ECE 448 FPGA and ASIC Design with VHDL Variables vs. Signals (2) ARCHITECTURE behavioral OF test_delay IS
BEGIN
PROCESS(clk) IS VARIABLE var1, var2: STD_LOGIC; BEGIN if (rising_edge(clk)) THEN var1 := in1 AND in2; var2 := var1;
sig1_out <= in1 AND in2; sig2_out <= sig1_out; END IF;
var1_out <= var1; var2_out <= var2;
END PROCESS;
END behavioral; 5 ECE 448 FPGA and ASIC Design with VHDL Simulation result 6 ECE 448 FPGA and ASIC Design with VHDL Sequential Logic Synthesis for Advanced 7 ECE 448 FPGA and ASIC Design with VHDL Sequence detector (for 0111_1110) Step 1. prev_data = 1111_1111 Step 2. while(TRUE) do /* repeat forever */ data_in = next data input; prev_data = prev_data << 1; prev_data(0) = data_in; if (prev_data == 0111_1110) then detected = 1 else detected = 0 end while;
8 ECE 448 FPGA and ASIC Design with VHDL Sequence Detector Entity declaration LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all;
ENTITY seq_det_1 IS PORT( reset_n : IN STD_LOGIC; clk : IN STD_LOGIC; data_in : IN STD_LOGIC; detected : OUT STD_LOGIC ); END seq_det_1; 9 ECE 448 FPGA and ASIC Design with VHDL Architecture 1 with variables & SLL LIBRARY IEEE; USE IEEE.NUMERIC_STD.all;
ARCHITECTURE behavioral_1 OF seq_det_1 IS BEGIN PROCESS(reset_n, clk) VARIABLE prev_data: UNSIGNED(7 DOWNTO 0); BEGIN IF (reset_n = '0') THEN prev_data := B"1111_1111"; ELSIF rising_edge(clk) THEN prev_data := prev_data SLL 1; prev_data(0) := data_in; IF (prev_data = B"0111_1110") THEN detected <= '1'; ELSE detected <= '0'; END IF; END IF; END PROCESS; END behavioral_1; 10 ECE 448 FPGA and ASIC Design with VHDL Architecture 2 with variables ARCHITECTURE behavioral_2 OF seq_det_1 IS BEGIN PROCESS(reset_n, clk) VARIABLE prev_data: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN IF (reset_n = '0') THEN prev_data := B"1111_1111"; ELSIF rising_edge(clk) THEN prev_data := prev_data(6 downto 0) & data_in; IF (prev_data = B"0111_1110") THEN detected <= '1'; ELSE detected <= '0'; END IF; END IF;
END PROCESS; END behavioral_2; 11 ECE 448 FPGA and ASIC Design with VHDL Architecture 3 with signals ARCHITECTURE behavioral_3 OF seq_det_1 IS SIGNAL prev_data: STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN
PROCESS(reset_n, clk) BEGIN IF (reset_n = '0') THEN prev_data <= B"1111_1111"; ELSIF rising_edge(clk) THEN prev_data <= prev_data(6 downto 0) & data_in; IF (prev_data(6 downto 0) & data_in = B"0111_1110") THEN detected <= '1'; ELSE detected <= '0'; END IF; END IF;
END PROCESS; END behavioral_3; 12 ECE 448 FPGA and ASIC Design with VHDL Synthesised circuit data_in 13 ECE 448 FPGA and ASIC Design with VHDL Algorithmic State Machine (ASM) Charts 14 ECE 448 FPGA and ASIC Design with VHDL Algorithmic State Machine Algorithmic State Machine representation of a Finite State Machine suitable for FSMs with a larger number of inputs and outputs compared to FSMs expressed using state diagrams and state tables. 15 ECE 448 FPGA and ASIC Design with VHDL Elements used in ASM charts (1) Output signals or actions (Moore type) State name Condition expression 0 (False) 1 (True) Conditional outputs or actions (Mealy type) (a) State box (b) Decision box (c) Conditional output box 16 ECE 448 FPGA and ASIC Design with VHDL Elements used in ASM charts (2) State box represents a state. Equivalent to a node in a state diagram or a row in a state table. Moore type outputs are listed inside of the box. It is customary to write only the name of the signal that has to be asserted in the given state, e.g., z instead of z=1. Also, it might be useful to write an action to be taken, e.g., Count = Count + 1, and only later translate it to asserting a control signal that causes a given action to take place. 17 ECE 448 FPGA and ASIC Design with VHDL Elements used in ASM charts (3) Decision box indicates that a given condition is to be tested and the exit path is to be chosen accordingly The condition expression consists of one or more inputs to the FSM.
Conditional output box denotes output signals that are of the Mealy type. The condition that determines whether such outputs are generated is specified in the decision box. 18 ECE 448 FPGA and ASIC Design with VHDL Moore FSM Example 1: State diagram C z 1 = Reset B z 0 = A z 0 = w 0 = w 1 = w 1 = w 0 = w 0 = w 1 = 19 ECE 448 FPGA and ASIC Design with VHDL w w w 0 1 0 1 0 1 A B C z Reset w w w 0 1 0 1 0 1 A B C z Reset ASM Chart for Moore FSM Example 1 20 ECE 448 FPGA and ASIC Design with VHDL USE ieee.std_logic_1164.all ;
ENTITY simple IS PORT ( clock : IN STD_LOGIC ; resetn : IN STD_LOGIC ; w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END simple ;
ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN Example 1: VHDL code (1) 21 ECE 448 FPGA and ASIC Design with VHDL CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; WHEN C => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; END CASE ;
Example 1: VHDL code (2) 22 ECE 448 FPGA and ASIC Design with VHDL Example 1: VHDL code (3) END IF ; END PROCESS ;
z <= '1' WHEN y = C ELSE '0' ;
END Behavior ;
23 ECE 448 FPGA and ASIC Design with VHDL A w 0 = z 0 = w 1 = z 1 = B w 0 = z 0 = Reset w 1 = z 0 = Mealy FSM Example 2: State diagram 24 ECE 448 FPGA and ASIC Design with VHDL ASM Chart for Mealy FSM Example 2 w w 0 1 0 1 A B Reset z 25 ECE 448 FPGA and ASIC Design with VHDL LIBRARY ieee ; USE ieee.std_logic_1164.all ;
ENTITY Mealy IS PORT ( clock : IN STD_LOGIC ; resetn : IN STD_LOGIC ; w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END Mealy ;
ARCHITECTURE Behavior OF Mealy IS TYPE State_type IS (A, B) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (clock'EVENT AND clock = '1') THEN Example 2: VHDL code (1) 26 ECE 448 FPGA and ASIC Design with VHDL Example 2: VHDL code (2) CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; END CASE ; 27 ECE 448 FPGA and ASIC Design with VHDL Example 2: VHDL code (3) END IF ; END PROCESS ;
z <= '1' WHEN (y = B) AND (w=1) ELSE '0' ;
END Behavior ;
28 ECE 448 FPGA and ASIC Design with VHDL Control Unit Example: Arbiter (1) Arbiter reset r1 r2 r3 g1 g2 g3 clock 29 ECE 448 FPGA and ASIC Design with VHDL Idle 000 1xx Reset gnt1 g 1 1 = x1x gnt2 g 2 1 = xx1 gnt3 g 3 1 = 0xx 1xx 01x x0x 001 xx0 Control Unit Example: Arbiter (2) 30 ECE 448 FPGA and ASIC Design with VHDL Control Unit Example: Arbiter (3) r 1 r 2 r 1 r 2 r 3 Idle Reset gnt1 g 1 1 = gnt2 g 2 1 = gnt3 g 3 1 = r 1 r 1 r 1 r 2 r 3 r 2 r 3 r 1 r 2 r 3 r 1 r 2 r 1 r 2 r 3 Idle Reset gnt1 g 1 1 = gnt2 g 2 1 = gnt3 g 3 1 = r 1 r 1 r 1 r 2 r 3 r 2 r 3 r 1 r 2 r 3 31 ECE 448 FPGA and ASIC Design with VHDL ASM Chart for Control Unit - Example 3 r 1 r 3 0 1 1 Idle Reset r 2 r 1 r 3 r 2 gnt1 gnt2 gnt3 1 1 1 0 0 0 g 1 g 2 g 3 0 0 1 r 1 r 3 0 1 1 Idle Reset r 2 r 1 r 3 r 2 gnt1 gnt2 gnt3 1 1 1 0 0 0 g 1 g 2 g 3 0 0 1 32 ECE 448 FPGA and ASIC Design with VHDL Example 3: VHDL code (1) LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY arbiter IS PORT ( Clock, Resetn : IN STD_LOGIC ; r : IN STD_LOGIC_VECTOR(1 TO 3) ; g : OUT STD_LOGIC_VECTOR(1 TO 3) ) ; END arbiter ;
ARCHITECTURE Behavior OF arbiter IS TYPE State_type IS (Idle, gnt1, gnt2, gnt3) ; SIGNAL y : State_type ;
33 ECE 448 FPGA and ASIC Design with VHDL Example 3: VHDL code (2) BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= Idle ; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE y IS WHEN Idle => IF r(1) = '1' THEN y <= gnt1 ; ELSIF r(2) = '1' THEN y <= gnt2 ; ELSIF r(3) = '1' THEN y <= gnt3 ; ELSE y <= Idle ; END IF ; WHEN gnt1 => IF r(1) = '1' THEN y <= gnt1 ; ELSE y <= Idle ; END IF ; WHEN gnt2 => IF r(2) = '1' THEN y <= gnt2 ; ELSE y <= Idle ; END IF ; 34 ECE 448 FPGA and ASIC Design with VHDL Example 3: VHDL code (3) WHEN gnt3 => IF r(3) = '1' THEN y <= gnt3 ; ELSE y <= Idle ; END IF ; END CASE ; END IF ; END PROCESS ;
g(1) <= '1' WHEN y = gnt1 ELSE '0' ; g(2) <= '1' WHEN y = gnt2 ELSE '0' ; g(3) <= '1' WHEN y = gnt3 ELSE '0' ; END Behavior ;