Chapter 4

Digital Design Chapter 4 Sequential Basics 22 January 2009
1
Digital Design:
An Embedded Systems
Approach Using Verilog
Chapter 4
Sequential Basics
Portions of this work are from the book, Digital Design: An Embedded
Systems Approach Using Verilog, by Peter J. Ashenden, published by Morgan
Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved. Digital Design Chapter 4 Sequential Basics 2
Verilog
Sequential Basics
Sequential circuits
Outputs depend on current inputs and
previous inputs
Store state: an abstraction of the history of
inputs
Usually governed by a periodic clock
signal
Digital Design Chapter 4 Sequential Basics 3
Verilog
D-Flipflops
1-bit storage element
We will treat it as a basic component
Other kinds of flipflops
SR (set/reset), JK, T (toggle)
D Q
clk
D
clk
Q
Verilog
Registers
Store a multi-bit encoded value
One D-flipflop per bit
Stores a new value on
each clock cycle
wi r e [ n: 0] d;
r eg [ n: 0] q;
. . .
al ways @( posedge cl k)
q <= d;
event list
nonblocking
asignment
D Q
clk
D Q
clk
D Q
clk
d(0)

d(1)
d(n)
n n
q(0)
q(1)
q(n)
clk
D Q
clk
Verilog
Pipelines Using Registers
Total delay = Delay
1
+ Delay
2
+ Delay
3
Interval between outputs > Total delay
Clock period = max(Delay
1
, Delay
2
, Delay
3
)
Total delay = 3 clock period
Interval between outputs = 1 clock period
D Q
clk
combin-
ational
circuit 1
D Q
clk
combin-
ational
circuit 2
D Q
clk
combin-
ational
circuit 3
d_in
clk
d_out
combin-
ational
circuit 1
combin-
ational
circuit 2
combin-
ational
circuit 3
d_in d_out
Verilog
Pipeline Example
Compute the average of corresponding
numbers in three input streams
New values arrive on each clock edge
modul e aver age_pi pel i ne ( out put r eg si gned [ 5: - 8] avg,
i nput si gned [ 5: - 8] a, b, c,
i nput cl k ) ;
wi r e si gned [ 5: - 8] a_pl us_b, sum, sum_di v_3;
r eg si gned [ 5: - 8] saved_a_pl us_b, saved_c, saved_sum;
. . .
2
Verilog
Pipeline Example
. . .
assi gn a_pl us_b = a + b;
al ways @( posedge cl k) begi n / / Pi pel i ne r egi st er 1
saved_a_pl us_b <= a_pl us_b;
saved_c <= c;
end
assi gn sum= saved_a_pl us_b + saved_c;
al ways @( posedge cl k) / / Pi pel i ne r egi st er 2
saved_sum<= sum;
assi gn sum_di v_3 = saved_sum* 14' b00000001010101;
al ways @( posedge cl k) / / Pi pel i ne r egi st er 3
avg <= sum_di v_3;
endmodul e
Verilog
D-Flipflop with Enable
Storage controlled by a clock-enable
stores only when CE = 1 on a rising edge
of the clock
CE is a synchronous control input
D
CE
Q
clk D
CE
clk
Q
Verilog
Register with Enable
One flipflop per bit
clk and CE wired in common
wi r e [ n: 0] d;
wi r e ce;
r eg [ n: 0] q;
. . .
i f ( ce) q <= d;
Verilog
Register with Synchronous Reset
Reset input forces stored value to 0
reset input must be stable around rising
edge of clk
i f ( r eset ) q <= 0;
el se i f ( ce) q <= d;
D
CE
Q
clk
reset
D
CE
reset
clk
Q
1 2 3 4 5 6 7 8
Verilog
Register with Asynchronous Reset
Reset input forces stored value to 0
reset can become 1 at any time, and effect
is immediate
reset should return to 0 synchronously
D
CE
Q
clk
reset
D
CE
reset
clk
Q
1 2 3 4 5 6 7 8
Verilog
Asynch Reset in Verilog
al ways @( posedge cl k or posedge r eset )
i f ( r eset ) q <= 0;
el se i f ( ce) q <= d;
reset is an asynchronous control input here
include it in the event list so that the process
responds to changes immediately
3
Verilog
Example: Accumulator
Sum a sequence of signed numbers
A new number arrives when data_en = 1
Clear sum to 0 on synch reset
modul e accumul at or
( out put r eg si gned [ 7: - 12] dat a_out ,
i nput si gned [ 3: - 12] dat a_i n,
i nput dat a_en, cl k, r eset ) ;
wi r e si gned [ 7: - 12] new_sum;
assi gn new_sum= dat a_out + dat a_i n;
i f ( r eset ) dat a_out <= 20' b0;
el se i f ( dat a_en) dat a_out <= new_sum;
endmodul e
Verilog
Flipflop and Register Variations
modul e f l i p_f l op_n ( out put r eg Q,
out put Q_n,
i nput pr e_n, cl r _n, D,
i nput cl k_n, CE ) ;
al ways @( negedge cl k_n or
negedge pr e_n or negedge cl r _n ) begi n
i f ( ! pr e_n && ! cl r _n)
$di spl ay( "I l l egal i nput s: pr e_n and cl r _n bot h 0") ;
i f ( ! pr e_n) Q <= 1' b1;
el se i f ( ! cl r _n) Q <= 1' b0;
el se i f ( CE) Q <= D;
end
assi gn Q_n = ~Q;
endmodul e
D
CE
Q
Q clk
pre
clr
Verilog
Shift Registers
Performs shift operation on stored data
Arithmetic scaling
Serial transfer
of data
D
D_in
CE
load_en
Q
clk
D
CE
Q
clk
0
1
D
CE
Q
clk
0
1
D
CE
Q
clk
0
1
Q(n1)
Q(n2)
Q(0)
D(n1)
D(n2)
D(0)
clk
CE
load_en
D_in
Verilog
Example: Sequential Multiplier
1616 multiply over 16 clock cycles, using
one adder
Shift register for multiplier bits
Shift register for lsbs of accumulated product
17-bit reg
reset
CE
D Q
clk
D
16-bit reg
CE
Q
clk
D_in
15-bit
shift reg
CE
Q
clk
16-bit
shift reg
D_in
D
CE
load_en
Q
clk
x
16-bit
adder
c0
y
c16
s
15...0
16
15
0
31...16
P(14...0)
P(31...15)
y(15...0)
x(15...0)
y_load_en
y_ce
x_ce
P_reset
P_ce
clk
Verilog
Latches
Level-sensitive storage
Data transmitted while enable is '1'
transparent latch
Data stored while enable is '0'
D Q
LE
D
LE
Q
Verilog
Feedback Latches
Feedback in gate circuits produces
latching behavior
Example: reset/set (RS) latch
S
R
Q
Current RTL synthesis tools dont accept
Verilog models with unclocked feedback
+V
Q
Q
R
S
4
Verilog
Latches in Verilog
Latching behavior is usually an error!
al ways @*
i f ( ~sel ) begi n
z1 <= a1; z2 <= b1;
end
el se begi n
z1 <= a2; z3 <= b2;
end
Oops!
Should be
z2 <= ...
Values must be stored
for z2 while sel = 1
for z3 while sel = 0
Verilog
Counters
Stores an unsigned integer value
increments or decrements the value
Used to count occurrences of
events
repetitions of a processing step
Used as timers
count elapsed time intervals by
incrementing periodically
Verilog
Free-Running Counter
Increments every rising edge of clk
up to 2
n
1, then wraps back to 0
i.e., counts modulo 2
n
This counter is synchronous
all outputs governed by clock edge
D Q
clk
+1 Q
clk
Verilog
Example: Periodic Control Signal
Count modulo 16 clock cycles
Control output = 1 every 8
th
and 12
th
cycle
decode count values 0111 and 1011
+1
clk
ctrl
0
1
2
3
0
1
2
3
D Q
clk
D Q
clk
D Q
clk
D Q
clk
Verilog
Example: Periodic Control Signal
modul e decoded_count er ( out put ct r l ,
i nput cl k ) ;
r eg [ 3: 0] count _val ue;
count _val ue <= count _val ue + 1;
assi gn ct r l = count _val ue == 4' b0111 | |
count _val ue == 4' b1011;
endmodul e
Verilog
Count Enable and Reset
Use a register with control inputs
Increments when CE = 1 on rising clock
edge
Reset: synch or asynch
+1
Q
clk
CE
reset
clk
D
CE
Q
reset
5
Verilog
Terminal Count
Status signal indicating final count value
TC is 1 for one cycle in every 2
n
cycles
frequency = clock frequency / 2
n
Called a clock divider
counter
Q0
Q1
Qn clk
TC
Verilog
Divider Example
Alarm clock beep: 500Hz from 1MHz clock
count
tone2
tone
clk
10-bit
counter
Q
TC clk
D
CE
Q
clk
tone
tone2
count
clk
1 1 0 0 2 2 1 0 2 1 0
1023 1023 1023
Verilog
Divide by k
Decode k1 as terminal count and reset
counter register
Counter increments modulo k
Example: decade counter
Terminal count = 9
clk Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
clk
reset
counter
Verilog
Decade Counter in Verilog
modul e decade_count er ( out put r eg [ 3: 0] q,
i nput cl k ) ;
q <= q == 9 ? 0 : q + 1;
endmodul e
Verilog
Down Counter with Load
Load a starting value, then decrement
Terminal count = 0
Useful for interval timer
D Q
clk
1
=0?
Q
TC
clk
load
D
0
1
Verilog
Loadable Counter in Verilog
modul e i nt er val _t i mer _r t l ( out put t c,
i nput [ 9: 0] dat a,
i nput l oad, cl k ) ;
r eg [ 9: 0] count _val ue;
i f ( l oad) count _val ue <= dat a;
el se count _val ue <= count _val ue - 1;
assi gn t c = count _val ue == 0;
endmodul e
6
Verilog
Reloading Counter in Verilog
modul e i nt er val _t i mer _r epet i t i ve ( out put t c,
i nput [ 9: 0] dat a,
i nput l oad, cl k ) ;
r eg [ 9: 0] l oad_val ue, count _val ue;
i f ( l oad) begi n
l oad_val ue <= dat a;
count _val ue <= dat a;
end
el se i f ( count _val ue == 0)
count _val ue <= l oad_val ue;
el se
count _val ue <= count _val ue - 1;
assi gn t c = count _val ue == 0;
endmodul e
Verilog
Ripple Counter
Each bit toggles between 0 and 1
when previous bit changes from 1 to 0
D
Q
Q
clk
D
Q
Q
clk
D
Q
Q
clk
D
Q
Q
clk
Q0
Q1
Q2
Qn
clk
Q1
Q0
Q0
clk
Q1
Q2
Q2
Verilog
Ripple or Synch Counter?
Ripple counter is ok if
length is short
clock period long relative to flipflop delay
transient wrong values can be tolerated
area must be minimal
E.g., alarm clock
Otherwise use a synchronous counter
Verilog
Datapaths and Control
Digital systems perform sequences of
operations on encoded data
Datapath
Combinational circuits for operations
Registers for storing intermediate results
Control section: control sequencing
Generates control signals
Selecting operations to perform
Enabling registers at the right times
Uses status signals from datapath
Verilog
Example: Complex Multiplier
Cartesian form, fixed-point
operands: 4 pre-, 12 post-binary-point bits
result: 8 pre-, 24 post-binary-point bits
Subject to tight area constraints
i r
ja a a + =
i r
jb b b + =
) ( ) (
r i i r i i r r i r
b a b a j b a b a jp p ab p + + = + = =
4 multiplies, 1 add, 1 subtract
Perform sequentially using 1 multiplier, 1
adder/subtracter
Verilog
Complex Multiplier Datapath
0
1
0
1
D
CE
Q
clk
D
CE
Q
clk

D
CE
Q
clk
D
CE
Q
clk
p_r
p_i
a_r
a_i
b_r
b_i
a_sel
b_sel
pp1_ce
pp2_ce
sub
p_r_ce
p_i_ce
clk
7
Verilog
Complex Multiplier in Verilog
modul e mul t i pl i er
( out put r eg si gned [ 7: - 24] p_r , p_i ,
i nput si gned [ 3: - 12] a_r , a_i , b_r , b_i ,
i nput cl k, r eset , i nput _r dy ) ;
r eg a_sel , b_sel , pp1_ce, pp2_ce, sub, p_r _ce, p_i _ce;
wi r e si gned [ 3: - 12] a_oper and, b_oper and;
wi r e si gned [ 7: - 24] pp, sum
r eg si gned [ 7: - 24] pp1, pp2;
. . .
Verilog
Complex Multiplier in Verilog
assi gn a_oper and = ~a_sel ? a_r : a_i ;
assi gn b_oper and = ~b_sel ? b_r : b_i ;
assi gn pp = {{4{a_oper and[ 3] }}, a_oper and, 12' b0} *
{{4{b_oper and[ 3] }}, b_oper and, 12' b0};
al ways @( posedge cl k) / / Par t i al pr oduct 1 r egi st er
i f ( pp1_ce) pp1 <= pp;
al ways @( posedge cl k) / / Par t i al pr oduct 2 r egi st er
i f ( pp2_ce) pp2 <= pp;
assi gn sum= ~sub ? pp1 + pp2 : pp1 - pp2;
al ways @( posedge cl k) / / Pr oduct r eal - par t r egi st er
i f ( p_r _ce) p_r <= sum;
al ways @( posedge cl k) / / Pr oduct i magi nar y- par t r egi st er
i f ( p_i _ce) p_i <= sum;
. . .
endmodul e
Verilog
Multiplier Control Sequence
Avoid resource conflict
First attempt
1. a_r * b_r pp1_reg
2. a_i * b_i pp2_reg
3. pp1 pp2 p_r_reg
4. a_r * b_i pp1_reg
5. a_i * b_r pp2_reg
6. pp1 + pp2 p_i_reg
Takes 6 clock cycles
Verilog
Multiplier Control Sequence
Merge steps where no resource conflict
Revised attempt
1. a_r * b_r pp1_reg
2. a_i * b_i pp2_reg
3. pp1 pp2 p_r_reg
a_r * b_i pp1_reg
4. a_i * b_r pp2_reg
5. pp1 + pp2 p_i_reg
Takes 5 clock cycles
Verilog
Multiplier Control Signals
1 0 0 0 0 5
0 0 1 0 0 1 4
0 1 1 0 1 1 0 3
0 0 1 0 1 1 2
0 0 0 1 0 0 1
p_i_ce p_r_ce sub pp2_ce pp1_ce b_sel a_sel Step
Verilog
Finite-State Machines
Used the implement control sequencing
Based on mathematical automaton theory
A FSM is defined by
set of inputs:
set of outputs:
set of states: S
initial state: s
0
S
transition function: : S S
output function: : S or : S
8
Verilog
FSM in Hardware
Mealy FSM: : S
Moore FSM: : S
Mealy FSM
only
D
reset
Q
clk
current_state
outputs
inputs
clk
reset
next
state
logic
output
logic
Verilog
FSM Example: Multiplier Control
One state per step
Separate idle state?
Wait for input_rdy = 1
Then proceed to steps 1, 2, ...
But this wastes a cycle!
Use step 1 as idle state
Repeat step 1 if input_rdy 1
Proceed to step 2 otherwise
Output function
Defined by table on slide 43
Moore or Mealy?
step5 step4
step1 step5
step4 step3
step3 step2
step2 1 step1
step1 0 step1
next_
state
input_
rdy
current_
state
Transition function
Verilog
State Encoding
Encoded in binary
N states: use at least log
2
N bits
Encoded value used in circuits for transition
and output function
encoding affects circuit complexity
Optimal encoding is hard to find
CAD tools can do this well
One-hot works well in FPGAs
Often use 000...0 for idle state
reset state register to idle
Verilog
FSMs in Verilog
Use parameters for state values
Synthesis tool can choose an alternative
encoding
par amet er [ 2: 0] st ep1 = 3' b000, st ep2 = 3' b001,
st ep3 = 3' b010, st ep4 = 3' b011,
st ep5 = 3' b100;
r eg [ 2: 0] cur r ent _st at e, next _st at e ;
. . .
Verilog
Multiplier Control in Verilog
al ways @( posedge cl k or posedge r eset ) / / St at e r egi st er
i f ( r eset ) cur r ent _st at e <= st ep1;
el se cur r ent _st at e <= next _st at e;
al ways @* / / Next - st at e l ogi c
case ( cur r ent _st at e)
st ep1: i f ( ! i nput _r dy) next _st at e = st ep1;
el se next _st at e = st ep2;
st ep2: next _st at e = st ep3;
endcase
Verilog
Multiplier Control in Verilog
al ways @* begi n / / Out put _l ogi c
a_sel = 1' b0; b_sel = 1' b0; pp1_ce = 1' b0; pp2_ce = 1' b0;
sub = 1' b0; p_r _ce = 1' b0; p_i _ce = 1' b0;
case ( cur r ent _st at e)
st ep1: begi n
pp1_ce = 1' b1;
end
st ep2: begi n
a_sel = 1' b1; b_sel = 1' b1; pp2_ce = 1' b1;
end
st ep3: begi n
b_sel = 1' b1; pp1_ce = 1' b1;
sub = 1' b1; p_r _ce = 1' b1;
end
st ep4: begi n
a_sel = 1' b1; pp2_ce = 1' b1;
end
st ep5: begi n
p_i _ce = 1' b1;
end
endcase
end
9
Verilog
State Transition Diagrams
Bubbles to represent states
Arcs to represent transitions
Example
S = {s1, s2, s3}
Inputs (a1, a2):
= {(0,0), (0,1), (1,0), (1,1)}
defined by diagram
s1 s2
s3
0, 0
0, 0
0, 1
1, 0
0, 1
1, 0
1, 1
1, 1
Verilog
State Transition Diagrams
Annotate diagram to
define output
function
Annotate states for
Moore-style outputs
Annotate arcs for
Mealy-style outputs
Example
x
1
, x
2
: Moore-style
y
1
, y
2
, y
3
: Mealy-style
s1 s2
s3
0, 0 / 0, 0, 0
1, 0 0, 0
0, 1
0, 0 / 0, 0, 0
0, 1 / 0, 1, 1
/ 0, 1, 1
1, 0 / 1, 0, 0
0, 1 / 0, 1, 1
1, 0 / 1, 0, 0
1, 1 / 1, 1, 1
1, 1 / 1, 1, 1
Verilog
Multiplier Control Diagram
Input: input_rdy
Outputs
a_sel, b_sel, pp1_ce, pp2_ce, sub, p_r_ce, p_i_ce
step1
0, 0, 1, 0, , 0, 0
0
1 step2
1, 1, 0, 1, , 0, 0
step4
1, 0, 0, 1, , 0, 0
step5
, , 0, 0, 0, 0, 1
step3
0, 1, 1, 0, 1, 1, 0
Verilog
Bubble Diagrams or Verilog?
Many CAD tools provide editors for
bubble diagrams
Automatically generate Verilog for
simulation and synthesis
Diagrams are visually appealing
but can become unwieldy for complex
FSMs
Your choice...
or your manager's!
Verilog
Register Transfer Level
RTL a level of abstraction
data stored in registers
transferred via circuits that operate on
data
control section
outputs
inputs
Verilog
Clocked Synchronous Timing
Registers driven by a common clock
Combinational circuits operate during clock
cycles (between rising clock edges)
t
co
+ t
pd
+ t
su
< t
c
Q1 D2
t
pd t
co
t
su
Q1
clk
D2
t
co
t
c
t
pd
t
su
t
slack
10
Verilog
Control Path Timing
t
co
+ t
pd-s
+ t
pd-o
+ t
pd-c
+ t
su
< t
c
t
co
+ t
pd-s
+ t
pd-ns
+ t
su
< t
c
Ignore t
pd-s
for a Moore FSM
t
pd-s
t
pd-c
t
pd-o
t
pd-ns
t
co
t
su
t
su
Verilog
Timing Constraints
Inequalities must hold for all paths
If t
co
and t
su
the same for all paths
Combinational delays make the difference
Critical path
The combinational path between registers with
the longest delay
Determines minimum clock period for the entire
system
Focus on it to improve performance
Reducing delay may make another path critical
Verilog
Interpretation of Constraints
1. Clock period depends on delays
System can operate at any frequency up
to a maximum
OK for systems where high performance
is not the main requirement
2. Delays must fit within a target clock
period
Optimize critical paths to reduce delays if
necessary
May require revising RTL organization
Verilog
Clock Skew
Need to ensure clock edges arrive at all
registers at the same time
Use CAD tools to insert clock buffers and
route clock signal paths
Q1 D2
Q1
clk1
clk2
D2
t
h
Verilog
Off-Chip Connections
Delays going off-chip and inter-chip
Input and output pad delays, wire delays
Same timing rules apply
Use input and output registers to avoid
adding external delay to critical path
Q1 D2
Verilog
Asynchronous Inputs
External inputs can change at any time
Might violate setup/hold time constraints
Can induce metastable state in a flipflop
Unbounded time to recover
May violate setup/hold time
of subsequent flipflop
2 1
2
f f k
e
MTBF
f
t k
=
0
2
>> k
0 1 0 1
11
Verilog
Synchronizers
If input changes outside setup/hold window
Change is simply delayed by one cycle
If input changes during setup/hold window
First flipflop has a whole cycle to resolve
metastability
See data sheets for metastability parameters
D Q
clk
D Q
clk
clk
asynch_in
synch_in
Verilog
Switch Inputs and Debouncing
Switches and push-buttons suffer from
contact bounce
Takes up to 10ms to settle
Need to debounce to avoid false triggering
Requires two inputs
and two resistors
Must use a break-
before-make double-
throw switch
Q
R
S
+V
Verilog
Switch Inputs and Debouncing
Alternative
Use a single-throw switch
Sample input at intervals longer than bounce time
Look for two successive samples with the same
value
Assumption
Extra circuitry inside the chip
is cheaper than extra
components and connections
outside
+V
Verilog
Debouncing in Verilog
modul e debouncer ( out put r eg pb_debounced,
i nput pb,
i nput cl k, r eset ) ;
r eg [ 18: 0] count 500000; / / val ues ar e i n t he r ange 0 t o 499999
wi r e cl k_100Hz;
r eg pb_sampl ed;
al ways @( posedge cl k or posedge r eset )
i f ( r eset ) count 500000 <= 499999;
el se i f ( cl k_100Hz) count 500000 <= 499999;
el se count 500000 <= count 500000 - 1;
assi gn cl k_100Hz = count 500000 == 0;
i f ( cl k_100Hz) begi n
i f ( pb == pb_sampl ed) pb_debounced <= pb;
pb_sampl ed <= pb;
end
endmodul e
Verilog
Verifying Sequential Circuits
DUV may take multiple and varying number
of cycles to produce output
Checker needs to
synchronize with test generator
ensure DUV outputs occur when expected
ensure DUV outputs are correct
ensure no spurious outputs occur
Design Under
Verification
(DUV)
Apply
Test Cases
Checker
Verification Testbench
Verilog
Example: Multiplier Testbench
`t i mescal e 1ns/ 1ns
modul e mul t i pl i er _t est bench;
par amet er t _c = 50;
r eg cl k, r eset ;
r eg i nput _r dy;
wi r e si gned [ 3: - 12] a_r , a_i , b_r , b_i ;
wi r e si gned [ 7: - 24] p_r , p_i ;
r eal r eal _a_r , r eal _a_i , r eal _b_r , r eal _b_i ,
r eal _p_r , r eal _p_i , er r _p_r , er r _p_i ;
t ask appl y_t est ( i nput r eal a_r _t est , a_i _t est ,
b_r _t est , b_i _t est ) ;
begi n
r eal _a_r = a_r _t est ; r eal _a_i = a_i _t est ;
r eal _b_r = b_r _t est ; r eal _b_i = b_i _t est ;
i nput _r dy = 1' b1;
@( negedge cl k) i nput _r dy = 1' b0;
r epeat ( 5) @( negedge cl k) ;
end
endt ask
12
Verilog
mul t i pl i er duv ( . cl k( cl k) , . r eset ( r eset ) ,
. i nput _r dy( i nput _r dy) ,
. a_r ( a_r ) , . a_i ( a_i ) ,
. b_r ( b_r ) , . b_i ( b_i ) ,
. p_r ( p_r ) , . p_i ( p_i ) ) ;
al ways begi n / / Cl ock gener at or
#( t _c/ 2) cl k = 1' b1;
#( t _c/ 2) cl k = 1' b0;
end
i ni t i al begi n / / Reset gener at or
r eset <= 1' b1;
#( 2*t _c) r eset = 1' b0;
end
Verilog
i ni t i al begi n / / Appl y t est cases
@( negedge r eset )
@( negedge cl k)
appl y_t est ( 0. 0, 0. 0, 1. 0, 2. 0) ;
appl y_t est ( 1. 0, 1. 0, 1. 0, 1. 0) ;
/ / f ur t her t est cases . . .
$f i ni sh;
end
assi gn a_r = $r t oi ( r eal _a_r * 2**12) ;
assi gn a_i = $r t oi ( r eal _a_i * 2**12) ;
assi gn b_r = $r t oi ( r eal _b_r * 2**12) ;
assi gn b_i = $r t oi ( r eal _b_i * 2**12) ;
Verilog
al ways @( posedge cl k) / / Check out put s
i f ( i nput _r dy) begi n
r eal _p_r = r eal _a_r * r eal _b_r - r eal _a_i * r eal _b_i ;
r eal _p_i = r eal _a_r * r eal _b_i + r eal _a_i * r eal _b_r ;
r epeat ( 5) @( negedge cl k) ;
er r _p_r = $i t or ( p_r ) / 2**( - 24) - r eal _p_r ;
er r _p_i = $i t or ( p_i ) / 2**( - 24) - r eal _p_i ;
i f ( ! ( - ( 2. 0**( - 12) ) < er r _p_r && er r _p_r < 2. 0**( - 12) &&
- ( 2. 0**( - 12) ) < er r _p_i && er r _p_i < 2. 0**( - 12) ) )
$di spl ay( "Resul t pr eci si on r equi r ement not met ") ;
end
endmodul e
Verilog
Asynchronous Timing
Clocked synchronous timing requires
global clock distribution with minimal skew
path delay between registers < clock period
Hard to achieve in complex multi-GHz systems
Globally asynch, local synch (GALS) systems
Divide the systems into local clock domains
Inter-domain signals treated as asynch inputs
Simplifies clock managements and constraints
Delays inter-domain communication
Delay-insensitive asynchronous systems
no clock signals
Verilog
Other Clock-Related Issues
Inter-chip clocking
Distributing high-speed clocks on PCBs is hard
Often use slower off-chip clock, with on-chip clock
a multiple of off-chip clock
Synchronize on-chip with phase-locked loop (PLL)
In multi-PCB systems
treat off-PCB signals as asynch inputs
Low power design
Continuous clocking wastes power
Clock gating: turn off clock to idle subsystems
Verilog
Summary
Registers for storing data
synchronous and asynchronous control
clock enable, reset, preset
Latches: level-sensitive
usually unintentional in Verilog
Counters
free-running dividers, terminal count,
reset, load, up/down
13
Verilog
Summary
RTL organization of digital systems
datapath and control section
Finite-State Machine (FSM)
states, inputs, transition/output functions
Moore and Mealy FSMs
bubble diagrams
Clocked synch timing and constraints
critical path and optimization
Asynch inputs, switch debouncing
Verification of sequential systems

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Digital Design Chapter 4 Sequential Basics 22 January 2009

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