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1. Schottky TTL
Non-saturated
2. Emitter Coupled Logic (ECL)
family
(transistors are operated between cut-off and active states)
Advantages:
- RTL gates are almost as simple as DL gates, and remain inexpensive.
- Using low power supply for each gate.
- RTL integrated circuits are sometimes used as inexpensive small-
signal amplifiers, or as interface devices between linear and digital circuits.
Limitations:
- RTL gates cannot switch at the high speeds used by today's computers
- These are not designed for linear operation
- low noise margin
RTL gate with both inputs low. The transistors are replaced by the cutoff model.
the diode AND function on the front end and the transistor NOT at
the output end. The extra resistors and diodes are
used to maintain appropriate currents, to maintain proper
functioning, and to guarantee
certain noise margins.
Quantitatively, we will start with one or more inputs held low, at 0.2 Volts. From
the logic function of the NAND gate, we know that the output is supposed to be
high. Therefore, the transistor must be cutoff. To begin with, we will assume the
two diodes D1 and D2 in series will also be cutoff. All the current coming down
through the 5K resistor must all go out through the input diode, causing it to be
on. The circuit with the models indicated is shown in Figure.
From this circuit we can calculate all
voltages and currents and prove (or
disprove) our assumptions about the
condition of each element.
This current leaves through the input diode, hence it is on. The current entering
the input terminal is
Iin = - I1 = -0.82 mA
The negative sign occurs because the input current is defined as going into the terminal.
We can now verify that the output voltage is 5 Volts because the transistor has
been shown to be cutoff. Thus,
VO = 5.0 Volts
Department of Electronics and Computer
Engineering
Pulchowk Campus, Institute of Engineering,
Diode Transistor Logic (DTL): …
One other characteristic of the DTL gate that can be obtained at this point
is the range of input voltages that will be recognized as a "low". From the
logic function of the NAND gate, this can be translated into the question
of how high the input voltage may rise and still keep the transistor cutoff.
The transistor will remain cutoff as long as the voltage at the base does
not rise above 0.5 volts. At this voltage, there will be current down
through the lower 5K resistor to ground. This current must come from the
+5 supply down through the upper 5K resistor and the diodes, D1 and D2.
Hence the diodes must be conducting. This current will be 0.1 mA. The
voltage at point P will be
VP = 0.5 + 0.7 + 0.7 = 1.9 Volts
The current I1 is
I1 = (5-1.9)/5K = 0.62 mA
The current going out through the input diode will be
Iin = -(0.62 - 0.1) = -0.52 mA
Department of Electronics and Computer
Engineering
Pulchowk Campus, Institute of Engineering,
Diode Transistor Logic (DTL): …
indicating that the input diode is still conducting. Figure next slide
shows the resulting circuit with the circuit models included. The
maximum voltage at the input that is guaranteed to be recognized as
a low is
VinLmax = 1.9 -0.7 =1.2 Volts.
at saturation, the current coming down through the 2.2K collector resistor is
I3 = (5-0.2)/2.2K = 2.182 mA
this current is much less than the maximum saturation current and
we see that with no load, the transistor will, indeed, be in saturation.
Fanout = 11
The analysis of this circuit follows very much the same path as the
analysis of the DTL gate. For the most part, we will consider the
input transistor, Q1, to act just like two diodes. The transistor Q2,
however, will operate in all three regions. The treatment of the
output voltages and currents will be treated the same as the DTL
gate and Q3 will either be cutoff or saturated, corresponding to an
output high and an output low, respectively.
Department of Electronics and Computer
Engineering
Pulchowk Campus, Institute of Engineering,
ANALYSIS WITH ONE OR MORE INPUTS LOW
Figure 3
Figure 4
Department of Electronics and Computer
Engineering
Pulchowk Campus, Institute of Engineering,
ANALYSIS WITH ONE OR MORE INPUTS LOW …
We turn now to finding VInLmax . We will use the criterion that Vin will
be considered as a low as long as Q3 is kept cutoff. If the base voltage
for Q3 can be raised to 0.5 Volts without turning it on, then there will
be 0.5 mA current in the 1KΩ resistor. This current can only come
from Q2, which means it must be conducting. Even assuming all this
0.5 mA comes through the collector of Q2, the voltage drop across
the 1.4 KΩ resistor will be 0.7 Volts, not enough to cause the
transistor to saturate. Thus, the active model for Q2 is appropriate as
shown in Figure 4.
If we assume that β=30, the base current in Q2 is
I1 = (5.0-2.3) / 4K
= 0.675mA
Figure 5
TTL gate circuit model with all inputs high
Department of Electronics and Computer
Engineering
Pulchowk Campus, Institute of Engineering,
CALCULATIONS WITH INPUT HIGH …
The current coming out of the emitter of Q2 is the sum of the base
and collector currents. Part of this current will go down through the 1
KΩ resistor to ground and the rest will enter the base of Q3.
IB3 = IB2 + IC2 - I3 = 0.675 + 2.857 - 0.8 = 2.732 mA
Department of Electronics and Computer
Engineering
Pulchowk Campus, Institute of Engineering,
CALCULATIONS WITH INPUT HIGH …
The maximum collector current that Q3 can carry and still be in
saturation is βIB3 = 81.96 mA, assuming β=30. The maximum
current the gate can sink when the output is low
IoLmax = ICsatmax - I4 = 81.96 - 1.2 = 80.76 mA
Now let's turn our attention back to the input and determine VinHmin
and IinH . We will define the input voltage to be high as long as no
current goes out the input terminal.
Thus, all we have to do is keep the input voltage high enough so that
the B-E p-n junction of Q1 does not turn on. Thus,
VinHmin = 2.3 - 0.6 = 1.7 Volts
Department of Electronics and Computer
Engineering
Pulchowk Campus, Institute of Engineering,
TTL FAMILIES
ECL family include the fact that the large current requirement is
approximately constant, and does not depend significantly on the state
of the circuit. This means that ECL circuits generate relatively little
power noise, unlike many other logic types which typically draw far
more current when switching than quiescent, for which power noise
can become problematic. In an ALU - where a lot of switching occurs
- ECL can draw lower mean current than CMOS.
Emitter Coupled Logic (ECL) … …
The ECL circuits available on the open market usually operated with
negative power supplies (-5.2 volts), and logic levels incompatible with
other families (required additional interface circuits). The fact that the
high and low logic levels are relatively close meant that ECL suffers from
small noise margins, which can be troublesome.
The drawbacks associated with ECL have meant that it has been used
mainly when high performance is a vital requirement.
The logic voltage levels are very close (High: 0.7V, Low: 0.2V), I2L has
high noise immunity because it operates by current instead of voltage.
- The circuit uses BJTs, both pnp and npn. Therefore operating speed
is quite high.
- The circuit is similar to RTL, except that there are no base resistors
used. This minimizes the circuit area and simplifies the circuit lay-
out.
- All the gate transistors are operated in the inverted mode. Not only
does this facilitate the use of low voltage supply for the circuit.
- The circuit requires no isolation unlike the previous digital ICs.
This facilitates higher packing density and also reduces the
fabrication cost, as fewer masks (e.g. only four) are required for the
complete process.
- Parasitics in the circuit are greatly reduced. This also improves the
operating speed of the IC.