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-- PROJECT: D0 Run IIb Trigger L1 Calorimeter upgrade

--- MODULE: RS232 to generic bus converter test bench


--- ELEMENT: bus2rs232_test
--- DESCRIPTION: ACIA + RS232 to generic bus converter + RAM
--- AUTHOR: J.Marquet marquet@efrei.fr
--- DATE AND HISTORY:
-- July 2004: created
-- September 2004: revised by D. Calvet
--------------------------------------------------------------------------------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.utility_pkg.all;
use work.constant_package.all;
-------------------------------------------------------------------------------entity bus2rs232_test is
constant
constant
constant
constant
constant
constant

H_CLK_PERIOD
H_RAM_CLK_PERIOD
ADDR_SIZE
DATA_SIZE
B_RATE
RAM_SIZE

:
:
:
:
:
:

TIME :=
TIME :=
integer
integer
integer
integer

500000000 ns / FREQ_REF;
125 ns;
:= 12;
:= 8;
:= 307200;
:= 16;

end bus2rs232_test;
architecture behavior of bus2rs232_test is
--- Generic RS232 controller
-component acia
generic (
TX_FIFO_SIZE : NATURAL := 4;
RX_FIFO_SIZE : NATURAL := 4
);
port (
------------------------------------------------------------------------ Miscellaneous signals
-RESET
: in std_logic; -- RESET
--------------------------------------------------------------------------------------------------------------------------------------------

-- Local bus signals


-SPEED
: in NATURAL;
-- port speed
TX_DATA
: in std_logic_vector(7 downto 0); -- TX port
TX_STROBE : in std_logic;
-- TX strobe
TX_READY : out std_logic;
-- TX ready
RX_DATA
: out std_logic_vector(7 downto 0); -- RX port
RX_STROBE : in std_logic;
-- RX strobe
RX_READY : out std_logic;
-- RX ready
--------------------------------------------------------------------------------------------------------------------------------------------- RS232 signals
-TX_OUT
: out std_logic; -- TX serial output
RX_IN
: in std_logic -- RX serial input
---------------------------------------------------------------------);
end component;
--- RS 232 to generic bus converter
-component bus2rs232
generic (
ADDR_BUS_SIZE : integer := 12;
DATA_BUS_SIZE : integer := 8;
BAUD_RATE
: integer := 307200
);
port (
--- General control signals
-RESET
: in std_logic;
CLK
: in std_logic;

-- Asynch. Reset
-- Reference Clock

--- RS232 signals


-RX_IN
: in std_logic;
TX_OUT : out std_logic;
--- External bus signals
-ADDR
: out std_logic_vector(ADDR_BUS_SIZE-1 downto 0); -- ad
dress bus
DBE_B

: out std_logic_vector(3 downto 0);

-- by

: out std_logic;

-- ac

: out std_logic;

-- ac

te selection
WE
tive high write enable
CS_B
tive low chip select
DATA_OUT
ta bus output (write)
DATA_IN

: out std_logic_vector(DATA_BUS_SIZE-1 downto 0); -- da


: in std_logic_vector(DATA_BUS_SIZE-1 downto 0); -- da

ta bus input (read)


DTACK_B : in std_logic
tive low transfer acknowledge
);
end component;
--- RAM
-component RAM
generic (
ADDR_BUS_SIZE : integer := 12;
DATA_BUS_SIZE : integer := 8;
RAM_SIZE
: integer := 4096
);
port (
RESET
: in std_logic;
ynch. RESET
CLK
: in std_logic;
ock
ADDR
: in std_logic_vector(ADDR_BUS_SIZE-1 downto 0);
dress bus
DBE_B
: in std_logic_vector(3 downto 0);
te selection
WE
: in std_logic;
tive high write enable
CS_B
: in std_logic;
tive low chip select
DATA_OUT : out std_logic_vector(DATA_BUS_SIZE-1 downto 0);
ta bus output (read)
DATA_IN : in std_logic_vector(DATA_BUS_SIZE-1 downto 0);
ta bus input (write)
DTACK_B : out std_logic
tive low transfer acknowledge
);
end component;

-- ac

-- As
-- Cl
-- ad
-- by
-- ac
-- ac
-- da
-- da
-- ac

------------------------------------------------------------------------- Miscellaneous signals


-signal RESET
: std_logic := '0'; -- Register RESET
----------------------------------------------------------------------------------------------------------------------------------------------- ACIA Host bus signals
-signal HOST_RS232_SPEED
: NATURAL:= 307200;
-- Host R
S232 port speed
signal HOST_RS232_TX_DATA
: std_logic_vector(7 downto 0); -- Host TX
port
signal HOST_RS232_TX_STROBE : std_logic;
-- Host TX
strobe
signal HOST_RS232_TX_READY : std_logic := '1';
-- Host TX
ready
signal HOST_RS232_RX_DATA
: std_logic_vector(7 downto 0):= "00001010"
; -- Host RX port
signal HOST_RS232_RX_STROBE : std_logic;
-- Host RX
strobe

signal HOST_RS232_RX_READY

: std_logic := '1';

-- Host RX

ready
----------------------------------------------------------------------------------------------------------------------------------------------- RS232 Host signals
-signal HOST_RS232_TX_OUT
: std_logic;
signal HOST_RS232_RX_IN
: std_logic;
----------------------------------------------------------------------------------------------------------------------------------------------- Bus signals
-signal CLK
: std_logic := '0';
signal ADDR
: std_logic_vector(ADDR_SIZE-1 downto 0);
signal DBE_B
: std_logic_vector(3 downto 0);
signal CS_B
: std_logic;
signal WE
: std_logic;
signal DATA_OUT : std_logic_vector(DATA_SIZE-1 downto 0);
signal DATA_IN : std_logic_vector(DATA_SIZE-1 downto 0);
signal DTACK_B : std_logic;
signal CLK_RAM : std_logic := '0';
begin
--- Clocks and permanent signals
-RESET <= '0' after 0 ns, '1' after 100 ns, '0' after 200 ns;
CLK
<= not CLK after H_CLK_PERIOD;
CLK_RAM <= not CLK_RAM after H_RAM_CLK_PERIOD;
Memoire: RAM
generic map (
ADDR_SIZE,
DATA_SIZE,
RAM_SIZE
)
port map (
RESET
=>
CLK
=>
ADDR
=>
DBE_B
=>
CS_B
=>
WE
=>
DATA_OUT =>
DATA_IN =>
DTACK_B =>
);

RESET,
CLK_RAM,
ADDR,
DBE_B,
CS_B,
WE,
DATA_IN, -- output of RAM is input to bus
DATA_OUT, -- output of bus is input to RAM
DTACK_B

--- RS 232 to generic bus converter


-RS232_to_Bus: bus2rs232
generic map (
ADDR_SIZE,
DATA_SIZE,

B_RATE
)
port map (
--- General control signals
-RESET
=> RESET,
CLK
=> CLK,
--- RS232 signals
-RX_IN
=> HOST_RS232_TX_OUT,
TX_OUT => HOST_RS232_RX_IN,
--- External
-ADDR
=>
DBE_B
=>
WE
=>
CS_B
=>
DATA_OUT =>
DATA_IN =>
DTACK_B =>

bus signals
ADDR,
DBE_B,
WE,
CS_B,
DATA_OUT,
DATA_IN,
DTACK_B

);
PC_ACIA: acia
generic map(
4,
24
)
port map (
------------------------------------------------------------------------ Miscellaneous signals
-RESET
=> RESET,
--------------------------------------------------------------------------------------------------------------------------------------------- Local bus signals
-SPEED
=> HOST_RS232_SPEED,
TX_DATA
=> HOST_RS232_TX_DATA,
TX_STROBE => HOST_RS232_TX_STROBE,
TX_READY => HOST_RS232_TX_READY,
RX_DATA
=> HOST_RS232_RX_DATA,
RX_STROBE => HOST_RS232_RX_STROBE,
RX_READY => HOST_RS232_RX_READY,
--------------------------------------------------------------------------------------------------------------------------------------------

-- RS232 signals
-TX_OUT
=> HOST_RS232_TX_OUT,
RX_IN
=> HOST_RS232_RX_IN
---------------------------------------------------------------------);
end behavior;