Microprocessor/microcontroller Program

INDEX
1. BLOCK TRANSFER AND BLOCK EXCHANGE OF DATA
BYTES
2. ARRANGING ELEMENTS OF A BLOCK OF DATA IN
ASCENDING AND DESCENDING ORDER.
3. MULTIPLICATION OF TWO 8-BIT NUMBERS USING THE
METHOD OF SUCCESSIVE ADDITION AND SHIFT AND
ADD.
4. CONVERTING TWO DIGIT NUMBER TO THEIR
EQUIVALENTS
5. GENERATION OF FIBONACCI SERIES
6. INTERFACING DAC 0808
7. INTERFACING OF THUMBWHEEL SWITCH.
8. ARRANGING BLOCK IN DESCENDING AND ASCENDING
9. 8051 TIMER BASED EXPERIMENT.
10. INTERFACING OF DOT MATRIX DISPLAY USING 8051

EXPERIMENT NO – 1
BLOCK TRANSFER
AND BLOCK
EXCHANGE OF DATA
BYTES
BLOCK TRANSFER AND BLOCK EXCHANGE OF
DATA BYTES
Program Statement:
Write a program to transfer block of bytes from location
2040 to 2050. Then exchange block of data at 2040 and 2050. Block length is
stored at 203F.
Apparatus:
8085 based single chip Microprocessor kit (VINYTICS
VMC-8501), Scratch Pad RAM used from 2000h to 2770h.
Learning Objective:
1. How transfer byte from one location to other?
2. Use of indirect addressing mode.
3. Exchange of data between two memory locations.
Logic:
BLOCK TRANSFER:
Block length is copied from location 203F and is used as
counter. Data from memory location 2040 is copied to accumulator and from
accumulator to 2050.After data is copied pointers for source and destination
block is incremented by one and counter is decremented. Procedure is
repeated till counter is not zero.
BLOCK EXCHANGE:
Content of memory location pointed by HL pair is copied
to register B and from location pointed by DE pair to accumulator. Then data
from accumulator is copied to location pointed by HL pair and from Reg. B to
location pointed by DE pair and thus exchange is carried out. HL and DE pair
is incremented counter is decremented . Exchange is carried out till counter is
not zero.
ALGORITHM:
BLOCK TRANSFER:
1. Start
2. Copy length of block
3. Initialize memory pointer of source block
4. Initialize memory pointer of destination block
5. Copy content of memory location from source block to accumulator
6. Copy content of memory location from accumulator to destination
block
7. Increment both pointers
8. Decrement counter
9. If counter is not zero go to step 5
10. Stop
Stop
Copy length of block
Initialize source block

pointer
Initialize destination
block pointer
Copy content from

source memory location
Copy content to
destination memory
location
Increment both pointers

Decrement counter
No Is Yes
counter
=0?
Stop
BLOCK EXCHANGE
Stop
Initialize source block

pointer
Initialize destination
block pointer
Exchange content of
source and destination
memory location
Increment both pointers

Decrement counter
No Is Yes
counter
=0?
Stop
BLOCK TRANSFER OF DATA BYTES
Memory OP
Label Mnemonic Comment
Address CODE
2000 21 LXI H, 203F Point where length
2001 3F Is stored
2002 20
2003 4E MOV C, M Copy length
2004 23 INX H
2005 11 LXI D,2050 Initialize destination
2006 50 pointer
2007 20
2008 7E BACK: MOV A,M
2009 12 STAX D
200A 23 INX H Increment source pointer
Increment destination
200B 13 INX D pointer
200C 0D DCR C
200D C2 JNZ BACK
Check counter is zero or
200E 08
not?
200F 20
2010 EF RST 5
BLOCK EXCHANGE OF DATA BYTES
Memory OP
Address CODE
2001 3F Is stored
2002 20
2003 4E MOV C,M Copy count value
2004 23 INX H
2005 11 LXI D,2050 Initialize pointer
2006 50
2007 20
2008 46 BACK: MOV B,M
2009 1A LDAX D
200A 77 MOV M,A
200B 78 MOV A,B
200C 12 STAX D
200D 23 INX H Increment pointer
200E 13 INX D
200F 0D DCR C
2010 C2 JNZ BACK
2011 08
2012 20
2013 EF RST 5
Result:
Block transfer:
Memory Memory
Data Data
Address Address
2040 11 2050 11
2041 22 2051 22
2042 55 2052 55
2043 78 2053 78
2044 63 2054 63
2045 48 2055 48
2046 54 2056 54
Exchange Data
2047 87 2057 87
2048 23 Bytes: 2058 23
2049 65 2059 65
Memory Data Memory Data
Address Address
2040 11 2050 87
2041 22 2051 78
2042 55 2052 65
2043 78 2053 63
2044 63 2054 55
Memory Data Memory Data
2045 48 2055 54
Address Address
2046 54 2056 48
2040 87 2050 11
2047 87 2057 23
2041 78 2051 22
2048 23 2058 22
2042 65 2052 55
2049 65 2059 11
2043 63 2053 78
2044 55 2054 63
2045 54 2055 48
2046 48 2056 54
2047 23 2057 87
2048 22 2058 23
2049 11 2059 65
EXPERIMENT NO – 2
ARRANGING
ELEMENTS OF
BLOCK IN
ASCENDING AND
DESCENDING ORDER
ARRANGING BLOCK OF DATA IN ASCENDING AND
DESCENDING ORDER
Program Statement:
Write a program to arrange given block of data starting
from 2051h in ascending order and descending order. Store result from 2070
for ascending order and from 2080 for descending order. Length of data is
stored in memory location 2050h.
Apparatus:
8085 based single chip Microprocessor kit (VINYTICS
VMC-8501), Scratch Pad RAM used from 2000h to 2770h.
Learning Objective:
1. How to arrange block in ascending and descending order?
2. Why to use two counters?
3. Use of compare instruction.

4. Effect of compare instruction on flag.
Logic:
Ascending Order:
Technique to arrange data bytes in ascending order is to
compare two bytes at a time and arrange them at same time. Two counters
are used for arranging data in ascending order. Two Numbers at successive
memory locations are compared. Smaller number is stored at first memory
location and larger number stored at next memory location. First counter is
decremented by one and when first counter is zero then second counter is
decremented by one and first counter is loaded again. So when second
counter is also zero block is arranged in ascending order.
Descending Order:
Technique to arrange data bytes in descending order is to
compare two bytes at a time and arrange them at same time. Two counters
are used for arranging data in descending order. Two Numbers at successive
memory locations are compared. Larger number is stored at first memory
location and smaller number at next memory location. First counter is
decremented by one and when first counter is zero then second counter is
decremented by one and first counter is loaded again. So when second
counter is also zero block is arranged in descending order.
Algorithm:
Ascending Order:
1. Start
3. Initialize outer counter
4. Initialize inner counter
5. Initialize memory pointer
6. Compare two numbers
7. If carry flag is set go to step 9
8. If carry flag is not set exchange numbers
9. Decrement inner counter
10. If counter is not zero increment memory pointer go to step 6
11. If counter is zero decrement outer counter
13. Stop
Descending Order:
1. Start
3. Initialize outer counter
4. Initialize inner counter
5. Initialize memory pointer
6. Compare two numbers
7. If carry flag is reset go to step 9
8. If carry flag is set exchange numbers
9. Decrement inner counter
10. If counter is not zero increment memory pointer go to step 6
11. If counter is zero decrement outer counter
13. Stop
SORTING IN ASCENDING ORDER
Start
Initialize outer counter
Initialize inner counter
Initialize memory pointers
Compare two numbers
Increment
memory pointers
Is carry
flag
set? No
Yes
Exchange two numbers
Decrement inner counter
Is
No
counter
=0?
Yes
Yes
Decrement outer counter
No Is
counter
= 0 Yes
?
Yes
Stop
SORTING IN DESCENDING ORDER
Start
Initialize outer counter
Initialize inner counter
Initialize memory pointers
Compare two numbers
Increment
memory pointers
Is carry
flag
reset? No
Yes
Exchange two numbers
Decrement inner counter
Is
No
counter
=0?
Yes
Yes
Decrement outer counter
No Is
counter
= 0 Yes
?
Yes
Stop
SORTING IN ASCENDING ORDER
Memory OP
Address CODE
2001 4F Is stored
2002 20
2003 46 MOV B, M Copy length
2004 35 DCR M
2005 5E MOV E, M
2006 4B LOOP2: MOV C, E Initialize inner counter
2007 21 LXI H, 2051
2008 51 LOOP1: MOV A, M
2009 20 INX H
200A BE CMP M Compare two numbers
200B DA JC NEXT
200C 13
200D 20
200E 56 MOV D, M Exchange if carry is
200F 77 MOV M, A Not created
2010 2B DCX H
2011 72 MOV M, D
2012 23 INX H
2013 0D NEXT: DCR C Decrement inner counter
2014 C2 JNZ LOOP1
2015 08
2016 20
2017 05 DCR B Decrement outer counter
2018 C2 JNZ LOOP2
2019 06
201A 20
201B EF RST 5
SORTING IN DESCENDING ORDER
Memory OP
Address CODE
2000 21 LXI H, 2050 Point where length
2001 50 Is stored
2002 20
2003 46 MOV B, M Copy length
2004 35 DCR M
2005 5E MOV E, M
2006 4B LOOP2: MOV C, E Initialize inner counter
2007 21 LXI H, 2050
2008 50 LOOP1: MOV A, M
2009 20 INX H
200A BE CMP M Compare two numbers
200B DA JNC NEXT
200C 13
200D 20
200E 56 MOV D, M Exchange if carry is
200F 77 MOV M, A created
2010 2B DCX H
2011 72 MOV M, D
2012 23 INX H
2013 0D NEXT: DCR C Decrement inner counter
2014 C2 JNZ LOOP1
2015 08
2016 20
2017 05 DCR B Decrement outer counter
2018 C2 JNZ LOOP2
2019 06
201A 20
201B EF RST 5
Result:
Ascending order:
Before sorting After sorting
Memory Memory
Data Data
Address Address
2051 11 0500 11
2052 22 0501 22
2053 55 0502 23
2054 78 Descending 0503 48
2055 63 order: 0504 54
2056 48 0505 55
2057 54 Before sorting 0506 63
2058 87 After sorting 0507 65
2059 23 0508 78
Memory
205A Data
65 Memory
0509 Data
87
Address Address
2051 11 0500 87
2052 22 0501 78
2053 55 0502 65
2054 78 0503 63
2055 63 0504 55
2056 48 0505 54
2057 54 0506 48
2058 87 0507 23
2059 23 0508 22
205A 65 0509 11
Question Bank
1. Compare instructions SUB B and CMP B.
2. How compare instruction will affect on flags?
3. Where result of comparison is stored?

EXPERIMENT NO – 3
MULTIPLICATION OF
TWO 8 BIT
NUMBERS
MULTIPLICATION BY SHIFT AND ADD METHOD
Program Statement:
Write a program to multiply two 8-bit numbers by shift and add
method. Numbers are present at memory location 2100(multiplier) and
2101(multiplicand). The result is 16 bit and is to be stored in memory
location2102 and 2103.
Apparatus:
8085 based single chip Microprocessor kit (VINYTICS VMC-
8501), Scratch Pad RAM used from 2000h to 2770h.
Learning Objective:
a) Methods of multiplication.
b) Shift and add method for multiplication.
c) Use of DAD h in shift and add method.
Logic:
The technique used to multiply two 8 bit numbers is same as
used to multiply two binary numbers. In this method each bit of the multiplier
bit is multiplied with multiplicand. Each partial product is to be shifted left so
as to double the number.
If the multiplier bit is 0 the multiplicand is doubled placed as the
partial product. Therefore if multiplier ‘ n’ bit number of partial product will be
‘n’ if multiplicand is ‘m’ bits the product length will be 2 * m.
1101 (multiplicand)
*0011(multiplier)
---------------------------------
1101 (partial products)
1011x
0000 x x
0000 x x x
----------------------------------------------
00100011 (result)
Algorithm:
1. Start.
2. Set partial product register pair to 0.
3. Set up register pair as multiplicand, get multiplier is register C
as counter.
4. Double the partial product for next summand.
5. If multiplier is zero go to step 7.
6. If multiplier is not zero add multiplicand to the previous partial
product.
7. Decrement counter by 1.
8. If counter is not zero go to step 4.
9. If counter is zero save result in register pair in memory.
10. Stop.
Start
Set partial product register pair

to 0
Set up register pair as

multiplicand; get multiplier in
register C as counter
Double the partial product for

next summand
Yes
Is multiplier
zero?
No
Add multiplicand to the

previous partial product
Decrement counter by 1
No
Is counter
zero?
Yes
Save result in register pair

in memory
Stop
Memory OP
Address CODE
2000 2A LHLD 2050
2001 50 Initialize memory pointer
2002 20
2003 5D MOV E,L
2004 16 MVI D,00H
2005 00
2006 43 MOV B,H
2007 21 LXI H,0000H
2008 00
2009 00
200A 0E MVI C,08H Number of times to be
200B 08 rotated
200C 29 UP: DAD H
200D 78 MOV A,B
200E 07 RLC
200F 47 MOV B,A
2010 D2 JNC NEXT
2011 14
2012 20
2013 19 DAD D
2014 0D NEXT: DCR C
2015 C2 JNZ UP
2016 0C
2017 20
2018 22 SHLD 2052
2019 52
201A 20
201B EF RST 5
Result:
INPUT OUTPUT
Address Data Address Data
2100 3Fh 2102 1Bh
2101 70h 2103 90h
MULTIPLICATION BY SUCCESSIVE ADDITION
Algorithm:
1. Start
2. Copy contents of memory location to HL pair(First number)
3. Copy content of memory location to register C(Second number)
4. Add first number in itself
5. Decrement reg C
6. If not zero go to step 4
7. Store result
8. Stop.
Start
Copy 1st number from memory

location to register pair
Copy second number from

memory location to register C
Copy first number in DE pair
Add first number in itself

HL+DE Decrement reg C
No Is reg C
zero?
Yes
Store result in memory

location
Stop
Memory OP
Address CODE
2000 01 LXI B,2200 Load BC pair with content
2001 00 Of memory location
2002 22 2200
2003 0A LDAX B
2004 6F MOV L,A Copy first number
2005 26 MVI H,00
2006 00
2007 03 INX B
2008 0A LDAX B
2009 3D DCR A
200A 4F MOV C,A Copy second number
200B 5D MOV E,L
200C 16 MVI D,00
200D 00
200E 19 LOOP: DAD D
200F 0D DCR C
2010 C2 JNZ LOOP
2011 0E
2012 20
2013 01 LXI B, 2002
2014 02
2015 20
2016 7D MOV A,L Store result
2017 02 STAX B
2018 03 INX B
2019 7C MOV A,H Store result
201A 02 STAX B
201B EF RST 5
Result:
INPUT OUTPUT
2200 AA H 2202 E4 H
2201 AA H 2203 70 H
Question Bank
1. Compare RAR and RRC.
2. Explain following instructions
a) SHLD 2100
b) DAD D
c) XCHG
d) LHLD 2100
3. What is difference between hardware and software
interrupts?
4. What are vectored interrupts?
5. What are maskable and non maskable interrupts?
 
CONVERTING TWO DIGIT NUMBERS TO THEIR
EQUIVALENTS
Program Statement:
Write a program to convert two digit number from BCD to HEX.
Number is at location 2040 store result at location 2041.
Apparatus:
EXPERIMENT NO – 4
CONVERTING TWO
DIGIT NUMBER
TO THEIR
EQUIVALENTS
Learning Objective:
1. Unpacking of BCD number.
2. Division of number.
Logic:
BCD TO HEX CONVERSION:
BCD number is unpacked and LSB and MSB is
unpacked. MSB is multiplied by 10 and LSB is added in resulting value of
multiplication.
HEX TO BCD CODE CONVERSION:

HEX number is divided by 100 which is MSB.
Remaining value is divided by 10 and remainder will be LSB.
Algorithm:
BCD TO HEX CONVERSION:

1. Start
2. Copy number from memory location
3. Unpack both digits
4. Multiply MSB by 10
5. Add LSB into previous multiplication result
6. Store result
7. Stop
HEX TO BCD CODE CONVERSION:
1. Start
2. Copy number from memory location
3. Divide number by 100 it will give MSB
4. Divide number by 10
5. Remainder is LSB
6. Store result
7. Stop
BCD TO HEX CONVERSION
Start
Copy number from memory

location
Unpack number and separate

LSB and MSB
Multiply MSB by 10 add LSB

into it

location
Stop
HEX TO BCD CONVERSION
Start
Copy number from memory

location
Divide number by 100(MSB)
Divide number by 10,

Remainder is LSB

locations
Stop
BCD TO HEX CODE CONVERSION:
Memory OP
Address CODE
2000 21 LXI H,2040 Load HL pair with address of
2001 40 memory location
2002 20
2003 46 MOV B,M
2004 7E MOV A,M Unpack LSB
2005 E6 ANI 0FH
2006 0F
2007 4F MOV C,A
2008 78 MOV A,B
2009 E6 ANI F0H Unpack MSB
200A F0
200B CA JZ NEXT
200C 1B
200D 20
200E 0F RRC
200F 0F RRC
2010 0F RRC
2011 0F RRC
2012 57 MOV D,A
2013 AF XRA A
2014 1E MVI E,0AH Multiply MSB by 10
2015 0A
2016 83 ADD: ADD E Add both
2017 15 DCR D
2018 C2 JNZ ADD
2019 16
201A 20
201B 81 ADD C
201C 23 INX H
201D 77 MOV M,A Store result
201E EF RST 5
Result:
Input: Output:
Address Data
2040 12
Address Data
2041 0C
HEX TO BCD CODE CONVERSION
Memory OP
Address CODE
2000 21 LXI H,2040 Load HL pair with address of
2001 40 memory location
2002 20
2003 7E MOV A,M
2004 06 MVI B,64H
2005 64
2006 23 INX H
2007 36 MVI M,FFH
2008 FF
2009 90 NEXT: SUB B Divide number by 100
200A 34 INR M
200B D2 JNC NEXT
200C 09
200D 20
200E 80 ADD B
200F 23 INX H
2010 36 MVI M,FFH
2011 FF
2012 06 MVI B,0AH
2013 0A
2014 90 NEXT1: SUB B Divide number by 10
2015 34 INR M
2016 D2 JNC NEXT1
2017 14
2018 20
2019 80 ADD B
201A 23 INX H
201B 77 MOV M,A
201C EF RST 5
Result:
Input: Output:

2040 FF 2041 02
2042 05
2043 05
GENERATION OF FIBONACCI SERIES
Program Statement:
Write a program to generate Fibonacci series starting from
location 2040.
Apparatus:
EXPERIMENT NO – 5
GENERATION OF
FIBONACCI
SERIES
Learning Objective:
a. Generation of series
Logic:
Copy first two numbers to locations. For generating next

number add previous two numbers and store result. Go on repeating same
procedure till counter is not zero.
Algorithm:
1. Start
2. Initialize pointer
3. Initialize counter
4. Copy first two numbers
5. Generate next number by adding previous two
6. Store result
7. Increment Pointer
8. Decrement counter
10. Stop
Start
Initialize pointer and

counter
Copy first two

numbers
Generate next number

by addition of previous
numbers
Store result
Increment pointer
Decrement counter
No Is Yes
counter
=0?
Stop
Memory OP
Address CODE
2000 21 LXI H,2040H
2001 40 Initialize memory pointer
2002 20
2003 0E MVI C,09H Initialize counter
2004 09
2005 36 MVI M,00H Copy first number
2006 00
2007 23 INX H
2008 36 MVI M,01H Copy second number
2009 01
200A 7E BACK: MOV A,M
200B 2B DCX H
200C 86 ADD M Generate next number
200D 23 INX H
200E 23 INX H
200F 77 MOV M,A Store result
2010 0D DCR C
2011 C2 JNZ BACK
2012 0A
2013 20
2014 EF RST 5
Result:
Address Data
2040 00
2041 01
2042 01
2043 02
2044 03
2045 05
2046 08
2047 0D
2048 15
EXPERIMENT NO – 6
INTERFACING OF DAC
0808
INTERFACING OF DAC 0808
Program Statement:
Write program to generate triangular waveform using DAC 0808
Apparatus:
8501),Scratch Pad RAM used from 2000h to 2770h, Cathode Ray
Oscilloscope.
Learning Objective:
a) DAC 0808
b) OUT instruction
c) How to generate triangular wave?
Logic:
R-2R Ladder DAC: R
2R R R R
2R 2R 2R 2R
+5V
Only two values of resistors are used but result is same, input current is
proportional to bit inputs.
Features of DAC 0808 are:
a) It has 8 data inputs.
b) Fast setting time 150ns.
c) Low power consumption 33mW.
d) +5V power supply.
e) TTL and CMOS compatible.
TRIANGULAR WAVE GENERATION USING DAC 0808
Algorithm:
1. Initialize accumulator to 00H.
2. Output register A to DAC buffer A0H.
3. Increment accumulator.
4. Compare accumulator content with FFH.
5. If not zero go to step 2 or go to step 6.
6. Decrement accumulator.
7. Output register A to DAC buffer A0H.
8. Compare accumulator content with 00H.
9. If not zero go to step 6 or go to step 10.
10. Go to step 1.
Start
Load accumulator
with 00H
Out accumulator
content on A0H
Increment accumulator
Compare A with FFH
No
Is
ZF=1
?
Yes
Decrement accumulator
Out accumulator
content on A0H
Compare A with 00H
No
Is
ZF=1
?
Yes
Memory OP
Address CODE
2000 3E NEXT: MVI A, 00H Load A with 00H
2001 00
2002 D3 NEXTINR: OUT A0H Output A to DAC
2003 A0
2004 3C INR A Increment A
2005 FE CPI FFH
2006 FF
2007 C2 JNZ NEXTINR
2008 02
2009 20
200A 3D NEXTDCR: DCR A Decrement A
200B D3 OUT A0H
200C A0
200D FE CPI 00H
200E 00
200F C2 JNZ NEXTDCR
2010 0A
2011 20
2012 C2 JMP NEXT Jump to start again
2013 00
2014 20
Question Bank
1. Draw complete interfacing diagram and discuss a scheme
for generation of ramp waveform using DAC IC 8255 PPI
and 8085
2. Draw timing diagram of OUT 20H instruction and explain it
in detail.
 
EXPERIMENT NO – 4
INTERFACING
THUMBWHEEL
SWITCH
THUMBWHEEL SWITCH INTERFACE USING PPI 8255
Program Statement:
To interface thumbwheel switch to 8085 through PPI 8255.
Apparatus:
8501), Scratch Pad RAM used from 2000h to 2770h, Thumbwheel Switch Kit.
Memory Address Subroutine
0347h Clear Display
05D0h Character display
03BCh Delay
16h is the character code used to keep display blank; stored at memory
locations 2050 to 2054.
Learning Objective:
a) IN instruction.
b) Effect of XRA A instruction.
c) PPI 8255.
Logic:
Thumbwheel switch is interfaced to 8085 using PPI 8255. Each
time thumbwheel switch is rotated by one step corresponding BCD number is
read through PORT A by 8085 and that digit is displayed by using display
subroutine.
Algorithm:
1. Initialize stack
2. Call clear subroutine stored at 0347H
3. Load accumulator with control word and out it on control word
register.
4. Clear accumulator and register B to enable address field of display.
5. Load HL pair with starting address of data for address field display.
6. Call output subroutine at 05D0H.
7. Copy contents of port A into accumulator.
8. Mask upper four bits.
9. Load HL pair with starting address of data for data field display.
10. Copy contents of accumulator in 2055H.
11. Load accumulator with 01H and register B with 00H to enable data
field display.
12. Call display subroutine.
13. Load DE pair with 0000H as counter required by delay routine.
14. Call delay at 03BCH.
15. Go to step 7.
Start
Initialize stack
Call clear
subroutine
Initialize 8255 ports
Clear register A and B
Initialize HL pair
with 2050
Call output display

subroutine
Copy data from

Port A
Mask upper four bits
Call output
display
subroutine
Load DE pair with count
Call Delay
Subroutine
Memory OP
Address CODE
2000 31 LXI SP,2100H Initialize stack
2001 00
2002 21
2003 CD CALL CLEAR
2004 47
2005 03
2006 3E MVI A,90H
2007 90
2008 D3 OUT 03H
2009 03
200A AF UP: XRA A
200B 47 MOV B,A
200C 21 LXI H,2050H Memory pointer for
200D 50 Character code
200E 20
200F CD CALL OUTPUT Output subroutine
2010 D0
2011 05
2012 DB IN 00H
2013 00
2014 E6 ANI OFH
2015 0F
2016 21 LXI H,2054H
2017 54
2018 20
2019 32 STA 2055H
201A 55
201B 20
201C 3E MVI A,01H Enable data field of
201D 01 display
201E 06 MVI B,00H Disable dot of
201F 00 display
2020 CD CALL OUTPUT Output subroutine
2021 D0
2022 05
2023 11 LXI D,0000H
2024 00
2025 00
Memory OP
Address CODE
2026 CD CALL DELAY Delay subroutine
2027 BC
2028 03
2029 C3 JMP UP Repeat again
202A 0A
202B 20
2050 16H
2051 16H
2052 16H
2053 16H
2054 16H
2055 00H
Question Bank
1. Compare the execution of following instructions
a) MVI A, 00H
b) XRA A
c) SUB A
d) ANI 00H
2. Draw timing diagram of handshaking signals of 8255 in mode 1, input,
along with INTR, RD.
3. Give BSR control word and explain bi-directional mode of operation of
8255

EXPERIMENT NO – 8
ARRANGING BLOCK IN
DESCENDING
AND
ASCENDING
USING 8051
ARRANGING BLOCK OF DATA IN DESCENDING AND
ASCENDING ORDER
Program Statement:
Arrange given block of ten bytes in descending and
ascending order. Block is stored from location 30H.
Apparatus:
8031 based single chip Microcontroller kit (ANSHUMAN –
8031/V51), Scratch Pad RAM used from 6000h to 7FFFh, Power Supply.
Learning Objective:
1. How to use memory pointer?
2. Comparison between two numbers
3. Use of one of the sorting technique as Bubble sort
4. Using two counters nesting is done.
Logic:
For arranging block in descending order two memory
pointers are used. Both are pointing successive memory locations. First
pointers are pointing 30h and 31h both numbers are compared and larger
number is stored at location 30h and smaller at 31h.Both pointers are
incremented and counter is decremented. After comparing all numbers same
procedure is repeated for ten times for that second counter is used.
When second counter is decremented both pointers are
pointing again 30h and 31h and first counter is loaded with 09. Above steps
are repeated till second counter is zero. When second counter is zero block is
arranged in descending order. Two counters are used as first counter is for
comparison between two successive numbers and second for repeating the
comparison 9 times to arrange them in descending order.
ARRANGING BLOCK OF DATA IN DESCENDING ORDER
Start
Counter1=0Ah
Counter2=09h
Pointer1=30h
Pointer2=31h
No
Is number
pointed by
pointer1 >
pointer2 ?
Copy larger no. pointed

by pointer1 smaller at
Yes pointed by pointer2
Increment Pointers
decrement counter2
Is
counter2
No
zero?
Yes
Decrement counter1
No
Is
counter1
zero?
Yes
Stop
ARRANGING BLOCK OF DATA IN ASCENDING ORDER
Start
Counter1=0Ah
Counter2=09h
Pointer1=30h
Pointer2=31h
No
Is number
pointed by
pointer1 <
pointer2 ?
Copy larger no. pointed

by pointer1 smaller at
Yes pointed by pointer2
Increment Pointers
decrement counter2
Is
counter2
No
zero?
Yes
Decrement counter1
No
Is
counter1
zero?
Yes
Stop
ARRANGING BLOCK IN DESCENDING ORDER
Memory OP Mnemonic And

Lable Comment
Address CODE Operand
6000 7A MOV R2, #0AH ;Load counter1
6001 0A
6002 7B PASS2: MOV R3, #09H ;Load counter2
6003 09
6004 78 MOV R0, #30H ;Initialize Pointer1
6005 30
6007 31
6008 E6 PASS: MOV A, @R0
6009 87 MOV 40H, @R1
600A 40
600B B5 CJNE A, 40H,NEXT ;Compare values
600C 40 Pointed by
600D 02 pointers
600E 80 SJMP LOOP
600F 04
6010 50 NEXT: JNC LOOP
6011 02
6012 C7 XCH A, @R1
6013 F6 MOV @R0, A
6014 08 LOOP: INC R0
6015 09 INC R1
6016 DB DJNZ R3, PASS
6017 F0
6018 BA DJNZ R2, PASS2
6019 E8
601A 80 HERE: SJMP HERE
601B FE
ARRANGING BLOCK IN ASCENDING ORDER

Lable Comment
6000 7A MOV R2, #0AH ;Load counter1
6001 0A
6002 7B PASS2: MOV R3, #09H ;Load counter2
6003 09
6005 30
6007 31
6008 E6 PASS: MOV A, @R0
6009 87 MOV 40H, @R1
600A 40
600B B5 CJNE A, 40H,NEXT ;Compare values
600C 40 Pointed by
600D 02 pointers
600E 80 SJMP LOOP
600F 04
6010 50 NEXT: JC LOOP
6011 02
6012 C7 XCH A, @R1
6013 F6 MOV @R0, A
6014 08 LOOP: INC R0
6015 09 INC R1
6016 DB DJNZ R3, PASS
6017 F0
6018 BA DJNZ R2, PASS2
6019 E8
601A 80 HERE: SJMP HERE
601B FE
Result: Ascending and Descending
Input Block: Output Block:
Memory Memory
Data Data
Address Address
30 0A 30 01
31 05 31 03
32 0F 32 05
33 06 33 06
34 01 34 07
35 0B 35 08
36 0D 36 0A
37 08 37 0B
38 03 38 0D
39 07 39 0F
Input Block: Output Block:
Memory Memory
Data Data
Address Address
30 0A 30 0F
31 05 31 0D
32 0F 32 0B
33 06 33 0A
34 01 34 08
35 0B 35 07
36 0D 36 06
37 08 37 05
38 03 38 03
39 07 39 01
Question Bank
1. Why two pointers are required in this program?
2. How numbers are arranged in descending order?
3. Explain following instructions:
a) CJNE A, #data, relative address
b) DJNZ R1, relative address
c) XCH A, @R1
4. Which registers are allowed to be used for register indirect
addressing mode when accessing data in RAM?

EXPERIMENT NO – 8
SQUARE WAVE
GENERATION
USING TIMER
OF 8051
SQUARE WAVE GENERATION USING TIMER OF 8051
Program Statement:
Generation of square wave using timer of 8051.

Apparatus:
8031 based single chip Microcontroller kit (ANSHUMAN –8031/
V51), Scratch Pad RAM used from 6000h to 7FFFh, Cathode Ray
Oscilloscope, Power Supply.
Learning Objective:
1. Timers of 8051
2. Working of timer of 8051
3. Generation of square using timer of 8051
4. Calculating count to be loaded in timer register
5. Role of overflow flag in timer
6. Generating delay using timer
Logic:
For generating square wave port pin P1.1 is used. P1.1 is high
for delay period generated by timer and low for the same delay period.
TIMER0 in MODE1 is used. Count value is loaded in TH0 and
TL0. Count value is calculated according to the frequency of square wave to
be generated. P1.1 is made high. Timer is started and overflow flag is
checked. When timer will roll over from FFFFH to 0000H overflow flag will be
set. When overflow flag is set; P1.1 is complemented. Then stop the timer and
procedure is repeated for continuous generation of square wave. As delay is
same for high and low period square wave is having 50% duty cycle.
Algorithm:
1. Initialize timer and mode of timer.
2. Make P1.1 high
3. Load count value in THx and TLx
4. Start timer
5. Check overflow flag
6. When overflow flag is set complement P1.1
7. Clear overflow flag
8. Stop timer
9. For continuous display of square wave go to step 3

Start
Initialize timer
and mode
Make P1.1 high
Load count value
Start timer
Is
overflow
No flag
set?
Yes
Complement
P1.1
Clear overflow
flag
Stop Timer

Lable Comment
6000 75 MOV TMOD, #01H ;Initialize mode and
6001 89 timer
6002 01
6003 D2 SETB P1.1
6004 91
6005 75 UP: MOV TL0, #0FDH ;TL0 count
6006 8A
6007 FD
6008 75 MOV TH0, #0FFH ;TH0 count
6009 8C
600A FF
600B D2 SETB TR0 ;Start timer
600C 8C
600D 30 LOOP: JNB TF0, LOOP ;Check overflow flag
600E 8D
600F FD
6010 B2 CPL P1.1
6011 91
6012 C2 CLR TF0
6013 8D
6014 C2 CLR TR0 ;Stop timer
6015 8C
6016 80 SJMP UP ;For continuous
6017 ED wave
Question Bank
1. How many timers do 8051 have?
2. How timer is initialized?
3. How count value, which is to be loaded in timer is calculated?
4. What is the use of overflow flag?
5. What is role of timer in serial communication?
6. Explain TMOD register.
7. Write assembly language program to generate square wave of
1KHz at P1.0 (bit 0 at port 1).
8. What bit addresses are assigned to TCON register?

EXPERIMENT NO – 6
INTERFACING OF
DOT MATRIX
DISPLAY USING
8051
INTERFACING OF DOT MATRIX DISPLAY USING
8051
Program Statement:
Interfacing of 5 x 7 dot matrix display.
Apparatus:
8031 based single chip Microcontroller kit (ANSHUMAN – 8031/
V51), Scratch Pad RAM used from 6000h to 7FFFh, Dot Matrix Kit, Power
Supply.
Learning Objective:
1. How to display number on matrix display?
2. How to use single bit of port?
3. Calling subroutine from different memory page.
Logic:
For interfacing of 5x7 dot matrix display port 1 and port 3 are
used. Seven rows as R1 to R7 are interfaced with port 1 from P1.0 to P1.6.
Pin P1.7 is used for column 5. Four columns are interfaced using port 3 as C1
using P3.1, C2 using P3.3, C3 using P3.4 and C4 using P3.5.
For displaying character rows and columns are enabled accordingly.
By making port pins low of port 1 rows are enabled. And by making port pins of port
3 high columns are enabled. According to data to be displayed on matrix display,
rows and columns are enabled and delay is called.

Algorithm:
1. Make display blank by disabling all rows and columns.
2. Enable all rows and C3
3. Call delay
4. Disable all rows and C3
5. Enable all columns and R7.
6. Call delay
7. Disable all columns and R7
8. Enable R3 and C1
9. Call delay
10. Disable R3 and C1
11. Enable R2 and C2
12. Call delay
13. Disable R2 and C2
14. For continuous display go to step2.

INTERFACING OF DOT MATRIX DISPLAY USING 8051
Start
Make display blank
Enable all rows and

C3
Call delay
Disable all rows and

C3
Enable all columns

and R7
Call delay
Disable all columns

and R7
Enable R3 and C1
Call display
Disable R3 and C1
Enable R2 and C2
Call delay
Disable R2 and C2
INTERFACING OF DOT MATRIX DISPLAY USING
8051

Lable Comment
6000 75 MOV SP, #50H ;Initialize stack
6001 81
6002 50
6003 75 MOV P1, #7FH ;Blank Display
6004 90
6005 7F
6006 75 MOV P3, #00H ;Blank Display
6007 B0
6008 00
6009 75 UP: MOV P1, #00H ;Enable all rows
600A 90
600B 00
600C D2 SETB P3.4 ;Enable column C3
600D B4
600E 12 LCALL DELAY
600F 60
6010 40
6011 C2 CLR P3.4 ;Disable column C3
6012 B4
6013 75 MOV P1, #7FH ;Disable all rows
6014 90
6015 7F
6016 75 MOV P3, #0FFH ;Enable all columns
6017 B0
6018 FF
6019 D2 SETB P1.7 ;Enable C5
601A 97
601B C2 CLR P1.6 ;Enable R7
601C 96
601D 12 LCALL DELAY
601E 60
601F 40
6020 C2 CLR P1.7 ;Disable C5
6021 97
6022 D2 SETB P1.6 ;Disable R7
6023 96
6024 75 MOV P3, #00H ;Disable all columns
6025 B0
6026 50
6027 C2 CLR P1.2 ;Enable R3
6028 92
Continued……….
INTERFACING OF DOT MATRIX DISPLAY USING 8051

Lable Comment
602A B1
602B 12 LCALL DELAY
602C 60
602D 40
602E D2 SETB P1.2 ;Disable R2
602F 92
6030 C2 CLR P3.1 ;Disable C1
6031 B1
6032 C2 CLR P1.1 ;Enable R2
6033 91
6035 B3
6036 12 LCALL DELAY
6037 60
6038 40
6039 D2 SETB P1.1 ;Disable R2
603A 91
603B C2 CLR P3.3 ;Disable C2
603C B3
603D 02 LJMP UP
603E 60
603F 09
6040 76 DELAY: MOV R0, #0FFH ;Initialize counter

6041 FF
6042 D8 HERE: DJNZ R0, HERE ;Decrement counter if
6043 FE not zero go to HERE
6044 22 RET
Question Bank
1. How a port can be made input port?
2. Give memory organization of 8051 family.
3. How an element on matrix display can be made on?
4. Explain the difference between LJMP and SJMP.
5.How to calculate the relative address for forward and backward
jump?
6. What bit addresses are assigned to P3?

Microprocessor/microcontroller Program

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INDEX

1. BLOCK TRANSFER AND BLOCK EXCHANGE OF DATA

2. ARRANGING ELEMENTS OF A BLOCK OF DATA IN

ASCENDING AND DESCENDING ORDER.

3. MULTIPLICATION OF TWO 8-BIT NUMBERS USING THE

METHOD OF SUCCESSIVE ADDITION AND SHIFT AND

4. CONVERTING TWO DIGIT NUMBER TO THEIR

5. GENERATION OF FIBONACCI SERIES

6. INTERFACING DAC 0808

7. INTERFACING OF THUMBWHEEL SWITCH.

8. ARRANGING BLOCK IN DESCENDING AND ASCENDING

9. 8051 TIMER BASED EXPERIMENT.

10. INTERFACING OF DOT MATRIX DISPLAY USING 8051

2. Use of indirect addressing mode.

3. Exchange of data between two memory locations.

Copy length of block

Initialize source block

Copy content from

Increment both pointers

Copy length of block

Initialize source block

Increment both pointers

2. Why to use two counters?

3. Use of compare instruction.

2. Copy length of block

3. Initialize outer counter

4. Initialize inner counter

5. Initialize memory pointer

6. Compare two numbers

7. If carry flag is reset go to step 9

8. If carry flag is set exchange numbers

9. Decrement inner counter

10. If counter is not zero increment memory pointer go to step 6

11. If counter is zero decrement outer counter

12. If counter is not zero go to step 4

Copy length of block

Initialize outer counter

Initialize inner counter

Initialize memory pointers

Compare two numbers

Decrement inner counter

Copy length of block

Initialize outer counter

Initialize inner counter

Initialize memory pointers

Compare two numbers

Decrement inner counter

1. Compare instructions SUB B and CMP B.

2. How compare instruction will affect on flags?

3. Where result of comparison is stored?

2. Set partial product register pair to 0.

3. Set up register pair as multiplicand, get multiplier is register C

4. Double the partial product for next summand.

5. If multiplier is zero go to step 7.

6. If multiplier is not zero add multiplicand to the previous partial

8. If counter is not zero go to step 4.

9. If counter is zero save result in register pair in memory.

Set partial product register pair

Set up register pair as

Double the partial product for

Add multiplicand to the

Save result in register pair

Copy 1st number from memory