BASIC VLSI DESIGN

MINI PROJECT REPORT

BINARY 4-BIT UP/DOWN RIPPLE COUNTER

REALIZATION IN VERILOG AND VHDL

PERFORMED BY

JEYAHARIPRAKASH.M
Reg.no:9907005096
PREFINAL YEAR ECE-B
BINARY 4-BIT UP/DOWN RIPPLE COUNTER REALIZATION IN
VERILOG AND VHDL
AIM:
To realize a binary 4-bit up/down ripple counter in verilog and vhdl.

Apparatus required:

Synthesis tool : Xilink ISE.

Simulation tool : ModelSim Simulator.

Theory:
Flip-flops can be another name for bistable circuits that change state on the application of
a trigger pulse.

The simplest of all flip- flops is the SR(Set-Reset) flip flop. There are two possible
implementations for it. The first one uses NOR gates and the second one uses
NAND gates . The difference between the two implementations is that the
NOR implementation triggers for positive going pulses(Positive Logic) and the other
triggers for negative going pulses(Negative Logic). The truth tables and logic symbols
for both the implementations are also shown below.

S R Q Q’
0 0 Q Q’
1 0 1 0
0 1 0 0
1 1 x x

We can see from the tables that in each of the implementations, SR flip-flop suffers from
an inherent defect. It outputs an “invalid state” when both the inputs are ‘1’ &’1’ in NOR
implementation and ‘0’ & ‘0’ in NAND implementation.
This problem can be overcome by using additional feedback lines .The resulting flip- flop
is called a JK flip-flop.

J K Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 Q’n

The operation of a JK flip- flop is the same as that of a SR flip- flop, except for the fact
that the changes are synchronized with respect to the clock. As long as the clock is low,
the S and R inputs are both one irrespective of the inputs given at J and K, and so the
output state remains unchanged. We can also see from the truth table that the invalid
state is also no more.

As always nothing in this world comes without a catch. Likewise, when both J and K
inputs are ‘1’, the output changes state. If the clock is high for a long time, then the
output changes state continuously until the clock goes low.

T flip- flop as the name suggests, just toggles its output for every clock pulse. It is
constructed by shorting the J and K inputs of the JK flip- flop. The clock width constraint
holds ground for this flip- flop.

Counters:

As said earlier, counters are constructed using flip- flops as their fundamental units. We
will use the edge triggered JK flip-flop to construct counters. Counters are of two types.
Asynchronous and Synchronous counters. We will limit our discussions to synchronous
counters alone.
Synchronous Up-Counter Using JK Flip-Flop:

Synchronous Down-Counter Using JK Flip-Flop:

shows an up-down-counter using JK flip- flop. If the UP / Down signal is high

the counter acts as an up counter and if it s low, the system acts as a down counter.
Synchronous 3-bit Up/Down-Counter Using JK Flip-Flop:

Procedure:

For VHDL Program:

1.The 4 bit binary up down counter is designed.

2.The VHDL program source code for the circuit is written.
3.It is implemented in Model Sim and Simulated.
4.Signals are provided and the output Waveforms are viewed.
5.Synthesis this program in XILINX and flashed to the FGPA.

For Verilog HDL Program:

1.The 4 bit binary up down counter is designed.

2.The Verilog program source code for the circuit is written.
3.It is implemented in Model Sim and Simulated.
4.Signals are provided and the output Waveforms are viewed.
5.Synthesis this program in XILINX and flased to the FGPA.
JK FLIPFLOP CODING:-

library ieee;
use ieee.std_logic_1164.all;

entity jk is
port(clk,j,k,clr:in std_logic;
q,qbar:inout std_logic);
end jk;

architecture flop of jk is
begin
process(j,k,clk,clr)
begin
if (clr='1') then
if(rising_edge(clk)) then

if(j='0' and k='0') then

q<=q;
qbar<=not q;
elsif(j='0' and k='1') then
q<='0';
qbar<='1';
elsif(j='1' and k='0') then
q<='1';
qbar<='0';
else
q<=not q;
qbar<=not qbar;
end if;
end if;

else
q<='0';
qbar<='1';
end if;
end process;
end flop;
4-BIT UP/DOWN COUNTER:-
VERILOG CODING:-
module
jkff(q,qbar,j,k,clk,rst);
input j,k,clk,rst;
output q,qbar;
reg q;
assign qbar=~q;
always@(posedge clk)
if(~rst)
q=1'b0;
else
case ({j,k})
2'b00:q=q;
2'b01:q=1'b0;
2'b10:q=1'b1;
2'b11:q=~q;
endcase
endmodule

module
ad(q,qbar,j,k,clk,rst);
inout [3:0] q,qbar;
input j,k;
input clk,rst;
wire a,b,c,d,e,f,x;

jkff f0(q[0],qbar[0],j,k,clk,rst);
and (a,q[0],x);
and (b,qbar[0],(~x));
or(c,a,b);

jkff f1(q[1],qbar[1],c,c,clk,rst);
and (d,q[1],a);
and (e,qbar[1],b);
or(f,d,e);

jkff f2(q[2],qbar[2],f,f,clk,rst);
and (g,q[2],d);
and (h,qbar[2],e);
or(i,g,h);

jkff f3(q[3],qbar[3],i,i,clk,rst);
endmodule
4-BIT UP/DOWN COUNTER:-
VHDL CODING:-

library ieee;
use ieee.std_logic_1164.all;

entity ud is
port(clk,j,k,clr:in std_logic;
q,qbar:inout std_logic_vector(3 downto 0));
end ud;

architecture updown of ud is
component jk
port(clk,j,k,clr:in std_logic;
q,qbar:inout std_logic);
end component;
signal a,b,c,d,e,f,g,h,i,x:std_logic;

begin

d1:jk port map(clk,j,k,clr,q(0),qbar(0));

a<=q(0)and x;
b<=(qbar(0) and (not x));
c<=a or b;

d2:jk port map(clk,c,c,clr,q(1),qbar(1));

d<=q(1) and a;
e<=qbar(1) and b;
f<=d or e;

d3:jk port map(clk,f,f,clr,q(2),qbar(2));

g<=q(2) and d;
h<=qbar(2) and e;
i<=g or h;

d4:jk port map(clk,i,i,clr,q(3),qbar(3));

end updown;
WAVEFORM OF UP COUNTER:-
WAVEFORM OF DOWN COUNTER:-
 Up Counter –ModelSim Simulator Waveform:

Down Counter –ModelSim Simulator Waveform:

TECHNOLOGY SCHEMATIC:-
Internal blocks of FGPA:

LUT(Look-Up Table) Diagram:

 LUT2 ( INIT=9)

Schematic View:

Truth Table:

Karnaugh Map:
 LUT3 (INIT=A9)

Schematic View:

Truth Table:

Karnaugh Map:
 LUT3 (INIT=5C)

Schematic View:

Truth Table:

Karnaugh Map:
 LUT4 (INIT=AAA9)
Schematic View:

Truth Table:

Karnaugh Map:
Conclusion:

Thus the binary 4-bit Up/Down ripple counter is designed in Vhdl and Verilog HDL and the output
is verified.