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wl 2014 5.

1
ALU
RAM
CPU Organisation: Registers, ALU, Control
CPU
Register
file
R
1
..R
N
Program Counter
Instr. Register
I
n
t
e
r
n
a
l

B
u
s
000
001
002
003
3FD
3FE
3FF
Output Reg
Input Reg1
Input Reg2
Instr. Decoder
Control Unit
Address
Bus
Data
Bus
Control
Bus
Memory
CPU
CPU: Central Processing Unit, ALU: Arithmetic and Logic Unit
wl 2014 5.2
Fetch-Execute Cycle
Fetch the Instruction (address in Program Counter PC)
Increment PC (prepared to get next instruction)
Decode the Instruction (find out tasks to do)
Fetch the Operands (data needed for the tasks)
Execute the Operation (do the tasks, may involve ALU)
Store the Results (in a register or in memory)
Repeat Forever
wl 2014 5.3
High/Low-Level Languages, Machine Code
High-Level Language (e.g. Java, C++, Haskell)

A = B + C Assignment Statement

Low-Level Language: Assembly Language (e.g. Intel IA-32, PowerPC,
ARM etc, Java Bytecode)

LOAD R2, B R2 = M[b]
ADD R2, C R2 = R2 + M[c]
STORE R2, A M[a] = R2

(Binary) Machine Code

0001101000000001 Machine Code
0011101000000010 Instructions
0010101000000000
wl 2014 5.4
The Toy1 Architecture
Maximum of 1024 x 16-bit memory words
Memory is Word Addressed

Twos Complement Integer Representation

4 General Purpose Registers (16-bit) : R0, R1, R2, R3

Up to 16 Instructions, e.g. LOAD, ADD, STORE
wl 2014 5.5
Toy1 Instruction Set
LOAD Register , [MemoryAddress]
Register = Memory [MemoryAddress]

STORE Register , [MemoryAddress]
Memory [MemoryAddress] = Register

ADD Register , [MemoryAddress]
Register = Register + Memory [MemoryAddress]

SUB Register , [MemoryAddress]
Register = Register - Memory [MemoryAddress]

wl 2014 5.6
Toy1 Instruction Format
4-bit
OPCODE
2-bit
REG
10-bit
ADDRESS
Instruction Fields
OPeration CODE (Selects CPU Instruction)
REGister (Specifies 1st Operand for Instruction)
ADDRESS (Specifies 2nd Operand for Instruction)
Machine Code
ADD R2, C Assembly Instruction e.g.
wl 2014 5.7
Instruction Field Encoding
OPCODE LOAD 0001
(4-bit) STORE 0010
ADD 0011
SUB 0100
REG Register 0 00
(2-bit) Register 1 01
Register 2 10
Register 3 11
ADDRESS 10-bit Memory Word Address
4-bit 2-bit 10-bit
OPCODE REG ADDRESS
16-bit Instruction
wl 2014 5.8
Memory Placement (Program)
LOAD R2, [201H]
0001 10 10 0000 0001 00 1000 0000
A 0 1 1
ADD R2, [202H] 0011 10 10 0000 0010
A 0 2 3
00 1000 0001
0 8 1 H
STORE R2, [200H]
0010 10 10 0000 0000
A 0 0 2
00 1000 0010
0 8 2 H
Assembly
Instruction
Machine Instruction
OP REG ADDRESS
0 8 0 H
Memory
Address
MEMORY
wl 2014 5.9
Assembly
Instruction
Data

Memory
Address
MEMORY
Memory Placement (Data)
A = 0 0000 0000 0000 0000
0 0 0 0
10 0000 0000
2 0 0 H
B = 9 10 0000 0001
2 0 1 H
C = 6 10 0000 0010
2 0 2 H
0000 0000 0000 1001
0 0 0 9
0000 0000 0000 0110
0 0 0 6
wl 2014 5.10
ALU
RAM
CPU Organisation: Overview
CPU
Register
file
R
1
..R
N
Program Counter
Instr. Register
I
n
t
e
r
n
a
l

B
u
s
000
001
002
003
3FD
3FE
3FF
Output Reg
Input Reg1
Input Reg2
Instr. Decoder
Control Unit
Address
Bus
Data
Bus
Control
Bus
Memory
1. Fast Memory
CPU
2. Arithmetic/logic
3. Control
wl 2014 5.11
CPU
ALU
RAM
LOAD R2, [201H] R2=Memory[201H]



000
001
002
003
3FD
3FE
3FF
Instr. Decoder
Control Unit
080H

0
8
0
H

080H
080H
0
0

0
1
R2
PC
wl 2014 5.12
CPU
ALU
RAM
LOAD R2, [201H] R2=Memory[201H]



000
001
002
003
3FD
3FE
3FF
Instr. Decoder
Control Unit
080H
080H
0
2
R2
PC + 1
wl 2014 5.13
CPU
ALU
RAM
LOAD R2, [201H] R2=Memory[201H]



000
001
002
003
3FD
3FE
3FF
Instr. Decoder
Control Unit
081H
080H
0
3
R2
PC
wl 2014 5.14
CPU
ALU
RAM
LOAD R2, [201H] R2=Memory[201H]



000
001
3FD
3FE
3FF
Instr. Decoder
Control Unit
081H
080H
0
4
1A01
3A02H
2A00H
0000
0009
0006
080
081
082
200
201
202
R2
PC
1A01H
wl 2014 5.15
CPU
ALU
1A01H
3A02H
2A00H
0000
0009
0006
RAM
LOAD R2, [201H] R2=Memory[201H]



000
001
3FD
3FE
3FF
081H
5
080
081
082
200
201
202
1A01 1A01H

1
A
0
1
H

1A01H
1A01H 1A01H
1, 2, 201H
1, 2, 201H
201H
2
0
1
H

201H
0
0

0
R2
PC
wl 2014 5.16
CPU
ALU
1A01H
3A02H
2A00H
0000
0009
0006
RAM
LOAD R2, [201H] R2=Memory[201H]



000
001
3FD
3FE
3FF
081H
6
080
081
082
200
201
202
0009 0009
0009
1A01H
1, 2, 201H
0
0
0
9

201H
0
201H
0
0009 R2
PC
0009
wl 2014 5.17
CPU
ALU
1A01H
3A02H
2A00H
0000
0009
0006
RAM
ADD R2, [202H] R2=R2+Memory[202H]



000
001
3FD
3FE
3FF
081H
7
080
081
082
200
201
202
081H
0
8
1
H

0009 R2
PC
081H
0
0

0
wl 2014 5.18
CPU
ALU
1A01H
3A02H
2A00H
0000
0009
0006
RAM
ADD R2, [202H] R2=R2+Memory[202H]



000
001
3FD
3FE
3FF
8
080
081
082
200
201
202 081H
081H
0
0009 R2
PC + 1
wl 2014 5.19
CPU
ALU
1A01H
3A02
2A00H
0000
0009
0006
RAM
ADD R2, [202H] R2=R2+Memory[202H]



000
001
3FD
3FE
3FF
9
080
081
082
200
201
202
3A02H
082H
081H
0
0009 R2
PC
3A02H
3
A
0
2
H

3A02H
3A02H 3A02H
3, 2, 202H
3, 2, 202H
202H
2
0
2
H

202H
0
0
3A02H
0009
0
0
0
9

0009
0009
0009
0

wl 2014 5.20
CPU
ALU
1A01
3A02
2A00
0000
0009
0006
RAM
ADD R2, [202H] R2=R2+Memory[202H]



000
001
3FD
3FE
3FF
10
080
081
082
200
201
202
0006
082H
202H
0
0009 R2
PC
0006
0006
3A02H
3, 2, 202H
202H
0 0006
0006
ADD 000FH
000FH
0
0
0
F
H

000FH
000FH
0009
0
0
0
F
H

wl 2014 5.21
CPU
ALU
1A01H
3A02H
2A00H
0000
0009
0006
RAM
STORE R2, [200H] Memory[200H]=R2



000
001
3FD
3FE
3FF
082H
11
080
081
082
200
201
202
082H
0
8
2
H

000FH R2
PC
082H
0
0

0
wl 2014 5.22
CPU
ALU
1A01H
3A02H
2A00H
0000
0009
0006
RAM


000
001
3FD
3FE
3FF
12
080
081
082
200
201
202 082H
082H
0
000FH R2
PC + 1
STORE R2, [200H] Memory[200H]=R2
wl 2014 5.23
CPU
ALU
1A01H
3A02H
2A00
0000
0009
0006
RAM


000
001
3FD
3FE
3FF
13
080
081
082
200
201
202
2A00H
083H
082H
1
000F R2
PC
000FH
2
A
0
0
H

2A00H
2A00H 2A00H
2, 2, 200H
2, 2, 200H
200H
2
0
0
H

200H
1
1
2A00H
000FH
0
0
0
F
H

000FH
1

STORE R2, [200H] Memory[200H]=R2
wl 2014 5.24
CPU
ALU
1A01H
3A02H
2A00H
0000
0009
0006
RAM


000
001
3FD
3FE
3FF
14
080
081
082
200
201
202 083H
000FH R2
PC
000FH
STORE R2, [200H] Memory[200H]=R2
00FH
200H
1
00FH
200H
1