How To Write A Spi Program

SPI
CPE 311 Embedded System, Computer Engineering

Thai Nichi Institute of Technology
Course work
1
st
-half
o Introduction & LCD
o Design methodology (Agile) & Library
o ADC + Timer
o Block diagram & Temp sensor
o Music box

2
nd
-half
o SPI
o Control system (Op-Amp & SA ADC)
o RTOS
o Summary & Review
o Projects
Computer Engineering, Thai-Nichi Institute of Technology
CPE 213 : Embedded System 1/2557 - Slide 2
SPI - Overview
Overview
o Introduction to SPI
o SPI features in STM32L152RB
o Introduction to Microchip 23K640 SRAM
o Setup and program
Initial SPI mode
Communicate SPI
o Summary

Introduction to SPI
Data transmission
o Transmit data : 10011011

o Parallel
i.e. 8-bit line

o Serial
One line

CPE 213 : Embedded System
1
0
0
1
1
B
0
1
1
A 1 0 0 1 1 0 1 1 B
1/2557 - Slide 4
Introduction to SPI
Data transmission
o Asynchronous

o Synchronous

Clock
A B
Data
A B
Data
1/2557 - Slide 5
Review block diagram
Block diagram

Output Interface Input Interface
Physical
Environments
i.e. Switch,
Temp sensor,
Microphone

G
P
I
O

U
S
A
R
T

S
P
I

A
D
C

I
2
C

U
S
B

G
P
I
O

U
S
A
R
T

S
P
I

D
A
C

I
2
C

U
S
B

Physical
Environments
i.e. LCD,
7-segments
Speaker,
Motor

SYSCFG
Timer
CPU
RCC
Comp+RI
OpAmp
Memory /
DMA
RAM
CRC
WDG
RTC PWR
Processor
Input Output
1/2557 - Slide 6
SPI Peripheral interface
Peripheral interface

i.e.

Switch,
Temp sensor,
Microphone,
7-segments,
Speaker,
Motor
LCD

G
P
I
O

U
S
A
R
T

S
P
I

ADC
I
2
C

U
S
B

CPU CPU
Physical
Environments
DAC
Interface
Standard
Synchronous
Asynchronous
Standard
USB 2.0 BUS
Standard
Serial I
2
C BUS
Processor
1/2557 - Slide 7
Interface
o Input Output ports
General-purpose I/Os (GPIO)
o Specific interface
Serial peripheral interface (SPI)
Universal synchronous asynchronous receiver
transmitter (USART)
Universal serial bus full-speed device interface
(USB)
Inter-integrated circuit (I
2
C) interface

SPI - Overview
Overview
o Setup and program
Initial SPI mode
Communicate SPI
o Summary

o Serial communication with external devices
o Synchronous communication
o Half / Full duplex communication
Master configuration
Slave configuration
Can be multimaster
configuration
o Possible to switch to
I
2
S audio protocol by
software

SPI features
SPI features in STM32L152RB
o Full-duplex synchronous 3 lines
o Simplex synchronous 2 lines
o 8- or 16- bit frame format
o 8 master baud rate prescalers (f
PCLK
/2 max.)
o Slave frequency (f
PCLK
/2 max)
o NSS management by hardware or software
o Programmable data order MSB-first or LSB-first
o Hardware CRC feature
CRC in last byte in Tx mode
Automatic CRC error checking for last Rx byte
o 1-byte Tx and Rx buffer with DMA
SPI Block diagram

SPI 4 pins
SPI is connected through 4 pins
o MISO: Master In / Slave Out data
o MOSI: Master Out / Slave In data
o SCK: Serial Clock
output for
SPI masters and
input for
SPI slaves
o NSS: Slave select.
This pin acts as a
chip select
SPI Interconnections
A basic example of interconnections between a single master and a single slave
How to use SPI inside STM32L152
Initialization
1) Select Baud Rate in SPI_CR1 Register.
2) Select Clock Polarity (CPOL) and Clock Phase
(CPHA) in SPI_CR1 Register.
3) Set Data Frame Format(DFF) bit to use either 8
bit or 16 bit transmission.
4) Set to sent MSB/LSB First using LSBFIRST bit
in SPI_CR1 Register.
5) Using GPIO as SS pin.
6) Set SPE and MSTR bit.

SPI Transmission
Transmit data
1) Wait until TXE bit = 1
2) Write data to SPI_DR register

Receive data
1) Wait until RXNE bit = 1
2) Read data in SPI_DR register

SPI - Overview
Overview
o Setup and program
Initialize SPI
Data transmission by SPI
o Summary

Static RAM Integrated Circuit (23K640)
Microchip 23K640 SRAM
o 64K SPI Bus Low-Power Serial SRAM
Package type

Pin function table
1/2557 - Slide 18
23K640 SPI Timing
Serial Input Timing
1/2557 - Slide 19
23K640 SPI Timing
Serial Output Timing
1/2557 - Slide 20
23K640 Data frame format
Byte Read Sequence
1/2557 - Slide 21
Byte Write Sequence
1/2557 - Slide 22
Read STATUS Register Sequence
1/2557 - Slide 23
SPI - Overview
Overview
o Setup and program
Initialize SPI
o Summary

Design hardware
Design
o Design Hardware

Design pins in 23K640 SRAM
SS
MISO
MOSI
SCLK
1/2557 - Slide 25
Design hardware
Design
Design pins in STM32L152 controller
1/2557 - Slide 26
Design Hardware
Design
1/2557 - Slide 27
Design software
Design
o Design Software (Top-down design)

Start
Initial
main
End
Enable
Clocks &
GPIOs
Initial SPI
Initialization
1) Select PINs
2) Set CLOCKs
3) Set Mode for
GPIOs
4) Set Speed for
GPIOs
1/2557 - Slide 28
Design software
Design

Start
Initial
main
End
Enable
Clocks &
GPIOs
Initial SPI
SPI Initialization
1) Select Baud Rate in SPI_CR1
Register.
2) Select Clock Polarity (CPOL)
and Clock Phase (CPHA) in
SPI_CR1 Register.
3) Set Data Frame Format(DFF)
bit to use either 8 bit or 16
bit transmission.
4) Set to sent MSB/LSB First
using LSBFIRST bit in SPI_CR1
Register.
1/2557 - Slide 29
Design software
Design

Start
main
End
Initial
Read
data
Write data
1) Enable CS
2) Write write
command
3) Write address
4) Write data
5) Disable CS
1/2557 - Slide 30
Write
data
Design software
Design

Start
main
End
Initial
Read
data
Read data
1) Enable CS
2) Write read
command
3) Write address
4) Read data
5) Disable CS
1/2557 - Slide 31
Write
data
Design software
Design

Read data
1) Enable CS
2) Write read
command
3) Write
address
4) Read data
5) Disable CS
Wait until TXE
bit = 1?
Write data to
SPI_DR register
Yes
No
Transmit data
Design software
Design

Read data
1) Enable CS
2) Write read
command
3) Write
address
4) Read data
5) Disable CS
Wait until RXNE
bit = 1?
Read data in
SPI_DR register
Yes
No
Transmit data
SPI - Overview
Overview
o Setup and program
Initialize SPI
o Summary

SPI Peripheral interface

i.e.

Switch,
Temp sensor,
Microphone,
7-segments,
Speaker,
Motor
LCD

G
P
I
O

U
S
A
R
T

S
P
I

ADC
I
2
C

U
S
B

CPU CPU
Physical
Environments
DAC
Interface
Standard
Synchronous
Asynchronous
Standard
USB 2.0 BUS
Standard
Serial I
2
C BUS
Processor
1/2557 - Slide 35
HOMEWORK
SPI - Homework
Homework

o Write code for the following requirements (use library)
o Enable SSOE output to 'master mode'
Set baud rate (BR[2:0]) to 4 MHz' (f
CLK
/2)
Set clock phase (CPHA) for 'first clock transition'
Set clock polarity (CPOL) for 'CK to 0 when idle'
Set data frame format (DFF) in '8 bit'
Set data transition in '2 line' (BIDIMODE) both
MISO & MOSI
Set 'MSB' transmit first
Set Master/Slave configuration (MSTR) to
'master'
o Enable SPI (SPE)

LAB
Design hardware
Design
o Design Hardware

Design pins in 23K640 SRAM
SS
MISO
MOSI
SCLK
1/2557 - Slide 39
Design Hardware
Design
1/2557 - Slide 40
Design software
Design
o Design Software (Bottom-up design)

Initialization
1) Select PINs
1) Set CLOCKs
2) Set Mode for
GPIOs
3) Set Speed for
GPIOs
Enable
Clocks &
GPIOs
Initial SPI
1/2557 - Slide 41
Start
Initial
main
End
Design software
Design

SPI Initialization
1) Select Baud Rate in SPI_CR1
Register.
2) Select Clock Polarity (CPOL)
and Clock Phase (CPHA) in
SPI_CR1 Register.
3) Set Data Frame Format(DFF)
bit to use either 8 bit or 16
bit transmission.
4) Set to sent MSB/LSB First
using LSBFIRST bit in SPI_CR1
Register.
Enable
Clocks &
GPIOs
Initial SPI
1/2557 - Slide 42
Start
Initial
main
End
Design software
Design

Wait until TXE
bit = 1?
Write data to
SPI_DR register
Yes
No
Read data
1) Enable CS
2) Write read
command
3) Write
address
4) Read data
5) Disable CS
1/2557 - Slide 43
Transmit data
Design

Receive data
Design software
Wait until RXNE
bit = 1?
Read data in
SPI_DR register
Yes
No
Read data
1) Enable CS
2) Write read
command
3) Write
address
4) Read data
5) Disable CS
1/2557 - Slide 44
Design software
Design

Start
main
End
Initial
Read
data
1/2557 - Slide 45
Write
data
References
References
o SPI registers
o STM32L1xx Library
o SPI NSS, CPHA, CPOL setting & timing
diagrams
Reference SPI registers
SPI registers
o SPI control register1 (SPI_CR1)

o SPI control register2 (SPI_CR2)

Reference SPI registers
SPI registers
o SPI status register (SPI_SR)

o SPI data register (SPI_DR)

Reference Library
Library

SPI Slave select (NSS) pin
Slave select (NSS) pin management
o Set by using SSM bit in SPI_CR1 register
Software NSS management (SSM = 1)
Slave select is driven internally by SSI bit in SPI_CR1
Hardware NSS management (SSM = 0)
Configure with NSS output configuration (SSOE bit in SPI_CR1)
Clock phase and clock polarity
o Clock phase (CPHA) bit in SPI_CR1 register
CPHA=1, 2
nd
edge on SCK is MSBit capture strobe
CPHA=0, 1
st
edge on SCK in MSBit capture strobe
o Clock polarity (CPOL) bit in SPI_CR1 register
CPOL=1, SCK has high-level idle state
CPOL=0, SCK has low-level idle state
SPI NSS, CPHA, CPOL
Data clock timing diagram
o CPHA = 1
1/2557 - Slide 51
SPI NSS, CPHA, CPOL
Data clock timing diagram
o CPHA = 0
1/2557 - Slide 52

How To Write A Spi Program

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CPE 311 Embedded System, Computer Engineering

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