Dell n5010 - Wistron Berry Amd Discrete Uma - Rev A00

5
Berry Discrete/UMA Schematics Document

D
AMD Danube CPU S1g4

AMD GPU Madison-LP/M96-LP M2
RS880M + SB820M
2010-03-08
REV : A00
<Core Design>
Size
A4
Document Number
Rev
Sheet
ai
Berry AMD Discrete/UMA
Date: Monday, March 08, 2010

5
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Cover Page
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Title
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21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
om
Wistron Corporation
A00
95
CHARGER
BQ24745
INPUTS
4
85,86,87,88
M96-M2 LP
DDR III 1333
35W Max
DDR III 1333

8,9,10,11
SYSTEM DC/DC
RT8205B
INPUTS
DDRIII DIMM2
800/1066/1333 19
IN
OUT
HyperTransport
16X16
PCIe x 16
80,81,82,83
North Bridge
SIDE-PORT
OUTPUTS
+3.3V_RTC_LDO
+5V_ALW
+3.3V_ALW
CPU VDDR
RJ45
CONN
VRAM
64Mx16bx1 (1GB)
RT9025
INPUTS
48
OUTPUTS
+1.5V_SUS
+CPU_VDDR
CPU CORE
14
ISL6265AHRTZ-T-GP 47
INPUTS
OUTPUTS
CPU I/F
HDMI(Share PCIe x 4)
AMD RS880M
57
46
+PWR_SRC
DDR3
800MHz
AMD Graphic
AMD Champlain
CPU S1G4
+PWR_SRC
+VCHGR
DDRIII DIMM1
800/1066/1333 18
28,
45
OUTPUTS
+DC_IN_SS
VRAM
64Mx16bx8 (1GB)
HDMI
Berry DG15 Discrete/UMA Block Diagram
Project code :91.4HH01.001

PCB P/N
:
Revision
:X-Build
10/100 NIC
PCIE x 1
LVDS, CRT I/F
Realtek RTL8103T
INTEGRATED GRAHPICS
+VCC_CORE
+VDDNB
+PWR_SRC
AMD RS880M CORE

12,13,14,15
USB 2.0 x 1
54
A-LINK
4X4
USB x 2
OUTPUTS
+PWR_SRC
+NB_VDDC
AMD SB820M S5 POWER
SATA x 1
South Bridge
RGB CRT
E-SATA/USB
COMBO
RT9025
INPUTS
OUTPUTS
+3.3V_ALW
+1.1V_ALW
PCIE x 2& USB 2.0 x 2
14 USB 2.0 ports
OUTPUTS
+PWR_SRC
+1.5V_SUS
WLAN&WWAN
76
High Definition Audio
CardReader
Realtek
RTS5159
6 SATA ports
Card Reader
Connector
USB2.0
78
49
DDR III SUS&VTT
2 PCIE GPP
USB 2.0 x 1
USB 2.0
ACPI 1.1
RT8207
INPUTS
Camera Conn
54
(LVDS & Camera Conn.)
49
+PWR_SRC
LPC I/F
+0.75V_DDR_VTT
USB 2.0 x 1
RT8208B
INPUTS
Bluetooth Conn
LPC Bus
73
20,21,22,23,24
89
OUTPUTS
+PWR_SRC
IDT 92HD79B1
30
HDD
ODD
NPCE781BA0DX
Flash ROM
2MB
62
59
Touch
PAD
68
Int.
KB
37
Thermal
<Core Design>
Wistron Corporation
EMC2102
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

2539
68
Title
Fan
Size
58
A3
Date:
Block Diagram
Document Number

Thursday, March 04, 2010
Sheet
1
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x
2CH SPEAKER
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59
NUVOTON
SPI
Top
VCC
Signal
Signal
GND
Bottom
l.c
AZALIA
SATA
HP1
Azalia
CODEC
&
OP AMP
L1:
L2:
L3:
L4:
L5:
L6:
KBC
SATA
+VGA_CORE
PCB LAYER
SD/SDIO/MMC
MS/MS Pro/xD
MIC IN
AMD GPU CORE
PCI/PCI BRIDGE
Internal Analog MIC
OUTPUTS
ai
48
RT8207
INPUTS
MiniCard x 2
ETHERNET (10/100/1000Mb)
77
DDR III SUS&VTT
AMD SB820M
USB2.0 x 2
50
om
CRT Board
Connector
CRT
RT8209
INPUTS
USB x 1
I/O Board
Connector
LVDS(Dual Channel)
LCD Conn
(LVDS & Camera Conn.)
of
Rev
A00
95
Power Shape
Regulator
Power Block Diagram
LDO
Switch
+PWR_SRC
Adapter
ISL6265AHRTZ
RT8208B
RT8209EGQW
+VGA_CORE
+1.1V_RUN
RT8207
AO4407A
Charger
+VCC_CORE
BQ24745
+VDDNB(CPU)
+1.5V_SUS
+VCHGR
Battery
AO4468
RT8205B
AO4468
APL5930
RT9025
+3.3V_RTC_LDO
+5V_ALW
+1.5V_RUN
+3.3V_ALW
UP7534
AO4468
UP7534
AO4468
PA102FMG
+5V_USB1
+5V_RUN
+5V_USB2
+3.3V_RUN
+3.3V_LAN
VDDR(CPU)
+1.5V_RUN_VGA +1.0V_RUN_VGA
APL5930
+1.8V_RUN
APL5930
RT9025
+1.8V_RUN_VGA
+1.1V_ALW
RESISTER
RESISTER
SI2301BDS
+PVDD
+AVDD
+3.3V_RUN_VGA
G5285T11U
+LCDVDD
RTS5159
RT9013-25PB
+3.3V_RUN_CARD
+2.5V_RUN
RTL8103T
+1.2V_LOM
<Core Design>
om
Wistron Corporation
Date:
A
Power Block Diagram

Document Number
Rev

Sheet
E
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KBC SMBus Block Diagram
SB820M SMBus Block Diagram

D
+5V_RUN
+3.3V_RUN
CLK GEN
SB_SMBCLK
SB_SMBDATA
SCL
SDA
SRN10KJ-5-GP
SRN2K2J
TouchPad Conn.
SMBus Address:0xD2
SB820M
SCL0
SDA0
SB_SMBCLK
SB_SMBDATA
SMB_CLK
SDA1
SMB_DATA
TPDATA
TPDATA
TPDATA
PSCLK1
TPCLK
TPCLK
TPCLK
DIMM 1
SB_SMBCLK_R
SB_SMBDATA_R
SCL1
PSDAT1
+3.3V_ALW
+KBC_PWR
SCL
C
SDA
SMBus address:
SMBus Address:0xA0,0x30
SRN4K7J-8-GP
SCL3_LV/IMC_GPIO13
CPU_SIC
SDA3_LV/IMC_GPIO14
CPU_SID
DIMM 2
SRN10KJ-5-GP
SB_SMBCLK
SB_SMBDATA
Battery Conn.
SRN100J-3-GP
SCL
SDA
SCL1 BAT_SCL
PBAT_SMBCLK1
CLK_SMB
SDA1 BAT_SDA
PBAT_SMBDAT1
DAT_SMB
SMBus Address:0xA4,0x34
SB_SMBCLK
SB_SMBDATA
BQ24745RHDR
WWAN
MINI CARD
KBC
NPCE781
SMB_CLK
SMB_DATA
SCL
SDA
SMBus address:0x12
+3.3V_RUN
SMBus address:
WLAN
MINI CARD
SB_SMBCLK
SMB_CLK
SB_SMBDATA
SMB_DATA
+3.3V_ALW
+3.3V_RUN
SRN4K7J-8-GP
Thermal
THERM_SCL
SRN4K7J-8-GP
+1.5V_SUS
THERM_SDA
SMBus address:
SCL
SDA
SMBus address:0x7A
CPU S1G4
SRN1KJ-7-GP
CPU_SIC
CPU_SID
GPIO61/SCL2
KBC_SCL1
GPIO62/SDA2
KBC_SDA1
2N7002SPT
SIC
SID
SMBus address:
om
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<Core Design>
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Wistron Corporation
Document Number
Rev
ai
Date:
5
SMBUS BLOCK DIAGRAM

Sheet

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Thermal Block Diagram
Audio Block Diagram
SPKR_PORT_D_L+
AUD_SPK_L+
SPKR_PORT_D_L-
AUD_SPK_L-
SPKR_PORT_D_R-
AUD_SPK_R-
SPKR_PORT_D_R+
AUD_SPK_R+
SPEAKER
60
CPU
DP1
H_THERMDA
60D4R2F
THERMDA
HP1_PORT_B_L
AUD_HP1_JACK_L
Bead
AUD_HP1_JACK_L1
HP1_PORT_B_R
AUD_HP1_JACK_R
Bead
AUD_HP1_JACK_R1
SC470P50V3JN-2GP
DN1
HP
OUT
60D4R2F
H_THERMDC
THERMDC
Codec
92HD79B1
Thermal
EMC2102
60
GPU
VGA_THERMDA
DPLUS
VREFOUT_A_OR_F
AUD_VREFOUT_B
DN2
VGA_THERMDC
4K7R2J-2-GP
SC470P50V3JN-2GP
DMINUS
HP0_PORT_A_L
AUD_EXT_MIC_L
HP0_PORT_A_R
AUD_EXT_MIC_R
4K7R2J-2-GP
DP2
MIC
IN
60
PMBS3904
SC1U10V3KX-3GP
DP3
EMC2102_DP3
AUD_INT_MIC_R_L
PMBS3904
INT_MIC_L_R
PORT_C_L
SC470P50V3JN-2GP
DN3
EMC2102_DN3
PORT_C_R
System sensor, put

between CPU and NB.
AUD_INT_MIC_R_L
Internal
MIC
VREFOUT_C
AUD_VREFOUT_C
60
4K7R2J-2-GP
30
<Core Design>
om
Wistron Corporation
Date:
5
THERMAL/AUDIO BLOCK DIAGRAM

Document Number
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Capture from 45484 Rev. 1.02 AMD SB8xx-Series Southbridge Design Guide
LPCCLK0
Strap Name
ECEnableStrap
Schematic Note
DAC_VSYNC
0 V Disabled
3.3 V - Enabled
Strap Function
STRAP_DEBUG_BUS_GPIO
_ENABLE#
EC_PWM3
EC_PWM2
ROMTYPE_1
ROMTYPE_0
ROM TYPE
3.3V
0V
SPI ROM
3.3V
3.3V
{ROMTYPE_1,
ROMTYPE_0 }
0V
0V
0V
3.3V
Reserved
LPCCLK1
DAC_HSYNC
SIDE_PORT_EN#
SUS_STAT#
LOAD_EEPROM_STRAPS#
External clock mode: Use 100-MHz PCIeR

clock as reference clock and generate i
nternal clocks only.
0V
Schematic Note
Enables debug bus access
through memory I/O pads and GPIOs.
0: Enable
* 1: Disable
Indicates if memory side-port is available or not

0: Available(UMA)
1: Not available(Discrete)
Firmware Hub
LPC ROM
(supports both LPC and PMC ROM types)
Defines clock generator

CLKGEN
Capture from 46113_rs880m_ds_nda_1.03

Name
Embedded Controller (EC)
RS880M Strapping
SB820M Strapping
Name
Selects loading of strap values from EEPROM.

0: I2C master can load strap values from EEPROM if
connected, or use default values if EEPROM is not
connected. Please refer to RS880M's reference
schematics for system level implementation details.
1:
Use default values
*
3.3V Integrated clock mode: Use 25-MHz crystal
clock and generate both internal and external clocks
Set PCIe to Gen II mode

PCICLK1
BIF_GEN2_
COMPLIANCE_Strap
0V Force PCIe interface at Gen I mode

3.3V- PCIe interfacce is at Gen II mode
Not Applicable to SB820M but provision for

pull-down is required.
USB Table
Watchdog function
PCICLK2
BootFailTmrEn
0V Disable the boot fail timer function

3.3V- Enable the boot fail timer function
Default Debug Straps
PCICLK3
DefaultStrapMode
0V
3.3V
Disable Debug Straps.

Select external Debug Straps
CPU/NB HT Clock Selection

PCICLK4
CPUClkSel
0V
3.3V
Reserved.
Required setting for integrated clock mode.
This strap is not used if the strap CLKGEN is
configured for external clock generator mode.
Slow down core clock for low power platform.

AZ_SDOUT
CoreSpeedMode
0V
3.3V-
PCIE Routing
USB
Pair
RS880M
Device
USB0 (I/O Board/ESATA)
USB1 (I/O Board)
USB2 (CRT Board)
USB3 (CRT Board)
WLAN USB
WWAN USB
RESERVED
RESERVED
RESERVED
BLUETOOTH
10
CARD READER
11
CAMERA (LVDS CONN)
12
RESERVED
13
RESERVED
LANE0
MiniCard WLAN
LANE1
LAN
LANE2
MiniCard WWAN
Performance mode
Low Power mode
<Core Design>
Wistron Corporation
Title
Size
A2
Date:
5
Table of Content
Document Number
Rev

Sheet

1
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A00
95
C709
C708
SCD1U10V2KX-5GP
2
1
C707
SCD1U10V2KX-5GP
2
1
C706
SCD1U10V2KX-5GP
2
1
C705
SCD1U10V2KX-5GP
2
1
1119-3
D
C717
FS0
SB_14M_CLK
FS2
HTT0T_LPRS/66M
HTT0C_LPRS/66M
USB_48M_CLK (21)
SB820M_USB(48MHz)
1
2
1
2
1116-9
DY
R715 1
33
GND
65
0225-2
0105-3
10
18
GNDSB_SRC
DY DY
+3.3V_RUN
For EMI
2 158R2F-GP
0105-1
NB_14M_CLK (13)
SB_14M_CLK (21)
NB OSCIN(14MHz)
SB OSCIN(14MHz)
54
53
CPU_CLK(200MHz)
DY
2
37
36
32
31
22R2J-2-GP
CPU_CLK
CPU_CLK#
CPU_CLK (10)
CPU_CLK# (10)
R712
NB_GPPSB_CLK_R
NB_GPPSB_CLK#_R
SB_PCIE_CLK_R
SB_PCIE_CLK#_R
43
24
7
52
60
46
1
4
3
SRN10KJ-5-GP
10R4P2R-PAD
4
2
3
RN708
R710 1
2
1
1
59
58
57
W LAN_CLK_REQ# 1
W W AN_CLK_REQ# 2
2
2
48M_CLK
SRC0T_LPRS
SRC0C_LPRS
48MHZ_0
SRC1T_LPRS
SRC1C_LPRS
SRC2T_LPRS
REF0/SEL_HTT66
SRC2C_LPRS
REF1/SEL_SATA
SRC3T_LPRS
REF2/SEL_27
SRC3C_LPRS
SRC4T_LPRS
SRC4C_LPRS
SRC6T/SATAT_LPRS
GNDSATA
SRC6C/SATAC_LPRS
GNDATIG
SRC7T_LPRS/27MHZ_SS
GND
SRC7C_LPRS/27MHZ_NS
GNDHTT
GNDREF
GNDCPU
SB_SRC0T_LPRS
GND48
SB_SRC0C_LPRS
SB_SRC1T_LPRS
GNDSRC
SB_SRC1C_LPRS
GNDSRC
+3.3V_RUN
RN711
W LAN_CLK_REQ# (76)
W W AN_CLK_REQ# (76)
64
22
21
20
19
15
14
13
12
9
8
42
41
6
5
Need External PU Resistor
CPU_HT_CLK
CPU_HT_CLK#
9/23
50
49
VGA(100MHz)
NB_GFX_CLK (13)
NB_GFX_CLK# (13)
CPUKG0T_LPRS
CPUKG0C_LPRS
W LAN_CLK_REQ#
W W AN_CLK_REQ#
TP_CLKREQ3#
TP_CLKREQ4#
10R4P2R-PAD
4
2
3
RN707
2
SC47P50V2JN-3GP
2
SC47P50V2JN-3GP
SC10P50V2JN-4GP
EC705
23
45
44
39
38
CLK_PCIE_VGA (80)
CLK_PCIE_VGA# (80)
1
C722 1
C723
R717
RN
SB(100MHz)
CLKREQ0#
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#
R_NB_GPP_CLK
R_NB_GPP_CLK#
CLK_MINI1_R
CLK_MINI1#_R
CLK_SRC2
CLK_SRC2#
LAN_CLK_R
LAN_CLK#_R
TP_CLK_SRC4
TP_CLK_SRC4#
TP_CLK_SRC6
TP_CLK_SRC6#
R_VGA_27M_SS_CLK
R_VGA_27M_NSS_CLK
10/5
10/2
TP_CLKREQ0#
RN709
SRN0J-6-GP
4
3
R718
(20) SB_PCIE_CLK
(20) SB_PCIE_CLK#
2RN705
3
1
4
0R4P2R-PAD
PD#
NB_GFX_CLK_R
NB_GFX_CLK_R#
DIS
8K2R2J-3-GP
2RN704
3
1
4
0R4P2R-PAD
1113-2
51
1
2
90D9R2F-1-GP
NB(100MHz)
(13) NB_GPPSB_CLK
(13) NB_GPPSB_CLK#
RN
(82) CLK_VGA_27M_SS
(82) CLK_VGA_27M_NSS
VDDSATA
VDD
VDDHTT
VDDREF
VDD48
GFX_CLKP
GFX_CLKN
8K2R2J-3-GP
R711
DIS
DIS
VGA(27MHz)
40
4
55
56
63
30
29
28
27
SB_SMBCLK_CK
SB_SMBDATA_CK
SB_SMBCLK_R (18,21)
SB_SMBDATA_R (18,21)
8K2R2J-3-GP
2RN703
3
1
4
0R4P2R-PAD
R713 1
2 47R2J-2-GP
R714 1
2 33R2J-2-GP
VDDSB_SRC
VDDSB_SRC_IO
ATIG0T_LPRS
ATIG0C_LPRS
ATIG1T_LPRS
ATIG1C_LPRS
0107-1
SC12P50V2JN-3GP
4 RN712
3 SRN33J-5-GP-U
EC703
(76) CLK_PCIE_LAN
(76) CLK_PCIE_LAN#
10/5
35
34
SMBCLK
SMBDAT
1
2
SC4D7P50V2CN-1GP
LAN(100MHz)
2RN710
3
1
4
0R4P2R-PAD
(76) CLK_PCIE_W W AN
(76) CLK_PCIE_W W AN#
RN
RN
WWAN(100MHz)
2RN702
3
1
4
0R4P2R-PAD
(76) CLK_PCIE_W LAN

(76) CLK_PCIE_W LAN#
VDDSRC
VDDSRC_IO
VDDSRC_IO
SB_SMBCLK_CK
SB_SMBDATA_CK
EC704
SC10P50V2JN-4GP
WLAN(100MHz)
16
17
11
2
3
RN
CLKGEN_PD#
VDDCPU
VDDCPU_IO
C719
1
2
0114-2
DY
48
47
CLKGEN_X1
CLKGEN_X2
61
62
0R2J-2-GP
X1
X2
2
2
DY
C721
EC702
SC10P50V2JN-4GP
DY
VDDATIG
VDDATIG_IO
RN
R706
(21,41) SB_PW RGD
R705
SCD1U10V2KX-5GP
2
1
+3.3V_RUN
10KR2J-3-GP
1119-3
9/22
26
25
SC12P50V2JN-3GP
No use
CLKSRC1 WLAN
CLKSRC2 WWAN
CLKSRC3 LAN
No use
X701
1231-1
+3.3V_CLK_VDDIO
+3.3V_CLK_VDDREF
R704
+3.3V_CLK_VDDREF
1 R701
2
0R0603-PAD
U701
C718
1
2
C716
SCD1U10V2KX-5GP
2
1
C715
SCD1U10V2KX-5GP
2
1
C714
SCD1U10V2KX-5GP
2
1
C713
SCD1U10V2KX-5GP
2
1
10/1
+3.3V_CLK_VDD
+3.3V_RUN
CLKREQ0#
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#
1119-3
X-14D31818M-37GP
C712
SCD1U10V2KX-5GP
2
1
1
2
DY
9/22
CLKREQ# MAP
1MR2J-L2-GP
SC10U6D3V5KX-1GP
1231-1
+3.3V_CLK_VDDIO
1 R703
2
0R0603-PAD
C710
SCD1U10V2KX-5GP
2
1
+3.3V_RUN
C704
SCD1U10V2KX-5GP
2
1
9/22
+3.3V_CLK_VDD (40 mils)

C703
SCD1U10V2KX-5GP
2
1
SC10U6D3V5KX-1GP
1231-1
C701
SCD1U10V2KX-5GP
2
1
+3.3V_CLK_VDD
1 R702
2
0R0603-PAD
+3.3V_RUN
RN
(13) CLK_NBHT_CLK
(13) CLK_NBHT_CLK#
2RN706
3
1
4
0R4P2R-PAD
TP701
TP702
TP703
TP704
TP705
TP706
TP707
TP709
TP708
1
1
1
1
1
1
1
1
1
TP_CLK_SRC6
TP_CLK_SRC6#
TP_CLKREQ0#
TP_CLKREQ3#
TP_CLKREQ4#
TP_CLK_SRC4
TP_CLK_SRC4#
R_NB_GPP_CLK
R_NB_GPP_CLK#
Place together
ICS9LPRS480BKLFT-GP
71.09480.A03
1st
2nd
RN
10/1
CLK_NBHT_CLK_R
CLK_NBHT_CLK#_R
71.09480.A03
71.08628.003
NB ALINK
(100MHz)
SB PCIE
(100MHz)
VGA Madison
(27MHz)
SEL_HTT66
FS0
66 MHz 3.3V single ended HTT clock
0*
100 MHz differential HTT clock
SEL_SATA
FS1
1*
100 MHz non-spreading differential SRC clock
0
SEL_27MHz
FS2
1*
100 MHz spreading differential SRC clock

27MHz non-spreading singled clock on pin 5
and 27MHz spread clock on pin 6
100MHz differential spreading SRC clock
<Core Design>
Wistron Corporation

Title
* default
Size
A3
Date:
5
Clock Generator ICS9LPRS480

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Rev

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1
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1 OF 6
CPU1A
1
2
1
2
1
2
1
2
1
2
C807
DY
SC180P50V2JN-1GP
C806
1.1V(1.5A) for VLDT

SC180P50V2JN-1GP
1119-3
C805
SCD22U10V2KX-1GP
SKT-BGA638H176
1'nd 62.10055.111
2'nd 62.10055.171
C804
DY
SCD22U10V2KX-1GP
C803
SC4D7U6D3V3KX-GP
C802
DY
Place close to socket

SC4D7U6D3V3KX-GP
C801
SC22U6D3V5MX-2GP
+1.1V_RUN
SSID = CPU
D1
D2
D3
D4
VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3
DANUBE
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
AE2
AE3
AE4
AE5
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
HT_CPU_NB_CAD_H0 (12)
HT_CPU_NB_CAD_L0 (12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7
HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
(12)
(12)
(12)
(12)
HT_NB_CPU_CLK_H0
HT_NB_CPU_CLK_L0
HT_NB_CPU_CLK_H1
HT_NB_CPU_CLK_L1
J3
J2
J5
K5
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
Y1
W1
Y4
Y3
HT_CPU_NB_CLK_H0
HT_CPU_NB_CLK_L0
HT_CPU_NB_CLK_H1
HT_CPU_NB_CLK_L1
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
HT_NB_CPU_CTL_H0
HT_NB_CPU_CTL_L0
HT_NB_CPU_CTL_H1
HT_NB_CPU_CTL_L1
N1
P1
P3
P4
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
R2
R3
T5
R5
HT_CPU_NB_CTL_H0
HT_CPU_NB_CTL_L0
HT_CPU_NB_CTL_H1
HT_CPU_NB_CTL_L1
(12)
(12)
(12)
(12)
<Core Design>
Wistron Corporation

Title
CPU_HT_LINK I/F_(1/4)
Document Number
Size
A4
Date: Thursday, March 04, 2010

5
Rev

2
Sheet
of
1
A00
95
SSID = CPU
3 OF 6
4.7UF*4
0.22UF*4
1000PF*4
180PF*4
1231-2
Set empty: C905,C906,C903,C909,C913,C910,C915
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1231-2
0.9V, 1.25A--DDR1066
1.05V, 1.75A---DDR1333
(18) MEM_MA_CKE0
(18) MEM_MA_CKE1
J22
J20
N19
N20
E16
F16
Y16
AA16
P19
P20
(18) MEM_MA_CLK0_P
(18) MEM_MA_CLK0_N
(18) MEM_MA_CLK1_P
(18) MEM_MA_CLK1_N
(18) MEM_MA_ADD[0..15]
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
MA0_CS#0
MA0_CS#1
MA1_CS#0
MA1_CS#1
MB0_CS#0
MB0_CS#1
MB1_CS#0
V26
W25
U22
MEM_MB0_CS#0 (19)
MEM_MB0_CS#1 (19)
MA_CKE0
MA_CKE1
MB_CKE0
MB_CKE1
J25
H26
MEM_MB_CKE0 (19)
MEM_MB_CKE1 (19)
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
P22
R22
A17
A18
AF18
AF17
R26
R25
MEM_MB_CLK0_P (19)
MEM_MB_CLK0_N (19)
MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15
(19)
1
2
DANUBE
MEM_MB0_ODT0 (19)
MEM_MB0_ODT1 (19)
T20
U19
U20
V20
DDR3_B_DRAMRST#
W26
W23
Y26
(18) MEM_MA0_CS#0
(18) MEM_MA0_CS#1
B18
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB_RESET#
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
DY
SC10U6D3V3MX-GP
2
1
T19
V22
U21
V19
TP901
W17
1117-8
Remove
R905
(18) MEM_MA0_ODT0
(18) MEM_MA0_ODT1
MEMVREF
C920
MA_RESET#
+0.75V_SUS_CPU_M_VREF
Y10 TP_CPU_VDDR_SENSE
1KR3F-GP
H16
VDDR_SENSE
R902
MEMZP
MEMZN
(18) DDR3_A_DRAMRST#
AF10
AE10
W10
AC10
AB10
AA10
A10
C918
MEMZP
MEMZN
VDDR
VDDR
VDDR
VDDR
VDDR
C919
SC1000P50V3JN-GP-U
C917
2 39D2R2F-L-GP
2 39D2R2F-L-GP
VDDR
VDDR
VDDR
VDDR
1KR3F-GP
R901 1
R903 1
D10
C10
B10
AD10
1119-3
SCD1U10V2KX-5GPSCD1U10V2KX-5GP
+1.5V_SUS
+1.5V_SUS
2 OF 6
CPU1B
+CPU_VDDR
1
2
1
2
1
2
1
2
C912
C916
SC180P50V2JN-1GP
C911
SC180P50V2JN-1GP
C910
DY
SC180P50V2JN-1GP
C909
DY
SC180P50V2JN-1GP
C908
SC1000P50V3JN-GP-U
C915
DY
SC1000P50V3JN-GP-U
C907
SC1000P50V3JN-GP-U
1119-3
C906
DY
SC4D7U6D3V3KX-GP
C905
DY
SCD22U10V2KX-1GP
C914
SCD22U10V2KX-1GP
C904
SCD22U10V2KX-1GP
C913
DY
SCD22U10V2KX-1GP
C903
DY
SC4D7U6D3V3KX-GP
C902
SC4D7U6D3V3KX-GP
C901
Place near to CPU

SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
+CPU_VDDR
1119-1 CLOSE TO CPU
(18) M_A_DM[7..0]
MEM_MB_CLK1_P (19)
MEM_MB_CLK1_N (19)
MEM_MB_ADD[0..15] (19)
N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24
(18) MEM_MA_BANK0
(18) MEM_MA_BANK1
(18) MEM_MA_BANK2
R20
R23
J21
MA_BANK0
MA_BANK1
MA_BANK2
MB_BANK0
MB_BANK1
MB_BANK2
R24
U26
J26
MEM_MB_BANK0 (19)
MEM_MB_BANK1 (19)
MEM_MB_BANK2 (19)
(18) MEM_MA_RAS#
(18) MEM_MA_CAS#
(18) MEM_MA_W E#
R19
T22
T24
MA_RAS#
MA_CAS#
MA_WE#
MB_RAS#
MB_CAS#
MB_WE#
U25
U24
U23
MEM_MB_RAS# (19)
MEM_MB_CAS# (19)
MEM_MB_W E# (19)
(18)
(18)
(18)
(18)
(18)
(18)
(18)
(18)
(18)
(18)
(18)
(18)
(18)
(18)
(18)
(18)
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
E12
C15
E19
F24
AC24
Y19
AB16
Y13
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
M_A_DQS0
M_A_DQS#0
M_A_DQS1
M_A_DQS#1
M_A_DQS2
M_A_DQS#2
M_A_DQS3
M_A_DQS#3
M_A_DQS4
M_A_DQS#4
M_A_DQS5
M_A_DQS#5
M_A_DQS6
M_A_DQS#6
M_A_DQS7
M_A_DQS#7
CPU1C
DANUBE
(18) M_A_DQ[63..0]
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
A12
B16
A22
E25
AB26
AE22
AC16
AD12
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
M_B_DQ[63..0] (19)
M_B_DM[7..0] (19)
B
M_B_DQS0 (19)
M_B_DQS#0 (19)
M_B_DQS1 (19)
M_B_DQS#1 (19)
M_B_DQS2 (19)
M_B_DQS#2 (19)
M_B_DQS3 (19)
M_B_DQS#3 (19)
M_B_DQS4 (19)
M_B_DQS#4 (19)
M_B_DQS5 (19)
M_B_DQS#5 (19)
M_B_DQS6 (19)
M_B_DQS#6 (19)
M_B_DQS7 (19)
M_B_DQS#7 (19)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
CPU_DDR_(2/4)
Document Number
Rev

Sheet
1
of
A00
95
SSID = CPU
1119-1
+2.5V_RUN_VDDA
1
2
Y6
AB6
VDD1_FB_H
VDD1_FB_L
VDDNB_FB_H
VDDNB_FB_L
H6
G6
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
G10
AA9
AC9
AD9
AF9
DBRDY
TMS
TCK
TRST#
TDI
CPU_TEST23
AD7
TEST23
CPU_TEST18
CPU_TEST19
H10
G9
TEST18
TEST19
TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
CPU_TEST9
C2
AA6
TEST9
TEST6
1231-1
A3
A5
B3
B5
C1
RSVD#A3
RSVD#A5
RSVD#B3
RSVD#B5
RSVD#C1
CPU_PROCHOT# (20)
TP1002
S1G4 not support MEMHOT
H_THERMDC (39)
H_THERMDA (39)
TP_CPU_VDDIO_SUS_FB_H
TP_CPU_VDDIO_SUS_FB_L
C
CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L
(47)
(47)
R1015
E10
CPU_DBREQ# 1
TDO
AE9
CPU_TDO
TEST28_H
TEST28_L
J7
H8
TP_CPU_TEST28_H
TP_CPU_TEST28_L
TEST17
TEST16
TEST15
TEST14
D7
E7
F7
C7
TP_CPU_TEST17
TP_CPU_TEST16
TP_CPU_TEST15
TP_CPU_TEST14
TEST7
TEST10
C3
K8
TEST8
C4
TP_CPU_TEST7
CPU_TEST10
1
R1021
TP_CPU_TEST8
TEST29_H
TEST29_L
C9
C8
RSVD#H18
RSVD#H19
RSVD#AA7
RSVD#D5
RSVD#C5
H18
H19
AA7
D5
C5
+1.5V_SUS
300R2J-4-GP
+1.1V_RUN
DY
2
300R3-GP
CPU_TEST29H
CPU_TEST29L
1
R1024
2
80D6R2F-L-GP
LAYOUT: Route FBCLKOUT_H/L

differentially impedance 80
B
HDT Connectors
+1.5V_SUS
CPU_PROCHOT#
CPU_MEMHOT#
DBREQ#
TEST25_H
TEST25_L
AB8
AF7
AE7
AE8
AC8
AF8
4
3
1
2
W9
Y9
0R0402-PAD
1231-1
DANUBE
VDDIO_FB_H
VDDIO_FB_L
CPU_TEST21
CPU_TEST20
CPU_TEST24
CPU_TEST22
CPU_TEST12
CPU_TEST27
CPU_THERMTRIP#
AF6
AC7
AA8
VDD0_FB_H
VDD0_FB_L
E9
E8
1
2
1
2
1
2
1
2
2
1
CPU_SVC (47)
CPU_SVD (47)
W7
W8
R1023
THERMTRIP#
PROCHOT#
MEMHOT#
A6
A4
THERMDC
THERMDA
CPU_TEST25_H
CPU_TEST25_L
1231-1
SVC
SVD
SIC
SID
ALERT#
(47) CPU_VDD1_RUN_FB_H
(47) CPU_VDD1_RUN_FB_L
DYR1022
510R2F-L-GP
AF4
AF5
AE6
RESET#
PWROK
LDTSTOP#
LDTREQ#
F6
E6
1
2
4
3
1
2
B7
A7
F10
C6
SRN1KJ-8-GP
B
CLKIN_H
CLKIN_L
M11
W18
R1007
CPU_TEST20
CPU_TEST21
CPU_TEST24
CPU_TEST22
8
7
6
5
A9
A8
VSS
RSVD#W18
RN1006
SRN1KJ-7-GP
300R2J-4-GP
R1006
R1020
510R2F-L-GP
RN1004
VDDA
VDDA
HT_REF0
HT_REF1
4 SRN1KJ-7-GP CPU_TEST18
CPU_TEST19
3
1
2
3
4
F8
F9
R6
P6
R1019
510R2F-L-GP
DY
CPUCLK_IN
CPUCLK_IN#
2 44D2R2F-GP CPU_HTREF0
2 44D2R2F-GP CPU_HTREF1
+1.5V_SUS
R1018
510R2F-L-GP
9/25 9/14
4 OF 6
CPU1D
CPU_SIC
CPU_SID
CPU_ALERT#
1
1
+1.5V_SUS
1KR2J-1-GP
300R2J-4-GP
CPU_DBRDY
300R2J-4-GP TP_CPU_TEST14
300R2J-4-GP TP_CPU_TEST15
1KR2J-1-GP
CPU_TEST23
1KR2J-1-GP
CPU_TEST12
C1004
1231-2
1129-1
CPU_LDT_REQ#
SCD01U16V2KX-3GP
+1.5V_RUN
RN1002 1
2
EC1001
9/11 S1g4 no support LDTREQ#
R1010
R1011
1225-4
+1.5V_SUS
CPU_R_LDT_PW RGD
CPU_R_LDT_STOP#
CPU_LDT_REQ#
DY
+1.1V_RUN
DY
SC10P50V2JN-4GP
C1008
11/6
Close CPU
C1003
0R2J-2-GP
CPU_R_LDT_RST#
2
0R0402-PAD
CPU_R_LDT_PW RGD
2
0R0402-PAD
CPU_R_LDT_STOP#
2
0R0402-PAD
2 300R2J-4-GP
DY
SC3300P50V3KX-1GP
For HDT DBG
0108-5
C1007
HDT_RST_R#1
SCD1U10V2KX-5GP
R1009
1
R1001
1
R1002
1
R1003
2
2
2
2
2
R1008 1
2169R2F-GP
2SC3900P50V2KX-2GP
2SC3900P50V2KX-2GP
C1005 1
C1006 1
(7) CPU_CLK
(7) CPU_CLK#
1231-1
(13,20) CPU_LDT_STOP#
SCD22U10V2KX-1GP
C1002
CPU_CLK(200MHz)
RN1001
SRN300J-3-GP
DY
DY
DY
11/6
CPU_R_LDT_RST#
(20) CPU_LDT_RST#
SC10U10V5ZY-1GP
10/5
R1013 1
R1014 1
R1016 1
R1017 1
R1025 1
33R, 3A
Cloce To CPU
+1.5V_RUN
(20,42) CPU_LDT_PW RGD
2.5V(250mA) for VDDA
1
2
PBY160808T-330Y-N-GP
C1001
SC180P50V2JN-1GP
L1001
DY
LYAOUT:ROUTE VDDA TRACE APPROX.

50mils WIDE(USE 2X25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.
+2.5V_RUN
R1012 1
1
2
1 2
1
2
1
2
2
1
(21,39) TALERT#
+1.5V_SUS
CPU_ALERT#
(21,37,39,42,82) H_THERMTRIP#
Q1001
PMBS3904-1-GP
CPU_R_LDT_RST#1
R1038
1.5V
CPU_THERMTRIP#
Q1002
PMBS3904-1-GP
3.3V
1
1
R1041
Wistron Corporation

1 2
1
1 2
1 2
HDT_RST_R#
DY 2PMBS3904-1-GP
Q1003
3
(47) CPU_PW RGD_SVID_REG
R1035
2K2R2J-2-GP
Q1004
R1034
DY
HDT_RST#
Q1005
PMBS3904-1-GP
10KR2J-3-GP
CPU_PROCHOT#
SMC-CONN26A-FP
<Core Design>
R1036
2K2R2J-2-GP
DY
6
8
10
12
14
16
18
20
22
24
26
+1.8V_RUN
+1.8V_RUN
R1037
10KR2J-3-GP
+3.3V_RUN
R1039
+1.5V_RUN
2K2R2J-2-GP
R1040
8K2R2J-3-GP
(37) CPU_PROCHOT#_EC
+3.3V_RUN
+3.3V_RUN
2
DY0R2J-2-GP
DY 4
HDT_RST#
For old HDT tool (3.3V level)
1229-1
3
5
7
9
11
13
15
17
19
21
23
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
R1028
CPU_SID
(21) CPU_SID
2K2R2J-2-GP
DY
CPU_SIC
(21) CPU_SIC
+1.5V_RUN
R1027
TP_CPU_VDDIO_SUS_FB_H
TP_CPU_VDDIO_SUS_FB_L
TP_CPU_TEST28_H
TP_CPU_TEST28_L
TP_CPU_TEST17
TP_CPU_TEST16
TP_CPU_TEST15
TP_CPU_TEST14
TP_CPU_TEST8
TP_CPU_TEST7
8K2R2J-3-GP
1
1
1
1
1
1
1
1
1
1
+KBC_PW R
R1033
RN1005
SRN1KJ-7-GP
TP1001
TP1003
TP1004
TP1005
TP1006
TP1007
TP1008
TP1009
TP1010
TP1011
3
4
9/22
R1029
300R2J-4-GP
11/11
11/6
1KR2J-1-GP
CPU_TEST27
R1032
DY
HDT1
+1.5V_SUS
2K2R2J-2-GP
2 1
R1026
1KR2J-1-GP
Title
PMBS3904-1-GP
CPU_R_LDT_PW RGD
2
DY
2
0R2J-2-GP
2
0112-2
Size
A3
Date:
CPU_Control&Debug_(3/4)
Document Number
Rev

Sheet
1
10
of
A00
95
SSID = CPU
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
DANUBE
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1231-2
DY
C1129
0.01UF
0.1UF
0.22UF
4.7UF
180PF
DY
SC4D7U6D3V3KX-GP
C1128
1119-3
DY
SC4D7U6D3V3KX-GP
C1127
DY
SC4D7U6D3V3KX-GP
C1126
DY
SC4D7U6D3V3KX-GP
C1125
C1114
SC10U6D3V5KX-1GP
C1141
DY
SCD22U10V2KX-1GP
C1124
DY
C1121
SCD01U16V2KX-3GP
C1135
SCD1U10V2KX-5GP
C1120
SCD1U10V2KX-5GP
C1134
1119-3
SC180P50V2JN-1GP
C1133
SCD22U10V2KX-1GP
C1132
SCD22U10V2KX-1GP
C1131
SC10U6D3V5KX-1GP
C1130
SC10U6D3V5KX-1GP
1231-2
DY
1119-1
SC10U6D3V5KX-1GP
C1112
Bottom Side Decoupling
+1.5V_SUS
SCD22U10V2KX-1GP
C1123
1.5V(3A) for VDDIO
Place near to CPU

SCD22U10V2KX-1GP
C1122
+1.5V_SUS
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
SCD22U10V2KX-1GP
C1119
1231-2
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
1231-2
22uF *2
10uF *2
0.22uF *1
0.01uF *1
180pF *1
SC180P50V2JN-1GP
C1118
22UF *3
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
DY
1119-3
SC180P50V2JN-1GP
C1117
SC10U6D3V5KX-1GP
C1116
SC10U6D3V5KX-1GP
C1115
DY
K16
M16
P16
T16
V16
SC22U6D3V5MX-2GP
C1111
0.9V(4A) for VDDNB
SC22U6D3V5MX-2GP
C1110
+VDDNB
DY
SCD22U10V2KX-1GP
C1109
22uF *2
10uF *2
0.22uF *1
0.01uF *1
180pF *1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

SCD01U16V2KX-3GP
C1108
1119-3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2
SCD01U16V2KX-3GP
C1107
SC180P50V2JN-1GP
C1106
1231-2
SCD01U16V2KX-3GP
C1102
SCD22U10V2KX-1GP
C1105
SC10U6D3V5KX-1GP
C1104
SC22U6D3V5MX-2GP
C1103
DY
G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11
+VCC_CORE
5 OF 6
CPU1E

SC10U6D3V5KX-1GP
C1101
DANUBE
+VCC_CORE
SC22U6D3V5MX-2GP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
SC22U6D3V5MX-2GP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
(36A) for 35W S1G4 VDD
6 OF 6
CPU1F
AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4
1231-2
*1
*2
*4
*4
*2
9/14
10UF *2
0.22UF *2
180PF *1
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
CPU_Power_(4/4)
Document Number
Rev

Sheet
1
11
of
A00
95
U1A
RS880M : 71.RS880.M05
D
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
H24
H25
L21
L20
HT_NB_CPU_CLK_H0 (8)
HT_NB_CPU_CLK_L0 (8)
HT_NB_CPU_CLK_H1 (8)
HT_NB_CPU_CLK_L1 (8)
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
M24
M25
P19
R18
HT_NB_CPU_CTL_H0
HT_NB_CPU_CTL_L0
HT_NB_CPU_CTL_H1
HT_NB_CPU_CTL_L1
HT_RXCALP
HT_RXCALN
HT_TXCALP
HT_TXCALN
B24
B25
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
HT_CPU_NB_CAD_H4
HT_CPU_NB_CAD_L4
HT_CPU_NB_CAD_H5
HT_CPU_NB_CAD_L5
HT_CPU_NB_CAD_H6
HT_CPU_NB_CAD_L6
HT_CPU_NB_CAD_H7
HT_CPU_NB_CAD_L7
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
HT_CPU_NB_CAD_H8
HT_CPU_NB_CAD_L8
HT_CPU_NB_CAD_H9
HT_CPU_NB_CAD_L9
HT_CPU_NB_CAD_H10
HT_CPU_NB_CAD_L10
HT_CPU_NB_CAD_H11
HT_CPU_NB_CAD_L11
HT_CPU_NB_CAD_H12
HT_CPU_NB_CAD_L12
HT_CPU_NB_CAD_H13
HT_CPU_NB_CAD_L13
HT_CPU_NB_CAD_H14
HT_CPU_NB_CAD_L14
HT_CPU_NB_CAD_H15
HT_CPU_NB_CAD_L15
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
(8)
(8)
(8)
(8)
HT_CPU_NB_CLK_H0
HT_CPU_NB_CLK_L0
HT_CPU_NB_CLK_H1
HT_CPU_NB_CLK_L1
T22
T23
AB23
AA22
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
(8)
(8)
(8)
(8)
HT_CPU_NB_CTL_H0
HT_CPU_NB_CTL_L0
HT_CPU_NB_CTL_H1
HT_CPU_NB_CTL_L1
M22
M23
R21
R20
C23
A24
R1201 1
2 301R2F-GP
HT_RXCALP
HT_RXCALN
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
PART 1 OF 6
HYPER TRANSPORT CPU I/F
SSID = N.B
HT_TXCALP
HT_TXCALN
R1202 1
PCIE_NTX_GRX_P[12..15]
PCIE_NTX_GRX_N[12..15]
PCIE_NRX_GTX_P[0..15]
(8)
(8)
(8)
(8)
PCIE_NRX_GTX_N[0..15]
(57)
(57)
(80)
(80)
(80)
(80)
2 301R2F-GP
RS880M-1-GP
Place < 100mils from pin B25 and B24
9/11
WLAN
LAN
WWAN
A-LINK
(20)
(20)
(20)
(20)
(20)
(20)
(20)
(20)
(76)
(76)
(76)
(76)
(76)
(76)
1119-3
U1B
PCIE_NRX_GTX_P15
PCIE_NRX_GTX_N15
PCIE_NRX_GTX_P14
PCIE_NRX_GTX_N14
PCIE_NRX_GTX_P13
PCIE_NRX_GTX_N13
PCIE_NRX_GTX_P12
PCIE_NRX_GTX_N12
PCIE_NRX_GTX_P11
PCIE_NRX_GTX_N11
PCIE_NRX_GTX_P10
PCIE_NRX_GTX_N10
PCIE_NRX_GTX_P9
PCIE_NRX_GTX_N9
PCIE_NRX_GTX_P8
PCIE_NRX_GTX_N8
PCIE_NRX_GTX_P7
PCIE_NRX_GTX_N7
PCIE_NRX_GTX_P6
PCIE_NRX_GTX_N6
PCIE_NRX_GTX_P5
PCIE_NRX_GTX_N5
PCIE_NRX_GTX_P4
PCIE_NRX_GTX_N4
PCIE_NRX_GTX_P3
PCIE_NRX_GTX_N3
PCIE_NRX_GTX_P2
PCIE_NRX_GTX_N2
PCIE_NRX_GTX_P1
PCIE_NRX_GTX_N1
PCIE_NRX_GTX_P0
PCIE_NRX_GTX_N0
PCIE_RXP0
PCIE_RXN0
PCIE_RXP1
PCIE_RXN1
PCIE_RXP2
PCIE_RXN2
ALINK_NBRX_SBTX_P0
ALINK_NBRX_SBTX_N0
ALINK_NBRX_SBTX_P1
ALINK_NBRX_SBTX_N1
ALINK_NBRX_SBTX_P2
ALINK_NBRX_SBTX_N2
ALINK_NBRX_SBTX_P3
ALINK_NBRX_SBTX_N3
D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
PART 2 OF 6
PCIE I/F GFX
LANE REVERSAL
9/15
PCIE I/F GPP
PCIE I/F SB
RS880M-1-GP
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
PCIE_NTX_GRX_C_P15
PCIE_NTX_GRX_C_N15
PCIE_NTX_GRX_C_P14
PCIE_NTX_GRX_C_N14
PCIE_NTX_GRX_C_P13
PCIE_NTX_GRX_C_N13
PCIE_NTX_GRX_C_P12
PCIE_NTX_GRX_C_N12
PCIE_NTX_GRX_C_P11
PCIE_NTX_GRX_C_N11
PCIE_NTX_GRX_C_P10
PCIE_NTX_GRX_C_N10
PCIE_NTX_GRX_C_P9
PCIE_NTX_GRX_C_N9
PCIE_NTX_GRX_C_P8
PCIE_NTX_GRX_C_N8
PCIE_NTX_GRX_C_P7
PCIE_NTX_GRX_C_N7
PCIE_NTX_GRX_C_P6
PCIE_NTX_GRX_C_N6
PCIE_NTX_GRX_C_P5
PCIE_NTX_GRX_C_N5
PCIE_NTX_GRX_C_P4
PCIE_NTX_GRX_C_N4
PCIE_NTX_GRX_C_P3
PCIE_NTX_GRX_C_N3
PCIE_NTX_GRX_C_P2
PCIE_NTX_GRX_C_N2
PCIE_NTX_GRX_C_P1
PCIE_NTX_GRX_C_N1
PCIE_NTX_GRX_C_P0
PCIE_NTX_GRX_C_N0
C1231 1
C1232 1
C1229 1
C1230 1
C1227 1
C1228 1
C1225 1
C1226 1
C1223 1
C1224 1
C1221 1
C1222 1
C1219 1
C1220 1
C1217 1
C1218 1
C1215 1
C1216 1
C1213 1
C1214 1
C1211 1
C1212 1
C1209 1
C1210 1
C1207 1
C1208 1
C1205 1
C1206 1
C1203 1
C1204 1
C1201 1
C1202 1
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
2 SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
SCD1U10V2KX-5GP
2DIS
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
PCIE_C_TXP0
PCIE_C_TXN0
PCIE_C_TXP1
PCIE_C_TXN1
PCIE_C_TXP2
PCIE_C_TXN2
C1264 1
C1261 1
C1266 1
C1262 1
C1265 1
C1263 1
2
2
2
2
2
2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
ALINK_NBTX_SBRX_C_P0
ALINK_NBTX_SBRX_C_N0
2
2
2
2
2
2
2
2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PCE_CALRP
PCE_CALRN
AC8
AB8
PCE_PCAL
PCE_NCAL
9/15
PCIE_NTX_GRX_P15
PCIE_NTX_GRX_N15
PCIE_NTX_GRX_P14
PCIE_NTX_GRX_N14
PCIE_NTX_GRX_P13
PCIE_NTX_GRX_N13
PCIE_NTX_GRX_P12
PCIE_NTX_GRX_N12
PCIE_NTX_GRX_P11
PCIE_NTX_GRX_N11
PCIE_NTX_GRX_P10
PCIE_NTX_GRX_N10
PCIE_NTX_GRX_P9
PCIE_NTX_GRX_N9
PCIE_NTX_GRX_P8
PCIE_NTX_GRX_N8
PCIE_NTX_GRX_P7
PCIE_NTX_GRX_N7
PCIE_NTX_GRX_P6
PCIE_NTX_GRX_N6
PCIE_NTX_GRX_P5
PCIE_NTX_GRX_N5
PCIE_NTX_GRX_P4
PCIE_NTX_GRX_N4
PCIE_NTX_GRX_P3
PCIE_NTX_GRX_N3
PCIE_NTX_GRX_P2
PCIE_NTX_GRX_N2
PCIE_NTX_GRX_P1
PCIE_NTX_GRX_N1
PCIE_NTX_GRX_P0
PCIE_NTX_GRX_N0
PCIE_TXP0
PCIE_TXN0
PCIE_TXP1
PCIE_TXN1
PCIE_TXP2
PCIE_TXN2
(76)
(76)
(76)
(76)
(76)
(76)
LANE REVERSAL
Place < 100mils from pin C23 and A24
WLAN
LAN
WWAN
9/11
A-LINK
R1203 1
R1204 1
C1237 1
C1238 1
C1239 1
C1240 1
C1241 1
C1242 1
C1243 1
C1244 1
2 1K27R2F-L-GP
2 2KR2F-3-GP
ALINK_NBTX_SBRX_P0
ALINK_NBTX_SBRX_N0
ALINK_NBTX_SBRX_P1
ALINK_NBTX_SBRX_N1
ALINK_NBTX_SBRX_P2
ALINK_NBTX_SBRX_N2
ALINK_NBTX_SBRX_P3
ALINK_NBTX_SBRX_N3
(20)
(20)
(20)
(20)
(20)
(20)
(20)
(20)
<Core Design>
Wistron Corporation

Title
+1.1V_RUN_VDDPCIE
Size
A3
Place < 100mils from pin AC8 and AB8
Date:
5
AMD-RS880M_HT LINK&PCIe(1/4)
Document Number
Rev

Sheet
1
12
of
A00
95
UMA DAC Signal:

GREEN/BLUE: Connected to GND through two separate
150- 1% resistors.
1
1
1NB_GPP_CLK
1NB_GPP_CLK#
1120-6
STRP_DATA
TP1305
R1318
2KR2J-1-GP
1
R1319
B10
TP_NB_RESERVED G11
2 RS780_AUX_CAL
150R2F-1-GP
C8
LVDS_DIGON
LVDS_BLON
LVDS_ENA_BL
E9
F7
G12
UMA
C1309
SC2D2U6D3V3KX-GP
UMA/DIS
NB_LCDPW R_EN (55)

NB_BL_PW M (55)
NB_BL_EN (55)
9/22
4
3
UMA
1
2
1
SRN10KJ-5-GP
I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N
DDC_CLK0/AUX0P
DDC_CLK1/AUX1P
DDC_DATA1/AUX1N
D9
D10
TP_TMDS_HPD
1
HDMI_HPD_DET
SUS_STAT#
D12
NB_SUS_STAT#
THERMALDIODE_P
THERMALDIODE_N
AE8
AD8
TESTMODE
D13
MIS.
TMDS_HPD
HPD
STRP_DATA
RESERVED
TP1308
0225-1
R1317
2
UMA
HDMI_HPD_DET
(57,82)
SUS_STAT# (21)
0R2J-2-GP
TESTMODE_NB
AUX_CAL
+3.3V_RUN
<Core Design>
R1314
4K7R2J-2-GP
Wistron Corporation

NB_ALLOW _LDTSTOP
R1321
3KR2J-2-GP
ALLOW_LDTSTOP:
R1316
0R0402-PAD 1 = LDTSTOP# can be asserted
0 = LDTSTOP# has to be de-asserted
Title
AMD-RS880M_LVDS&CRT_(2/4)
Size
A3
Document Number
DY
Date:
UMA
L1306 1
2
220R, 2A
UMA UMA/DIS
11/6
1
2
2
C14
D15
C16
C18
C20
E20
C22
GPPSB_REFCLKP
GPPSB_REFCLKN
NB_SUS_STAT#
VSSLT1
VSSLT2
VSSLT3
VSSLT4
VSSLT5
VSSLT6
VSSLT7
220R, 0.3A
L1305 1
2
BLM15AG221SS1D-GP
1.8V, 300mA
VDDLT18_R
RN1301
R1315
1KR2J-1-GP
(20) ALLOW _LDTSTOP
A15
B15
A14
B14
+1.8V_RUN
1119-1
1.8V, 15mA
1
2
+1.8V_RUN
VDDLT18_1
VDDLT18_2
VDDLT33_1
VDDLT33_2
(55)
(55)
(55)
(55)
11/12-4
RS880M-1-GP
NB_LDT_STOP#
B9
A9
B8
A8
B7
A7
A13 VDDLTP18_R
B13
R1320
NC7W Z07P6X-1GP
V4
V3
(7) NB_GPPSB_CLK
(7) NB_GPPSB_CLK#
VDDLTP18
VSSLTP18
1K8R2F-GP
6
5
4
1
2
TP1306
TP1307
(55) LDDC_CLK
(55) LDDC_DATA
(57) NB_DDC_DATA0
(57) NB_DDC_CLK0
C1314
Y1
VCC
Y2
GPP_REFCLKP
GPP_REFCLKN
DY
(7) NB_GFX_CLK
(7) NB_GFX_CLK#
10/2
9/15
SCD1U10V2KX-5GP
A1
GND
A2
GFX_REFCLKP
GFX_REFCLKN
U1
U2
10/7
R1311
2K2R2J-2-GP
U1301
1
2
3
(10,20) CPU_LDT_STOP#
2 0R2J-2-GP
DY
T2
T1
NB_GFX_CLK
NB_GFX_CLK#
REFCLK_P/OSCIN
REFCLK_N
C1315
R1322 1
SYSRESET#
POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP
HT_REFCLKP
HT_REFCLKN
9/15
R1309
300R2J-4-GP
D8
A10
C10
C12
E11
F11
R1313
4K7R2F-GP
+1.8V_RUN
VDDA18PCIEPLL1
VDDA18PCIEPLL2
C25
C24
9/25
+1.5V_RUN
2
1
R1341
D7
E7
NB_REFCLK_P
NB_REFCLK_N
(7) NB_14M_CLK
VDDA18HTPLL
2
0R0402-PAD
1
2
1
2
1231-2 1
H17
SCD1U10V2KX-5GP
SC180P50V2JN-1GP
EC1301
R1312
4K7R2F-GP
1119-3
NB_LDT_STOP#
NB_ALLOW _LDTSTOP
SC180P50V2JN-1GP
EC1302
(7) CLK_NBHT_CLK
(7) CLK_NBHT_CLK#
PLLVDD
PLLVDD18
PLLVSS
VGA_TXACLK+
VGA_TXACLKVGA_TXBCLK+
VGA_TXBCLK-
C1313
9/16
DAC_RSET
A12
D14
B12
B16
A16
D16
D17
SC4D7U6D3V3KX-GP
C1310
(20,37,80) PLTRST#_NB_GPU
(41) NB_PW RGD_IN
+1.1V_RUN
G14
TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN
SCD1U10V2KX-5GP
+1.8V_VDDA18PCIEPLL
C1305
C1304
C1301
SC22U6D3V5MX-2GP
0R0603-PAD
+1.8V_VDDA18HTPLL
+1.8V_VDDA18PCIEPLL
SCD1U10V2KX-5GP
SC2D2U6D3V3KX-GP
1 R1343
2 DAC_RSET
715R2F-GP
PLLVDD
PLLVDD18
(55)
(55)
(55)
(55)
(55)
(55)
R1306
DAC_HSYNC
DAC_VSYNC
DAC_SCL
DAC_SDA
VGA_TXBOUT0+
VGA_TXBOUT0VGA_TXBOUT1+
VGA_TXBOUT2-
Trace at least 10 mil
10/8
A11
B11
F8
E8
B18
A18
A17
B17
D20
D21
D18
D19
150R2F-1-GP
VGA_HSYNC
VGA_VSYNC
DDC_CLK_CON
DDC_DATA_CON
(77) VGA_HSYNC
(77) VGA_VSYNC
(77) DDC_CLK_CON
(77) DDC_DATA_CON
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
RED
REDb
GREEN
GREENb
BLUE
BLUEb
R1328
1.8V, 120mA
9/22
UMA: DAC_CLK and DATA

with 5V-tolerant.
not need level shift
C1303
SCD1U10V2KX-5GP
220R, 0.3A
C1302
BLM15AG221SS1D-GP
SC1U6D3V2KX-GP
L1301
R1327
(77) M_BLUE
1.8V, 20mA
+1.8V_VDDA18HTPLL
1119-3
+1.8V_RUN
G18
G17
E18
F18
E19
F19
(55)
(55)
(55)
(55)
(55)
(55)
(77) M_GREEN
UMA2150R2F-1-GP
UMA2
UMA2150R2F-1-GP
VGA_TXAOUT0+
VGA_TXAOUT0VGA_TXAOUT1+
VGA_TXAOUT2-
R1326 1
C_Pr
Y
COMP_Pb
A22
B22
A21
B21
B20
A20
A19
B19
(77) M_RED
E17
F17
F15
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
PART 3 OF 6
CRT/TVOUT
Layout Note
Trace at least 15 mil
C1308
SC2D2U6D3V3KX-GP
UMA/DIS
9/22
AVDD1
AVDD2
AVDDDI
AVSSDI
AVDDQ
AVSSQ
PLL PWR
LVTM
1.8V, 4mA
0R3J-0-U-GP
UMA/DIS
1
2
1
+1.8V_RUN_AVDDDQ
F12
E12
F14
G15
H15
H14
CLOCKs PM
2
UMA
U1C
UMA/DIS
1119-1
R1344
220R, 0.3A
+1.8V_RUN
C1311
BLM15AG221SS1D-GP
SC2D2U6D3V3KX-GP
PLLVDD18
*DEFAULT
1.8V, 20mA
0R3J-0-U-GP
1
UMA
Loading of STRAPS From EEPROM

Default Values
Master can load strap values from EEPROM if connected,
use default values if not connected
C1306
SCD1U10V2KX-5GP
2
UMA
1.8V, 20mA
L1307
Selects
*1 : use
0 : I2C
or
+1.8V_RUN_AVDDDI
1 R1333
+1.8V_RUN
LOAD_EEPROM_STRAPS#(RS880M use SUS_STAT#)
DY
SPM_Enable
1
2
+1.8V_RUN
1 = Memory Side port Not available DIS

0 = Memory Side port available UMA_SPM
R1305
UMA/DIS
10/8
UMA/DIS
R1303
0106-2
3KR2J-2-GP
R1304
10/8
SIDE_PORT_EN# ( RS880M use DAC_HSYNC)

VGA_VSYNC
VGA_HSYNC
3.3V, 110mA
3KR2J-2-GP
220R, 0.3A
2
UMA
0R3J-0-U-GP
C1312
BLM15AG221SS1D-GP
1 R1342
PLLVDD
C1307
SC1U6D3V2KX-GP
1
UMA
SPM_Disable
+3.3V_RUN_AVDD
SC1U6D3V2KX-GP
1.1V, 65mA
L1308
3KR2J-2-GP
R1302
+3.3V_RUN
3KR2J-2-GP
+1.1V_RUN
Enables debug bus access through memory I/O pads and GPIOs.
: Disable
0 : Enable
*1
RED: Connected to GND through two separate 133- 1%

resistors.(For match resistor on CRT/B 150- 1%)
RS880M : 71.RS880.M05
STRAP_DEBUG_BUS_GPIO_ENABLE# ( RS880M use DAC_VSYNC)
+3.3V_RUN
SSID = N.B
Rev

Sheet
1
13
of
A00
95
SSID = N.B
MEM_VDDQ
U1D
U1401
M2
N8
M3
BA0
BA1
BA2
SPM_CLKP
SPM_CLKN
J7
K7
CK
CK#
SPM_CKE
K9
CKE
SPM_DM1
SPM_DM0
D3
E7
DMU
DML
SPM_W E#
SPM_CAS#
SPM_RAS#
L3
K3
J3
WE#
CAS#
RAS#
SPM_DQS1P
SPM_DQS1N
MEM_VDDQ
DQSL
DQSL#
F3
G3
SPM_DQS0P
SPM_DQS0N
ODT
K1
SPM_ODT
CS#
RESET#
R1411
10KR2J-3-GP
SPM_CS#
L2
T2
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
SPM_CLKP
SPM_CLKN
9/15
UMA_SPM
R1409
R1410
SP_DDR3_RST# (21)
MEM_VDDQ
1
R1401
AD16
AE17
AD17
MEM_BA0
MEM_BA1
MEM_BA2
SPM_RAS#
SPM_CAS#
SPM_W E#
SPM_CS#
SPM_CKE
SPM_ODT
2
100R2F-L1-GP-U
W12
Y12
AD18
AB13
AB18
V14
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT
V15
W14
MEM_CKP
MEM_CKN
MEM_COMPP
MEM_COMPN
AE12
AD12
DY
UMA_SPM
2 40D2R2F-GP
1
1
2 40D2R2F-GP
UMA_SPM
MEM_DQ0/DVO_VSYNC
MEM_DQ1/DVO_HSYNC
MEM_DQ2/DVO_DE
MEM_DQ3/DVO_D0
MEM_DQ4
MEM_DQ5/DVO_D1
MEM_DQ6/DVO_D2
MEM_DQ7/DVO_D4
MEM_DQ8/DVO_D3
MEM_DQ9/DVO_D5
MEM_DQ10/DVO_D6
MEM_DQ11/DVO_D7
MEM_DQ12
MEM_DQ13/DVO_D9
MEM_DQ14/DVO_D10
MEM_DQ15/DVO_D11
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
SPM_DQ0
SPM_DQ1
SPM_DQ2
SPM_DQ3
SPM_DQ4
SPM_DQ5
SPM_DQ6
SPM_DQ7
SPM_DQ8
SPM_DQ9
SPM_DQ10
SPM_DQ11
SPM_DQ12
SPM_DQ13
SPM_DQ14
SPM_DQ15
MEM_DQS0P/DVO_IDCKP
MEM_DQS0N/DVO_IDCKN
MEM_DQS1P
MEM_DQS1N
Y17
W18
AD20
AE21
SPM_DQS0P
SPM_DQS0N
SPM_DQS1P
SPM_DQS1N
MEM_DM0
MEM_DM1/DVO_D8
W17
AE19
SPM_DM0
SPM_DM1
IOPLLVDD18
IOPLLVDD
AE23
AE24
IOPLLVDD18
IOPLLVDD
IOPLLVSS
AD23
MEM_VREF
AE18
MEM_COMPP
MEM_COMPN
SPM_VREF0
RS880M-1-GP
DY
10/7
+1.8V_RUN
1.8V(0.015A) for IOPLLVDD18
L1401
IOPLLVDD18
SC2D2U6D3V3KX-GP
SPM_BA0
SPM_BA1
SPM_BA2
C7
B7
SPM_BA0
SPM_BA1
SPM_BA2
C1401
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
DQSU
DQSU#
C1415
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
SPM_DQ13
SPM_DQ8
SPM_DQ10
SPM_DQ12
SPM_DQ15
SPM_DQ11
SPM_DQ14
SPM_DQ9
SCD1U10V2KX-5GP
SPM_A0
SPM_A1
SPM_A2
SPM_A3
SPM_A4
SPM_A5
SPM_A6
SPM_A7
SPM_A8
SPM_A9
SPM_A10
SPM_A11
SPM_A12
SPM_A13
D7
C3
C8
C2
A7
A2
B8
A3
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
SBD_MEM/DVO_I/F
UMA_SPM
VREFDQ
VREFCA
ZQ
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
PAR 4 OF 6
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14
SPM_VREF1 H1
SPM_VREF2 M8
SPM_ZQ
L8
2243R2F-2-GP
SPM_DQ2
SPM_DQ1
SPM_DQ5
SPM_DQ3
SPM_DQ7
SPM_DQ0
SPM_DQ4
SPM_DQ6
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
E3
F7
F2
F8
H3
H8
G2
H7
A8
A1
C1
C9
D2
E9
F1
H9
H2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
R1408 1
K8
K2
N1
R9
B2
D9
G7
R1
N9
SPM_A0
SPM_A1
SPM_A2
SPM_A3
SPM_A4
SPM_A5
SPM_A6
SPM_A7
SPM_A8
SPM_A9
SPM_A10
SPM_A11
SPM_A12
SPM_A13
2
0R0402-PAD
1231-1
UMA_SPM
+1.1V_RUN
1.1V(0.026A) for IOPLLVDD
L1402
1
2
C1402
UMA_SPM_Samsung
SC2D2U6D3V3KX-GP
IOPLLVDD
K4W 1G1646E-HC12-GP
2
0R0402-PAD
1231-1
UMA_SPM
MEM_VDDQ
<Core Design>
Wistron Corporation
UMA_SPM
UMA_SPM UMA_SPM
UMA_SPM
UMA_SPM UMA_SPM

Title
UMA_SPM
Size
A3
Date:
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
0R3J-0-U-GP
C1412
UMA_SPM
SC10U6D3V5KX-1GP
C1411
SC10U6D3V5KX-1GP
SCD1U10V2KX-5GP
C1409
SCD1U10V2KX-5GP
C1410
C1413
C1414
R1412
1
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
C1407
1KR3F-GP
R1407
SCD1U10V2KX-5GP
UMA_SPM
+1.5V_RUN
1.5V(0.35A) for IOPLLVDD

SC1U6D3V2KX-GP
UMA_SPM
SPM_VREF2
UMA_SPM
SCD1U10V2KX-5GP
UMA_SPM
C1408
1KR3F-GP
R1404
UMA_SPM
C1405
1KR3F-GP
UMA_SPM
SCD1U10V2KX-5GP
C1406
UMA_SPM/DIS_NOSPM
UMA_SPM
SPM_VREF1
R1406
SCD1U10V2KX-5GP
C1403
1KR3F-GP
R1405
UMA_SPM
1KR3F-GP
UMA_SPM
SPM_VREF0
MEM_VDDQ
MEM_VDDQ
R1403
UMA_SPM
A
SCD1U10V2KX-5GP
C1404
R1402
1KR3F-GP
MEM_VDDQ
AMD-RS880M_SidePort_(3/4)
Document Number
Rev

Sheet
1
14
of
A00
95
SSID = N.B
1231-1
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
1
2
1
2
0R3J-0-U-GP
1
2
UMA_SPM9/11
1
2
1
2
1
2
1
2
1
2
1
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
15 mils
PART 6/6
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15
RS880M-1-GP
Layout Note
DY
1231-2
VDD18_MEM
1117-2
UMA/DIS
+NB_VDDC
9/15
+1.1V_RUN
0104-1
R1507
1
2
R1508
1
2
R1509
1
2
R1510
1
2
R1511
1
2
Layout Note
A
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
GROUND
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
15 mils
+1.5V_RUN
UMA_SPM
UMA_SPM
1231-2
C1536
1
2
1
2
1
2
10/5
R1506
+3.3V_RUN
1
2
1
2
1
2
1
2
POWER
1
2
1
2
1
1
1
2
2
1
2
1
2
C1527
2
GAP-CLOSE-PW R-3-GP
C1526
2
GAP-CLOSE-PW R-3-GP
SC10U6D3V5KX-1GP
C1525
SC10U6D3V5KX-1GP
C1524
1231-2
SCD1U10V2KX-5GP
2
GAP-CLOSE-PW R-3-GP
550 mils
C1540
SCD1U10V2KX-5GP
C1539
2
GAP-CLOSE-PW R-3-GP
+NB_VDDC
DY
3.3V(0.06A) for VDD33

C1535
1.8V(0.025A) for VDD18
DY
UMA_SPM
SCD1U10V2KX-5GP
H11
H12
SCD1U10V2KX-5GP
C1538
G1504
1
10/8
DY
SCD1U10V2KX-5GP
C1537
AE10
AA11
Y11
AD10
AB10
AC10
SCD1U10V2KX-5GP
C1541
G1503
1
SCD1U10V2KX-5GP
C1522
SCD1U10V2KX-5GP
C1520
SCD1U10V2KX-5GP
10/8
1231-2
VDD_MEM_SDP
SCD1U10V2KX-5GP
C1505
SCD1U10V2KX-5GP
C1510
C1509
SC1U6D3V2KX-GP
C1504
G1502
1
1231-2
SBD MEM ENABLE

1.5V(0.1A) for VDD_MEM
C1542
SC1U10V3KX-3GP
0R3J-0-U-GP
VDD33_1
VDD33_2
G1501
1
+NB_VCORE
RS880M-1-GP
15 mils
VDD18_1
VDD18_2
VDD18_MEM1
VDD18_MEM2
VDD_MEM1
VDD_MEM2
VDD_MEM3
VDD_MEM4
VDD_MEM5
VDD_MEM6
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
DY
+1.1V_RUN
1215-1
130 mils
0.95~1.1V(12A) for VDDC
UMA_SPM/DIS_NOSPM
C1534
SC1U6D3V2KX-GP
R1502
UMA
F9
G9
AE11
AD11
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
DY
1231-2
SC4D7U6D3V3KX-GP
15 mils 1.8V(0.01A) for VDD18
+1.8V_RUN
VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
C1519
+1.8V_RUN
AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17
J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10
C1533
C1532
SCD1U10V2KX-5GP
C1531
SCD1U10V2KX-5GP
DY
VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
SCD1U10V2KX-5GP
C1518
C1517
SCD1U10V2KX-5GP
C1530
SCD1U10V2KX-5GP
DY
H18
G19
F20
E21
D22
B23
A23
PART 5/6
SC1U6D3V2KX-GP
C1513
C1516
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1529
1119-1
SC4D7U6D3V3KX-GP
220R, 2A
DY
1231-2
for VDDA18PCIE
40 mils 1.8V(0.7A)
+1.8V_RUN_VDDA18PCIE
C1528
SC4D7U6D3V3KX-GP
1
2
DY
SCD1U10V2KX-5GP
L1505
C1515
+1.8V_RUN
C1514
0R0603-PAD
DY
for VDDHTTX
20 mils 1.1V(0.4A)
+1.2V_RUN_VDDHTTX
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
C1512
R1503
SCD1U10V2KX-5GP
DY
1231-2
+1.1V_RUN
SCD1U10V2KX-5GP
C1507
SCD1U10V2KX-5GP
0R0603-PAD
for VDDHTRX
40 mils 1.1V(0.7A)
+1.1V_RUN_VDDHTRX
C1511
SC4D7U6D3V3KX-GP
VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7
SCD1U10V2KX-5GP
R1505
J17
K16
L16
M16
P16
R16
T16
C1508
+1.1V_RUN
1.1V(2.5A) for VDDPCIE
U1E
DY
SC4D7U6D3V3KX-GP
U1F
+1.1V_RUN_VDDPCIE
C1503
C1506
DY
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1502
SCD1U10V2KX-5GP
0R0603-PAD
for VDDHT
40 mils 1.1V(0.6A)
+1.1V_RUN_VDDHT
C1501
SC4D7U6D3V3KX-GP
R1501
+1.1V_RUN
AMD-RS880M_PWR&GD_(4/4)
Document Number
Rev

Sheet
1
15
of
A00
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
Reserved
Rev

Sheet
1
16
of
A00
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
Reserved
Rev

Sheet
1
17
of
A00
95
SSID = MEMORY
11/10
DM1
SODIMM A DECOUPLING (ONE CAP PER POWER PIN)
1
2
1
2
1
2
Layout Note:
Place these Caps near
SO-DIMMA.
+1.5V_SUS
DY
C1817
DY
C1816
DY
C1815
DY DY
C1814
C1813
DY
C1812
1225-1
1
2
1
2
1
2
RN
SC10P50V2JN-4GP
2
SC10P50V2JN-4GP
DY
TC1801
VTT1
VTT2
DY2
Note:
SA0 = 0, SA1 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30
SC10U10V5ZY-1GP
RESET#
1.5V, 3.5A
1
1
C1823
C1824
SE330U2VDM-L-GP
VREF_CA
VREF_DQ
9/23
+1.5V_SUS
SB_SMBCLK
SB_SMBDATA
9/23
C1809
DY
ODT0
ODT1
199
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
SB_SMBDATA_R (7,21)
SB_SMBCLK_R (7,21)
3.3V, 2mA
197
201
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
10R4P2R-PAD
4
2
3
RN1801
(19,76) SB_SMBDATA
(19,76) SB_SMBCLK
+3.3V_RUN
SC10U10V5ZY-1GP
203
204
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PM_EXTTS#0
SCD1U10V2KX-5GP
C1808
C1822
10/7
0108-3
30
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
198
77
122
125
R1806
0107-4
SC10U10V5ZY-1GP
(9) DDR3_A_DRAMRST#
NC#1
NC#2
NC#/TEST
200
202
SB_SMBDATA
SB_SMBCLK
SCD1U10V2KX-5GP
C1807
126
1
SCD1U10V2KX-5GP
C1811
C1810
SCD1U10V2KX-5GP
SCD01U50V3KX-4GP
C1825
SCD1U10V2KX-5GP
9/23
SA0
SA1
MEM_MA_CLK1_P (9)
MEM_MA_CLK1_N (9)
M_A_DM[7..0] (9)
SC10U10V5ZY-1GP
116
120
(9) MEM_MA0_ODT0
(9) MEM_MA0_ODT1
VDDSPD
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
SCD1U10V2KX-5GP
C1806
12
29
47
64
137
154
171
188
EVENT#
11
28
46
63
136
153
170
187
SC10U10V5ZY-1GP
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
SDA
SCL
DY
MEM_MA_CLK0_P (9)
MEM_MA_CLK0_N (9)
102
104
SCD1U10V2KX-5GP
C1805
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
PM_EXTTS#0
1
4K7R2J-2-GP
SC10U10V5ZY-1GP
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
10
27
45
62
135
152
169
186
BA0
BA1
MEM_MA_CKE0 (9)
MEM_MA_CKE1 (9)
SCD1U10V2KX-5GP
C1804
+V_DDR_REF
9/14
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
CK1
CK1#
73
74
101
103
+1.5V_SUS
SCD1U10V2KX-5GP
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
CK0
CK0#
MEM_MA0_CS#0 (9)
MEM_MA0_CS#1 (9)
C1802
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
CKE0
CKE1
MEM_MA_RAS# (9)
MEM_MA_WE# (9)
MEM_MA_CAS# (9)
114
121
SCD1U10V2KX-5GP
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
CS0#
CS1#
NP1
NP2
110
113
115
109
108
(9) MEM_MA_BANK0
(9) MEM_MA_BANK1
(9) M_A_DQ[63..0]
NP1
NP2
RAS#
WE#
CAS#
(9) MEM_MA_BANK2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
(9) MEM_MA_ADD[0..15]
DDR3-204P-41-GP-U
62.10017.N41
+0.75V_DDR_VTT
H =5.2mm
DY
2
1
2
C1821
C1820
DY
1231-2
SCD1U10V2KX-5GP
C1819
SCD1U10V2KX-5GP
SC2D2U6D3V3KX-GP
Place these caps

close to VTT1 and
VTT2.
0.75V, 0.5A
<Core Design>
Wistron Corporation
Title
DDR3-SODIMM1
Size
Document Number
Rev
A00

Date:
5
Sheet

1
18
of
95
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2
9/23
1.5V, 3.5A
9/23
DY
2
R1906
Note:
SA0 = 0, SA1 = 1
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34
C
SODIMM B DECOUPLING (ONE CAP PER POWER PIN)
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
1
2
1
C1917
DY
DY
1
2
C1916
DY
C1915
C1914
DY DY
C1913
DY
C1912
Layout Note:
Place these Caps near
SO-DIMMB.
+1.5V_SUS
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
+3.3V_RUN
+1.5V_SUS
77
122
125
+1.5V_SUS
PM_EXTTS#1
1
4K7R2J-2-GP
197
201
1
2
1
2
1
2
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
199
SC10U10V5ZY-1GP
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SB_SMBDATA (18,76)
SB_SMBCLK (18,76)
+3.3V_RUN
3.3V, 2mA
C1911
DY
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
PM_EXTTS#1
SC10U10V5ZY-1GP
203
204
NC#1
NC#2
NC#/TEST
198
9/23
SCD1U10V2KX-5GP
C1910
C1921
10/7
0108-3
30
SA0
SA1
SB_SMBDATA
SB_SMBCLK
SC10U10V5ZY-1GP
(9) DDR3_B_DRAMRST#
VDDSPD
200
202
SCD1U10V2KX-5GP
C1909
126
1
SCD1U10V2KX-5GP
C1905
C1904
SCD1U10V2KX-5GP
SCD01U50V3KX-4GP
C1922
SCD1U10V2KX-5GP
9/23
EVENT#
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
SC10U10V5ZY-1GP
116
120
(9) MEM_MB0_ODT0
(9) MEM_MB0_ODT1
SDA
SCL
MEM_MB_CLK1_P (9)
MEM_MB_CLK1_N (9)
M_B_DM[7..0] (9)
11
28
46
63
136
153
170
187
SCD1U10V2KX-5GP
C1908
12
29
47
64
137
154
171
188
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SC10U10V5ZY-1GP
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
BA0
BA1
MEM_MB_CLK0_P (9)
MEM_MB_CLK0_N (9)
102
104
SCD1U10V2KX-5GP
C1907
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
CK1
CK1#
MEM_MB_CKE0 (9)
MEM_MB_CKE1 (9)
101
103
SC10U10V5ZY-1GP
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
10
27
45
62
135
152
169
186
CK0
CK0#
MEM_MB0_CS#0 (9)
MEM_MB0_CS#1 (9)
73
74
SCD1U10V2KX-5GP
C1906
+V_DDR_REF
9/14
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
CKE0
CKE1
MEM_MB_RAS# (9)
MEM_MB_WE# (9)
MEM_MB_CAS# (9)
114
121
SCD1U10V2KX-5GP
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
CS0#
CS1#
C1902
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
NP1
NP2
110
113
115
SCD1U10V2KX-5GP
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
NP1
NP2
RAS#
WE#
CAS#
109
108
(9) MEM_MB_BANK0
(9) MEM_MB_BANK1
(9) M_B_DQ[63..0]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
(9) MEM_MB_BANK2
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15
(9) MEM_MB_ADD[0..15]
SSID = MEMORY
11/10
DM2
DDR3-204P-40-GP-U
+0.75V_DDR_VTT
SO-DIMMB is placed farther from

the Processor than SO-DIMMA
DY
2
1
2
H = 9.2mm
C1920
C1919
DY
1231-2
SCD1U10V2KX-5GP
C1918
SCD1U10V2KX-5GP
SC2D2U6D3V3KX-GP
Place these caps

close to VTT1 and
VTT2.
0.75V, 0.5A
<Core Design>
Wistron Corporation
Title
DDR3-SODIMM2
Size
Document Number
Rev
A00

Date:
5
Sheet

1
19
of
95
SB820M : 71.SB820.M02
SSID = S.B
U2A
U29
U28
NB_DISP_CLKP
NB_DISP_CLKN
T26
T27
1nd 82.30020.791
2nd 82.30020.851
2 1MR2J-1-GP
N29
N28
GPP_CLK1P
GPP_CLK1N
M29
M28
GPP_CLK2P
GPP_CLK2N
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
1
1
9/25
A_RST#
DY
VCC
GND
1231-1
DY
R2005
2
PLTRST#
GPU,NB
PLTRST#_EC (37)
KBC
11/6
TP2004
PLTRST#_NB_GPU (13,37,80)
0R0402-PAD
1231-1
SB_GPIO46
0R0402-PAD
R2008
2
1
R2021
0R0402-PAD
PM_CLKRUN# (37)
9/23
1118-2
GPP_CLK6P
GPP_CLK6N
N26
N27
GPP_CLK7P
GPP_CLK7N
T29
T28
GPP_CLK8P
GPP_CLK8N
L25
14M_25M_48M_OSC
32K_X1
C1
32K_X1
25M_X1
L26
25M_X1
32K_X2
C2
32K_X2_R
L27
25M_X2
RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G
D2
B2
B1
RTC_CLK
INTRUDER_ALERT#
25M_X2
CLOCK GENERATOR
P29
P28
1
C2018
RN2008
LPCCLK0_R
LPCCLK1_R
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
1
2
TP_LPC_LDRQ0#
TP_LPC_LDRQ1#
1
1
4
3
SRN22-3-GP
G21
H21
K19
G22
J24
TP2005
TP2006
DY
9/23
2
SC10P50V2JN-4GP
PCLK_KBC (24,37)
LPCCLK1 (24)
LPC_LAD0 (37,70)
LPC_LAD1 (37,70)
LPC_LAD2 (37,70)
LPC_LAD3 (37,70) LPC Bus Routing first connects to
LPC_LFRAME# (37,70)
MINICARD then connects to KBC
to EC
INT_SERIRQ
11/12-1
1
2
C2011
SC18P50V2JN-1-GP
R2014
20MR3-GP
(37)
32K_X1
ALLOW _LDTSTOP (13)

CPU_PROCHOT# (10)
CPU_LDT_PW RGD (10,42)
CPU_LDT_STOP# (10,13)
CPU_LDT_RST# (10)
X2002
X-32D768KHZ-38GPU
R2016
32K_X2_R
32K_X2
1
2
C2012
SC15P50V2JN-2-GP
0R0402-PAD
SB820M-1-GP
1119-1
74LVC1G08GW -1-GP
GPP_CLK5P
GPP_CLK5N
C2015
SC12P50V2JN-3GP
P25
M25
ALLOW_LDTSTP/DMA_ACTIVE#
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#
U2001
(21) GP_PCIE_RST#
AJ6
AG6
AG4
AJ4
H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19
+3.3V_ALW
GPP_CLK4P
GPP_CLK4N
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/CLK_REQ6#/GPIO49
SERIRQ/GPIO48
0R2J-2-GP
TP2009
TP2001
1119-1
L24
L23
2
1
GPP_CLK0P
GPP_CLK0N
TP_PCI_AD28
TP_PCI_AD29
PCI_AD25 (24)
PCI_AD26 (24)
PCI_AD27 (24)
R2018
2
10R2J-2-GP
RTCCLK_KBC (37)
<Core Design>
1231-1
11/12-1
RTC_CLK (39)
Wistron Corporation
TP2007

+RTC_CELL
C2017
L29
L28
R2028
2 DY
VDDR_SEL (24,51)
GPP_CLK3P
GPP_CLK3N
XTAL-25MHZ-96GP
1113-1
SLT_GFX_CLKP
SLT_GFX_CLKN
11/6
9/22
PCI_AD23 (24)
SCD1U10V2KX-5GP
C2014
SC12P50V2JN-3GP
CPU_HT_CLKP
CPU_HT_CLKN
V23
T23
PLTRST#_LAN_W LAN (70,76,78)
C2013
SC150P50V2KX-GPDY
T25
V25
25M_X2
X2001
2
V21
T21
25M_X1
R2017
NB_HT_CLKP
NB_HT_CLKN
PLTRST#_LAN_W LAN
PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN
PCIE_RST#_SB
M23
P23
R2025
22R2J-2-GP
2
1
C2010
SB_PCIE_CLK
SB_PCIE_CLK#
R2026
10KR2J-3-GP
11/6
SCD1U10V2KX-5GP
9/23
(7) SB_PCIE_CLK
(7) SB_PCIE_CLK#
+3.3V_RUN
11/6
9/11
9/16
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
AA22
Y21
AA25
AA24
W23
V24
W24
W25
9/24
TP2008
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
STRAP PIN
PCIE_CALRP
PCIE_CALRN
AA28
AA29
Y29
Y28
Y26
Y27
W28
W29
AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7
PCI_CLK1 (24)
PCI_CLK2 (24)
PCI_CLK3 (24)
PCLK_FW H (24,70)
22R2J-2-GP
NOTE: SB8XX ONLY SUPPORTS 2 GPP

PORT 2 AND 3 IS NOT SUPPORTED. (From CRB)
AD29
AD28
PCI_RST# 1
DY2
2 590R2F-GP SB_PCIE_CALRP
2 2KR2F-3-GP SB_PCIE_CALRN
A_RX0P
A_RX0N
A_RX1P
A_RX1N
A_RX2P
A_RX2N
A_RX3P
A_RX3N
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT0#
GNT1#/GPO44
GNT2#/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLKRUN#
LOCK#
V2
R2029
R2002 1
R2007 1
AE24
AE23
AD25
AD24
AC24
AC25
AB25
AB24
PCIRST#
PCLK_FW H_R
+1.1V_RUN_PCIE_VDDR
A_TX0P
A_TX0N
A_TX1P
A_TX1N
A_TX2P
A_TX2N
A_TX3P
A_TX3N
W2
W1
W3
W4
Y1
Place R <100mils form

pins AD29,AD28
AD26
AD27
AC28
AC29
AB29
AB28
AB26
AB27
PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39
ALINK_NBTX_SBRX_P0
ALINK_NBTX_SBRX_N0
ALINK_NBTX_SBRX_P1
ALINK_NBTX_SBRX_N1
ALINK_NBTX_SBRX_P2
ALINK_NBTX_SBRX_N2
ALINK_NBTX_SBRX_P3
ALINK_NBTX_SBRX_N3
2
2
2
2
2
2
2
2
ALINK_NBRX_SBTX_C_P0
ALINK_NBRX_SBTX_C_N0
Title
DY
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
1
1
1
1
1
1
1
1
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Part 1 of 5
PCIE_RST#
A_RST#
PCI INTERFACE
ALINK_NBRX_SBTX_P0
ALINK_NBRX_SBTX_N0
ALINK_NBRX_SBTX_P1
ALINK_NBRX_SBTX_N1
ALINK_NBRX_SBTX_P2
ALINK_NBRX_SBTX_N2
ALINK_NBRX_SBTX_P3
ALINK_NBRX_SBTX_N3
2 22R2J-2-GP
LPC
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
C2002
C2003
C2004
C2005
C2006
C2007
C2008
C2009
RTC
R2024
CPU
A_RST#
PCIE_RST#_SB P1
A_RST#_R
L1
PCI CLKS
2 SC150P50V2KX-GP
PCI EXPRESS INTERFACES
C2001 1
SB820M_PCIE&PCI_(1/5)
Size
A3
Document Number
Date:
Friday, March 05, 2010
Rev

Sheet
1
20
of
A00
95
SSID = S.B
U2D
DY 2
R2114
KBC_RSMRST#
10KR2J-3-GP
DY 2
DY 2
R2117
SIO_EXT_SMI#
10KR2J-3-GP
R2118
SB_SDIN_CODEC
10KR2J-3-GP
R2119
ACZ_BIT_CLK
10KR2J-3-GP
(7) SB_14M_CLK
DY 2
R2116
SIO_EXT_SCI#
10KR2J-3-GP
9/22
(10,39) TALERT#
1116-3
VRAMUMA_SPM_Hynix
0225-4
R2120
R2121
1
1
1
1
TP2132
TP2131
TP2130
1 USB_OC4#
1 USB_OC3#
1 USB_OC2#
USB_OC#2_3
USB_OC#0_1
33R2J-2-GP
33R2J-2-GP
ACZ_BIT_CLK
1
1
1 EC2101
SC180P50V2JN-1GP
33R2J-2-GP
2
33R2J-2-GP
2
ACZ_SYNC_R
ACZ_RST#_R
EC2102
SC180P50V2JN-1GP
R2122
R2123
(30) SB_AZ_CODEC_SYNC
(30) SB_AZ_CODEC_RST#
2
2
9/16
2
DY
1
2
3
4
GBE_COL
GBE_CRS
GBE_RXERR
GBE_MDIO
8
7
6
5
9/16
RN2102
DY
10/1
SRN10KJ-6-GP
R2124 1
210KR2J-3-GP GBE_PHY_INTR
RN2104
1
2
SCL2
SDA2
4
3
USB_OC7#
USB_OC6#
J10
H11
USB_FSD0P/GPIO185
USB_FSD0N
H9
J8
H3
D1
E4
D4
E8
F7
E7
F8
BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GEVENT17#
USB_OC4#/IR_RX0/GEVENT16#
USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC2#/TCK/GEVENT14#
USB_OC1#/TDI/GEVENT13#
USB_OC0#/TRST#/GEVENT12#
M3
N1
L2
M2
M1
M4
N2
P2
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST#
T1
T4
L6
L5
T9
U1
U3
T2
U2
T5
V5
P5
M5
P9
T7
P7
M7
P4
M9
V7
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR
B12
A12
USB_HSD12P
USB_HSD12N
F11
E11
USB_HSD11P
USB_HSD11N
E14
E12
USB_PP11 (54)
USB_PN11 (54)
USB_HSD10P
USB_HSD10N
J12
J14
USB_PP10 (78)
USB_PN10 (78)
USB_HSD9P
USB_HSD9N
A13
B13
USB_PP9 (73)
USB_PN9 (73)
USB_HSD8P
USB_HSD8N
D13
C13
USB_HSD7P
USB_HSD7N
G12
G14
USB_HSD6P
USB_HSD6N
G16
G18
USB_HSD5P
USB_HSD5N
D16
C16
USB_HSD4P
USB_HSD4N
B14
A14
USB_HSD3P
USB_HSD3N
E18
E16
USB_PP3 (77)
USB_PN3 (77)
USB_HSD2P
USB_HSD2N
J16
J18
USB_PP2 (77)
USB_PN2 (77)
USB_HSD1P
USB_HSD1N
B17
A17
USB_HSD0P
USB_HSD0N
A16
B16
SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
D25
F23
B26
E26
F25
E22
F22
E21
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
G24
G25
E28
E29
D29
D28
C29
C28
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226
B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22
SRN10KJ-5-GP
9/23
9/24
TP2135
TP2134
1
1
GBE_COL
GBE_CRS
GBE_MDIO
GBE_RXERR
GBE_PHY_INTR
TP_DEBUG_DAT
TP_DEBUG_CLK
TP2116
1
TP2117
1
EC Not Implemented
SPI_CS2#
GPO160
E23
E24
F21
G29
PS2_DAT/SDA4/GPIO187
PS2_CLK/SCL4/GPIO188
SPI_CS2#/GBE_STAT2/GPIO166
FC_RST#/GPO160
D27
F28
F29
E27
PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192
SB820M-1-GP
10/7
USB
USB_PP5
USB_PN5
Pair
USB_PP5 (76)
USB_PN5 (76)
USB_PP4 (76)
USB_PN4 (76)
USB_PP1
USB_PN1
Device
USB0 (I/O Board/ESATA)
USB1 (I/O Board)
USB2 (CRT Board)
USB3 (CRT Board)
WLAN USB
WWAN USB
RESERVED
RESERVED
RESERVED
BLUETOOTH
10
CARD READER
11
CAMERA (LVDS CONN)
12
RESERVED
13
RESERVED
USB_PP1 (76)
USB_PN1 (76)
USB_PP0 (76)
USB_PN0 (76)
SCL2
SDA2
Not use
CPU_SIC (10)
CPU_SID (10)
B
SB_GPO199 (24)
SB_GPO200 (24)
Strap Pin / define to use LPC or SPI ROM
<Core Design>
Wistron Corporation
Title
Date:
4

Size
A3
5
DY
USB_HSD13P
USB_HSD13N
RSMRST#
CLK_REQ4#/SATA_IS0#/GPIO64
SMARTVOLT1/SATA_IS2#/GPIO50
SATA_IS4#/FANOUT3/GPIO55
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#
GBE_LED0/GPIO183
GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN/IDLEEXT#
USB_48M_CLK (7)
1
2
R2102
11K8R2F-GP
(24) ACZ_SDATAOUT_R
(30) SB_AZ_CODEC_BITCLK
(30) SB_AZ_CODEC_SDOUT
(30) SB_SDIN_CODEC
+3.3V_ALW
9/23
TP2133
TP2129
(63) USB_OC#2_3
(63) USB_OC#0_1
SP_VRAM_SEL
2 R2133
0R2J-2-GP
DY
9/23
DY 2
(14) SP_DDR3_RST#
1
2
(30) ACZ_SPKR
(7,18) SB_SMBCLK_R
(7,18) SB_SMBDATA_R
SIO_EXT_W AKE#
2 R2115
10KR2J-3-GP
Close SB
AD19
AA16
GP_PCIE_RST# AB21
AC18
AF20
AE19
AF19
SB_SMBCLK_R
AD22
SB_SMBDATA_R AE22
SMB_CLK
F5
SMB_DATA
F4
TP2127
1 CLK_REQ2# AH21
SP_VRAM_SEL AB18
E1
R2131
TP2113
1 SB_GPIO51 AJ21
GEVENT7#
H4
1
2
UMA_SPM
0R2J-2-GP
D5
D7
G5
K3
1
AA20
DY 2R2128 SB_OSCIN
0R2J-2-GP
9/25
C2103
SB_TEST0
SCD1U10V2KX-5GP
R2112
2K2R2J-2-GP
1231-1
GP_PCIE_RST#
(20) GP_PCIE_RST#
PCIE_W AKE#
2 R2113
10KR2J-3-GP
SB_TEST1
DY 2
2 R2110
2K2R2J-2-GP
PM_RSMRST#_R G1
C2101
DY
SB_TEST2
R2111 1
0R0402-PAD
SCD1U10V2KX-5GP
R2108
2K2R2J-2-GP
SB_THERMTRIP#
2
0R0402-PAD
1
R2109
H_THERMTRIP#
(41) NB_PW RGD
(37) KBC_RSMRST#
C2104
TALERT#
(10,37,39,42,82)
SCD1U10V2KX-5GP
2 R2132
10KR2J-3-GP
DY 2
SYS_RESET#
9/22
1
(76) PCIE_W AKE#
SRN10KJ-5-GP
TP2120
USB_48M_CLK
EC Not Implemented
C2105
SCD047U10V2KX-2GP
EMBEDDED CTRL
SMB_DATA
SMB_CLK
4
3
EMBEDDED CTRL
RN2103
1
2
1
C2102
SIO_A20GATE
SIO_RCIN#
SIO_EXT_SCI#
SIO_EXT_SMI#
USB
USB
MISC
1.1
(37)
(37)
(37)
(37)
SIO_RCIN#
A10
G19 USB_RCOMP
USB_FSD1P/GPIO186
USB_FSD1N
USB 2.0
10/7
0113-1
USB_RCOMP
HD AUDIO
9/22
1231-1
DY
USBCLK/14M_25M_48M_OSC
GBE LAN
9/23
PM_PW RBTN#_R
2
R2106
SUS_STAT#
SB_TEST0
SB_TEST1
2
SC180P50V2JN-1GP
SB_TEST2
1
0R0402-PAD
PCI_PME#/GEVENT4#
RI#/GEVENT22#
SPI_CS3#/GBE_STAT1/GEVENT21#
SLP_S3#
Part 4 of 5
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST0
TEST1/TMS
TEST2
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/GEVENT23#
GEVENT5#
SYS_RESET#/GEVENT19#
WAKE#/GEVENT8#
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
NB_PWRGD
ACPI / WAKE UP EVENTS
(37,41,42,49,52,89) PM_SLP_S3#
(37,49) PM_SLP_S5#
(37) PM_PW RBTN#
(7,41) SB_PW RGD
(13) SUS_STAT#
SRN4K7J-8-GP
+3.3V_ALW
9/23
J2
K1
D3
F1
H1
F2
H5
G6
B3
C4
F6
AD21
AE21
K2
J29
H2
J1
H6
F3
J6
AC19
EC2103
SB_SMBDATA_R
SB_SMBCLK_R
4
3
TP_PCI_PME#
SC180P50V2JN-1GP
1
2
GPIO
TP2101
(37) SIO_EXT_W AKE#
USB OC
1119-5
RN2101
GbE MAC Not Enabled
+3.3V_RUN
SB820M_USB&GPIO_(2/5)
Document Number
Rev

Sheet
1
21
of
A00
95
SSID = S.B
U2B
SATA ODD
E-SATA
AH9
AJ9
SATA_TX0P
SATA_TX0N
(59) SATA_RXN0
(59) SATA_RXP0
C2203 1
C2204 1
2SCD01U50V2ZY-1GP SATA_RXN0_C
2SCD01U50V2ZY-1GP SATA_RXP0_C
AJ8
AH8
SATA_RX0N
SATA_RX0P
(59) SATA_TXP1
(59) SATA_TXN1
C2205 1
C2206 1
2SCD01U50V2ZY-1GP SATA_TXP1_C
2SCD01U50V2ZY-1GP SATA_TXN1_C
AH10
AJ10
SATA_TX1P
SATA_TX1N
(59) SATA_RXN1
(59) SATA_RXP1
C2208 1
C2207 1
2SCD01U50V2ZY-1GP SATA_RXN1_C
2SCD01U50V2ZY-1GP SATA_RXP1_C
AG10
AF10
SATA_RX1N
SATA_RX1P
(76) SATA_TXP2
(76) SATA_TXN2
C2211 1
C2214 1
AG12
AF12
SATA_TX2P
SATA_TX2N
AJ12
AH12
SATA_RX2N
SATA_RX2P
AH14
AJ14
SATA_TX3P
SATA_TX3N
AG14
AF14
SATA_RX3N
SATA_RX3P
AG17
AF17
SATA_TX4P
SATA_TX4N
AJ17
AH17
SATA_RX4N
SATA_RX4P
AJ18
AH18
SATA_TX5P
SATA_TX5N
AH19
AJ19
SATA_RX5N
SATA_RX5P
SATA_RXN2
SATA_RXP2
(76) SATA_RXN2
(76) SATA_RXP2
10/6
PLACE SATA AC DECOUPLING
CAPS CLOSE TO SB820M
Very Close
to SB820
+1.1V_RUN_AVDD_SATA
AD11
AD16
SATA_ACT#/GPIO67
SATA_X1
AC16
SATA_X2
J5
E2
K4
K9
G2
SPI ROM in KBC side
9/24
SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/GPIO161
SB820M-1-GP
SPI ROM
R2204
SATA_X2
HW MONITOR
SATA_X2
DY
2
DY
X2201
SC12P50V2JN-3GP
SATA_X1
SATA_CALRP
SATA_CALRN
SATA_X1
10MR2J-L-GP
DY
XTAL-25MHZ-102-GP
XTAL
1'nd 82.30020.851
2'nd 82.30020.791
DY
SC12P50V2JN-3GP
C2210
1
1KR2F-3-GP
1
2 SATA_CALP AB14
1
2 SATA_CALN AA14
R2202
931R2F-1-GP
(66) SATA_LED#
9/15
C2209
1
R2201
SERIAL ATA
SATA HDD
FLASH
Part 2 of 5
(59) SATA_TXP0
(59) SATA_TXN0
C2201 1
C2202 1
FC_CLK
FC_FBCLKOUT
FC_FBCLKIN
AH28
AG28
AF26
FC_OE#/GPIOD145
FC_AVD#/GPIOD146
FC_WE#/GPIOD148
FC_CE1#/GPIOD149
FC_CE2#/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147
AF28
AG29
AG26
AF27
AE29
AF29
AH27
FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143
AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26
GPIOD[150:128] are open drain GPIO pins

where as GPO160 is an open drain GPO pin.
These pins are not programmed to GPIO mode by default.
If use as GPIO, need to pull up to 1.8V_RUN
FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54
W5
W6
Y9
FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58
W7
V9
W8
TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174
TEMP_COMM
B6
A6
A5
B5
C7
TEMPIN0
TEMPIN1
TEMPIN2
TEMPIN3
VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182
A3
B4
A4
C5
A7
B7
B8
A8
VIN0
VIN1
VIN2
VIN3
MEM_1V5
VIN5
VIN6
VIN7
1119-1
Move to P.51
9/22
10/9
MEM_1V5
(51)
+3.3V_ALW
RN2201
NC#G27
NC2#Y2
G27
Y2
TEMPIN0
TEMPIN1
TEMPIN2
TEMPIN3
1
2
3
4
9/16
10/1
8
7
6
5
SRN10KJ-6-GP
+3.3V_ALW
RN2202
VIN2
VIN0
VIN1
VIN3
1
2
3
4
10/9
8
7
6
5
SRN10KJ-6-GP
+3.3V_ALW
RN2203
VIN7
VIN6
VIN5
1
2
3
4
8
7
6
5
SRN10KJ-6-GP
1116-1
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
SB820M_SATA-IDE_(3/5)
Document Number
Rev

Sheet
22
of
A00
95
Part 5 of 5
U2C
+1.1V_RUN
Part 3 of 5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
CORE S0
PCI/GPIO I/O
1
2
1
2
1
1
2
1
2
1
2
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSPL_SYS
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
VSSIO_PCIECLK
M20
H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20
1
2
CORE S5
3.3V_S5 I/O
2
1
2
FLASH I/O
PCI EXPRESS
SERIAL ATA
220R, 0.3A
10/1
Removed
DY
2
BLM15AG221SS1D-GP
1
2
1
2
220R, 0.3A
3.3V_RUN_VDDPL
C2350
VSSXL
P21
P20
M22
M24
M26
P22
P24
P26
T20
T22
T24
V20
J23
<Core Design>
Wistron Corporation
Title
Size
A3

Date:
5
VSSAN_HWM
M19
C2345
BLM15AG221SS1D-GP
12mA
SCD1U10V2KX-5GP
L2313
SC2D2U6D3V3KX-GP
1.1V_ALW _VDDPL
C2349
+3.3V_RUN
L2312
SC2D2U6D3V3KX-GP
C2342
C2341
DY
SC2D2U6D3V3KX-GP
SCD1U10V2KX-5GP
9/15
220R, 0.3A
EFUSE
C2348
C2347
+1.1V_ALW
L2308
1
2
BLM15AG221SS1D-GP
Y4
D8
46mA
+3.3V_ALW
3.3V_ALW _VDDXL
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
VSSIO_USB
AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8
+3.3V_AVDD_USB
1
2
1
2
USB I/O
1
1
2
1
2
1
2
1
2
1
2
CLKGEN I/O
GBE LAN
1
2
1
2
1
2
1
2
1
2
88mA
A9
B10
K11
B9
D10
D12
D14
D17
E9
F9
F12
F14
F16
C9
G11
F18
D9
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SB820M-1-GP
9/17
16mA
SB820M-1-GP
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
VSSIO_SATA
1119-1
+3.3V_ALW
220R, 0.3A
3.3V_ALW _VDDXL
SC2D2U6D3V3KX-GP
PLL
1
2
1
2
1
2
1
2
1
2
1
2
+1.1V_ALW
L2306
1
2
BLM15AG221SS1D-GP
C2336
L20
C2328
VDDAN_33_HWM_S
C2324
DY
F19
D6
SCD1U10V2KX-5GP
TC2302
1.1V_ALW _VDDPL
SC10U6D3V5KX-1GP
VDDPL_11_SYS_S
VDDPL_33_USB_S
SC1U6D3V2KX-GP
L22
+1.1V_ALW _VDDR_USB
58mA
M21 3.3V_RUN_VDDPL
VDDPL_33_SYS
SC2D2U6D3V3KX-GP
20R0402-PAD
C2335
C2311
SC10U6D3V5KX-1GP
+3.3VALW _VDDIO_AZ
A11
B11
VDDXL_33_S
65mA
SC10U6D3V5KX-1GP
M8
1
R2303
C2327
VDDIO_AZ_S
+3.3V_ALW
15mA
1231-1
VDDCR_11_USB_S
VDDCR_11_USB_S
C2323
C2340
VDDAN_11_USB_S
VDDAN_11_USB_S
VDDCR_11_S
VDDCR_11_S
F26
G26
+1.1V_ALW
113mA
C2344
5mA
C2343
220R, 0.3A
SCD1U10V2KX-5GP
SC2D2U6D3V3KX-GP
C2339
L2309
BLM15AG221SS1D-GP
SC10U10V5ZY-1GP
C2338
SC10U6D3V5KX-1GP
+1.1V_AVDD_USB
C2337
+1.1V_ALW
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
220R, 2A
C11
D11
A21
D21
B21
K10
L10
J9
T6
T8
SCD1U10V2KX-5GP
534mA
1
2
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
VDDIO_33_S
C2334
+3.3V_AVDD_USB
L2307
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
VDDAN_33_USB_S
M6
P8
SCD1U10V2KX-5GP
A18
A19
A20
B18
B19
B20
C18
C20
D18
D19
D20
E19
C2333
DY
SCD1U10V2KX-5GP
C2332
DY
SCD1U10V2KX-5GP
C2331
C2330
SC1U6D3V2KX-GP
1119-1
+3.3V_ALW
TC2304
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
33R, 3A
C2318
1350mA
VDDIO_GBE_S
VDDIO_GBE_S
49mA
SC1U6D3V2KX-GP
L2305
1
2
1231-1
+3.3V_ALW
VDDCR_11_GBE_S
VDDCR_11_GBE_S
SC2D2U6D3V3KX-GP
+1.1V_RUN_AVDD_SATA
SC1U6D3V2KX-GP
DY
+1.1V_RUN
2
0R0603-PAD
GBE PHY not used

L7
L9
C2329
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
VDDAN_11_SATA
DY
1
R2304
M10
VDDIO_33_GBE_S
SC2D2U6D3V3KX-GP
VDDPL_33_SATA
AJ20
AF18
AH20
AG19
AE18
AD18
AE16
C2310
C2326
C2325
1119-1
SCD1U10V2KX-5GP
SC2D2U6D3V3KX-GP
220R, 0.3A
9/15
AD14
DY
15mA
BLM15AG221SS1D-GP
+1.1V_RUN
VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE
VDDAN_11_PCIE
DY
C2317
L2304
VDDPL_33_PCIE
U26
V22
V26
V27
V28
V29
W22
W26
C2322
DY
SCD1U10V2KX-5GP
C2321
DY
SCD1U10V2KX-5GP
C2320
C2319
SC1U6D3V2KX-GP
+3.3V_VDDPL_SATA
TC2303
+3.3V_RUN
690mA
SC1U6D3V2KX-GP
33R, 3A
SC10U6D3V5KX-1GP
+1.1V_RUN_PCIE_VDDR
L2303
1
2
SC1U6D3V2KX-GP
AE28
+1.1V_RUN
C
V1
VDDRF_GBE_S
C2309
POWER
C2316
DY
VDDIO_18_FC
VDDIO_18_FC
VDDIO_18_FC
VDDIO_18_FC
SC1U6D3V2KX-GP
9/15
AF22
AE25
AF24
AC22
SCD1U10V2KX-5GP
1119-1
11mA
C2314
220R, 0.3A
C2313
BLM15AG221SS1D-GP
SCD1U10V2KX-5GP
SC2D2U6D3V3KX-GP
DY
382mA
C2315
+3.3V_VDDPL_PCIE
L2301
DY
+1.1V_RUN_SB_CLKGEN
K28
K29
J28
K26
J21
J20
K21
J22
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
VDDAN_11_CLK
SCD1U10V2KX-5GP
+3.3V_RUN
DY
SC1U6D3V2KX-GP
Removed
C2307
SCD1U10V2KX-5GP
9/17
0R0603-PAD
1231-1
C2308
0.15mA
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
VDDCR_11
C2304
R2302
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
VDDIO_33_PCIGP
SCD1U10V2KX-5GP
+1.8V_SB_VDDIO_FC
790mA
N13
R15
N17
U13
U17
V12
V18
W12
W18
SCD1U10V2KX-5GP
+1.8V_RUN
AH1
V6
Y19
AE5
AC21
AA2
AB4
AC8
AA7
AA9
AF7
AA19
Y14
Y16
AB16
AC14
AE12
AE14
AF9
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ7
AJ11
AJ13
AJ16
GROUND
1
2
U2E
DY
1
2
DY
C2303
SCD1U10V2KX-5GP
C2302
SCD1U10V2KX-5GP
C2301
SCD1U10V2KX-5GP
1231-1
TC2301
SC10U6D3V5KX-1GP
0R0603-PAD
78mA
SSID = S.B
+3.3V_SB_VDDIO
R2301
+3.3V_RUN
SB820M_POWER&GND_(4/5)
Document Number
Rev

Sheet
1
23
of
A00
95
SSID = S.B
REQUIRED STRAPS
R2408
R2407
R2409
PCI_AD25 (20)
PCI_AD26 (20)
PCI_AD27 (20)
R2405
R2406
(20,37) PCLK_KBC
1 R2415
1 R2414
1 R2413
1 R2412
1 R2411
2
2K2R2J-2-GP
2K2R2J-2-GP
2K2R2J-2-GP
2K2R2J-2-GP
10KR2J-3-GP
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCLK_FW H
DYDYDYDYDY
2K2R2J-2-GP
2
2K2R2F-GP
2
2K2R2F-GP
10KR2J-3-GP
2
10KR2J-3-GP
R2404
R2403
R2402
VDDR_SEL (20,51)
DY DY DY DY
10KR2J-3-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
10KR2J-3-GP
9/22
PCI_AD23 (20)
Removed
9/23
C
1119-1
DYDYDYDY
(20)
(20)
(20)
(20,70)
DEBUG STRAPS
9/15
+3.3V_ALW
9/15
R2401
+3.3V_RUN
(20) LPCCLK1
R2424
R2422
R2423
R2420
R2421
R2419
2
10KR2J-3-GP
2
2K2R2F-GP
2
2K2R2F-GP
10KR2J-3-GP
2
10KR2J-3-GP
DY
10KR2J-3-GP
2
10KR2J-3-GP
DY
10KR2J-3-GP
10KR2J-3-GP
DY
R2418
R2417
R2416
(21) SB_GPO200
(21) SB_GPO199
(21) ACZ_SDATAOUT_R
USE this pin to determine INT/EXT CLK
REQUIRED SYSTEM STRAPS

AZ_SDOUT#
PULL
HIGH
LOW POWER
MODE
PCI_CLK1
Allow
PCIE GEN2
PCI_CLK2
WatchDOG
(NB_PWRGD)
ENABLED
PCLK_KBC
PCLK_FWH
(PCI_CLK3)
(PCI_CLK4)
USE
DEBUG
STRAPS
non_Fusion
CLOCK mode
DEFAULT
LPCCLK0
ENABLE EC
DEFAULT
LPCCLK1
SB_GPO200 , SB_GPO199
ROM TYPE:
CLKGEN
ENABLED
H, H = Reserved
(Use Internal)
H, L = SPI ROM
PULL
HIGH
DEFAULT
PULL
LOW
PERFORMANCE
MODE
DEFAULT
Force
PCIE GEN1
WatchDog
(NB_PWRGD)
DISABLED
IGNORE
DEBUG
STRAPS
DEFAULT
DEFAULT
Fusion
CLOCK mode
DISABLE EC
DEFAULT
CLKGEN
DISABLED
L, H = LPC ROM
(Use External)
L, L = FWH ROM
DEFAULT
PULL
LOW
PCI_AD27 PCI_AD26
PCI_AD25
PCI_AD24
USE PCI
PLL
Disable ILA
AUTORUN
USE FC
PLL
USE DEFAULT
PCIE STRAPS Disable PCI
MEM BOOT
PCI_AD23
(DEFAULT)
(DEFAULT)
(DEFAULT)
(DEFAULT)
(DEFAULT)
BYPASS
PCI PLL
Enable ILA
AUTORUN
BYPASS FC
PLL
USE EEPROM
PCIE STRAPS
Enable PCI
MEM BOOT
Note: SB820M has 15K internal PU FOR PCI_AD[27:23]
<Core Design>
Wistron Corporation

Title
SB820M_STRAPPING_(5/5)
Size
A3
Document Number
Date:
Rev

Sheet
1
24
of
A00
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Reserved
Size
Document Number
Rev

5
Sheet
25
of
1
A00
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
Reserved
Document Number
Rev

Date:
5
Sheet
1
26
of
A00
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Reserved
Size
Document Number
Rev

Date:
5
Sheet
1
27
of
A00
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
Reserved
Rev

Sheet
1
28
of
A00
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
Reserved
Rev

Sheet
1
29
of
A00
95
SSID = AUDIO
3.3V, 25mA
+AVDD
(21) SB_AZ_CODEC_SYNC
(21) SB_AZ_CODEC_RST#
TP3001
TP3002
+3.3V_RUN
1
1
SB_AZ_CODEC_SYNC
10
SB_AZ_CODEC_RST#
11
AUD_DMIC_CLK
AUD_DMIC_IN0
2
4
HDA_SDO
HDA_SYNC
48
R3008
10KR2J-3-GP
AMP_MUTE#
(37) AMP_MUTE#
47
C3014
SC2D2U6D3V3KX-GP
35
EAPD
36
PUMP_CAPP
11/9
42
49
C3010
SC10U10V5ZY-1GP
C3009
SC1U10V3KX-3GP
1
2
C3008
SCD1U10V2KX-5GP
1
2
AUD_VREFOUT_B
R3005
R3006
AUD_INT_MIC_R_L
2 60D4R2F-GP
2 60D4R2F-GP
1
1
C3011 1
AUD_VREFOUT_C
INT_MIC_L_R
(60)
(60)
(60)
2 2K2R2J-2-GP
9/17
1129-2
C3012
AUD_SPK_L+ (60)
AUD_SPK_L- (60)
AUD_SPK_RAUD_SPK_R+
AUD_SPK_RAUD_SPK_R+
(60)
(60)
2SCD1U10V2KX-5GP
SB_SPKR_R
2
SCD1U10V2KX-5GP
KBC_BEEP_R
C3013
R3009
120KR2F-L-GP
1
2
1
2
R3010
499KR2F-1-GP
From SB
ACZ_SPKR
(21)
KBC_BEEP (37)
From EC
AUD_PC_BEEP
AUD_PC_BEEP
Trace width>15 mils
12
PC_BEEP
CAP+
(60)
AUD_HP1_JACK_L2
AUD_HP1_JACK_R2
SC1U10V3KX-3GP
R3007 1
AUD_SPK_L+
AUD_SPK_L-
17
18
PORT_F_L
PORT_F_R
25
MONO_OUT
33
30
26
AUD_EXT_MIC_L (60)
AUD_EXT_MIC_R (60)
15
16
PORT_E_L
PORT_E_R
CAP-
AUD_AGND
AUD_HP1_JACK_L
AUD_HP1_JACK_R
43
44
SPKR_PORT_D_RSPKR_PORT_D_R+
PUMP_CAPN
AMP_MUTE#
AUD_EXT_MIC_L
AUD_EXT_MIC_R
AUD_VREFOUT_B
40
41
SPKR_PORT_D_L+
SPKR_PORT_D_L-
DMIC1/GPIO0/SPDIF_OUT_1
SPDIF_OUT_0
28
29
23
19
20
24
PORT_C_L
PORT_C_R
VREFOUT_C
DMIC_CLK/GPIO1
DMIC0/GPIO2
AUD_SENSE_A
AUD_SENSE_B
31
32
HP1_PORT_B_L
HP1_PORT_B_R
HDA_RST#
46
HP0_PORT_A_L
HP0_PORT_A_R
VREFOUT_A_OR_F
13
14
DVSS
AVSS
AVSS
AVSS
VREFFILT
CAP2
PVSS
V-
GND
VREG
22
AUD_CAP2
21
AUD_VREFFLT
34
AUD_V_B
37
AUD_VREG
92HD79B1A5NLGXTAX-GP
AUD_AGND
AUD_AGND
AUD_AGND
AUD_AGND
Reserve
AUD_HP1_JACK_R2
AUD_AGND
AUD_HP1_JACK_L2
Close to codec
DY
Q3002
P8503BMG-GP
(21) SB_AZ_CODEC_SDOUT
HDA_SDI
R3004
0R0603-PAD
DY
CODEC_Q2602_04
CODEC_Q2601_03
+15V_ALW
R3013
DY
DY
P8503BMG-GP
Q3005
P8503BMG-GP
Q3004
Q3003
P8503BMG-GP
SB_AZ_CODEC_SDOUT
SENSE_A
SENSE_B
HDA_BITCLK
0R0603-PAD
C3015
SC1U6D3V2KX-GP
SB_SDIN_CODEC_C0
SB_AZ_CODEC_BITCLK
+5V_RUN
R3003
1
2 33R2J-2-GP
9/23
R3001 1
(21) SB_SDIN_CODEC
C3018
SC10U6D3V5MX-3GP
(21) SB_AZ_CODEC_BITCLK
39
45
PVDD
PVDD
1231-1
+PVDD
1.4A
AUD_AGND
DVDD
DVDD_IO
0R0603-PAD
C3017
SC10U6D3V5MX-3GP
27
38
AVDD
AVDD
DVDD_CORE
C3006
SC1U10V3KX-3GP
U3001
1
R3002
1
C3003
SC10U6D3V5KX-1GP
1
2
1
2
AUD_DVDDCORE
C3004
SCD1U10V2KX-5GP
1
2
1
2
C3001
SCD1U10V2KX-5GP
C3002
SC1U6D3V2KX-GP
Close to codec
84mA
C3005
SCD1U10V2KX-5GP
Close to codec
D
+5V_RUN
1231-1
+3.3V_RUN
C3016
SC4D7U6D3V3KX-GP
+3.3V_RUN
DY100KR2J-1-GP
2
Azalia I/F EMI
HP_CODEC_MUTE
R3015
47R2J-2-GP
1231-1
AUD_HP1_JD#
(60)
R3017
AMP_MUTE#
DY
2N7002A-7-GP
0R0603-PAD
R3019
2K49R2F-GP
0R0603-PAD
C3019
SC1000P50V3JN-GP-U
2
R3022
39K2R2F-L-GP
1
R3021
20KR2F-L-GP
EXT_MIC_JD# (60)
2 R3020
0R0603-PAD
AUD_SENSE_B
Q3001
R3014
2
+AVDD
2
AUD_SENSE_A
C3020
SCD1U10V2KX-5GP
SB_AZ_CODEC_SDOUT1
1
R3016
20KR2F-L-GP
2
R3018
2K49R2F-GP
DY
+AVDD
DY
SB_AZ_CODEC_SDOUT
AUD_AGND
AUD_AGND
Close to Pin13
AUD_AGND
Close to Pin14
<Core Design>
Wistron Corporation
Title
Audio Codec 92HD79B1

Size
A2
Date:
5
Document Number
Rev

of
Sheet
30
A00
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
Reserved
Rev

Sheet
1
31
of
A00
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Reserved
Size
A4
Document Number

5
Rev
A00

2
Sheet
32
of
1
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
Reserved
Rev

Sheet
1
33
of
A00
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
Reserved
Rev

Sheet
1
34
of
A00
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
A
Document Number
Reserved
Rev

Sheet
E
35
of
A00
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
Reserved
Rev

Sheet
1
36
of
A00
95
(76) 8103_GPO
PM_SLP_S3#
2
R3715
(42,49) 1.5V_RUN_EN
(66) PWRLED#
(66) PWR_BTN_LED#
(66) AMBER_LED#_KBC
(68) KB_LED_BL_DET
(21) KBC_RSMRST#
(21,49) PM_SLP_S5#
(46,50) 3V_5V_POK
(39,41) EC_RESET_OUT
(62) EC_SPI_WP#_R
C3717
SCD1U10V2KX-5GP
64
95
93
94
PCB_VER0
119
KBC_BIOS_ID
1
6
DIS2K2R2J-2-GP
109
PCB_VER1
120
65
PWR_BTN_LED#
66
16
17
20
21
KBC_PLTRST_DELAY# 22
23
SYS_PWRGD
1
24
0R0402-PAD
25
EC_SHUTDOWN#
26
27
28
73
74
75
110
2
R3747
0105-4
(54) BLON_OUT
(47) IMVP_VR_ON
(76) PSID_DISABLE#
(89) GFX_CORE_EN
(90) 1.0V_RUN_VGA_EN
(63) USB_PWR_EN#
GPI94
GPI95
GPI96
GPI97
GPIO74/SDA2
GPIO73/SCL2
GPIO22/SDA1
GPIO17/SCL1
SMB
2
0R2J-2-GP
ECSCI#_KBC
PANEL_BKEN
ECSWI#_KBC
KBC_SCL1
KBC_SDA1
DY 2
1
(55) C3725
R3708 1
SCD1U10V2KX-5GP
DY
KBC_ON_R# 2
THERM_SCL (39)
+KBC_PWR
G
D
Q3705
2N7002A-7-GP
10KR2J-3-GP
Close to Q3703
DY 0R2J-2-GP
2
D3703
BAT54C-U-GP
0113-1
2
10KR2J-3-GP
BAT_SDA (44,45)
BAT_SCL (44,45)
1231-1
+KBC_PWR
RN3704
SP
GPIO66/G_PWM
GPIO77
GPIO76/SHBM
GPIO75
GPIO81
SPI
GPIO
81
84
83
82
91
1.8V_VGA_RUN_EN
KBC_SCL1
KBC_SDA1
BAT_SDA
BAT_SCL
(52,90)
8
7
6
5
ECSMI#_KBC
NB_VDDC_EN 1
TP3714
S5_ENABLE
1
2
3
4
1
R3723
1
R3724
BLUETOOTH_EN
1
R3726
IMVP_VR_ON
1
R3727
KCOL0
SRN4K7J-10-GP
BLUETOOTH_EN (73)
WIFI_RF_EN (76)
D3701
1
(21) SIO_EXT_WAKE#
AC_IN#_KBC
3
ECSWI#_KBC
GPO83/SOUT_CR/BADDR1
GPIO87/SIN_CR
GPO84/BADDR0
SER/IR
GPIO16
GPIO34
GPIO36
111
113
112
2
1
BAS16PT-GP
D3704
3
4
+3.3V_RUN
ECSCI#_KBC
2
KBC_VCORF
AGND
SC1U10V3KX-3GP
44
E51_RxD
BAS16PT-GP
D3705
1
(21) SIO_EXT_SMI#
SIO_RCIN#
DY
DY
0R2J-2-GP
1
DY
KBC_PLTRST_DELAY#
2 R3739
10KR2J-3-GP
10KR2J-3-GP
2
10KR2J-3-GP
Internal PU
VDDC_PWRGD
1
R3713
BAS16PT-GP
1119-1
DY
R3711
KBC_AGND
1
R3710
SIO_A20GATE
3ECSMI#_KBC
1
10KR2J-3-GP
R3753
1119-1
9/11
EC_RESET_OUT
1
R3752
S0_LKG_DET
100KR2J-1-GP
1
R3754
100KR2J-1-GP
11/10
PLTRST#_EC (20)
1
9/24
C3713
SC470P50V3JN-2GP
+3.3V_RTC_LDO
DY
2
100KR2J-1-GP
2 OF 2
KCOL[0..16]
77
1
C3716
(30) AMP_MUTE#
(62)
(62)
(62)
(62)
0112-1
2
(45) AD_IA
GPIO02
79
30
32KX2
GPIO55/CLKOUT
GPIO14/TB1
GPIO20/TA2
GPIO56/TA1
GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM
0208-2
THERMTRIP_VGA_GATE
EC_SPI_DI
EC_SPI_DO
EC_SPI_CS#
EC_SPI_CLK
1
R3737
2
33R2J-2-GP
EC_SPI_CLK_C
13
12
11
10
71
72
GPIO12/PSDAT3
GPIO25/PSCLK3
GPIO27/PSDAT2
GPIO26/PSCLK2
GPIO35/PSDAT1
GPIO37/PSCLK1
86
87
90
92
F_SDI
F_SDO
F_CS0#
F_SCK
KBC
53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33
KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17 1
FIU
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
54
55
56
57
58
59
60
61
KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
VCC_POR#
85
ECRST#
(68)
TP3705
KROW[0..7]
PS/2
1117-5
1 AD_IA_KBC
R3757
C3724
0R0402-PAD
SC10P50V2JN-4GP
63
117
31
32
118
62
EC_SPI_DI
EC_SPI_DO
EC_SPI_CS#
EC_SPI_CLK
KBSOUT0/JENK#
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KBSOUT4/JEN0#
KBSOUT5/TDO
KBSOUT6/RDY#
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17
(68)
2
1
1
2
DY
10KR2J-3-GP
R3735
10KR2J-3-GP
R3734
DY
TP3713
(68) KB_DET#
(54) LCD_CBL_DET#
(82) THERMTRIP_VGA_GATE
(54) LCD_TST
(68) TPDATA
(68) TPCLK
1
2
10KR2J-3-GP
R3731
10KR2J-3-GP
R3730
R3733
10KR2J-3-GP
0
1
0
1
32KX1/32KCLKIN
DY
2
SC10P50V2JN-4GP
10/7
(41,47,48,51) IMVP_PWRGD
(21) PM_PWRBTN#
(54) LCD_TST_EN
(30) KBC_BEEP
(66) WHITE_LED#_KBC
(68) KB_BL_CTRL
+3.3V_RUN
0
0
1
1
10KR2J-3-GP
SRN100KJ-6-GP
(20) RTCCLK_KBC
0
0
0
0
10KR2J-3-GP
2
1231-1
(21) SIO_EXT_SCI#
U3701B
X00
X01
X02
A00
10KR2J-3-GP
2
100KR2J-1-GP
KBC_PWRBTN#
1
R3716
PCB_VER0
PCB_VER1
PCB_VER2
10KR2J-3-GP
2
R3749
LCD_CBL_DET#
KB_DET#
2
(90)
PM_LAN_ENABLE (76)
VDDC_PWRGD (41,48)
S5_ENABLE (42)
R3732
0R2J-2-GP
1
2KBC_AGND 103
GND
GND
GND
GND
GND
GND
116
89
78
45
18
5
E51_TxD (76)
E51_RxD (76)
3.3V_RUN_VGA_EN
114
14
15
DY
VER0
DY
RN3702
E51_TxD
E51_RxD
Remove reserved crystal.
MB VERSION
VER2 VER1
ID
AC_IN#_KBC
1205-1
KBC_SDA1
KBC_SCL1
9/14
DY
AC_IN# (45)
R3750
C3720
SCD1U10V2KX-5GP
9/15
0R2J-2-GP
PLTRST#_EC
R3729
10KR2J-3-GP
EC_SHUTDOWN#
R3756
G
DMN66D0LDW-7-GP
KBC_ON#
Q3703
SI2301CDS-T1-GE3-GP
(39) THERM_SDA
U3702
PCLK_KBC (20,24)
LPC_LFRAME# (20,70)
LPC_LAD0 (20,70)
LPC_LAD1 (20,70)
LPC_LAD2 (20,70)
LPC_LAD3 (20,70)
INT_SERIRQ (20)
PM_CLKRUN# (20)
SIO_RCIN# (21)
SIO_A20GATE (21)
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
R3704
10KR2J-3-GP
+3.3V_RTC_LDO
DY
+KBC_PWR
PLTRST#_EC
1
R3702
(76)
WWAN_RADIO_DIS#
1
R3714
68
67
69
70
2
2
D3702
BAT54C-U-GP
LPC
124
7
2
3
126
127
128
1
125
8
122
121
29
9
123
+3.3V_RTC_LDO
(66) KBC_PWRBTN#
BAT_IN# (44)
9/24
VCORF
NPCE781BA0DX-GP
DY
A/D
D/A
GPIO01/TB2
GPIO03
GPIO06
GPIO07
GPIO23
GPIO24
GPIO30
GPIO31
GPIO32/D_PWM
GPIO33/H_PWM
GPIO40/F_PWM
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO45/E_PWM
GPIO46/TRST#
GPIO47
GPIO50/TDO
GPIO51
GPIO52/RDY#
GPIO53
GPIO70
GPIO71
GPIO72
GPO82/TRIS#
1 OF 2
GPIO10/LPCPD#
LRESET#
LCLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
SERIRQ
GPIO11/CLKRUN#
KBRST#
GA20
ECSCI#/GPIO54
GPIO65/SMI#
GPIO67/PWUREQ#
KBC_PWRBTN_EC#
1
0R2J-2-GP
1
2
DY
R3709
2
GPIO41
VREF
GPI90/AD0
GPI91/AD1
GPI92/AD2
GPI93/AD3
GPIO05
GPIO04
R3703
100KR2J-1-GP
1120-5
C3703
SC2D2U10V3KX-1GP
+3.3V_RUN
80
102
AVCC
VDD
115
88
76
46
19
VCC
VCC
VCC
VCC
VCC
1
2
1
2
C3709
SC2D2U6D3V3KX-GP
C3710
SCD1U10V2KX-5GP
101
105
106
107
KB_DET_KBC
KBC_PWRBTN_EC#
AC_IN#_KBC
(69) LID_CLOSE#
1229-1
PCB_VER2
+KBC_PWR
0108-5
DISCRETE_ID
1R3705
KBC_THERMTRIP#
10KR2J-3-GP
1
0R2J-2-GP
97
98
99
100
108
96
1216-2
PD for Berry Keyboard Matrix

PU for DJ Keyboard Matrix
DY
DY
1
C3718
AD_IA_KBC
S0_LKG_DET
2
2
R3751
2
SCD1U10V2KX-5GP
R3712
1
2
2K2R2J-2-GP
H_THERMTRIP#
(10) CPU_PROCHOT#_EC
PM_SLP_S5#
11/6
+KBC_PWR
PU for Discrete
Internal PL for UMA
U3701A
+KBC_PWR
(21,41,42,49,52,89)
3.3V, 23mA
104
10KR2J-3-GP
0108-5
C3708
SCD1U10V2KX-5GP
1
2
C3707
SCD1U10V2KX-5GP
1
2
R3707
(82) THERMTRIP_VGA#
(76) PSID_EC
(10,21,39,42,82)
1119-1
KBC_AGND
+KBC_PWR
Reserved
C3706
SCD1U10V2KX-5GP
1
2
DY
SSID = KBC
3.3V, 2mA
VBAT
2 BLM18AG601SN-3GP
C3705
SCD1U10V2KX-5GP
C3704
SCD1U10V2KX-5GP
1
2
C3701
SC2D2U6D3V3KX-GP
L3701 1
3
+3.3V_RUN
CAP close to VCC-GND pin pair
+3.3V_RTC_LDO
C3711
DY
C3702
SCD1U10V2KX-5GP
2
1
R3701
1
2
0R3J-0-U-GP
5
9/16
+KBC_PWR
NPCE781BA0DX-GP
DY
KBC CLK
PCLK_KBC
EMI
2
+3.3V_RUN
4K7R2J-2-GP
PSID_EC
1
2
SC10P50V2JN-4GP
1
C3719
SC56P50V2JN-2GP
C3722
1
DY
<Core Design>
4K7R2J-2-GP
1231-1
1
R3744
(39,42) PURE_HW_SHUTDOWN#
2
DY
1
C3723
SC56P50V2JN-2GP
VCC
RESET#
ECRST#
G690L293T73UF-GP
DY
SC56P50V2JN-2GP
R3743
GND
2
SCD1U10V2KX-5GP
0108-5
Wistron Corporation
C3721
1
C3715
+KBC_PWR
U3703
+PWR_SRC
1117-5
1217-1
0108-4
1118-2
10/7
ECRST#_C
2
0R0402-PAD
DY
2
E51_TxD
DYR3741

C3714
SC1U10V3KX-3GP
Title
Q3701
PMBS3906-GP
KBC Nuvoton NPCE781BA0DX Rev
Size
A2
Document Number
Date:
A00

Sheet
37
of
95
(Blanking)
C
<Core Design>
Wistron Corporation

Title
Size
A4
Document Number
Rev
Berry AMD Discrete/UMA A00

5
Reserved
Sheet
38
of
1
95
+5V_RUN
SSID = Thermal
+5V_RUN
+3.3V_RUN
R3901
10KR2J-3-GP
R3915
DY 2
1
2
DY
0R2J-2-GP
1
2
1
2
C3902
SCD1U10V2KX-5GP
R3916
C3901
SC10U10V5KX-2GP
10KR2J-3-GP
5V, 600mA
D3901
EMC2102_FAN_TACH_1
EMC2102_FAN_TACH (58)
9/25
CH751H-40PT-GP
EMC2102_FAN_DRIVE
EMC2102_FAN_DRIVE
(58)
RN3901
3
4
2
1
+3.3V_RUN
SRN4K7J-8-GP
23
24
25
26
22
SMDATA
SMCLK
VDD_5Vb
FANb
DP1
ALERT#
19
ALERT#
CLK_IN
18
CLK_32K
EMC2102
DN3
RESET#
16
EMC2102_DP3
DP3
NC#15
15
0R2J-2-GP
EC_RESET_OUT (37,41)
+3.3V_RUN
1
2
+3.3V_RUN
RN3902
SRN10KJ-5-GP
R3906
DY2
0R2J-2-GP
H_THERMTRIP# (10,21,37,42,82)
1119-1
Q3902
2N7002A-7-GP
R3909
10KR2J-3-GP
THERMAL_P_HW _SHT
+3.3V_RUN
C3908
SCD1U10V2KX-5GP
PURE_HW _SHUTDOW N#
R3911
10KR2F-2-GP
(37,42)
G
S
+KBC_PW R
R3908
10KR2J-3-GP
R3910
0R0402-PAD
1
2
GND = Fan is OFF

OPEN = Fan is at 60% full-scale
+3.3V = Fan is at 75% full-scale
DY2
EMC2102_FAN_mode
Both DN3 and DP3 routing 10 mil

trace width and 10 mil spacing.
B
R3914
DY
EM2102_RESET#
R3907
1
2
10KR2J-3-GP
GND = Internal Oscillator Selected

+3.3V = External 32.768kHz Clock Selected
0226-1
+3.3V_RUN
3.HW T8 sensor
Layout notice :
TALERT# (10,21)
4
3
14
13
12
11
10
EMC2102_SHDN
2 0R2J-2-GP
DY
0105-4 Remove
THERM_POW ER_OK#
THERMTRIP#
THERM_SYS_SHDN#
DY
1
2
10KR2J-3-GP
C3907
SC470P50V3JN-2GP
EMC2102-DZK-GP
R3905
2
1
C3906
SC470P50V3JN-2GP
GND = Channel 1
OPEN = Channel 3
+3.3V = Disabled
R3903
POWER_OK#
EMC2102_DN3
THERMTRIP#
17
SYS_SHDN#
CLK_SEL
TRIP_SET
DP2
FAN_MODE
NC#8
2
2
DY
FANa
20
DN2
2.VGA Sensor
Layout notice :
VGA_THERMDA
27
28
TACH
29
21
GND
Both VGA_THERMDA and VGA_THERMDC routing

10 mil trace width and 10 mil spacing.
Q3901
PMBS3904-1-GP
NC#21
DN1
0107-3
UMA
GND
(82) VGA_THERMDA
Q3904
PMBS3904-1-GP
VDD_3V
C3905
SC470P50V3JN-2GP
0107-5
Removed
VGA_THERMDC
+3.3V_RUN
SHDN_SEL
(82) VGA_THERMDC
C3904
SC470P50V3JN-2GP
U3901
C3903
SCD1U10V2KX-5GP
DY
(10) H_THERMDA
EMC2102_VDD_3D3
C3910
SC470P50V3JN-2GP
(10) H_THERMDC
1.For CPU Sensor
Layout notice :
Both H_THERMDA and THERMDC routing
10 mil trace width and 10 mil spacing
Pleace near to CPU side
THERM_SCL (37)
THERM_SDA (37)
3.3V, 0.75mA
VDD_5Va
R3902
49D9R2F-GP
+3.3V_RUN
V_DEGREE
R3912
2K37R2F-GP
C3909
SCD1U10V2KX-5GP
TRIP_SET Pin Voltage

V_DEGREE=(((Degree-75)/21)
T8 shutdown is 88 deg-C.
32K suspend clock output

Q3903
2N7002A-7-GP
R3913
CLK_32K_R
CLK_32K
10R2J-2-GP
DY
2
<Core Design>
(20) RTC_CLK
Wistron Corporation
C3911
SC4D7P50V2CN-1GP

(42) RUN_ENABLE
Title
Size
A3
Date:
5
Thermal/Fan
Controllor EMC2102
Document Number
Rev
A00

Sheet
1
39
of
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
Reserved
Rev

Sheet
1
40
of
A00
95
SSID = Reset.Suspend
+3.3V_RUN
BAT54APT-GP
NC#1
A
GND
1
2
1
2
3
VCC
DY
(37,39) EC_RESET_OUT
(37,47,48,51) IMVP_PWRGD
C4102
NB_PWRGD_IN (13)
(21) NB_PWRGD
2
C
0R0402-PAD
SB_PWRGD_R
0105-4
2
R4106
0R0402-PAD
BAT54APT-GP
1
DY
R4104
C4101
VCC
SB_PWRGD (7,21)
D4102
1
NC#1
A
GND
SNAUC1G17DCKR-1GP
SNAUC1G17DCKR-1GP
C
1
2
3
SB_PWRGD_D
CH751H-40PT-GP
U4102
U4101
R4103
(21,37,42,49,52,89) PM_SLP_S3#
1DY
D4101
2
300R2J-4-GP
R4102
(37,48) VDDC_PWRGD
DY
+3.3V_ALW
R4101
D4103
1
10KR2J-3-GP
9/28
100KR2J-1-GP
+3.3V_RUN
+1.8V_RUN
+1.8V_RUN
VDDC_PWRGD
2
SCD1U10V2KX-5GP
IMVP_PWRGD
2
SCD1U10V2KX-5GP
1116-5
R4105
1
(37,48) VDDC_PWRGD
DY
EC_RESET_OUT (37,39)
B
0R2J-2-GP
<Core Design>
Wistron Corporation

Title
Power On Logic
Document Number
Size
A4

5
Rev

2
Sheet
41
of
1
A00
95
SSID = Reset.Suspend
E
H_THERMTRIP# (10,21,37,39,82)
R4201
2
D4201
CHT2222APT-GP
DY
PURE_HW _SHUTDOW N#
(37,39)
1
R4203
200KR2J-L1-GP
BAS16PT-GP
0226-1
DY
0222-2
1
R4202
2
1KR2J-1-GP
S5_ENABLE (37)
+15V_ALW
1
2
3
4
AO4468-GP
1117-2
Remove
C4202
SC10U10V5KX-2GP
10KR2J-3-GP
5V_RUN_ENABLE
S
S
S
G
U4207
DMN66D0LDW -7-GP
U4201
D
D
D
D
R4206
D G S
+5V_RUN
8
7
6
5
R4205
100KR2J-1-GP
+5V_ALW
+3.3V_RTC_LDO
100KR2J-1-GP
R4204
1
2RUN_ON_5V#
S G D
C4201
SC6800P25V2KX-1GP
RUN_ENABLE
PM_SLP_S3#
(39) RUN_ENABLE
+3.3V_ALW
+3.3V_RUN
8
7
6
5
U4202
D
D
D
D
R4207
1
2
3
4
AO4468-GP
3.3V_RUN_ENABLE
C4204
SC10U6D3V5KX-1GP
S
S
S
G
(21,37,41,49,52,89)
DYQ4201
(46) 3V_5V_EN
C4217
SCD047U10V2KX-2GP
H_PW RGD_R
1KR2J-1-GP
C4216
DY
SCD1U10V2KX-5GP
(10,20) CPU_LDT_PW RGD
Run Power
10KR2J-3-GP
C4203
SCD01U50V2KX-1GP
+1.5V_RUN
R4226
10R3J-3-GP
DY
+3.3V_RTC_LDO
100KR2J-1-GP
R4211
1
2RUN_ON_1.5V#
RUN_ON_1.5V#
+15V_ALW
Q4207
2N7002A-7-GP
DY
+1.5V_RUN
8
7
6
5
S G D
U4204
D
D
D
D
S
S
S
G
AO4468-GP
1.5V_RUN_ENABLE_R
(37,49) 1.5V_RUN_EN
1.5V_RUN_ENABLE
R4213
0R0402-PAD
C4207
SCD01U50V2KX-1GP
1
2
3
4
SC10U6D3V5KX-1GP
+1.5V_SUS
R4212
100KR2J-1-GP
U4209
DMN66D0LDW -7-GP
C4208
2
1
D G S
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
Power Plane Enable
Document Number
Rev

Sheet
1
42
A00
of
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
Reserved
Rev

Sheet
1
43
of
A00
95
SSID = BATT CONN
Batt Connecter
PC4402
SCD1U50V3KX-GP
GAP-CLOSE-PWR-3-GP
10/7
PC4401
SC2200P50V2KX-2GP
(45) BATT_SENSE
PG4401
1
+VCHGR
2
BATT1
PRN4401
2
3
4
5
6
7
8
9
11
PBAT_SMBCLK1
PBAT_SMBDAT1
PBAT_PRES1#
100R2J-2-GP
2
PR4402
1BAT_ALERT
AFTP4401
DY
DY
2
470KR2J-2-GP
SRN100J-3-GP
C4401
SC47P50V2JN-3GP
+KBC_PWR
PR4401
1
1
2
SC47P50V2JN-3GP
C4402
10
1
4
3
(37,45) BAT_SCL
(37,45) BAT_SDA
(37) BAT_IN#
ALP-CON9-2-GP-U
0222-2
20.81316.009
For actual location, need to be swap all pin
Close to Batt Connector
PD4401
BAV99-4-GP
PD4403
BAV99-4-GP
PD4402
BAV99-4-GP
PBAT_PRES1#
PBAT_SMBDAT1
PBAT_SMBCLK1
+VCHGR
BAT_SCL
1
1
1
1
BAT_SDA
BAT_IN#
AFTP4402
AFTP4403
AFTP4404
AFTP4405
+KBC_PWR
<Core Design>
Wistron Corporation

Title
Document Number
Size
A4
4
Rev

5
BATT CONN
Sheet
44
of
1
A00
95
SSID = Charger
modify +VCHGR
+SDC_IN
15
2
PC4523
1
GND
VFB
PR4528
BAT_SENSE 2
1
0R0402-PAD
2
GAP-CLOSE-PWR-3-GP
PG4505
1
PC4509
SCD1U50V3KX-GP
BQ24745_CSOP
DY
CHG_AGND
CHG_AGND
DY
DY
1
0R0402-PAD
PR4529
PD4502
1SMA18AT3G-GP
PC4519
SCD1U50V3KX-GP
A
K
PC4518
SC10U25V6KX-1GP
2
1
DY
DY
BQ24745_PR4505
BQ24745_CSON
BATT_SENSE (44)
1
PC4508
SC10U25V6KX-1GP
2
1
1
2
PU4504
SI4800BDY-T1-GP
PC4507
SC10U25V6KX-1GP
2
1
1
PR4523
EC4502
SCD1U25V2ZY-1GP
EC4501
SC2200P50V2KX-2GP
0R0402-PAD
PR4530
1K8R6J-GP
SCD01U50V2KX-1GP
PU4501
BQ24745RHDR-GP
16
PC4529
SC1U6D3V2KX-GP
NC#16
PC4528
CHG_AGND
FBO
EAI
EAO
VREF
CE
GND
29
DY
2
0R0402-PAD
DY
DY
6
BQ24745_EAI
5
BQ24745_EAO
4
BQ24745_REF
3
2 BQ24745_CE 7
12
PR4527
PC4527 SC56P50V2JN-2GP
PC4530
SCD1U10V2KX-4GP
PC4522
PR4526
2SC2200P50V2KX-2GP
2
1PR4526_01
2 7K5R2F-1-GP
1
PC4521
PC4525
SC150P50V2JN-3GP
1
2
+VCHGR
PR4519
VICM
0114-1
65MOS
G
S
S
S
BQ24745_CSOP_1
17
IND-5D6UH-52-GP
4
3
2
1
4K7R2J-2-GP
18
GAP-CLOSE-PWR-3-GP
PG4504
1
5
6
7
8
D
D
D
D
DY
PR4522
200KR2F-L-GP
1
2
DY
SCD1U50V3KX-GP
2
CSOP
CSON
GAP-CLOSE-PWR-3-GP
2
PG4501
1
2
1
2
PC4514
SC220P50V2JN-3GP
SCD1U50V3KX-GP
PGND
+VCHGR1
2
D01R2512F-4-GP
19
PC4520
SCD1U50V3KX-GP
1
2
NC#14
CHG_AGND
BQ24745_VICM
BQ24745_FBO
PL4501
1
PC4517
SC10U25V6KX-1GP
2
1
20
PC4513
SC3300P50V3KX-1GP
BQ24745_LX1
PC4516
SC10U25V6KX-1GP
2
1
LGATE
DY
2
1
PC4515
SC10U25V6KX-1GP
2
1
SDA
PC4506
SC1U6D3V2KX-GP
1
2
PC4512
SCD1U50V3KX-GP
PR4524
0R2J-2-GP
PR4518
0R0603-PAD
BQ24745_PHASE_GND
BQ24745_LGATE_1
D
D
D
D
(37,44) BAT_SDA
23
PC4531
SCD1U50V3KX-GP
UGATE
SCL
modify +VCHGR
1124 Change P/N
PG4509
GAP-CLOSE-PWR-3-GP
1
2
10
BQ24745_CHARGER_UGATE
Charger Current=1.4~3.6A
2
PG4508
BAT_SDA_1
1
GAP-CLOSE-PWR-3-GP
24
65MOS
1117-7
BAT_SCL_1
1
GAP-CLOSE-PWR-3-GP
BQ24745_BOOT_1
1
2BQ24745_BST1 K
A
BQ24745_LDO
0R0603-PAD
SD103AWS-1-GP
DY
PG4510
GAP-CLOSE-PWR-3-GP
1
2
2
PG4507
25
21
DY
CHG_AGND
1
2
PC4511
SCD1U50V3KX-GP
G
S
S
S
BOOT
VDDP
ACOK
GAP-CLOSE-PWR-3-GP
PG4506
1
2
1
DY
CHG_AGND
PR4517
PU4505
SI4800BDY-T1-GP
13
PR4506
470KR2J-2-GP
CHAGER_SRC
4
3
2
1
BQ24745_ACOK
CHG_AGND
SCD01U50V2KX-1GP
2
1
1
PR4521
PC4524
1
SC220P50V2JN-3GP
2
1BQ24745_FBO1
2
PR4525
1
8K45R2F-2-GP
27
26
SCD1U50V3KX-GP
BQ24745_CSSN
BQ24745_ICOUT
DY
5
6
7
8
PR4512
2
1
0R0402-PAD
14
PC4505
BQ24745_CSSP 1
2
PR4513
33R3J-2-GP
2
1
CSSN
ICOUT
VDDSMB
28
ACIN
Id=-12A
Qg=-25nC
Rdson=10~38mohm
CHAGER_SRC
PD4501
PC4526
1
2
PR4533_02
CSSP
0R2J-2-GP
DY
PR4524_03
PR4520
15K8R3F-GP
2
1
PR4501
PR4507
0R2J-2-GP
PC4532
SCD1U25V2ZY-1GP
BQ24745_ACIN
DCIN
PHASE
DY
CHG_AGND
22
11
PC4501
SCD1U10V2KX-4GP
(37,44) BAT_SCL
2009/08/04
1
2
PC4504
SCD1U50V3KX-GP
ACAV_IN
DY
CHG_AGND
BQ24745_DCIN
ICREF
PC4503
+KBC_PWR
DY
PR4516
10KR2F-2-GP
1
PR4515
10KR2F-2-GP
2
1
PC4510
SCD01U50V2KX-1GP
1
2
48K7R3F-1-GP
1
BQ24745_REF
1
2
PC4502
SCD1U50V3KX-GP
+VCHGR
PU4503
AO4407A-GP
S
D 8
S
D 7
S
D 6
G
D 5
PG4503
GAP-CLOSE-PWR-3-GP
PR4510
0R2J-2-GP
2
1
2
3
4
+DC_IN_SS
PG4502
0R2J-2-GP
PR4508
2
1
SCD1U50V3KX-GP
PR4514
2
1
2
GAP-CLOSE-PWR-3-GP
PR4505
10KR2F-2-GP
D01R2512F-4-GP
DMN66D0LDW-7-GP
PR4511
0R0402-PAD
(37) AD_IA
PR4504
1
2
10KR2J-3-GP
316KR3F-2-GP
PQ4501
BQ24745_ACOK
PQ4502_05
Id=-12A
PR4513_03
Qg=-25nC
Rdson=10~38mohm
PQ4502_03
PR4509
AO4407A-GP
+PWR_SRC
PR4502
1
2
3
4
PR4503
100KR2J-1-GP
+DC_IN_SS
PU4502
S
S
S
G
8 D
7 D
6 D
5 D
+DC_IN_SS
BQ24745_LDO
CHG_AGND
CHG_AGND
This Resistor
must be 1%
tolerance.
SCD1U25V2ZY-1GP
2
DY
PC4533
2N7002A-7-GP
B
PQ4502
G
ACAV_IN
(37) AC_IN#
<Core Design>
Wistron Corporation
Title
Size
A2
Document Number
Date:
Monday, March 08, 2010
CHARGER BQ24745
Rev
A00

Sheet
1
45
of
95
SSID = PWR.Plane.Regulator_3p3v5v
+3.3V_ALW_2
1
1
2
1
2
PR4622
1
1
51125_EN
PC4606
SC1U25V3KX-1-GP
RT8205B
ASM
PR4603
127KR2F-GP
DY
2
PC4605
SC18P50V2JN-1-GP
TPS51125
DY
PD3903_2
1225-2
+5V_PWR
PD3903_04
PR4622
PG4612
GAP-CLOSE-PWR-3-GP
51125_ENTIP2
GAP-CLOSE-PWR
PG4614
1
2
+15V_ALW
GAP-CLOSE-PWR
PD4602
BAT54S-5-GP
2
PD4601
BAT54S-5-GP
PU4606
DMN66D0LDW-7-GP
GAP-CLOSE-PWR
PG4613
1
2
GAP-CLOSE-PWR
PG4615
1
2
PC4604
SCD1U25V3KX-GP
GAP-CLOSE-PWR
PG4610
1
2
GAP-CLOSE-PWR
PG4611
1
2
PR4601
127KR2F-GP
GAP-CLOSE-PWR
PG4609
2
1
51125_ENTIP1
PQ4601
2N7002A-7-GP
PC4601 DY
SC18P50V2JN-1-GP
(42) 3V_5V_EN
PD3904_1
GAP-CLOSE-PWR
PG4608
1
2
GAP-CLOSE-PWR
PG4607
2
1
51125_ENTRIP
GAP-CLOSE-PWR
PG4605
1
2
PC4603
SCD1U25V3KX-GP
2
PG4604
2
1
GAP-CLOSE-PWR
PG4606
2
1
PC4602
SC1KP50V2KX-1GP
+PWR_SRC
GAP-CLOSE-PWR
PG4603
2
1
PD3903_1
51125_VCLK
PR4602
100KR2J-1-GP
+PWR_SRC_3D3V
51125_VCLK
1
GAP-CLOSE-PWR
PG4602
2
1
+3D3V_PWR
PG4601
+3.3V_ALW
PC4607
SCD1U25V3KX-GP
PC4608
SCD1U25V3KX-GP
GAP-CLOSE-PWR
+PWR_SRC
12
51125_DRVL1
24
51125_VO1
51125_FB1
1
2
1
2
5
6
7
8
1
19
0210-1
+5V_PWR
ENTRIP1
REF
PGND
TONSEL
GND
SKIPSEL
LG1_CP
DY
PR4621
1
0R2J-2-GP
TPS51125
DY
ASM
PR4616
PR4617
1124 Change P/N

PTC4603
ST220U6D3VDM-15GP
GAP-CLOSE-PWR
PG4627
1
2
GAP-CLOSE-PWR
PG4628
2
1
GAP-CLOSE-PWR
PG4629
1
2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
PG4630
1
2
1
PR4612
33KR2F-GP
2
51125_FB1_R
DY
PR4615
21K5R2F-GP
2
Close to VFB Pin (pin2)
2
1
2
PC4626
GAP-CLOSE-PWR
PG4625
1
2
GAP-CLOSE-PWR
PG4624
2
1
17
PC4624
SC18P50V2JN-1-GP
+KBC_PWR
1
3D3V_AUX_S5_5_51125 8
1
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 3.3UH PCMC063T-3R3MN Cyntec 28mohm/30mohm Isat =13.5Arms 68.3R310.20A
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081
H/S: FDS8884 23mohm/30mOhm@4.5Vgs/ 84.08884.037
L/S: FDS6690AS 12mOhm/15mOhm@4.5Vgs/ 84.06690.E37
1 2
VREG3
DY
PR4614
100KR2J-1-GP
DY
GAP-CLOSE-PWR
PG4621
1
2
GAP-CLOSE-PWR
PR4611
0R2J-2-GP
51125_VCLK
18
+5V_ALW2
SC10U10V5KX-2GP
PR4618
1
0R2J-2-GP
PR4619
2
1
0R0402-PAD
2
GAP-CLOSE-PWR
PG4619
1
2
25
SC22U6D3V5MX-2GP
PC4627
+3.3V_ALW_2
1225-3
DY
GAP-CLOSE-PWR-3-GP
PC4625
SC4D7U10V5KX-4GP
51125_VREF
PR4616
1
0R0402-PAD
PR4617
1
0R2J-2-GP
PG4631
1
+3.3V_ALW_2
PC4620
SC560P50V-GP
PG4616
2
15
RT8205BGQW-GP
51125_VREF
GAP-CLOSE-PWR
PG4620
2
1
14
51125_SKIPSEL
+3.3V_ALW_2
51125_ENTIP1
3V_5V_POK
DY
PG4618
2
GAP-CLOSE-PWR
PG4617
1
2
65MOS
23
PG4626
1125-1
VREG5
1
2
PGOOD
ENTRIP2
EN
51125_ENTIP2 6
PR4607
2D2R5F-2-GP
4
3
2
1
13
FB1
PU4605
+5V_ALW
1
+PWR_SRC_5V
GAP-CLOSE-PWR
PG4622
2
1
PL4602
1
2
IND-2D2UH-46-GP-U
5
6
7
8
VOUT1
51125_LL1
4
3
2
1
16
VOUT2
FB2
51125_FB2_R
PC4623
51125_TONSEL
DYSC18P50V2JN-1-GP
51125_FB2
2 51125_EN
DY820KR2F-GP
PR4610
0R2J-2-GP
PR4613
10KR2F-2-GP
51125_VO2
1
PR4608
51125_VREF
1
1 2
DY
LGATE1
51125_DRVH1
20
8
7
6
5
D
D
D
D
1
1
S
S
S
G
1
2
PC4622
65MOS
SCD22U10V2KX-1GP
0210-1
PR4609
6K65R2F-GP
PU4604
1
2
3
4
1
2
1
2
SCD1U10V2KX-5GP
2
1
DY S
LGATE2
21
FDS6690AS-GP
S
S
S
G
PC4621
SC330P50V2KX-3GP
PHASE1
GAP-CLOSE-PWR-3-GP
DY
PG4623
UGATE1
PHASE2
51125_DRVL2
UGATE2
51125_VBST1_1
11
22
Design Current = 7.3A

11.45A<OCP< 16A
10
51125_LL2
BOOT1
+5V_PWR
+PWR_SRC
PC4619
SCD1U10V2KX-4GP
51125_DRVH2
BOOT2
65MOS
SCD1U25V3KX-GP
PC4617
1
2
PC4614
PR4605
4D7R3F-L-GP
51125_VBST1 1
2
D
D
D
D
PR4606
2D2R5F-2-GP
D
FDS6690AS-GP
GAP-CLOSE-PWR-3-GP
DY
PTC4602
ST220U6D3VDM-15GP
PC4618
ST100U6D3VBM-5GP
PTC4601
PU4603
PC4613
PL4601
1118-2
VIN
PR4604
4D7R3F-L-GP
51125_VBST2_1 1
251125_VBST2
2
1
COIL-3D3UH-15-GP
1
2
1
2
8
7
6
5
D
D
D
D
1
2
3
4
S
S
S
G
RT8205B
4R7
SC10U25V6KX-1GP
TPS51125
0R3J
SC10U25V6KX-1GP
PU4601
PC4616
SCD1U25V3KX-GP
1117-7
PR4605
FDS8884-GP
S
S
S
G
PU4602
FDS8884-GP
65MOS
DY
D
D
D
D
SCD1U25V2KX-GP
PC4609
2
1
RT8205B
4R7
SCD01U50V2KX-1GP
PR4604
SC10U25V6KX-1GP
TPS51125
0R3J
PC4610
0114-1
+3D3V_PWR
+PWR_SRC_5V
PC4611 PC4612
820KR3J-GP
SC10U25V6KX-1GP
Design Current =7.57A

11.89A<OCP<14.053A
0.55mA
PC4615
SCD1U25V2KX-GP
+PWR_SRC_3D3V
1117-7
3V_5V_POK (37,50)
+3.3V_ALW_2
+3.3V_RTC_LDO
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 2.2uH PCMC063T-2R2MN Cyntec 18mohm/20mohm Isat =14Arms 68.2R210.20B
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081
H/S: FDS8884 23mohm/30mOhm@4.5Vgs/ 84.08884.037
L/S: FDS6690AS 12mOhm/15mOhm@4.5Vgs/ 84.06690.E37
PR4620
1
0R0402-PAD
0105-5
RT8205B
ASM
DY
TPS51125:
CH1
CH2
GND
TONSEL
200kHz
265kHz
VREF
245kHz
305kHz
VREG3
300kHz
375kHz
VREG5
365kHz
460kHz
RT8205B(74.08208.A73):
TONSEL
CH1
CH2
GND
200kHz
250kHz
VREF
300kHz
375kHz
VREG3
365kHz
460kHz
VREG5
365kHz
460kHz
TPS51125
74.51125.073
RT8208BGQW
74.08208.A73
SKIPSEL
VREG3 or VREG5
VREF(2V)
Operating
Mode
OOA Auto Skip
Auto Skip
EN0
Operating
Mode
Open
enable both
LDOs, VCLK on
and ready to
turn on
switcher
channels
GND
PWM only
820k to GND
enable both LDOs,
VCLK off and
ready to turn on
switcher channels
GND
disable all
circuit
<Core Design>
Wistron Corporation
Title
Size
A2
Date:
RT8205B_5V/3D3V
Document Number
Rev
A00

Sheet

E
46
of
95
SSID = CPU.Regulator
1
2
5
6
7
8
4
3
2
1
1
2
1
5
6
7
8
4
3
2
1
1
2
49
48
47
46
45
44
43
42
41
40
39
38
37
GND
VIN
VCC
FB_NB
COMP_NB
FSET_NB
VSEN_NB
RTN_NB
OCSET_NB
PGND_NB
LGATE_NB
PHASE_NB
UGATE_NB
1
2
1
2
1
2
4
3
2
1
DY
PR4731
ISP0
SCD1U16V3KX-3GP
PR4732
ISP0_R
1
DY 2
10R2F-L-GP
1
2
2
DY
NTC-10K-26-GP
0114-1
Parallel
1
2
PC4721
SC330P50V2KX-3GP
0210-1
PR4728
1
2
4K02R2F-GP
PC4720
1
2
PG4702
GAP-CLOSE-PWR-3-GP
0907
ISN0
65MOS
COIL-D36UH-3-GP
0114-1
1
PU4705
4
3
2
1
DY
5
6
7
8
65MOS
4
3
2
1
5
6
7
8
5
6
7
8
4
3
2
1
5
6
7
8
1PHASE0_RC 2
ISP0
ISN0
VSEN0
RTN0
RTN1
VSEN1
VDIFF1
FB1
COMP1
VW1
ISP1
ISN1
PHASE_NB_R
6265_VIN
6265_VCC
6265_FB_NB
6265_COMP_NB
6265_FSET_NB
CPU_VDDNB_RUN_FB_H_R
2
1
6265_OFS/VFIXEN
1
2
1
2
1
13
14
15
16
17
18
19
20
21
22
23
24
PC4719
1
2
SCD22U25V3KX-GPPU4708
PTC4705
BOOT0_R
SE330U2VDM-L-GP
PTC4704
SE330U2VDM-L-GP
PTC4703
PR4724
SIS402DN-T1-GE3-GP
S
S
S
G
+VCC_CORE
LGATE0
PR4736
PR4735
10R2J-2-GP
10R2J-2-GP
PL4701
SE330U2VDM-L-GP
6265_VSEN0
6265_RTN0
6265_RTN1
6265_VSEN1
6265_VDIFF1
6265_FB1
6265_COMP1
6265_VW1
UGATE0
PHASE0
+VCC_CORE
Design Current: 36A
39.6A<OCP<54A
65MOS
PR4722
ISN1
ISP1
PC4717
65MOS
PU4704
SCD1U25V2ZY-1GP
PC4715
D
PU4710
SIS406DN-T1-GE3-GP
SC10U25V6KX-1GP
PC4714
LGATE1
PHASE1
UGATE1
BOOT1
16KR2F-GP
+PWR_SRC
+5V_RUN
LGATE0
D
D
D
D
BOOT_NB
BOOT0
UGATE0
PHASE0
S
S
S
G
0210-1
36
35
34
33
32
31
30
29
28
27
26
25
BOOT_NB
BOOT0
UGATE0
PHASE0
PGND0
LGATE0
PVCC
LGATE1
PGND1
PHASE1
UGATE1
BOOT1
SC10U25V6KX-1GP
PC4713
PC4711
SC330P50V2KX-3GP
DY
SC10U25V6KX-1GP
PTC4701
PC4710
SE330U2VDM-L-GP
SC4D7U6D3V5KX-3GP
PC4709
SC1U10V2KX-1GP
LGATE_NB
D
D
D
D
2 0R0402-PAD
2 0R0402-PAD
S
S
S
G
65MOS
1R3J-L1-GP
PR4733 1
PR4734 1
PC4705
(10)
BOOT0
2 0R0402-PAD
2 0R0402-PAD
SC10U25V6KX-1GP
CPU_VDDNB_RUN_FB_L
PHASENB_RC
2
PR4712
0R0402-PAD
ISL6265AHRTZ-T-GP
PR4729 1
PR4730 1
PC4738
SIS402DN-T1-GE3-GP
CPU_VDD1_RUN_FB_H
SCD1U25V2ZY-1GP
UGATE_NB
CPU_VDDNB_RUN_FB_L_R
PR4723
PR4727
1KR2J-1-GP
0R2J-2-GP
PR4726
10R2J-2-GP
0114-1
IND-4D7UH-88-GP
PR4711
2D2R5F-2-GP
DY
PU4703
D
D
D
D
+VCC_CORE +VCC_CORE
S
S
S
G
ISP0
ISN0
+1.8V_RUN
SIS406DN-T1-GE3-GP
S
S
S
G
GNDA_VCORE
SCD22U25V3KX-GP
LGATE_NB
PHASE_NB
D
D
D
D
PG4701
2
GAP-CLOSE-PWR
0R0603-PAD
PL4702
PHASE_NB
S
S
S
G
9/15
PC4708
1
2
2BOOT_NB_R
D
D
D
D
DY
1117-7
+VDDNB
PR4708
BOOT_NB 1
PC4712
PC4718
SCD01U50V2KX-1GP
GNDA_VCORE
293K1R2F-L-GP
1229-2
OFS/VFIXEN
PGOOD
PWROK
SVD
SVC
ENABLE
RBIAS
OCSET
VDIFF0
FB0
COMP0
VW0
(10)
PR4716
1 PR4717 2 0R0402-PAD
1 PR4718 2 0R0402-PAD
CPU_VDDNB_RUN_FB_H
PHASE_NB
SC2D2U10V3KX-1GP
1
2
3
CPU_SVD_R
4
CPU_SVC_R
5
VCC_CORE_EN 6
6265_RBIAS
7
6265_OCSET
8
6265_VDIFF0
9
6265_FB0
10
6265_COMP0
11
6265_VW0
12
+VDDNB
Design Current: 2.8A
Peak current: 4A
4.4A<OCP<5.6A
UGATE_NB
10R2F-L-GP
PR4715
0R2J-2-GP
GNDA_VCORE
GNDA_VCORE
PU4701
1125-1
65MOS
SIS412DN-T1-GE3-GP
DY
DY
1 PR4707 2
8K06R2F-GP
PU4702
D
D
D
D
0R0402-PAD
PR4706
1
2
PR4710
0R2J-2-GP
PR4714
PR4713
10KR2J-3-GP
10KR2J-3-GP
DY
1%
SIS412DN-T1-GE3-GP
22KR2F-GP
GNDA_VCORE
0R0402-PAD
PR4709
GNDA_VCORE
PR4705
+3.3V_RUN
+VDDNB
10R2J-2-GP
+5V_RUN
PR4720 1
+PWR_SRC
PC4704
1
2
PC4707
SCD1U50V3KX-GP
2
2R3J-GP
PC4703
1
2
SC1200P50V2KX-1GP
SC1KP50V2KX-1GP
PR4704
1
2
PR4703
1
1 PR4719 2
0R0402-PAD
1 PR4721 2
24KR2F-GP
6265_FB_NB_R
GNDA_VCORE
+PWR_SRC
(37,41,48,51) IMVP_PWRGD
(10) CPU_PWRGD_SVID_REG
(10) CPU_SVD
(10) CPU_SVC
(37) IMVP_VR_ON
44K2R2F-1-GP
PR4702
1
2R3J-GP
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor:4.7uH PCMC063T-4R7MN 35mohm Isat =10Arms CYNTEC/68.4R710.20D
O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3.0Arms Panasonic/79.33719.L01
H/S:VISHAY SIS412DN-T1-GE3/ 24mohm/30mOhm@4.5Vgs/ 84.00412.037
L/S:VISHAY SIS412DN-T1-GE3/ 24mohm/30mOhm@4.5Vgs/ 84.00412.037
SC33P50V2JN-3GP
PC4701
SC1U10V3KX-3GP
PR4725
2D2R5F-2-GP
5V, 10mA
PR4701
1
+3.3V_RUN
ISL6265HRTZ-T for +VCC_CORE&+VDDNB

PC4702
1
2
+5V_RUN
DY
Close to CPU socket
B
+PWR_SRC
6265_FB0_C
1
2
1
2
1
2
1
2
1
2
5
6
7
8
4
3
2
1
PL4703
SCD1U16V3KX-3GP
PR4750
PR4751
ISP1_R 1
2
DY
10R2F-L-GP
0210-1
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 0.36UH PCMC104T-R36MN1R05J CYNTEC DCR 1.05(+5%~-5%)mohm
Isat =60Arms 68.R3610.20C
O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3.0Arms Panasonic/79.33719.L01
H/S:VISHAY SiR462DP/ POWERPAK-8.2/810mOhm/ 4.5Vgs/ 84.00462.037
L/S:VISHAY SI7658ADP/ POWERPAK-2.3/ 2.8mOhm/ 4.5Vgs/ 84.07658.037
2
DY
A
<Core Design>
Wistron Corporation
Title
Date:
4
DY
NTC-10K-26-GP
0114-1
Size
A2
5
1
2
PG4703
GAP-CLOSE-PWR-3-GP
1
2
PC4737
SC330P50V2KX-3GP
ISP1
1PHASE1_RC 2
PR4747
2D2R5F-2-GP
5
6
7
8
5
6
7
8
4
3
2
1
DY
PR4749
1
2
4K02R2F-GP
PC4736
1
2
DY
PTC4708
LGATE1
0907
SE330U2VDM-L-GP
PTC4707
COIL-D36UH-3-GP
SE330U2VDM-L-GP
PTC4709
65MOS
DY
PR4748
SIS402DN-T1-GE3-GP
S
S
S
G
PU4707
SE330U2VDM-L-GP
D
D
D
D
D
65MOS
S
S
S
G
SIS402DN-T1-GE3-GP
PU4709
SCD22U25V3KX-GP
16KR2F-GP
PC4735
BOOT1_R 1
2
D
D
D
D
1R3J-L1-GP
+VCC_CORE
2
ISN1
5
6
7
8
1
2
1
2
1
2
PTC4710
PTC4706
SE100U25VM-14GP
S
S
S
G
0114-1
PR4746
BOOT1 1
65MOS
UGATE1
PHASE1
PC4734
65MOS
PU4706
SE100U25VM-14GP
DY
6265_FB1_R
SIS406DN-T1-GE3-GP
S
S
S
G
PU4711
SIS406DN-T1-GE3-GP
PC4731
SCD1U50V3KX-GP
DY
6K81R2F-1-GP
D
D
D
D
PC4733
PR4743
DY
PC4730
PR4742
2
SC10U25V6KX-1GP
SC1KP50V2KX-1GP
D
D
D
D
DY
1KR2F-3-GP
SC1200P50V2KX-1GP
0210-3
DY
SC180P50V2JN-1GP
PR4741
2
6K81R2F-1-GP
54K9R2F-L-GP
PC4728
SC1200P50V2KX-1GP
PR4744
54K9R2F-L-GP
6265_FB0_R
DY
SC4700P50V2KX-1GP
PR4740
2
1KR2F-3-GP
DY
PC4722
1
2
4
3
2
1
DY 2
249R2F-GP
PC4727
1
2
PC4729
PR4739
1
SC1KP50V2KX-1GP
PC4726
6265_FB1_C 1
2
SC10U25V6KX-1GP
SC180P50V2JN-1GP
PR4738
4
3
2
1
PC4725
1
2
SC10U25V6KX-1GP
1
249R2F-GP
SC4700P50V2KX-1GP
PC4724
1
2
PC4723
2
1
2
PR4737
VREG : +VCC_CORE&+VDDNB
Document Number
Rev

Sheet

1
47
of
A00
95
SSID = PWR.Plane.Regulator_+1.1V_RUN
1117-2
RT8209EGQW for +1.1V_RUN
1
2
1
2
1
2
1
2
2
1
PTC4803
ST330U2VDM-3GP
2
1
PTC4802
ST330U2VDM-3GP
1
2
PR4807
38K3R2F-GP
R2
Vout=0.75V*(R1+R2)/R2
1
2
DY
+1.1V_VOUT_VFB
PR4805
R1
18KR2F-GP
0210-1
SC18P50V2JN-1-GP
PC4805
+1.1V_VOUT
DY
65MOS
DY
DY
RT8209EGQW -GP
0308-1
5
6
7
8
(37,41)
4
3
2
1
VDDC_PW RGD
PU4805
SIR164DP-T1-GE3-GP
5
6
7
8
SI7686DP-T1-GP
4
3
2
1
4
3
2
1
PU4802
5
6
7
8
+1.1V_VOUT
VDDC_PW RGD
5
6
7
8
1
2
1
2
1
2
3
6
7
8
15
EN/DEM
TON
CS
+1.1V_RUN
1
2
COIL-1D5UH-25-GP
PC4809
VOUT
PGOOD
GND
PGND
NC#15
+VDDC_EN
1
+1.1V_VOUT_TON
2
+1.1V_VOUT_TRIP 11
PL4801
S
S
S
G
+1.1V_LL
2
1
PR4803
9K31R2F-GP
A
K
12
PTC4801
PHASE
SE330U2D5VM-GP
PC4807
FB
BOOT
SCD1U10V2KX-4GP
PC4804
5
14
SC4D7U6D3V5KX-3GP
+1.1V_VOUT_VFB
+1.1V_VOUT_BST
PG4817
+1.1V_DRVH
+1.1V_DRVL
GAP-CLOSE-PWR-3-GP
13
9

11.65A<OCP < 15.89A
0114-1
PR4802
UGATE
LGATE
1119-2
2D2R5F-2-GP SC330P50V2KX-3GP
VDD
VDDP
PU4803
D
D
D
D
4
10
SIR164DP-T1-GE3-GP
+1.1V_VOUT_V5FILT
PC4806
PU4801
PC4810
DY
S
S
S
G
SCD1U25V3KX-GP
SIR164DP-T1-GE3-GP
PU4804
D
S
D
S
D
S
D
G
DY
PC4808
SC4700P50V2KX-1GP
20R0402-PAD
2 300KR2F-GP
65MOS
S
S
S
G
4D7R3J-L1-GP
5V, 1.25mA
PC4811
1
+1.1V_LL1
SCD1U50V3KX-GP
PR4806
D
D
D
D
PRb
PC4803
PRa
SC10U25V6KX-1GP
0 ohm
*DEFAULT
SC10U25V6KX-1GP
4.7 ohm
300 ohm
PC4802
SC1U10V3KX-3GP
PR4808 1
PR4804 1
(37,41,47,51) IMVP_PW RGD
10 ohm
D
D
D
D
PR4801
10R3J-3-GP
PD4801
RB551V30-GP
PC4801
SC1U10V3KX-3GP
+5V_ALW
TPS51117
SC10U25V6KX-1GP
PC4812
*RT8209B
0222-3
+PW R_SRC
PRb
+5V_ALW
PRa
PWM TYPE
0222-3
Remove
4
3
2
1
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 1.5UH PCMC104T-1R5MN 33Arms CYNTEC/ 68.1R510.10J
O/P cap: 330U 2.5V EEFCX0E331QR 15mOhm 2.7Arms PANASONIC/ 79.3371V.20L
H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037
L/S: SiR164DP/ POWERPAK-8/ 2.6mOhm/3.2mohm@4.5Vgs/ 84.00164.037
<Core Design>
Wistron Corporation

Title
RT8209E_+1.1V_RUN
5
Size
A3
Document Number
Date:
Rev

Sheet
1
48
of
A00
95
SSID = PWR.Plane.Regulator_1p5v0p75v
+5V_ALW
PR4901
5D1R3J-GP
+5V_ALW
21
PHASE
20
TPS51116_PHS
NC#7
LGATE
19
TPS51116_LGT
PGND
NC#17
18
17
VDDQ
TPS51116_VDDQSNS
FB
51116_VDDQSET
DEM
VTTGND
MODE
+5V_ALW
DY
GAP-CLOSE-PW R
PG4909
2
1
+5116_PW R_SRC
0R2J-2-GP
GAP-CLOSE-PW R
PG4911
2
1
DY PC4907
VTTREF
On
On
VTT
TPS51116_LGT
On
Lo
Hi
On
On
Off(Hi-Z)
Lo
Lo
Off
Off
Off
1
2
TPS51116_VDDQSNS
NOTE
GND
2.5
VVDDQSNS/2
DDR
V5IN
1.8
VVDDQSNS/2
DDR2
PR4915
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
30KR2F-GP
Inductor: 1.5UHPCMC104T-1R5MN DCR:3.8/4.2mohm Isat =33Arms Cyntec/ 68.1R510.10J
O/P cap: 220U 2V EEFCX0D221R 15mOhm 2.7Arms PANASONIC/ 79.22719.20L
FB Resistors
Adjustable
VVDDQSNS/2
2
2
2
VTTREF and VTT
PC4921
SC18P50V2JN-1-GP
51116_VDDQSET
VDDQ (V)
DY
PR4914
30KR2F-GP
VDDQSET
1125-1
S3
S4/S5
PC4920
SC680P50V3JN-GP
PC4918
SC4D7U6D3V5KX-3GP
VDDR
S5
Hi
PC4912
SC4D7U25V5KX-GP
1
1
2
Hi
S3
0225-3
TPS51116_PHS_SET
S0
4
3
2
1
S
S
S
G
65MOS
State
0114-1
PR4913
3D9R5J-GP
PU4903
SIR164DP-T1-GE3-GP
GAP-CLOSE-PW R
1
2
COIL-1D5UH-25-GP
PG4918
GAP-CLOSE-PWR-3-GP
5
6
7
8
4
3
2
1
TPS51116_PHS
PC4917
SCD1U25V3KX-GP
5
6
7
8
PC4916
SC10U6D3V5MX-3GP
1
2
PC4915
SC10U6D3V5MX-3GP
PC4914
SC10U6D3V5MX-3GP
+1.5V_SUS
PL4901
D
D
D
D
PC4913
SCD1U10V2KX-4GP
TPS51116_VBST 1
9/18
28.99A<OCP< 34.3A
65MOS
TPS51116_UGT
GAP-CLOSE-PW R
PG4917
1
2
GAP-CLOSE-PW R
S
S
S
G
D
D
D
D
+0D75V_DDR_P
+0.75V_DDR_VTT
PG4901
1
2
PU4902
SI7686DP-T1-GP
PC4908
SC2D2U6D3V3KX-GP
+0D75V_DDR_P
1119-7
+V_DDR_REF
1 PR4912 2
0R0603-PAD
PC4911
SCD1U50V3KX-GP
SC1U10V3KX-3GP
RT8207GQW -GP
PR4911
1
1
GND
3
25
VTTREF
VTTSNS
VTT
GND
24
GAP-CLOSE-PW R
PG4907
2
1
PC4922
SC10U25V6KX-1GP
DY
+5116_PW R_SRC
PG4903
1
GAP-CLOSE-PW R
PG4905
2
1
PC4909
SC10U25V6KX-1GP
2 0R0402-PAD
PC4906
SC1KP50V2KX-1GP
+0D75V_DDR_P
1
+PW R_SRC
PTC4901
SE220U2VDM-8GP
VLDOIN
S3
23
PC4904
SCD1U10V2KX-4GP
10
S5
1116-6
TON
11
2 0R2J-2-GP
PTC4902
SE220U2VDM-8GP
12
2 TPS51116_VBST
2 0R2J-2-GP
UGATE
TPS51116_UGT
0D75V_EN
14
15
TPS51116_VBST1
PGOOD
DY
(37,42) 1.5V_RUN_EN
DY
DY
+5V_ALW
+1.5V_SUS
PR4910 1
PC4905
SC1U10V3KX-3GP
2 1M1R2J-GP
PR4904 1
0D75V_EN
+1.5V_SUS
PR4907 1
PR4908
0R0603-PAD
22
BOOT
(21,37) PM_SLP_S5#
(21,37) PM_SLP_S5#
PR49091
PD4901
CH551H-30PT-GP
PC4919
SCD1U10V2KX-4GP
13
PU4901
VDDP
CS
1PR4906
2
620KR2F-GP
TI: Non_ASM
RT: ASM
VDD
16
1120-7
2
1
0622
1118-3
(51,52,89,90) RUNPW ROK

+5116_PW R_SRC
DY
2 2D2R2J-GP
PC4923
PR4916
100KR2J-1-GP
Refer to DJ1 PR8606
PR4903 1
SCD1U10V2KX-4GP
11/9
1125-1
PM_SLP_S3#
(21,37,41,42,52,89)
+3.3V_RUN
+5V_ALW
PC4902
SC1KP50V2KX-1GP
SC1U10V3KX-3GP
PC4901
5V, 0.8mA
1
51116_VDD
PC4903
SC1U10V3KX-3GP
12KR2F-L-GP
1
2
PR4902
1125-1
<Core Design>
Wistron Corporation

1.5 V < VVDDQ < 3 V

Title
RT8207_+1.5V_SUS
Size
A3
Date:
5
Document Number
Rev

Sheet
1
49
A00
of
95
SSID = PWR.Plane.Regulator_+1.1V_ALW
1117-2
RT9025 for +1.1V_ALW
DY
1
2
1
2
1
2
GND
DY
PG5002
1
2
PC5003
PR5001
PC5002
PU5001
RT9025-25PSP-GP
+1.1V_ALW _ADJ
SC22U6D3V5MX-2GP
5
6
7
8
SC22U6D3V5MX-2GP
GAP-CLOSE-PW R
PG5001
1
2
GAP-CLOSE-PW R
Vo=0.8*(1+(R1/R2))
Vout=0.8V*(R1+R2)/R2
+1.1V_ALW
+1.1V_ALW _P
NC#5
VOUT
ADJ
GND
PC5001
VDD
VIN
EN
PGOOD
SCD01U16V2KX-3GP
11.1V_RUN_PW RGD
3
2
1
1K02R2F-1-GP
TP5001
PC5004
SC4700P50V2KX-1GP
+1.1V_VOUT_EN
1
2
1.2mA 4
DY
PC5006
PC5005
1
DY 2
PR5002
2K2R2J-2-GP
SC10U6D3V5MX-3GP
PR5004
10KR2J-3-GP
(37,46) 3V_5V_POK
SC1U10V3KX-3GP
+3.3V_ALW
0106-1
+5V_ALW
PR5003
2K7R2F-GP
<Core Design>
Wistron Corporation

Title
RT9025_+1.1V_ALW
Size
A3
Date:
5
Document Number
Rev
Sheet
1
50
of
A00
95
SSID = PWR.Plane.Regulator_VDDR
RT9025 for +VDDR

11/6
+5V_ALW
1
2
1
2
2
1
GAP-CLOSE-PW R
1
2
PR5106
8K2R2F-1-GP
0105-6
PR5104
100KR2J-1-GP
DY
1
DY
2
SCD047U16V2KX-1-GP
1.05V
0.9V
+1.5V_RUN +/- 5%
Peak current 1.15A
GAP-CLOSE-PW R
PG5102
1
2
VDDR_SEL_CNTL
PC5102
+CPU_VDDR
GND
2
2
BAT54APT-GP
DY
1225-6
PQ5101
2N7002A-7-GP
G
PR5103
10KR2F-2-GP
VDDR_SEL
2
MEM_1V5
PC5103
(22) MEM_1V5
PR5102
1K05R2F-GP
SC22U6D3V5MX-2GP
VDDR_SEL_R
DY
PG5101
1
2
PR5107
5K62R2F-GP
R2
1
3
R1
PU5101
RT9025-25PSP-GP
PR5105
10KR2F-2-GP
PD5101
VDDR_SEL
+VDDR_ADJ
PC5107
DY
(20,24) VDDR_SEL
5
6
7
8
+3.3V_RUN
+CPU_VDDR
+VDDR_P
NC#5
VOUT
ADJ
GND
SCD01U16V2KX-3GP
PR5108
1
2
0R2J-2-GP
VDD
VIN
EN
PGOOD
SC22U6D3V5MX-2GP
1116-2
VDDR_EN
DY
(37,41,47,48) IMVP_PW RGD
4
3
2
1
PC5105
1119-1
PC5104
Vo=0.8*(1+(R1/R2))
SC4700P50V2KX-1GP
1
2
PR5101
2K2R2J-2-GP
(49,52,89,90) RUNPW ROK
SC10U6D3V5MX-3GP
PC5106
SC1U10V3KX-3GP
PC5101
5V, 1.2mA
+1.5V_SUS
10/2
<Core Design>
A
Wistron Corporation

Title
Size
A3
Date:
5
RT9025 +VDDR
Document Number
Rev

Sheet
1
51
of
A00
95
SSID = PWR.Plane.Regulator_1p8v
APL5930 for +1.8V_RUN

D
PG5201
2
1
+5V_ALW
1
2
1
2
PR5204
13K3R2F-L1-GP
1
2
R2
DY
R1
1
2
VCNTL
5912_1.8V_RUN_FB
PC5207
SC4700P50V2KX-1GP
2
1
DY
SO-8-P
PG5203
2
GAP-CLOSE-PW R
PG5204
1
2
PC5206
SC22U6D3V5MX-2GP
APL5930KAI-TRG-GP
0R2J-2-GP
FB
+1.8V_RUN
GAP-CLOSE-PW R
PC5205
PR5202
PC5204
DY
+1.8V_RUN_P
+1.8V_RUN_P
SC68P50V2JN-1GP
3
4
PR5203
(37,90) 1.8V_VGA_RUN_EN
VOUT#3
VOUT#4
16K5R2F-2-GP
2K2R2J-2-GP
5
9
GND
EN
VIN#5
VIN#9
DY
SC22U6D3V5MX-2GP
POK
PC5203
PM_SLP_S3#
21D8V_RUN_EN
SC10U6D3V5MX-3GP
7
PR5201
PC5202
PU5201
(49,51,89,90) RUNPW ROK
SC10U6D3V5MX-3GP
GAP-CLOSE-PW R
PC5201
SC1U10V3KX-3GP
GAP-CLOSE-PW R
PG5202
2
1
(21,37,41,42,49,89)
+1.8V_RUN_VIN
5V, 1.5mA
1
+1.8V_RUN_VIN
+3.3V_ALW
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
APL5930_+1.8V_RUN
Document Number
Rev

Sheet
1
52
A00
of
95
SSID = PWR.Plane.Regulator_0P9v
B
RT9013-25PB for +2.5V_RUN
RT9013-25PB-GP
NC#4
DY
VOUT
SC1U10V3KX-3GP
2
1
PR5301
0R0402-PAD
VIN
GND
EN
PC5304
2D5V_RUN_EN
SC10U10V5ZY-1GP
PC5303
1
2
3
SC4D7U6D3V3KX-GP
+2.5V_RUN
PU5301
PC5302
PC5301
SC4D7U6D3V3KX-GP
+3.3V_RUN
+2.5V_RUN +/- 5%
Design Current: 175mA
Peak current 250mA
11/6
CHECK CURRENT IS ENOUGH OR NOT (CPU)

<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
VREG : +CPU_VDDR&+2.5V_RUN
Document Number
Rev

Sheet
1
53
of
A00
95
+3.3V_RUN
9/22
SSID = Inverter
SSID = VIDEO
+3.3V_RUN
LVDS CONNECTOR
R5402
43
44
45
46
47
3
4
3.3V_LCD_RUN
LCD_BRIGHTNESS
BLON_OUT_C
LCD_CBL_DET#_C
LCD_TST_C
DIS
2
2
UMA
GFX_PW R_SRC
+3.3V_RUN
0R2J-2-GP
F5401
LVDSB_TX0 (55)
LVDSB_TX0# (55)
POLYSW -1D1A24V-1-GP
C5407
SCD1U50V3KX-GP
Main:69.50007.A41
Second:69.50007.A31
RN5401
BLON_OUT_C
LCD_CBL_DET#_C
LCD_TST_C
LCD_DET_G
1120-1
1
2
3
4
8
7
6
5
2
1
1
LVDSB_TX1 (55)
LVDSB_TX1# (55)
C5406
SC1KP50V2KX-1GP
10/1
R5408
100KR2J-1-GP
+PW R_SRC
Change Poly-fuse
+3.3V_RUN_VGA
0R2J-2-GP
LVDSB_TX2 (55)
LVDSB_TX2# (55)
LCD_DET_G
1
R5404
1
R5407
42
3.3V_LCD_RUN
0105-7
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
51
LVDS_CLK
LVDS_DATA
100KR2J-1-GP
1
2
50
1
RN5402
SRN2K2J-1-GP
DY R5405
C5402
SC1U10V3KX-3GP
LCD1
INVERTER POWER
LBKLT_CTL (55)
0208-2
2
+LCDVDD
48
41
100R2J-2-GP
2
LCD_BRIGHTNESS
GFX_PW R_SRC
C5401
SCD1U16V2ZY-2GP
2
1
10/1
2
1
R5401
DY 10KR2J-3-GP
BLON_OUT (37)
LCD_CBL_DET# (37)
LCD_TST (37)
SRN100J-4-GP
LVDSB_TXC (55)
LVDSB_TXC# (55)
LVDSA_TXC (55)
LVDSA_TXC# (55)
LVDSA_TX2 (55)
LVDSA_TX2# (55)
LVDSA_TX1 (55)
LVDSA_TX1# (55)
0222-1
LVDSA_TX0 (55)
LVDSA_TX0# (55)
LVDS_DATA (55)
LVDS_CLK (55)
R5409
1
USB_CAMERA#
USB_CAMERA
USB_PN11 (21)
0R0603-PAD
R5411
+3.3V_CAMERA
USB_PP11 (21)
SSID = VIDEO
0R0603-PAD
49
LCD POWER
IPEX-CONN40-2R-GP-U
20.F1093.040
Close to LVDS connector

(55) LCDVDD_EN
3
2
1
ENVDD
OUT
GND
EN
IN#4
IN#5
G5285T11U-GP
DY
2
0R0402-PAD
R5413
49K9R2F-L-GP
2
(37) LCD_TST_EN
DY
2
DY
EC5402
SC33P50V2JN-3GP
DY
ENVDD_D
1
3
BAT54C-U-GP
EC5409
DY
EC5408
LCD_TST
EC5401
SC33P50V2JN-3GP
DY
SC5D6P50V2CN-1GP
2
C5403
SC10U6D3V5MX-3GP
EC5407
SC5D6P50V2CN-1GP
2
1
2
DY
2
EC5405
SCD1U10V2KX-5GP
DY
EC5406
2
0R0603-PAD
D5401
C5409
LCD_BRIGHTNESS
LVDSA_TXC
SCD1U10V2KX-5GP
R5414
+3.3V_RUN
U5401
R5412
LVDSA_TXC#
SC5D6P50V2CN-1GP
2
+3.3V_CAMERA
Camera Power
SC5D6P50V2CN-1GP
2
1231-1
+3.3V_RUN
+LCDVDD
1231-1
LVDSB_TXC
C5405
SC1U10V3KX-3GP
LVDSB_TXC#
For EMI request
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
LCD/Inverter Connector
Document Number
Rev

Sheet
54
of
A00
95
SSID = VIDEO
9/18
RN5501
(13)
(13)
(13)
(13)
5
6
7
8
VGA_TXACLKVGA_TXACLK+
UMA
RN5507
4
3
2
1
LVDSA_TX2# (54)
LVDSA_TX2 (54)
LVDSA_TXC# (54)
LVDSA_TXC (54)
(13)
(13)
(13)
(13)
SRN0J-7-GP
5
6
7
8
UMA
RN5503
(82)
(82)
(82)
(82)
5
6
7
8
DIS
SRN0J-7-GP
(82)
(82)
(82)
(82)
GPU_LVDSB_TX1#
GPU_LVDSB_TX1
GPU_LVDSB_TX2#
GPU_LVDSB_TX2
5
6
7
8
UMA
5
6
7
8
DIS
SRN0J-7-GP
RN5509
4
3
2
1
LVDSA_TX0# (54)
LVDSA_TX0 (54)
LVDSA_TX1# (54)
LVDSA_TX1 (54)
(13)
(13)
(13)
(13)
VGA_TXBCLKVGA_TXBCLK+
SRN0J-7-GP
5
6
7
8
UMA
RN5506
(82)
(82)
(82)
(82)
4
3
2
1
GPU_LVDSA_TX0#
GPU_LVDSA_TX0
GPU_LVDSA_TX1#
GPU_LVDSA_TX1
DIS
SRN0J-7-GP
4
3
2
1
RN5505
(13)
(13)
(13)
(13)
LVDSB_TX1# (54)
LVDSB_TX1 (54)
LVDSB_TX2# (54)
LVDSB_TX2 (54)
RN5508
4
3
2
1
GPU_LVDSA_TX2#
GPU_LVDSA_TX2
GPU_LVDSA_TXC#
GPU_LVDSA_TXC
4
3
2
1
4
3
2
1
LVDSB_TXC# (54)
LVDSB_TXC (54)
LVDSB_TX0# (54)
LVDSB_TX0 (54)
SRN0J-7-GP
RN5510
5
6
7
8
(82)
(82)
(82)
(82)
GPU_LVDSB_TXC#
GPU_LVDSB_TXC
GPU_LVDSB_TX0#
GPU_LVDSB_TX0
SRN0J-7-GP
4
3
2
1
5
6
7
8
DIS
SRN0J-7-GP
10/1
10/1
RN5502
(13) NB_LCDPWR_EN
(13) NB_BL_PWM
(13) NB_BL_EN
5
6
7
8
(82) VGA_LCDVDD_EN
(82) VGA_LBKLT_CTL
(82) VGA_BLEN
8
7
6
5
RN5512
4
3
2
1
LCDVDD_EN (54)
LBKLT_CTL (54)
PANEL_BKEN (37)
UMA
SRN0J-7-GP
1
2
(13) LDDC_CLK
(13) LDDC_DATA
UMA
RN5504
4
3
LVDS_CLK (54)
LVDS_DATA (54)
SRN0J-6-GP
RN5511
1
2
3
4
2
1
3
4
DIS
SRN0J-6-GP
(82) GPU_LVDS_CLK
(82) GPU_LVDS_DATA
DIS
SRN0J-7-GP
<Core Design>
Wistron Corporation

Title
LVDS_Switch
Size
Document Number
Rev

5
Sheet
55
of
1
A00
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
Reserved
Rev

Sheet
1
56
of
A00
95
HDMI CONNECTOR
HDMI CONN
(12) PCIE_NTX_GRX_P[12..15]
PCIE_N_H_TX_GRX_P[12..15]
(80)
(12) PCIE_NTX_GRX_N[12..15]
PCIE_N_H_TX_GRX_N[12..15]
(80)
10/1
22
20
1
10/1
HDMI DISCRETE/ UMA Co-lay

D
RN5708
PCIE_NTX_GRX_N13
PCIE_NTX_GRX_P13
PCIE_NTX_GRX_N12
PCIE_NTX_GRX_P12
5
6
7
8
PCIE_NTX_GRX_N15
PCIE_NTX_GRX_P15
PCIE_NTX_GRX_N14
PCIE_NTX_GRX_P14
5
6
7
8
SRN0J-7-GP
RN5706
4
3
DIS 2
1
PCIE_N_H_TX_GRX_P12
PCIE_N_H_TX_GRX_N12
PCIE_N_H_TX_GRX_P13
PCIE_N_H_TX_GRX_N13
5
6
7
8
SRN0J-7-GP
RN5712
4
3
DIS 2
1
PCIE_N_H_TX_GRX_P14
PCIE_N_H_TX_GRX_N14
PCIE_N_H_TX_GRX_P15
PCIE_N_H_TX_GRX_N15
NB_HDMI_TX2N
NB_HDMI_TX2P
NB_HDMI_TX1N
NB_HDMI_TX1P
NB_HDMI_TX1N
NB_HDMI_TX1P
NB_HDMI_TX2N
NB_HDMI_TX2P
4
3
2
1
HDMI_CN_CLK#
HDMI_CN_CLK
HDMI_CN_DATA0#
HDMI_CN_DATA0
SRN0J-7-GP
RN5709
4
3
UMA 2
1
HDMI_CN_DATA1#
HDMI_CN_DATA1
HDMI_CN_DATA2#
HDMI_CN_DATA2
5
6
7
8
5
6
7
8
UMA
SRN0J-7-GP
(82)
(82)
(82)
(82)
HDMI_PCH_DATA0#
HDMI_PCH_DATA0
HDMI_PCH_CLK#
HDMI_PCH_CLK
C5703
C5704
C5709
C5702
(82)
(82)
(82)
(82)
HDMI_PCH_DATA2#
HDMI_PCH_DATA2
HDMI_PCH_DATA1#
HDMI_PCH_DATA1
C5707
C5708
C5705
C5706
SRN0J-7-GP
11/12-3
1
DIS
1
DIS
1
DIS
1
DIS
2
SCD1U10V2KX-5GP
2
SCD1U10V2KX-5GP
2
SCD1U10V2KX-5GP
2
SCD1U10V2KX-5GP
HDMI_CN_DATA0#
HDMI_CN_DATA0
HDMI_CN_CLK#
HDMI_CN_CLK
1
DIS
1
DIS
1
DIS
1
DIS
2
SCD1U10V2KX-5GP
2
SCD1U10V2KX-5GP
2
SCD1U10V2KX-5GP
2
SCD1U10V2KX-5GP
HDMI_CN_DATA2#
HDMI_CN_DATA2
HDMI_CN_DATA1#
HDMI_CN_DATA1
AFTP5703
HDMI_CN_DATA2#1
HDMI_CN_DATA1 1
AFTP5705
AFTP5704
HDMI_CN_DATA1#1
HDMI_CN_DATA0 1
AFTP5701
AFTP5702
HDMI_CN_DATA0#1
HDMI_CN_CLK
1
AFTP5711
AFTP5710
HDMI_CN_CLK# 1
AFTP5708
DDC_CLK_HDMI 1
DDC_DATA_HDMI 1
AFTP5707
AFTP5706
HPD_HDMI_CON 1
AFTP5713
+5V_RUN
AFTP5709
SKT-HDMI19P-69-GP
C5701
PCIE_NTX_GRX_P14
PCIE_NTX_GRX_N14
PCIE_NTX_GRX_P15
PCIE_NTX_GRX_N15
5
6
7
8
SRN0J-7-GP
RN5710
4
3
UMA 2
1
NB_HDMI_TXCN
NB_HDMI_TXCP
NB_HDMI_TX0N
NB_HDMI_TX0P
HDMI_CN_DATA2 1
SCD1U10V2KX-5GP
PCIE_NTX_GRX_P12
PCIE_NTX_GRX_N12
PCIE_NTX_GRX_P13
PCIE_NTX_GRX_N13
UMA
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
23
RN5707
NB_HDMI_TX0N
NB_HDMI_TX0P
NB_HDMI_TXCN
NB_HDMI_TXCP
4
3
2
1
22.10296.211
HDMI1
SSID = VIDEO
AFTP5712
9/23
HDMI_CN_CLK#
HDMI_CN_CLK
HDMI_CN_DATA0#
HDMI_CN_DATA0
9/15
+5V_RUN
HDMI_CN_DATA1#
HDMI_CN_DATA1
HDMI_CN_DATA2#
HDMI_CN_DATA2
(82) GPU_HDMI_CLK
(82) GPU_HDMI_DATA
1
499R2F-2-GP
2
R5722
1
499R2F-2-GP
2
R5721
1
499R2F-2-GP
2
R5720
1
499R2F-2-GP
2
R5719
1
499R2F-2-GP
2
R5718
1
499R2F-2-GP
2
R5717
1
499R2F-2-GP
RN5713
SRN0J-6-GP
4
3
1
2
DDC_CLK_HDMI
UMA
R5716
RN5714
SRN0J-6-GP
4
3
R5715
(13) NB_DDC_CLK0
(13) NB_DDC_DATA0
1
499R2F-2-GP
1
2
5V Tolerance
2
1
RN5701
SRN4K7J-8-GP
3
4
10/5
DDC_DATA_HDMI
DIS
+5V_RUN
HDMI_PLL_GND
Q5703
2N7002A-7-GP
HDMI_PLL_GATE
R5714
100KR2J-1-GP
9/22
R5724
0R0402-PAD
Q5702
PMBS3904-1-GP
HPD_HDMI_1
R5710
1
HPD_HDMI_CON
150KR2J-L1-GP
+3.3V_RUN
R5712
(13,82) HDMI_HPD_DET
DY 200KR2J-L1-GP
<Core Design>
Wistron Corporation
R5713
10KR2J-3-GP
1
A

Title
Size
A3
Date:
HDMI Level Shifter/Connector
Document Number
Rev

Sheet
1
57
of
A00
95
SSID = User.Interface
SSID = Thermal
Fan Connector
B
3
*Layout* 15 mil
(39) EMC2102_FAN_TACH
EMC2102_FAN_TACH
(39) EMC2102_FAN_DRIVE
EMC2102_FAN_DRIVE
FAN1
AFTP5801
5
3
2
1
4
FOX-CON3-6-GP-U
D5801
CH551H-30PT-GP
AFTP5802
EMC2102_FAN_TACH
AFTP5803
EMC2102_FAN_DRIVE
20.D0210.103
20.F1293.003
C5801
SC10U10V5ZY-1GP
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
ITP/Fan Connector
Document Number
Rev

Sheet
1
58
A00
of
95
SSID = SATA
SATA HDD Connector

9/24
HDD1
+3.3V_RUN
1
C5901
V33
V33
V33
P7
P8
P9
V5
V5
V5
P13
P14
P15
C5906
C5904
SC10U6D3V5MX-3GP
2
1
1118-2
(22) SATA_RXP0
(22) SATA_RXN0
V12_1
V12_2
V12_3
S2
S3
A+
A-
S6
S5
B+
B-
16
17
18
16
17
18
GND
GND
GND
GND
GND
GND
GND
GND
S1
S4
S7
P4
P5
P6
P10
P12
DAS/DSS
P11
SKT-SATA7P-15P-17-GP
62.10065.C71
9/24
ODD Connector
ODD1
8
NP1
S1
SATA_RXN1 (22)
SATA_RXP1 (22)
SATA_RX- and SATA_RX+ Trace

Length match within 20 mil
+5V_RUN
1231-2
C5909
SC10U10V5ZY-1GP
P1
P2
P3
P4
P5
P6
NP2
9
SATA_TXP1 (22)
SATA_TXN1 (22)
S2
S3
S4
S5
S6
S7
C5905
SC10U10V5ZY-1GP
2
1
SC56P50V2JN-2GP
(22) SATA_TXP0
(22) SATA_TXN0
SC56P50V2JN-2GP
+5V_RUN
P1
P2
P3
C5910
SC10U10V5ZY-1GP
DY
SKT-SATA7P+6P-42-GP
62.10065.581
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
Document Number
HDD/ODD
Rev

Sheet
59
A00
of
95
SSID = AUDIO
Speaker
Connector
AUD_HP1_JACK_L1
AUD_HP1_JACK_R2
AUD_HP1_JACK_R1
AFTP6001
AFTP6005
AFTP6007
AFTP6009
AFTP6002
AFTP6003
AUD_SPK_LAUD_SPK_L+
AUD_SPK_RAUD_SPK_R+
1
1
1
1
AFTP6004
AFTP6008
AUD_HP1_JD#
AUD_HP1_JACK_L1
AUD_HP1_JACK_R1
EC6006
SC1KP50V2KX-1GP
1
2
1
1
EC6005
SC1KP50V2KX-1GP
AUD_HP1_JACK_L2
(30) AUD_HP1_JACK_R2
0303-1
DY
2
DY
(30) AUD_HP1_JACK_L2
LINEOUT1
L6002
BLM18BD601SN1D-GP
EC6004
SC100P50V2JN-3GP
EC6003
SC100P50V2JN-3GP
DY
2
EC6002
SC100P50V2JN-3GP
EC6001
SC100P50V2JN-3GP
DY
AUD_HP1_JD#
L6001
6
5
2
SCD01U16V2KX-3GP
2
3
4
X01 0713
BLM18BD601SN1D-GP
(30) AUD_HP1_JD#
EC6008
(30) AUD_SPK_L+
(30) AUD_SPK_R(30) AUD_SPK_R+
SPK1
FOX-CON4-24-GP
SCD01U16V2KX-3GP
EC6007
(30) AUD_SPK_L-
Main 20.F0693.004
SEC. 20.F0693.004
LINE1
OUT
4
1
3
7
8
PHONE-JK383-GP
0107-2
600ohm 100MHz
200mA 0.5ohm DC
AFTP6006
22.10133.K31
AUD_AGND
1117-1
MIC IN
Internal
Microphone
MIC1 is in DIP
C6003
SC1U10V3KX-3GP
3
4
(30) INT_MIC_L_R
MICIN1
MIC_IN_L_C
8
7
3
1
4
MIC_IN_R_C
2
5
6
R6001
(30) AUD_EXT_MIC_L
AUD_EXT_MIC_L C6001
1 SC1U10V3KX-3GP
MIC_IN_L_2
2
1
0R0603-PAD
R6002
(30) AUD_EXT_MIC_R
AUD_EXT_MIC_R C6002
1 SC1U10V3KX-3GP
MIC_IN_R_2
1
2
0R0603-PAD
X01 0713
MIC1
MICROPHONE-40-GP-U1
EC6009
SC1KP50V2KX-1GP
23.42143.001
2
RN6001
SRN4K7J-8-GP
2
1
(30) AUD_VREFOUT_B
1117-1
R6005 1
0R2J-2-GP
R6004 1
0R2J-2-GP
R6003 1
0R2J-2-GP
R6006 1
0R2J-2-GP
R6009 1
0R2J-2-GP
R6008 1
0R2J-2-GP
R6010 1
0R2J-2-GP
PHONE-JK383-GP
(30) EXT_MIC_JD#
EC6011
22.10133.K31
AFTP6012
AFTP6013
1
1
MIC_IN_R_C
EXT_MIC_JD#
SC100P50V2JN-3GP
AFTP6011
MIC_IN_L_C
SC100P50V2JN-3GP
2
EC6010
AFTP6010
2
2
DY 2
DY 2
2
DY 2
DY 2
AUD_AGND
AUD_AGND
1117-1
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
Audio Jack
Rev
Berry
A00
Sheet
1
60
of
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
Reserved
Rev

Sheet
1
61
of
A00
95
SSID = Flash.ROM
SPI FLASH ROM (16M bits) for KBC

+KBC_PW R
2
1
DY
DY
2
C6201
DY
C6203
SCD1U10V2KX-5GP
RN6201
SRN100KJ-6-GP
R6201
100KR2J-1-GP
SCD1U10V2KX-5GP
2
1
3
4
1118-2
C6202
SCD1U10V2KX-5GP
+KBC_PW R
1231-2
EC_SPI_HOLD#
1231-1
CS#
DO/IO1
WP#/IO2
GND
VCC
HOLD#/IO3
CLK
DI/IO0
8
7
6
5
EC_SPI_HOLD#
EC_SPI_DO_R
R6204
EC6202
SC4D7P50V2CN-1GP
1215-2
DY
33R2J-2-GP
EC_SPI_CLK (37)
EC_SPI_DO (37)
W 25Q16BVSSIG-GP
R6207
100KR2J-1-GP
DY
2
EC6201
SC4D7P50V2CN-1GP
1
2
3
4
1
1
R6202
R6203
+KBC_PW R
U6201
EC_SPI_CS#
2 0R0402-PAD EC_SPI_DI_R
2 0R0402-PAD EC_SPI_W P#
(37) EC_SPI_CS#
(37) EC_SPI_DI
(37) EC_SPI_W P#_R
EC6203
SC22P50V2JN-4GP
1117-6
PN:72.25Q16.001
SSID = RBATT
+3.3V_RTC_LDO
D6201
BAT54C-U-GP
0105-8
R6205
1
2
0R0402-PAD
RTC_PW R_L
RTC Connector
1
+RTC_CELL
3
+RTC_VCC
1225-5
C6204
SC1U10V3KX-3GP
RTC1
1
2
RTC_PW R
1 R6206 2
1KR2J-1-GP
AFTP6203
Width=20mils
1
2
NP1
NP2
<Core Design>
Wistron Corporation

BAT-CON2-1-GP-U
Title
AFTP6202
+RTC_VCC
62.70001.011
Size
A3
Date:
PWR
GND
NP1
NP2
Document Number
Flash/RTC
Rev

Sheet
1
62
A00
of
95
SSID = USB
Close to I/O connector
IO Board USB Power

Support 2A
+5V_ALW
+5V_USB1
U6301
(37) USB_PWR_EN#
GND
VIN
VIN
EN#
VOUT#8
VOUT#7
VOUT#6
OC#
at least 80 mil
8
7
6
5
C6301
DY
UP7534BRA8-15-GP
DY
C6302
SC1U10V3KX-3GP
1
2
3
4
SCD1U10V2KX-5GP
2
1
at least 80 mil
9/30
USB_OC#0_1 (21)
1231-2
CRT Board USB Power
Close to CRT Board connector

Support 2A
+5V_ALW
+5V_USB2
U6302
(37) USB_PWR_EN#
VOUT#8
VOUT#7
VOUT#6
OC#
at least 80 mil
8
7
6
5
GND
VIN
VIN
EN#
C6304
SC1U10V3KX-3GP
1
2
3
4
C6303
SCD1U10V2KX-5GP
2
1
at least 80 mil
DY
2
9/30
UP7534BRA8-15-GP
1231-2
USB_OC#2_3 (21)
1118-2
<Core Design>
Wistron Corporation

Title
Document Number
Size
USB Power SW
Rev

5
Sheet
63
of
1
A00
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Reserved
Size
A4
Document Number

5
Sheet
64
of
1
Rev
A00
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
Reserved
Rev

Sheet
1
65
of
A00
95
Power LED(White)
9/25
+5V_ALW
Q6602
R2
PW RLED#_C
R1
0111-2
E
LED_PW R
10/1
1
2
(22) SATA_LED#
(37) PW RLED#
SATA_LED#_C
PW RLED#_C
4
3
84.00143.M11
DYSC220P50V2KX-3GP
2
PDTA143ET-GP
RN6601
RN6602
4
3
9/25
Q6601
R2
SATA_LED#_C
POW ER_SW _LED_C

DY 21KR2J-1-GP
0208-1
SATA_LED_R
1215-3
0111-2
R1
2AMBER_LED#_KBC
SCD1U10V2KX-5GP
2W HITE_LED#_KBC
SCD1U10V2KX-5GP
POW ER_SW _LED_B

2
470R2J-2-GP
+5V_RUN
SRN15KJ-3-GP
1
C6601
1
C6602
1
R6603
SATA HDD LED(White)
AMBER_LED_BAT#
W HITE_LED_BAT#
PDTA143ET-GP
1116-7
DY
84.00143.M11
2
1KR2J-1-GP
SATA_LED
R6604
10/8
EC6604
SC220P50V2KX-3GP
1
2
PW R_LED_B
2
1KR2J-1-GP
1
R6609
SRN15KJ-3-GP
(37) AMBER_LED#_KBC
(37) W HITE_LED#_KBC
1
R6601
EC6601
LEDBD1
Battery LED1(White)
9/25
Q6603
R2
W HITE_LED_BAT#
0111-2
E
W HITE_LED_BAT
R1
PDTA143ET-GP
2
1KR2J-1-GP
SATA_LED
BAT_W HITE
BAT_AMBER
2
3
4
5
6
BAT_W HITE
R6602
EC6602
SC220P50V2KX-3GP
DY
2
84.00143.M11
PW R_LED_B
+5V_ALW
ACES-CON6-13-GP
20.K0320.006
Battery LED2(Amber)
9/25
R2
R1
AMBER_LED_BAT#
+5V_ALW
Q6604
0111-2
E
AMBER_LED_BAT
R6606
DY
2
84.00143.M11
BAT_AMBER
2
1KR2J-1-GP
PDTA143ET-GP
EC6603
SC220P50V2KX-3GP
Power button LED(White)

1216-1
(37) KBC_PW RBTN#
1
R6605
PW RBTN1
2
0R0402-PAD
5
1
+5V_ALW
9/25
Q6605
E
C
POW ER_SW _LED_R
1
R6608
EC6605
84.00143.M11
2
3
4
6
POW ER_SW _LED_B

DY 21KR2J-1-GP
ACES-CON4-10-GP-U
20.K0320.004
DY
PDTA143ET-GP
R1
SC180P50V2JN-1GP
2 PW R_BTN_LED#_C
15KR2J-1-GP
0208-1
<Core Design>
Wistron Corporation

9/16
Title
Size
A3
Date:
R2
(37) PW R_BTN_LED#
1
R6607
0208-1
POW ER_SW _LED_C
1
DY 21KR2J-1-GP
R6610
KBC_PW RBTN#_C
POW ER_SW _LED_C
POW ER_SW _LED_B
LED Bard/Power Button
Document Number
Rev
Berry
A00
Sheet
1
66
of
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
Reserved
Rev

Sheet
1
67
of
A00
95
SSID = KBC
SSID = Touch.Pad
Internal KeyBoard Connector
TouchPad Connector
0111-1
+5V_RUN
KB1
AFTP6801
31
1
AFTP6802
AFTP6803
AFTP6804
AFTP6805
AFTP6806
AFTP6807
AFTP6808
AFTP6809
AFTP6810
AFTP6811
AFTP6812
AFTP6813
AFTP6814
AFTP6815
AFTP6816
AFTP6817
AFTP6818
AFTP6819
AFTP6821
AFTP6823
AFTP6822
AFTP6824
AFTP6825
AFTP6826
AFTP6827
+5V_RUN
10/7
2
1
10/2
RN6801
SRN10KJ-5-GP
(37)
KCOL[0..16]
(37)
TPAD1
6
3
4
KROW [0..7]
4
3
2
1
1
(37) TPCLK
(37) TPDATA
C6802
SC33P50V2JN-3GP
1
AFTP6820
C6803
SC33P50V2JN-3GP
1
C
5
ACES-CON4-10-GP-U
20.K0320.004
20.K0326.004
AFTP6828
32
SCD1U10V2KX-5GP
C6801
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
KB_DET# (37)
KROW 7
KROW 6
KROW 4
KROW 2
KROW 5
KROW 1
KROW 3
KROW 0
KCOL5
KCOL4
KCOL7
KCOL6
KCOL8
KCOL3
KCOL1
KCOL2
KCOL0
KCOL12
KCOL16
KCOL15
KCOL13
KCOL14
KCOL9
KCOL11
KCOL10
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
AFTP6829
AFTP6830
AFTP6831
ACES-CON30-8-GP
1
1
1
+5V_RUN
TPCLK
TPDATA
20.K0524.030
20.K0461.030
KB Backlight Connector
0208-2
+5V_RUN
+5V_KB_BL
KB_LED_PW R 1
FUSE-D5A6V-2-GP
C6804
DY
BLM18PG181SN1D-GP
DY
DY
KBLIT1
C6805
SCD1U10V2KX-5GP
5
1
SC10U10V5KX-2GP
2
3
4
(37) KB_LED_BL_DET
DY
1
2
DYDY
DY
ACES-CON4-10-GP-U
1
+5V_KB_BL
KB_LED_BL_DET
KB_BL_CTRL#
1
1
1
AFTP6832
AFTP6833
AFTP6834
AFTP6835
<Core Design>
Wistron Corporation

0225-2
Title
Size
A3
Date:
SI3456DDV-T1-GE3-GP
R6801
100KR2J-1-GP
DY
SC10P50V2JN-4GP
EC6801
(37) KB_BL_CTRL
D 6
D 5
S 4
EC6802
SC10P50V2JN-4GP
Q6801
1 D
2 D
3 G
KB_BL_CTRL#
DY
20.K0320.004
L6801
F6801
Key Board/Touch Pad
Document Number
Rev

Sheet
1
68
A00
of
95
SSID = Hall.Sensor
D
9/29
+3.3V_ALW
+3.3V_ALW
LID_CLOSE#_1
9/29
11/9
+3.3V_ALW
9/17
1
DY
C6903
1
1
SCD1U10V2KX-5GP
2
1
AFTP6901
AFTP6902
R6901
100KR2J-1-GP
1231-1
R6902 1
2 0R0402-PAD
(37) LID_CLOSE#
LID_CLOSE#
DY
LID_CLOSE#_1
0208-3
HALLSW1
1
VDD
GND
OUTPUT
SOT23-2D8-213H56-COLAY-GP
C6902
SCD047U16V2KX-1-GP
74.06781.07B
AFTP6903
<Core Design>
Wistron Corporation

Title
Document Number
Size
A4
4
Rev

5
Hall Effect Sensor
Sheet
69
of
1
A00
95
SSID = Debug
D
+3.3V_RUN
DB1
(20,37) LPC_LAD0
(20,37) LPC_LAD1
(20,37) LPC_LAD2
(20,37) LPC_LAD3
(20,37) LPC_LFRAME#
(20,76,78) PLTRST#_LAN_WLAN
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
(20,24) PCLK_FWH
1
2
3
4
5
6
7
8
9
10
11
12
DY
MLX-CON10-7-GP
20.D0183.110
<Core Design>
Wistron Corporation

Title
Document Number
Size
A4
4
Rev

5
Dubug connector
Sheet
70
of
1
A00
95
(Blanking)
C
<Core Design>
Wistron Corporation

Title
RESERVED
Size
A4
Document Number

5
Sheet
71
of
1
Rev
A00
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
RESERVED
Rev

Sheet
1
72
A00
of
95
Bluetooth Module conn.
BT1
AFTP7302
AFTP7304
AFTP7305
AFTP7314
1
1
1
BLUETOOTH_DET#
W LAN_ACT
BDC_ON
BLUETOOTH_EN
BT_LED
BLUETOOTH_GPIO3
BLUETOOTH_GPIO5
3
5
7
9
11
13
15
NP1
2
4
6
8
10
12
14
NP2
16
HRS-CONN14D-GP-U
USB_PP9
USB_PN9
BT_ACT
BLUETOOTH_EN
W LAN_ACT
(21) USB_PP9
(21) USB_PN9
(76) BT_ACT
(37) BLUETOOTH_EN
(76) W LAN_ACT
+3.3V_RUN
BT_ACT
USB_PP9
USB_PN9
AFTP7301
C7301
SC2D2U6D3V3KX-GP
AFTP7313
AFTP7316
AFTP7317
AFTP7315
AFTP7318
AFTP7319
AFTP7320
1
1
1
1
1
1
W LAN_ACT
BLUETOOTH_EN
BT_ACT
+3.3V_RUN
USB_PP9
USB_PN9
EC7302
R7304
10KR2J-3-GP
DY
R7303
100KR2J-1-GP
SC56P50V2JN-2GP
2
1
1118-2
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
Bluetooth
Rev
Berry
A00
Sheet
1
73
of
95
(Blanking)
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
Reserved
Rev

Sheet
1
74
of
A00
95
(Blanking)
C
<Core Design>
Wistron Corporation

Title
Size
A4
Document Number
Rev

5
Reserved
Sheet
75
of
1
A00
95
SSID = Int.Conn
10/9
IOBD1
85
86
ESATA USB
SATA_TXN2 (22)
(21) USB_PN0
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
SATA_TXP2 (22)
83
82
81
NP2
(21) USB_PP5
(21) USB_PN5
USB PORT
(21) USB_PN1
(21) USB_PP1
WLAN USB
(21) USB_PP4
(21) USB_PN4
(37) E51_RXD
(37) E51_TXD
WWAN PCIE
WWAN PCIE
SMBUS
(12) PCIE_RXP2
(12) PCIE_RXN2
(12) PCIE_TXP2
(12) PCIE_TXN2
(18,19) SB_SMBDATA
(18,19) SB_SMBCLK
+DC_IN_SS
LAN PCIE
(37) WIFI_RF_EN
(7) WWAN_CLK_REQ#
(37) WWAN_RADIO_DIS#
(37) PSID_DISABLE#
(37) 8103_GPO
(12) PCIE_RXP1
(12) PCIE_RXN1
1216-2
LAN PCIE
(21) USB_PP0
WWAN USB
NP1
84
(12) PCIE_TXP1
(12) PCIE_TXN1
SATA(ESATA)
SATA_RXN2 (22)
SATA_RXP2 (22)
SATA(ESATA)
PCIE_TXP0 (12)
PCIE_TXN0 (12)
WLAN PCIE
PCIE_RXP0 (12)
PCIE_RXN0 (12)
WLAN PCIE
CLK_PCIE_WLAN (7)
CLK_PCIE_WLAN# (7)
WLAN CLK
CLK_PCIE_LAN (7)
CLK_PCIE_LAN# (7)
LAN CLK
CLK_PCIE_WWAN (7)
CLK_PCIE_WWAN# (7)
WWAN CLK
at least 80 mil
+5V_USB1
+5V_ALW
+3.3V_RUN
+3.3V_ALW
+1.5V_RUN
0208-2
PM_LAN_ENABLE (37)
PLTRST#_LAN_WLAN (20,70,78)
WLAN_CLK_REQ# (7)
PCIE_WAKE# (21)
BT_ACT (73)
WLAN_ACT (73)
PSID_EC (37)
ACES-CONN80D-GP
20.F1009.080
<Core Design>
Wistron Corporation
0107-6
C7602
C7601
1
1
DY2
SC10P50V2JN-4GP
2

USB_PP5
USB_PN5
Title
SC10P50V2JN-4GP
DY
IO Board Connector
Document Number
Size
A4

5
Sheet
76
of
1
Rev
A00
95
10/1
SSID = Int.Conn
CRT Board Connector

CRTBD1
11/12-5
CRT_R
2
1
BLM18BB220SN-GP
CRT_G
2
1
BLM18BB220SN-GP
CRT_B
2
1
BLM18BB220SN-GP
L7702
CRT_GREEN
DY
1116-8
C7704
SC15P50V2JN-2-GP
2
SC15P50V2JN-2-GP
2
C7702
SC15P50V2JN-2-GP
2
CRT_BLUE
DY
SC8P250V2CC-GP
C7707
4
3
2
1
DY
SC8P250V2CC-GP
C7705
5
6
7
8
SC8P250V2CC-GP
C7706
L7701
C7703
at least 80 mil
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CRT_RED
0108-2
Pin define modified

1117-3
21
L7703
RN7713
SRN150F-1-GP
+5V_USB2
+5V_RUN
USB_PN2 (21)
USB_PP2 (21)
USB PORT
USB_PN3 (21)
USB_PP3 (21)
USB PORT
CRT_RED
0208-4
CRT_GREEN
CRT RGB
CRT_RED
1
CRT_GREEN 1
CRT_BLUE 1
CRT_BLUE
CRT_HSYNC_CON
CRT_VSYNC_CON
CRT_DDCCLK_CON
CRT_DDCDATA_CON
CRT H/VSYNC
CRT SMBUS
AFTP7701
AFTP7702
AFTP7703
22
ACES-CON20-1-GP-U
20.F0772.020
SEC. 20.F1035.020
Close to CRT Board CONN
Close to CRT Board CONN
CRT Hsync & Vsync level shift
CRT RGB
C7701
SCD1U10V2KX-5GP
DIS
CRT_R
CRT_G
CRT_B
8
7
6
5
+5V_RUN_CRT
RN7701
1
2
3
4
(82) VGA_CRT_RED
(82) VGA_CRT_GREEN
(82) VGA_CRT_BLUE
1120-2
+5V_RUN_CRT
Filter design on CRT Board

+5V_RUN
D7701
1
CH551H-30PT-GP
SRN0J-7-GP
1
2
CRT_HSYNC_CON
CRT_VSYNC_CON
1
2
SRN33J-5-GP-U
13
14
U7702
CRT_DDCDATA_CON
CRT_DDCCLK_CON
10
2
1
14
3.3V Tolerance
9/29
CRT_DDCDATA_CON_C
0108-2
U7701D
12
(13) VGA_HSYNC
(13) VGA_VSYNC
UMA
RN7710
SRN0J-6-GP
4
3
DIS
RN7711
3
4
9/18
4
3
9/15
RN7712
SRN2K2J-1-GP
(82) VGA_CRT_DDCCLK
(82) VGA_CRT_DDCDATA
RN7705
CRT_VSYNC_OUT
+5V_RUN_CRT
9/29
RN7709
SRN0J-6-GP
4
3
TSAHCT125PW -GP
TSAHCT125PW -GP
1
2
CRT_HSYNC_OUT
+3.3V_RUN
5V Tolerance
U7701B
CRT DDCDATA & DDCCLK
(13) DDC_DATA_CON
(13) DDC_CLK_CON
U7701A
(80,82) VGA_CRT_HSYNC
(80,82) VGA_CRT_VSYNC
14
UMA
8
7
6
5
3.3V Tolerance
RN7702
1
2
3
4
(13) M_BLUE
(13) M_GREEN
(13) M_RED
9/18
14
SRN0J-7-GP
11
NB_HSYNC_OUT 3
4
TSAHCT125PW -GP
2
1
UMA
SRN0J-6-GP
U7701C
NB_VSYNC_OUT
8
TSAHCT125PW -GP
DMN66D0LDW -7-GP
CRT_DDCCLK_CON_C
DIS
5V Tolerance
Pull High 5V Design on CRT Board
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
Document Number
CRT Board Connector
Rev

Sheet
1
77
A00
of
95
SSID = SDIO
D
Card Reader connector

10/7
+3.3V_RUN
CARDBD1
7
1116-9
(20,70,76) PLTRST#_LAN_WLAN
(21) USB_PN10
(21) USB_PP10
2
3
4
5
6
8
MLX-CON6-21-GP
20.F1035.006
<Core Design>
Wistron Corporation

Title
CARD Reader CONN
Document Number
Size
A4

5
Rev

2
Sheet
78
A00
of
95
H2
HTE95BE95R29-R-5-GP
H3
HTE95BE95R29-R-5-GP
H4
HTE95BE95R29-R-5-GP
H6
HTE95BE95R29-R-5-GP
H7
HTE95BE95R29-R-5-GP
H8
HTE95BE95R29-R-5-GP
H9
HTE95BE95R29-R-5-GP
H5
HOLE256R111-GP
H1
HTE95BE95R29-R-5-GP
H11
HOLE256R111-GP
CPU Thermal module hole

HTML2
HOLE197R166-GP
stand off
HTML3
HOLE197R166-GP
HGPU1
STF237R117H83-1-GP
HBT1
STF237R117H123-GP
HTML1
HOLE197R166-GP
0210-2
GPU Thermal module hole
H10
HOLE335R115-GP
DY
DY
DY
DY
EMI Reserve
C
+PW R_SRC
+VGA_CORE
+5V_ALW
+3.3V_RUN
SPR1
DY
DY
SCD1U25V2KX-GP
DY
SPRING-58-GP
EC7912
DY
EC7911
SCD1U25V2KX-GP
EC7910
10/6
1
EC7907
SCD1U25V2KX-GP
SCD1U25V2KX-GP
EC7906
DY
SCD1U25V2KX-GP
EC7905
SCD1U10V2KX-5GP
2
1
1
EC7903
DY
2
SCD1U25V2KX-GP
EC7904
SCD1U25V2KX-GP
EC7902
SCD1U25V2KX-GP
EC7901
SCD1U25V2KX-GP
1118-2
10/5
1117-4
EMI Reserve
+3.3V_RUN
1118-2
DY
2
EC7923
DY
EC7917
SC10P50V2JN-4GP
1
DY
EC7920
SC10P50V2JN-4GP
1
DY
EC7916
SC10P50V2JN-4GP
1
SC10P50V2JN-4GP
1
EC7924
SC10P50V2JN-4GP
1
+3.3V_RUN
+5V_RUN
+5V_RUN
+VCC_CORE
+5V_RUN
+PW R_SRC
2
DY
1 EC7922
SC10P50V2JN-4GP
2
DY
1 EC7919
SC10P50V2JN-4GP
2
DY
1 EC7914
SC10P50V2JN-4GP
2
DY
1 EC7915
SC10P50V2JN-4GP
2
DY
1 EC7921
SC10P50V2JN-4GP
2
DY
1 EC7913
SC10P50V2JN-4GP
RF Team Solution
0106-3 RF Team Solution
0108-1
2
DY
1 EC7918
SC10P50V2JN-4GP
+1.5V_SUS
C7922
DY
EC7927
DY
SC56P50V2JN-2GP
2
1
C7917
SC56P50V2JN-2GP
2
1
C7902
SC56P50V2JN-2GP
2
1
C7904
DY
+PW R_SRC
SC56P50V2JN-2GP
2
1
C7905
SC56P50V2JN-2GP
2
1
C7906
DY
+5V_RUN
SC56P50V2JN-2GP
2
1
SC56P50V2JN-2GP
2
1
+1.5V_RUN
SC56P50V2JN-2GP
2
1
SC56P50V2JN-2GP
2
1
C7909
+1.5V_RUN
EMC reserved
+PW R_SRC
+3.3V_ALW
+5V_RUN
DY
EC7926
DY
SC56P50V2JN-2GP
2
1
+PW R_SRC
EC7925
DY
0224-1
+DC_IN_SS
<Core Design>
+SDC_IN
DY
DY
SC56P50V2JN-2GP
2
1
DY
SC56P50V2JN-2GP
2
1
DY
SC56P50V2JN-2GP
2
1
C7921
Wistron Corporation

Title
DY
Size
A3
Date:
0225-5
SC56P50V2JN-2GP
2
1
C7920
SC56P50V2JN-2GP
2
1
C7919
SC56P50V2JN-2GP
2
1
SC56P50V2JN-2GP
2
1
SC56P50V2JN-2GP
2
1
SCD1U25V2KX-GP
2
1
SCD1U25V2KX-GP
2
1
C7908
+PW R_SRC
EC7932
DY
C7910
+1.5V_SUS
EC7929
DY
C7911
+3.3V_RUN
EC7931
DY
C7915
+1.8V_RUN
EC7930
C7907
+1.1V_RUN
SC56P50V2JN-2GP
2
1
+15V_ALW
SCD1U25V2KX-GP
2
1
UNUSED PARTS/EMI Capacitors

Document Number
Rev
Berry
A00
Sheet
1
79
of
95
CONFIGURATION STRAPS
(57) PCIE_N_H_TX_GRX_P[12..15]
10/8
(57) PCIE_N_H_TX_GRX_N[12..15]
1 OF 8
VGA1A
(12) PCIE_NTX_GRX_P[0..11]
(12) PCIE_NTX_GRX_N[0..11]
(12)
(12)
x01 change tolerant 20091117
PCIE_NTX_GRX_P0
PCIE_NTX_GRX_N0
AA38
Y37
PCIE_RX0P
PCIE_RX0N
PCIE_TX0P
PCIE_TX0N
Y33
Y32
PEG_C_RXP0C8001
PEG_C_RXN0C8002
1
DIS
1
DIS
2 SCD1U10V2KX-5GP PCIE_NRX_GTX_P0
2 SCD1U10V2KX-5GP PCIE_NRX_GTX_N0
PCIE_NTX_GRX_P1
PCIE_NTX_GRX_N1
Y35
W36
PCIE_RX1P
PCIE_RX1N
PCIE_TX1P
PCIE_TX1N
W33
W32
PEG_C_RXP1C8003
PEG_C_RXN1C8004
1
DIS
1
DIS
PCIE_NTX_GRX_P2
PCIE_NTX_GRX_N2
W38
V37
PCIE_RX2P
PCIE_RX2N
PCIE_TX2P
PCIE_TX2N
U33
U32
PEG_C_RXP2C8005
PEG_C_RXN2C8006
1
DIS
1
DIS
PCIE_RX3P
PCIE_RX3N
PCIE_TX3P
PCIE_TX3N
U30
U29
PEG_C_RXP3C8008
PEG_C_RXN3C8007
1
DIS
1
DIS
PCIE_NTX_GRX_P4
PCIE_NTX_GRX_N4
U38
T37
PCIE_RX4P
PCIE_RX4N
PCIE_TX4P
PCIE_TX4N
T33
T32
PEG_C_RXP4C8009
PEG_C_RXN4C8010
1
DIS
1
DIS
PCIE_NTX_GRX_P5
PCIE_NTX_GRX_N5
T35
R36
PCIE_TX5P
PCIE_TX5N
T30
T29
PEG_C_RXP5C8011
PEG_C_RXN5C8012
1
DIS
1
DIS
PCIE_RX5P
PCIE_RX5N
PCIE_NTX_GRX_P6
PCIE_NTX_GRX_N6
R38
P37
PCIE_RX6P
PCIE_RX6N
PCIE_NTX_GRX_P7
PCIE_NTX_GRX_N7
P35
N36
PCIE_RX7P
PCIE_RX7N
PCIE_NTX_GRX_P8
PCIE_NTX_GRX_N8
N38
M37
PCIE_RX8P
PCIE_RX8N
PCIE_NTX_GRX_P9
PCIE_NTX_GRX_N9
M35
L36
PCIE_RX9P
PCIE_RX9N
PCIE_NTX_GRX_P10
PCIE_NTX_GRX_N10
L38
K37
PCIE_RX10P
PCIE_RX10N
PCIE_NTX_GRX_P11
PCIE_NTX_GRX_N11
K35
J36
PCIE_RX11P
PCIE_RX11N
PCIE_N_H_TX_GRX_P12
PCIE_N_H_TX_GRX_N12
PCIE_N_H_TX_GRX_P13
PCIE_N_H_TX_GRX_N13
J38
H37
H35
G36
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCI EXPRESS INTERFACE
V35
U36
TX_PWRS_ENB
GPIO0
Transmitter Power Savings Enable

0: 50% Tx output swing 1: Full Tx output swing
GPIO1
PCIE TRANSMITTER DE-EMPHASIS ENABLED

0:Tx de-emphasis disabled 1:Tx de-emphasis enabled
GPIO2
0:Advertises the PCIe device as 2.5GT/s capable at power on.

1:Advertises the PCIe device as 5.0GT/s capable at power on.
GPIO5_AC_BATT
GPIO5
optional input allow the system to request a fast

power reduction by setting GPIO5 to low.
RESERVED
GPIO8
RESERVED
P33
P32
PEG_C_RXP6C8013
PEG_C_RXN6C8014
1
DIS
1
DIS
PCIE_TX7P
PCIE_TX7N
P30
P29
PEG_C_RXP7C8016
PEG_C_RXN7C8015
1
DIS
1
DIS
PCIE_TX8P
PCIE_TX8N
N33
N32
PEG_C_RXP8C8018
PEG_C_RXN8C8017
1
DIS
1
DIS
PCIE_TX9P
PCIE_TX9N
N30
N29
PEG_C_RXP9C8020
PEG_C_RXN9C8019
1
DIS
1
DIS
PCIE_TX10P
PCIE_TX10N
L33
L32
PEG_C_RXP10
C8021
PEG_C_RXN10
C8022
1
DIS
1
DIS
PCIE_TX11P
PCIE_TX11N
L30
L29
PEG_C_RXP11
C8023
PEG_C_RXN11
C8024
1
DIS
1
DIS
PCIE_TX12P
PCIE_TX12N
K33
K32
PEG_C_RXP12
C8025
PEG_C_RXN12
C8026
1
DIS
1
DIS
PCIE_TX13P
PCIE_TX13N
J33
J32
PEG_C_RXP13
C8028
PEG_C_RXN13
C8027
1
DIS
1
DIS
PCIE_TX14P
PCIE_TX14N
K30
K29
PEG_C_RXP14
C8030
PEG_C_RXN14
C8029
1
DIS
1
DIS
PCIE_N_H_TX_GRX_P15
PCIE_N_H_TX_GRX_N15
F35
E37
PCIE_RX15P
PCIE_RX15N
PCIE_TX15P
PCIE_TX15N
H33
H32
PEG_C_RXP15
C8032
PEG_C_RXN15
C8031
1
DIS
1
DIS
1
R8018
10KR2F-2-GP
VGA_RST# AA30
0105-3
Remove
1
R8021
A
RESERVED
GPIO21
V2SYNC
NC#AJ21
NC#AK21
PWRGOOD
PERST#
RESERVED
0
0 0 1
(256MB)
VIP Device Strap Enable indicates to the software driver that it sense
whether or not a VIP device is connected on the VIP Host interface.
RSVD
H2SYNC
RESERVED
RSVD
GENERICC
RESERVED
AUD[1]
HSYNC
AUD[0]
VSYNC
AUD[1:0]:11-Audio for both DisplayPort and HDMI
R8001
(82) TX_DEEMPH_EN
R8002
(82) BIF_GEN2_EN_A
R8003
R8004
R8005
(82) GPIO8_ROMSO
(82) CONFIG0
R8006
(82) CONFIG1
R8007
(82) CONFIG2
R8008
RN8001 1
2
DY
DY
DY
DY
DY
DIS
DY
DY
DIS
+3.3V_RUN_VGA
PIN STRAPS
2
3KR2J-2-GP
3KR2J-2-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
4
3 SRN10KJ-5-GP
0105-3
PCIE_CALRP
PCIE_CALRN
R8017 DIS
Y30 PCIE_CALRP
1
2
1K27R2F-L-GP
Y29 PCIE_CALRN
1
R8019
DIS
(82) VSYNC_DAC2
+1.0V_RUN_VGA
DIS_GPU
R8013
(82) BIOS_ROM_EN
R8014
(82) GPIO5_AC_BATT
R8015
R8016
(82) HSYNC_DAC2
2
2KR2F-3-GP
R8012
(82) GPIO21_BB_EN
DY
DY
DY
DY
DY
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
MADISON-PRO-2-GP
2
0R0402-PAD
<Core Design>
10/7
Wistron Corporation
2
1
DY

C8033
SCD1U10V2KX-5GP
Title
Size
A3
Date:
5
0:Disable external BIOS ROM device

1:Enable external BIOS ROM device
BIOS_ROM_EN GPIO_22_ROMCSB
PCIE_REFCLKP
PCIE_REFCLKN
CALIBRATION
AJ21
AK21
AH16
GPIO[13:11]
(77,82) VGA_CRT_VSYNC
(77,82) VGA_CRT_HSYNC
CLOCK
DIS_Park/Mad
PW RGOOD
ROMIDCFG[2:0]
BIOS_ROM_EN=1, Config[2:0] defines the ROM type

BIOS_ROM_EN=0, Config[2:0] defines the primary memory aperture size
(82) VGA_DIS
PCIE_RX14P
PCIE_RX14N
1204-3
GPIO9
G38
F37
AB35
AA36
VGA_DIS
0:VGA Controller capacity enabled

1:The device won't be recognized as the system's VGA controller
(82) TX_PW RS_ENB
PCIE_N_H_TX_GRX_P14
PCIE_N_H_TX_GRX_N14
(7) CLK_PCIE_VGA
(7) CLK_PCIE_VGA#
TX_DEEMPH_EN
VIP_DEVICE_STRAP_EN
PCIE_TX6P
PCIE_TX6N
PLATFORM
SETTING
PIN
BIF_GEN2_EN_A
PCIE_NTX_GRX_P3
PCIE_NTX_GRX_N3
RECOMMEND
DESCRIPTION OF DEFAULT SETTINGS
STRAPS
RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 3K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
GPU_PCIE/STRAPPING(1/5)
Document Number
Rev
A00
Berry
Sheet
1
80
of
95
DIS
R8110 1
243R2F-2-GP
CASA0# (85)
CASA1# (86)
K24
K27
CSA0#_0 (85)
M13
K16
CSA1#_0 (86)
Reserved for JTAG
K21
J20
CKEA0 (85)
CKEA1 (86)
K26
L15
H23
J19
AD28
CLKTESTA AK10
CLKTESTB AL10
R8122
1KR2J-1-GP
MADISON-PRO-2-GP
CLKB0
CLKB0#
CLKB1
CLKB1#
RASB0#
RASB1#
CASB0#
CASB1#
CSB0#_0
CSB0#_1
CSB1#_0
CSB1#_1
CKEB0
CKEB1
MVREFDB
MVREFSB
WEB0#
WEB1#
TEST_EN
MAA13 (85,86)
RN8101
SRN4K7J-8-GP
TESTEN
MAB0_8
MAB1_8
CLKTESTA
CLKTESTB
F6
K3
P3
V5
AB5
AH1
AJ9
AM5
QSBP_0
QSBP_1
QSBP_2
QSBP_3
QSBP_4
QSBP_5
QSBP_6
QSBP_7
(87)
(87)
(87)
(87)
(88)
(88)
(88)
(88)
G7
K1
P1
W4
AC4
AH3
AJ8
AM3
QSBN_0
QSBN_1
QSBN_2
QSBN_3
QSBN_4
QSBN_5
QSBN_6
QSBN_7
(87)
(87)
(87)
(87)
(88)
(88)
(88)
(88)
T7
W7
CLKB0 (87)
CLKB0# (87)
AD8
AD7
CLKB1 (88)
CLKB1# (88)
T10
Y10
RASB0# (87)
RASB1# (88)
W10
AA10
CASB0# (87)
CASB1# (88)
P10
L10
CSB0#_0 (87)
AD10
AC10
CSB1#_0 (88)
U10
AA11
CKEB0 (87)
CKEB1 (88)
N10
AB11
+1.5V_RUN
WEB0# (87)
WEB1# (88)
T8
W8
AH11
(87)
(87)
(87)
(87)
(88)
(88)
(88)
(88)
ODTB0 (87)
ODTB1 (88)
L9
L8
** R_MEM_3
DY R8102
2K2R2J-2-GP
MAB13 (87,88)
DRAM_RST
** R_MEM_2
1
R8103
** R_MEM_1 R8105
10KR2J-3-GP
DIS_VRAMRST
2DIS_VRAMRST
0R2J-2-GP
** C_MEM
MEM_RST (85,86,87,88)
C8103
SC2200P50V2KX-2GP
3
4
DIS_VRAMRST
1218-2
2MEM_CALRP1
** This
basic topology should be used for DRAM_RST for

DDR3/GDDR3/GDDR5.These Capacitors and Resistor values
are an example only. The Series R and || Cap values
will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board
to pass Reset Signal Spec.
DIS_Mad
MEM_CALRP2
2
PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC
R8115
C8107
SCD1U10V2KX-5GP
For Mannhatton
For M96-M2
R_MEM_1
68pF
R_MEM_2
51R
R_MEM_3
DNI
DNI
C_MEM
10K
2.2nF
10K
0R/Short
X02-20091218
SCD1U10V2KX-5GP
MVREFSB
DIS
DISR8120
Rb 100R2F-L1-GP-U
C8106
MVREFDB
DIS
DISR8119
Rb 100R2F-L1-GP-U
2
SCD1U10V2KX-5GP
Ra 100R2F-L1-GP-U
DIS_MEMVREF
DIS_M96/Mad
R8118
C8105
DIS_M96/Mad
Rb 100R2F-L1-GP-U
Designator
R8116
Ra 100R2F-L1-GP-U
DIS_MEMVREF
MVREFSA
1
1
2
SCD1U10V2KX-5GP
1
R8114
100R2F-L1-GP-U
DIS_MEMVREF_M96/Mad
2
2
1
MVREFDA
DIS_M96/Mad
R8117
C8104
DIS_M96/Mad
Rb 100R2F-L1-GP-U
+1.5V_RUN
Ra
R8113
100R2F-L1-GP-U
DIS_MEMVREF_M96/Mad
Ra
+1.5V_RUN
+1.5V_RUN
+1.5V_RUN
1204-1
R8112 1
243R2F-2-GP
DQMB0
DQMB1
DQMB2
DQMB3
DQMB4
DQMB5
DQMB6
DQMB7
MADISON-PRO-2-GP
DIS_Mad
MEM_CALRP0
R8111 1
243R2F-2-GP
B
DRAM_RST#
H3
H1
T3
T5
AE4
AF5
AK6
AK5
DIS_GPU
DIS_M96
1215-4
2
R8107
ADBIB0/ODTB0
ADBIB1/ODTB1
DIS_Mad
DIS_GPU
R8106
Y12
AA12
R8121
10KR2J-3-GP
WEA0# (85)
WEA1# (86)
DIS_M96
MVREFDB
MVREFSB
+3.3V_RUN_VGA
DDBIB0_0/QSB_0#/WDQSB_0
MAB0 (87,88)
MAB1 (87,88)
MAB2 (87,88)
MAB3 (87,88)
MAB4 (87,88)
MAB5 (87,88)
MAB6 (87,88)
MAB7 (87,88)
MAB8 (87,88)
MAB9 (87,88)
MAB10 (87,88)
MAB11 (87,88)
MAB12 (87,88)
B_BA2 (87,88)
B_BA0 (87,88)
B_BA1 (87,88)
RASA0# (85)
RASA1# (86)
R8104
DIS_Mad MEM_CALRN2
1
243R2F-2-GP
CLKA1 (86)
CLKA1# (86)
DIS_Park/Mad
MEM_CALRN1
1
243R2F-2-GP
CLKA0 (85)
CLKA0# (85)
WCKB0_0/DQMB_0
WCKB0#_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0#_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1#_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1#_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9
M12
M27
AH12
DIS_Mad MEM_CALRN0
1
243R2F-2-GP
ODTA0 (85)
ODTA1 (86)
MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1
CSA1#_0
CSA1#_1
(88) MDB[32..63]
DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63
+1.5V_RUN
CSA0#_0
CSA0#_1
MAA0_8
MAA1_8
(85)
(85)
(85)
(85)
(86)
(86)
(86)
(86)
K20
K17
CASA0#
CASA1#
MEM_CALRP1
MEM_CALRP0
MEM_CALRP2
QSAN_0
QSAN_1
QSAN_2
QSAN_3
QSAN_4
QSAN_5
QSAN_6
QSAN_7
C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5
MEM_CALRP1
MEM_CALRP0
MEM_CALRP2
A34
E30
E26
C20
C16
C12
J11
F8
K23
K19
RASA0#
RASA1#
WEA0#
WEA1#
(85)
(85)
(85)
(85)
(86)
(86)
(86)
(86)
J14
H14
CLKA1
CLKA1#
MEM_CALRN0
MEM_CALRN1
MEM_CALRN2
QSAP_0
QSAP_1
QSAP_2
QSAP_3
QSAP_4
QSAP_5
QSAP_6
QSAP_7
(85)
(85)
(85)
(85)
(86)
(86)
(86)
(86)
MEM_CALRN0
L27
MEM_CALRN1
N12
MEM_CALRN2 AG12
C34
D29
D25
E20
E16
E12
J10
D7
H27
G27
CLKA0
CLKA0#
CKEA0
CKEA1
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
J21
G19
ADBIA0/ODTA0
ADBIA1/ODTA1
MVREFDA
MVREFSA
A32
C32
D23
E22
C14
A14
E10
D9
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
4 OF 8
DDR2
GDDR5/GDDR3
DDR3
GDDR5
L18
L20
DDBIA0_0/QSA_0#/WDQSA_0
MAA0 (85,86)
MAA1 (85,86)
MAA2 (85,86)
MAA3 (85,86)
MAA4 (85,86)
MAA5 (85,86)
MAA6 (85,86)
MAA7 (85,86)
MAA8 (85,86)
MAA9 (85,86)
MAA10 (85,86)
MAA11 (85,86)
MAA12 (85,86)
A_BA2 (85,86)
A_BA0 (85,86)
A_BA1 (85,86)
10/8
2
1
MVREFDA
MVREFSA
WCKA0_0/DQMA_0
WCKA0#_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0#_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1#_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1#_1/DQMA_7
GDDR5/DDR2/GDDR3
EDCA0_0/QSA_0/RDQSA_0
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17
MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_13_BA2
MAA1_6/MAA_14_BA0
MAA1_7/MAA_A15_BA1
(86) MDA[32..63]
DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63
VGA1D
DDR2
GDDR3/GDDR5
DDR3
(87) MDB[0..31]
C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5
3 OF 8
DDR2
GDDR5/GDDR3
DDR3
GDDR5
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
MEMORY INTERFACE A
10/8
VGA1C
DDR2
GDDR3/GDDR5
DDR3
(85) MDA[0..31]
MEMORY INTERFACE B
x01 Change tolerant 20091117
DDR3/GDDR3 Memory Stuff Option(Mad/Park)

GDDR5
GDDR3
DDR3
1.5V
1.8V/1.5V
1.5V
Ra
40.2R
40.2R
40.2R
Rb
100R
100R
100R
MVDDQ
DDR3/GDDR3 Memory Stuff Option(M96/M92)

GDDR3
DDR3
1.8V
1.5V
Ra
40.2R
100R
Rb
100R
100R
MVDDQ
<Core Design>
Wistron Corporation
Title
Size
A2
Date:
5
GPU_Memory(2/5)
Document Number
Rev
A00
Berry
Sheet

1
81
of
95
10/8
Description
TXCAP_DPA3P
TXCAM_DPA3N
DDR3 Hynix-H5TQ1G63BFR-12C (800MHz)
TX0P_DPA2P
TX0M_DPA2N
MUTI GFX
DPA
DDR3 Samsung-K4W1G1646E-HC12 (800MHz)
TX1P_DPA1P
TX1M_DPA1N
DIS
DDC channel for LVDS
0R4P2R-PAD
4
1 GPU_LVDS_CLK_C AK26
3
2 GPU_LVDS_DATA_C AJ26
RN8202
(55) GPU_LVDS_CLK
(55) GPU_LVDS_DATA
Straps
DIS
+3.3V_RUN_VGA
(80) GPIO5_AC_BATT
TP8207
(80) GPIO8_ROMSO
(80) VGA_DIS
R8205
10KR2J-3-GP
(80) CONFIG0
(80) CONFIG1
(80) CONFIG2
DIS
GPIO6_VGA
TPAD14-GP
(55) VGA_BLEN
JTAG_TMS_VGA
TP8208
(89) PWRCNTL_0
TPAD14-GP
VPIO14_VGA
TPAD14-GP
GPIO16_SSIN
TPAD14-GP
GPIO18_VGA
THERMTRIP_VGA
TP8203
TP8209
0107-5
(89) PWRCNTL_1
(80) GPIO21_BB_EN
(80) BIOS_ROM_EN
R8204
Madison Only
JTAG SIGNAL OPTION
"1"(PU)
"1"(PU)
"0"(PD)
JTAG_TCK
10/7
"1"(PU)
CLK
JTAG_TMS
2
DY
SCD1U10V2KX-5GP
1
C8229
"1"(PU)
"1"(PU)
"1"(PU)
R
R#
1
2
DIS DIS
SC1U6D3V2KX-GP
2
1
DIS
1204-2
DPLL_VDDC
(1.1V@150mA DPLL_VDDC For M96)
(1.0V@125mA DPLL_VDDC For Madison)
DIS
VGA_CRT_RED
AE36
AD35
VGA_CRT_GREEN
AB34
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
DY
AN31
1113-3
80D6R2F-L-GP
1 R8211 2
XTALIN
AV33
XTALOUT AU34
DIS
DIS
1 R8220 2
150R2F-1-GP
2
1
R8210
0R2J-2-GP
XO_IN
AW34
DY
AW35
DY
(39) VGA_THERMDC
TP8214
C8226
SC470P50V2JN-GP
AF29
AG29
1 TPAD14-GP
FAN_PWM
AK32
C8222
AL31
TSVDD
DIS
AJ32
AJ33
GPU_LVDSA_TX0 (55)
GPU_LVDSA_TX0# (55)
AR37
AU39
GPU_LVDSA_TX1 (55)
GPU_LVDSA_TX1# (55)
AP35
AR35
GPU_LVDSA_TX2 (55)
GPU_LVDSA_TX2# (55)
AN36
AP37
VGA_CRT_HSYNC
VGA_CRT_VSYNC
GPU_RSET
AD34
AE34
AVDD
AC33
AC34
VDD1DI
RN8204
DIS
2
499R2F-2-GP
DIS
8
7
6
5
SRN150F-1-GP
+1.8V_RUN_VGA
AVDD
(1.8V@70mA AVDD For M96)
AVDD For Madison)
L8202 DIS
(1.8V@70mA
1
2
BLM15BD121SS1D-GP
C8201
SC4D7U6D3V3KX-GP
AG31
AG32
120ohm, 0.3A
C8202
SC4D7U6D3V3KX-GP
HSYNC_DAC2
VSYNC_DAC2
(1.8V@40mA VDD2DI For M96)

(1.8V@50mA VDD2DI For Madison)
(80)
(80)
AA29
R2SET
1
R8218
DIS
A2VDDQ
2
715R2F-GP
DIS
VGA_CRT_DDCCLK (77)
VGA_CRT_DDCDATA (77)
(1.8V@20mA A2VDDQ For M96)

(1.8V@1.5mA A2VDDQ For Madison)
2
0R3J-0-U-GP
C8212
DDC channel for CRT
DY
SCD1U10V2KX-5GP
AM27
AL27
AUX1P
AUX1N
AM19
AL19
DDC2CLK
DDC2DATA
XO_IN
GPU_HDMI_CLK (57)
GPU_HDMI_DATA (57)
C8213
DY
DDC channel for HDMI
AN20
AM20
AUX2P
AUX2N
DDC1/DDC2/DDC6 have 5V-tolerant
AL30
AM30
DDCCLK_AUX3P
DDCDATA_AUX3N
AL29
AM29
DDCCLK_AUX4P
DDCDATA_AUX4N
AN21
AM21
DDCCLK_AUX5P
DDCDATA_AUX5N
TS_FDO
AJ30
AJ31
DDC6CLK
DDC6DATA
AK30
AK29
DDCCLK_AUX7P
DDCDATA_AUX7N
TSVDD
TSVSS
C8207
SCD1U10V2KX-5GP
DIS
A2VDDQ
AM26
AN26
DDC1CLK
DDC1DATA
TS_A
C8206
DIS
+3.3V_RUN_VGA
1
R8203
THERMAL
DIS
AF33
R2SET
XO_IN2
C8204
DISSC1U6D3V2KX-GP
+1.8V_RUN_VGA
(3.3V@65mA A2VDD For M96)

(3.3V@130mA A2VDD For Madison)
AG33
AD33
DPLL_PVDD
DPLL_PVSS
PLL/CLOCK
C8203
DIS
VDD1DI
(1.8V@45mA VDD1DI For M96)
VDD1DI For Madison)
AD29
AC29
H2SYNC
V2SYNC
DPLL_VDDC
DIS
L8203 DIS
(1.8V@45mA
1
2
BLM15BD121SS1D-GP
AC32
AD32
AF32
C
Y
COMP
VREFG
DPLUS
DMINUS
1
R8214
10/1
(77)
VGA_CRT_RED
1
VGA_CRT_GREEN 2
VGA_CRT_BLUE
3
4
(77,80)
(77,80)
AF30
AF31
B2
B2#
A2VDD
XTALIN
XTALOUT
VGA_CRT_BLUE
+3.3V tolerant
AD30
AD31
G2
G2#
A2VDDQ
1204-2
(39) VGA_THERMDA
GPU_LVDSA_TXC (55)
GPU_LVDSA_TXC# (55)
(77)
AC30
AC31
R2
R2#
DDC/AUX
11/6
AP34
AR34
AW37
AU35
MADISON-PRO-2-GP
(77)
120ohm, 0.3A
DY
AD39
AD37
AC36
AC38
HPD1
C8220
SC4D7U6D3V3KX-GP
C8221
470ohm, 1A
SC1U6D3V2KX-GP
2
1
2
BLM18PG471SN1D-GP
R8221 1 XO_IN
0R2J-2-GP
AM32
AN32
1
2
TXOUT_L3P
TXOUT_L3N
DPLL_PVDD
DPLL_VDDC
C8230
DIS
AH13
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
AF37
AE38
B
B#
HSYNC
VSYNC
A2VSSQ
SCD1U10V2KX-5GP
DIS
(7) CLK_VGA_27M_NSS
C8219
C8218
SCD1U10V2KX-5GP
1
L8207
G
G#
C8217
1215-5
SCD1U10V2KX-5GP
+1.0V_RUN_VGA
GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
DAC1
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCS#
GPIO_23_CLKREQ#
JTAG_TRST#
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
DAC2
GENERICF
GENERICG
PLACE VREFG DIVIDER AND CAP

CLOSE TO ASIC
GPU_VREFG
1
DPLL_PVDD
(1.8V@120mA DPLL_PVDD For M96)

(1.8V@75mA DPLL_PVDD For Madison)
DIS
AK24
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
AT23
AR22
VDD2DI
VSS2DI
2
+1.8V_RUN_VGA
DY
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
1
1
1
1
1
1
1
1
PEG_CLKREQ#
JTAG_TRST#_VGA
JTAG_TDI_VGA
JTAG_TCK_VGA
JTAG_TMS_VGA
JTAG_TDO_VGA
GEN_A
GEN_B
GENERICC
GENERICD
GENERICE_HPD4
GENERICF
GENERICG
(13,57) HDMI_HPD_DET
SCD1U10V2KX-5GP
R8217
249R2F-GP
C8205
SC4D7U6D3V3KX-GP
TP8205
TP8206
TP8211
TP8218
TP8219
TP8212
TP8220
TP8221
R8216
499R2F-2-GP
DIS
470ohm, 1A
TPAD14-GP
+1.8V_RUN_VGA
DIS L8201
1
2
BLM18PG471SN1D-GP
TPAD14-GP
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
AU22
AV21
TX5P_DPD0P
TX5M_DPD0N
JTAG_TRST#
0R2J-2-GP
1215-5
TP8202
TESTEN
Debug
mode
TP8225
Normal
mode
DIS
Signal
(7) CLK_VGA_27M_SS
JTAG_TCK_VGA
SCL
SDA
GENERAL PURPOSE I/O
AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AM23
AN23
AK23
AL24
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24
(80) TX_PWRS_ENB
(80) TX_DEEMPH_EN
(80) BIF_GEN2_EN_A
1 R8219
10KR2J-3-GP
AT21
AR20
TX4P_DPD1P
TX4M_DPD1N
I2C
GPU_LVDSB_TX2 (55)
GPU_LVDSB_TX2# (55)
AF35
AG36
JTAG_TRST#_VGA
GPU_LVDSB_TX1 (55)
GPU_LVDSB_TX1# (55)
AG38
AH37
VGA_BLEN
2 10KR2J-3-GP
DY
10/5
AU20
AT19
TXCDP_DPD3P
TXCDM_DPD3N
AH35
AJ36
SC1U6D3V2KX-GP
2 10KR2J-3-GP
DIS
AT17
AR16
TX2P_DPC0P
TX2M_DPC0N
GPU_LVDSB_TX0 (55)
GPU_LVDSB_TX0# (55)
LVTMDP
AU16
AV15
TX1P_DPC1P
TX1M_DPC1N
GPU_LVDSB_TXC (55)
GPU_LVDSB_TXC# (55)
DIS
R8201 1
RN
R8202 1
TXOUT_U3P
TXOUT_U3N
AT15
AR14
TX0P_DPC2P
TX0M_DPC2N
DPD
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
AU14
AV13
TXCCP_DPC3P
TXCCM_DPC3N
TX3P_DPD2P
TX3M_DPD2N
3
4
RN8201
SRN4K7J-8-GP
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
AT33
AU32
TX5P_DPB0P
TX5M_DPB0N
2
1
10/1
10/5
(37) THERMTRIP_VGA_GATE
AR32
AT31
TX4P_DPB1P
TX4M_DPB1N
AK35
AL36
AJ38
AK37
+3.3V_RUN_VGA
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
H_THERMTRIP#
VGA_LBKLT_CTL (55)
VGA_LCDVDD_EN (55)
S
(10,21,37,39,42)
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
AV31
AU30
TX3P_DPB2P
TX3M_DPB2N
DPC
AK27
AJ27
DIS 2N7002A-7-GP
3
4
DIS
Q8202
VARY_BL
DIGON
10KR2J-3-GP
2N7002EDW-GP
Q8203
(37)
LVDS CONTROL
THERMTRIP_VGA#
DY R8208
THERMTRIP_VGA
HDMI_PCH_DATA2 (57)
HDMI_PCH_DATA2# (57)
SCD1U10V2KX-5GP
TP8224
TP8222
TP8223
HDMI_PCH_DATA1 (57)
AT27
AR26
DIS
SRN10KJ-5-GP
AR30
AT29
TXCBP_DPB3P
TXCBM_DPB3N
DPB
AU26
AV25
2
1
7 OF 8
THERMTRIP_R
2 10KR2J-3-GP
1
1 TPAD14-GP
1 TPAD14-GP
TPAD14-GP
RN8203
10/8
VGA1G
VRAMDIS_Hynix
R8207 1
TX2P_DPA0P
TX2M_DPA0N
HDMI_PCH_DATA0 (57)
10/1
SC1U6D3V2KX-GP
+1.8V_RUN_VGA
DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
HDMI_PCH_CLK (57)
HDMI_PCH_CLK# (57)
AT25
AR24
MEM_ID Control
84.27002.F3F
AR8
AU8
AP8
AW8
AR3
AR1
MEM_ID0
AU1
MEM_ID1
AU3
MEM_ID2 AW3
MEM_ID3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12
LVDS Interface
AU24
AV23
0000
DVPDATA[0:3] Default:Pull down
DVPDATA[0:3]
1000
2 OF 8
VGA1B
MEMORY ID Table
DIS_GPU
MADISON-PRO-2-GP
A
TSVDD
X8201
<Core Design>
C8227
C8224
DIS
SC1U6D3V2KX-GP
2
C8225
SCD1U10V2KX-5GP
XTALIN
DY
SC18P50V2JN-1-GP
DY
DIS
DY
C8223
SC4D7U6D3V3KX-GP
120ohm, 0.3A
+1.8V_RUN_VGA
(1.8V@20mA TSVDD For M96)
L8204 DIS
(1.8V@5mA TSVDD For Madison)
1
2
BLM15BD121SS1D-GP
C8228
3
XTALOUT 1
DY
XTAL-27MHZ-85-GP
1
1218-1
5
R8222
SC18P50V2JN-1-GP
Clock Input Configuraiton -GDDR3/DDR3

a) 27MHz crystal connected to XTALIN or XTALOUT or
b) 27MHz (1.8V) oscillator connected to XTALIN or
c) 27MHz (3.3V) oscillator connected to XO_IN (Park, Madison, and Broadway only)
Wistron Corporation
Title
GPU_DP/LVDS/CRT/GPIO(3/5)
Size
A2
DY21MR2J-1-GP
Date:
3
Document Number
Rev
A00
Berry
Sheet

1
82
of
95
+1.5V_RUN
DIS_M96
1
L8306
VDDRH
2
BLM15BD121SS1D-GP
1
120ohm, 0.3A
SC1U6D3V2KX-GP
DIS
2
C8397
DIS_M96
PCIE_PVDD
1
R8301
2VSSRHB
0R2J-2-GP
(1.8V@68mA PCIE_PVDD For M96)

(1.8V@40mA PCIE_PVDD For Madison)
H7
H8
SPV18
DIS
NC_VDDRHA
NC_VSSRHA
NC_VDDRHB
NC_VSSRHB
PLL
AB37
MPV18
C8378
PCIE_PVDD
MPV18
MPV18
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
DIS
C8334
SC4D7U6D3V3KX-GP
DIS
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
C8370
DIS
C8371
DIS
C8342
DIS
C8350
SC1U6D3V2KX-GP
DIS
C8343
DIS
C8344
DIS
C8345
SC1U6D3V2KX-GP
DIS
10/6
C8359
DIS
C8360
DIS
C8372
DIS
C8361
DIS
C8362
DIS
C8363
DIS
C8364
DIS
SC1U6D3V2KX-GP
2
1
DIS
SC1U6D3V2KX-GP
2
1
DIS
C8349
DIS
SC1U6D3V2KX-GP
2
1
C8358
DIS
C8341
DIS
C8348
DIS
C8340
+VGA_CORE
SC1U6D3V2KX-GP
2
DIS
C8357
DIS
C8347
DY
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP
2
1
C8346
DIS
C8339
C8302
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
C8333
DIS
C8365
DIS
C
C8373
DIS
VDDCI and VDDC should have seperate regulators with a merge option on PCB
For Madison and Park, VDDCI and VDDC can share one common regulator
+VGA_CORE
DIS_M96
2FB_GND
0R2J-2-GP
AH29
FB_VDDCI
FB_GND
VCORE_SEN/RTN and VDDCI_SEN/RTN route as differetial pair
1204-4
ISOLATED
CORE I/O
DIS
DIS
C8387
SC1U6D3V2KX-GP
DIS
C8386
C8388
SC10U6D3V5KX-1GP
C8385
C8384
DIS
C8383
DIS
FB_VDDC
DIS
SC1U6D3V2KX-GP
2
AF28
C8382
0107-5
Removed
1
R8303
SPVSS
VOLTAGE
SENESE
AG28
1204-5
SPV10
SC1U6D3V2KX-GP
2
AN10
AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13
M97, Broadway, Madison and Park only

M96 do not support core vsense feature
C8381
DIS
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
DIS
C8380
(Same as VDDC)
SPV18
SC1U6D3V2KX-GP
2
1204-5
DIS
AN9
SCD1U10V2KX-5GP
C8379
+VGA_CORE
L8307
1
2
DIS_M96
BLM18PG471SN1D-GP
(For M96 SPV10 = VDDC)

(For M97, Broadway, Madison and Park SPV10 = 1.0V)
SC1U6D3V2KX-GP
2
1
(VDDC@136mA SPV10 For M96) AM10

(1.0V@100mA SPV10 For Madison)
SCD1U10V2KX-5GP
+1.0V_RUN_VGA
SPV10
L8303
1
2
DIS_Mad
BLM18PG471SN1D-GP
SC4D7U6D3V3KX-GP
2
1
DIS
DIS
V12
U12
C8376
SC4D7U6D3V3KX-GP
DIS_M96
C8377
M20
M21
2VSSRHA
0R2J-2-GP
DIS DY
C8356
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
2
1
2
BLM15BD121SS1D-GP
1
DIS
120ohm, 0.3A
SCD1U10V2KX-5GP
1
L8302
DIS_M96
1
R8302
SCD1U10V2KX-5GP
DIS
1204-5
C8375
VDDR4
VDDR4
VDDR4
VDDR4
C8332
DIS
SC10U6D3V5KX-1GP
2
1
AD12
AF11
AF12
AG11
DIS
C8338
SC1U6D3V2KX-GP
2
1
DIS
VDDR4
VDDR4
VDDR4
VDDR4
C8337
SC10U6D3V5KX-1GP
2
1
AF13
AF15
AG13
AG15
C8331
(3.3V@60mA VDDR3)
VDDR3
VDDR3
VDDR3
VDDR3
+1.0V_RUN_VGA
(1.1V@1.4A PCIE_VDDC For M96)

(1.0V@1.1A PCIE_VDDC For Madison)
SC1U6D3V2KX-GP
2
I/O
AF23
AF24
AG23
AG24
(1.8V@340mA VDDR4 For M96)

(1.8V@170mA VDDR4 For Madison)
C8374
SC1U6D3V2KX-GP
VDD_CT
VDD_CT
VDD_CT
VDD_CT
C8336
SC1U6D3V2KX-GP
2
DIS
C8317
SC4D7U6D3V3KX-GP
DIS
(25A VDDC For M96)

(23.6A VDDC For Madison)
AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
SC1U6D3V2KX-GP
2
SC1U6D3V2KX-GP
2
1
1
2
AF26
AF27
AG26
AG27
C8355
C8316
DIS
DIS
SC1U6D3V2KX-GP
2
1
C8369
C8354
DIS
C8330
DIS
SC10U6D3V5KX-1GP
2
1
DIS
DIS
C8329
DIS
C8315
DY
C8368
SC1U6D3V2KX-GP
2
1
2
1
DIS
C8353
C8328
DIS
C8314
DIS
SC1U6D3V2KX-GP
2
DIS
C8352
SC1U6D3V2KX-GP
2
1
C8367
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
2
SC1U6D3V2KX-GP
2
1
C8366
DIS
2
SC4D7U6D3V3KX-GP
+3.3V_RUN_VGA
C8351
DIS
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC/BIF_VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC/BIF_VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
CORE
POWER
2
BLM15BD121SS1D-GP
120ohm, 0.3A
LEVEL
TRANSLATION
VDDC_CT
(1.8V@136mA VDD_CT For M96)

(1.8V@17mA VDD_CT For Madison)
SCD1U10V2KX-5GP
1
L8301
DIS
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28
C8313
DY
SC1U6D3V2KX-GP
2
1
+1.8V_RUN_VGA
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
C8335
DIS
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
SC1U6D3V2KX-GP
2
C8327
DY
SC10U6D3V5KX-1GP
2
DIS
+1.8V_RUN_VGA
SC1U6D3V2KX-GP
2
1
C8326
DY
DIS
2
2
C8325
DY
C8312
SC1U6D3V2KX-GP
2
1
C8311
DY
SC1U6D3V2KX-GP
2
1
C8324
DY
C8310
DIS
SC1U6D3V2KX-GP
2
1
1
2
1
2
SC1U6D3V2KX-GP
2
1
C8323
DIS DY
C8309
DIS
(1.8V@210mA PCIE_VDDR For M96)

(1.8V@400mA PCIE_VDDR For Madion)
AA31
AA32
AA33
AA34
V28
W29
W30
Y31
SC1U6D3V2KX-GP
2
1
1
2
SC1U6D3V2KX-GP
2
1
1
2
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
1
2
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
1
SC10U6D3V5KX-1GP
2
C8322
DIS
5 OF 8
PCIE
AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7
SCD1U10V2KX-5GP
C8321
DIS DY
C8308
SCD1U10V2KX-5GP
C8320
C8307
DIS
SCD1U10V2KX-5GP
DIS
SCD1U10V2KX-5GP
C8306
SCD1U10V2KX-5GP
C8319
DY
C8303
C8305
DIS
SCD1U10V2KX-5GP
DIS
SCD1U10V2KX-5GP
C8304
SCD1U10V2KX-5GP
DY
SCD1U10V2KX-5GP
C8318
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C8301
DIS
10/8
MEM I/O
(1.5V@2.9A VDDR1 For M96)

(1.5V@3.4A VDDR1 For Madison)
For DDR3/GDDR5, MVDDQ = 1.5V
VGA1E
+1.5V_RUN
SC1U6D3V2KX-GP
2
1
SC10U6D3V5KX-1GP
2
1
DIS
B
MADISON-PRO-2-GP
SC4D7U6D3V3KX-GP
C8390
DIS_Mad
C8391
DIS_Mad
2
SC1U6D3V2KX-GP
2
2
BLM15BD121SS1D-GP
C8389
DIS_Mad
1
1
L8304
120ohm, 0.3A
SCD1U10V2KX-5GP
(1.8V@50mA SPV18)
DIS_Mad
SPV18
NOTE1:
Back Bias is not supported on M97, Broadway, Madison and Park
For the M96 Back Bias circuitry, refer to REF134
NOTE2:
FB_VDDC, FB_VDDCI and FB_GND are not support on M96
MPV18
(1.8V@150mA MPV18)
SC4D7U6D3V3KX-GP
SC1U6D3V2KX-GP
2
DIS_Mad
NOTE3:
M97 VDDC and VDDCI ball assignments are different from M96.
If M96 is populated on this design, VDDC and VDDCI will be shorted on the substrate.
C8393
C8396
DIS_Mad
DIS_Mad
C8392
BLM18PG471SN1D-GP
470ohm, 1A
SCD1U10V2KX-5GP
2
1
DIS_Mad
1
L8305
NOTE4:
For M2 design compatibility, refer to the document AN_M96_Ax and AN_M97_Ax
<Core Design>
Wistron Corporation
Title
Size
A2
Date:
GPU_POWER(4/5)
Document Number
Rev
A00
Berry
Sheet

1
83
of
95
VGA1H
10/8
8 OF 8
DPA_VDD18
DP A/B POWER
(1.8V@130mA DPC_VDD18)
1204-4
+1.0V_RUN_VGA
+1.8V_RUN_VGA
DPA_VDD18
0.3A
C8406
DIS_Mad
SC4D7U6D3V3KX-GP
DPB_VDD18
AP22
AP23
DPD_VDD18
DPD_VDD18
DPB_VDD18
DPB_VDD18
DPD_VDD10
DPD_VDD10
DPB_VDD10
DPB_VDD10
DPD_VSSR
DPD_VSSR
DPD_VSSR
DPD_VSSR
DPD_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
AP25
AP26
+1.0V_RUN_VGA
(1.1V@200mA DPD_VDD10 For M96)

(1.0V@110mA DPD_VDD10 For Madison)
AN33
AP33
1
R8402
(1.1V@200mA DPB_VDD10 For M96)

(1.0V@110mA DPB_VDD10 For Madison)
2
0R2J-2-GP
C8409
SC4D7U6D3V3KX-GP
DY
DPA_PVDD
DPA_PVSS
SCD1U10V2KX-5GP
AL33
AM33
DPE_VDD10
DPE_VDD10
DPB_PVDD
DPB_PVSS
DPE_VSSR
DPE_VSSR
DPE_VSSR
DPE_VSSR
C8425
SCD1U10V2KX-5GP
DPC_PVDD
DPC_PVSS
AF34
AG34
DPF_VDD18
DPE_PVDD
DPE_PVSS
DIS
1
DIS
AK33
AK34
C8427
SC1U6D3V2KX-GP
1
2
DIS
DPF_PVDD
DPF_PVSS
DPF_VDD10
LVDS mode
DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR
2DPEF_CALR
DIS
C8415
SC4D7U6D3V3KX-GP
DIS
DY
C8421
C8422
SCD1U10V2KX-5GP
DIS_Mad
DIS_Mad
AV19
AR18
AM37
AN38
AL38 DPF_PVDD
AM35
DIS_Park/Mad
1
R8407
C8429
1
R8408
DPEF_CALR
(1.8V@20mA DPF_PVDD)
2
0R2J-2-GP
2
0R2J-2-GP
DIS
C8430
DIS
C8416
1
L8406
DIS
2
BLM15BD121SS1D-GP
120ohm, 0.3A
DIS
DIS_GPU
MADISON-PRO-2-GP
R8406
150R2F-1-GP
DIS
C8434
2
0R2J-2-GP
AU18
AV17
1204-2
AM39
C8433
1
R8405
AV29
AR28
DIS_Park/Mad
DPF_PVSS
(1.1V@100mA DPF_VDD10 For M96)

(1.0V@120mA DPF_VDD10 For Madison)
2
BLM15BD121SS1D-GP
C8426
SC4D7U6D3V3KX-GP DIS
DIS
1
L8407
120ohm, 0.3A
SC1U6D3V2KX-GP
+1.0V_RUN_VGA
DPF_VDD10
DPF_VDD10
C8428
SCD1U10V2KX-5GP
AF39
AH39
AK39
AL34
AM34
DPD_VDD18
(1.8V@130mA DPD_VDD18)
DIS_Mad
(1.8V@20mA DPE_PVDD For M96) DPE_PVDD

(1.8V@20mA DPE_PVDD For Madison)
DPF_VDD18
DPF_VDD18
(1.8V@200mA DPF_VDD18 For M96)

(1.8V@200mA DPF_VDD18 For Madison)
L8405 DIS
1
2
BLM18PG471SN1D-GP
470ohm, 1A C8423
SC4D7U6D3V3KX-GP
C8411
DIS_Mad
SCD1U10V2KX-5GP
DIS0.3A
120ohm,
C8414
SC4D7U6D3V3KX-GP
(1.8V@20mA DPD_PVDD For M96)

(1.8V@20mA DPD_PVDD For Madison)
DPD_PVDD
DPD_PVSS
LVDS mode
+1.8V_RUN_VGA
DIS
SC4D7U6D3V3KX-GP
2
1
AN34
AP39
AR39
AU37
C8424
DIS DIS
2
2
BLM15BD121SS1D-GP
120ohm, 0.3A C8404
SC4D7U6D3V3KX-GP DIS
SC1U6D3V2KX-GP
2
1
DIS
C8413
DIS
(1.8V@20mA DPC_PVDD For M96)

(1.8V@20mA DPC_PVDD For Madison)
(1.1V@100mA DPE_VDD10 For M96)

(1.0V@120mA DPE_VDD10 For Madison)
1
L8408
DIS
(1.8V@20mA DPB_PVDD For M96)

(1.8V@20mA DPB_PVDD For Madison)
LVDS mode
+1.0V_RUN_VGA
C8412
DIS
AU28
AV27
DIS
DPE_VDD10
C8410
DIS_Mad
2
BLM15BD121SS1D-GP
DPE_VDD18
DPE_VDD18
C8419
1
2
AW28DPAB_CALR
150R2F-1-GP
AH34
AJ34
DPAB_CALR
DP PLL POWER
SC1U6D3V2KX-GP
2
1
C8418
DIS
2
DIS
2
1
2
BLM18PG471SN1D-GP
C8401
470ohm, 1A
SC4D7U6D3V3KX-GP
DP E/F POWER
1
L8404
DPCD_CALR
(1.8V@200mA DPE_VDD18 For

(1.8V@200mA DPE_VDD18 For Madison)
SC1U6D3V2KX-GP
L8401
DIS
DPB_VDD18
(1.8V@20mA DPA_PVDD For M96)

(1.8V@20mA DPA_PVDD For Madison)
SCD1U10V2KX-5GP
2
1
LVDS mode
+1.8V_RUN_VGA
+1.8V_RUN_VGA
DPA_PVDD
R8404
R8401 DIS
1
2DPCD_CALR AW18
150R2F-1-GP
DPE_VDD18
M96)
AN29
AP29
AP30
AW30
AW32
SC1U6D3V2KX-GP
AN19
AP18
AP19
AW20
AW22
C8408
DIS_Mad
SCD1U10V2KX-5GP
(1.8V@130mA DPB_VDD18)
DIS_Mad
AP14
AP15
C8407
DIS_Mad
2
BLM15BD121SS1D-GP
120ohm, 0.3A
1
L8402
(1.8V@130mA DPA_VDD18)
DIS_Mad
+1.0V_RUN_VGA
DNI for M96/M92
DPD_VDD18
DIS
2
BLM15BD121SS1D-GP
AN27
AP27
AP28
AW24
AW26
C8405
120ohm,
SC10U6D3V5KX-1GP
C8403
DIS
DIS
DIS
1
L8403
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
C8402
SC1U6D3V2KX-GP
DPC_VSSR
DPC_VSSR
DPC_VSSR
DPC_VSSR
DPC_VSSR
AP31
AP32
SC1U6D3V2KX-GP
2
1
AN17
AP16
AP17
AW14
AW16
DPA_VDD10
DPA_VDD10
DPC_VDD10
DPC_VDD10
AP13
AT13
(1.1V@200mA DPA_VDD10 For M96)

(1.0V@110mA DPA_VDD10 For Madison)
SC1U6D3V2KX-GP
2
1
DPA_VDD10
DPA_VDD18
DPA_VDD18
DPC_VDD18
DPC_VDD18
(1.1V@200mA DPC_VDD10 For M96)

(1.0V@110mA DPC_VDD10 For Madison)
+1.0V_RUN_VGA
AN24
AP24
SC1U6D3V2KX-GP
AP20
AP21
DP C/D POWER
DPD_VDD18
A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13
SCD1U10V2KX-5GP
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND/PX_EN
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39
6 OF 8
SCD1U10V2KX-5GP
2
1
10/8
SCD1U10V2KX-5GP
2
1
VGA1F
For M97/M96, DPF_VDD18 can be shared with DPE_VDD18

For M97/M96, DPF_VDD10 can be shared with DPE_VDD10
For dual link DVI using DPA AND DPB, DPA_VDDxx and DPB_VDDxx can be shared respectively
For dual link DVI using DPC AND DPD, DPC_VDDxx and DPD_VDDxx can be shared respectively
For dual link LVDS, DPE_VDDxx and DPF_VDDxx can be shared respectively
VSS_MECH
VSS_MECH
VSS_MECH
A39 VSS_MECH1
AW1 VSS_MECH2
AW39VSS_MECH3
TPAD14-GP1
TPAD14-GP1
TPAD14-GP1
TP8401
TP8402
TP8403
DIS_GPU
MADISON-PRO-2-GP
<Core Design>
Wistron Corporation
Title
GPU_DPPWR/GND(5/5)
Size
A2
Date:
5
Document Number
Rev
Berry
A00
Sheet

1
84
of
95
+1.5V_RUN
+1.5V_RUN
VRAM1
1
R8508
56R2J-4-GP
SC10U6D3V5MX-3GP
2
1
K9
(81) CKEA0
SCD01U50V2KX-1GP
DIS_M96/Mad
(81) W EA0#
(81) CASA0#
(81) RASA0#
L3
K3
J3
WE#
CAS#
RAS#
ODT
K1
ODTA0 (81)
CS#
RESET#
L2
T2
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
K8
K2
N1
R9
B2
D9
G7
R1
N9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A8
A1
C1
C9
D2
E9
F1
H9
H2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VRAM2_VREF
VRAM1_VREF
CSA0#_0 (81)
MEM_RST (81,86,87,88)
H1
M8
1
2VRAM_ZQ2 L8
DIS_M96/Mad
R8504
243R2F-2-GP
VREFDQ
VREFCA
ZQ
(81,86) MAA0
(81,86) MAA1
(81,86) MAA2
(81,86) MAA3
(81,86) MAA4
(81,86) MAA5
(81,86) MAA6
(81,86) MAA7
(81,86) MAA8
(81,86) MAA9
(81,86) MAA10
(81,86) MAA11
(81,86) MAA12
(81,86) MAA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
(81,86) A_BA0
(81,86) A_BA1
(81,86) A_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
(81) CKEA0
K9
CKE
(81) DQMA1
(81) DQMA3
D3
E7
DMU
DML
L3
K3
J3
WE#
CAS#
RAS#
(81) CLKA0
(81) CLKA0#
(81) W EA0#
(81) CASA0#
(81) RASA0#
K4W 1G1646E-HC12-GP
GPU_CLKA0_T
C8503
DMU
DML
QSAP_2 (81)
QSAN_2 (81)
QSAP_0 (81)
QSAN_0 (81)
CKE
D3
E7
C8522
DYDIS_M96/Mad
F3
G3
(81) DQMA2
56R2J-4-GP
DIS_M96/Mad
DIS_M96/Mad
(81) DQMA0
C8521
DQSL
DQSL#
R8507
C8520
SC1U6D3V2KX-GP
2
1
CK
CK#
(81) CLKA0
(81) CLKA0#
DIS_M96/Mad
DY
DIS_M96/Mad
DY
SC10U6D3V5MX-3GP
2
1
J7
K7
SC10U6D3V5MX-3GP
2
1
20090902
C7
B7
C8519
SC1U6D3V2KX-GP
2
1
BA0
BA1
BA2
DQSU
DQSU#
C8517
SC1U6D3V2KX-GP
2
1
M2
N8
M3
MDA20
MDA19
MDA23
MDA18
MDA22
MDA16
MDA21
MDA17
DY
SC10U6D3V5MX-3GP
2
1
(81,86) A_BA0
(81,86) A_BA1
(81,86) A_BA2
VRAM_ZQ1
243R2F-2-GP
D7
C3
C8
C2
A7
A2
B8
A3
DIS_M96/Mad
DY
DIS_M96/Mad
C8518
SC1U6D3V2KX-GP
2
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
1
2
DIS_M96/Mad
R8503
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
C8515
SC1U6D3V2KX-GP
2
1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
VRAM1_VREF
VRAM2_VREF
MDA3
MDA7
MDA1
MDA6
MDA2
MDA4
MDA0
MDA5
C8516
SC1U6D3V2KX-GP
2
1
(81,86) MAA0
(81,86) MAA1
(81,86) MAA2
(81,86) MAA3
(81,86) MAA4
(81,86) MAA5
(81,86) MAA6
(81,86) MAA7
(81,86) MAA8
(81,86) MAA9
(81,86) MAA10
(81,86) MAA11
(81,86) MAA12
(81,86) MAA13
C8505
E3
F7
F2
F8
H3
H8
G2
H7
C8524
SC1U6D3V2KX-GP
2
1
VREFDQ
VREFCA
ZQ
C8502
DIS_M96/Mad
DIS_M96/Mad
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
1.5V, 350mA
MDA[0..31] (81)
C8525
SC1U6D3V2KX-GP
2
1
H1
M8
L8
C8513
SC1U6D3V2KX-GP
2
1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
C8514
SC1U6D3V2KX-GP
2
1
A8
A1
C1
C9
D2
E9
F1
H9
H2
C8511
SC1U6D3V2KX-GP
2
1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DIS_M96/MadDIS_M96/Mad
DY
DY
DY
DY
VRAM2
K8
K2
N1
R9
B2
D9
G7
R1
N9
C8512
SC1U6D3V2KX-GP
2
1
C8509
SC1U6D3V2KX-GP
2
1
C8510
SC1U6D3V2KX-GP
2
1
C8507
SC1U6D3V2KX-GP
2
1
C8508
SC1U6D3V2KX-GP
2
1
1.5V, 350mA
MDA[0..31] (81)
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDA29
MDA24
MDA30
MDA26
MDA28
MDA27
MDA25
MDA31
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDA8
MDA14
MDA9
MDA10
MDA15
MDA12
MDA13
MDA11
DQSU
DQSU#
C7
B7
QSAP_1 (81)
QSAN_1 (81)
DQSL
DQSL#
F3
G3
QSAP_3 (81)
QSAN_3 (81)
ODT
K1
ODTA0 (81)
CS#
RESET#
L2
T2
CSA0#_0 (81)
MEM_RST (81,86,87,88)
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
K4W 1G1646E-HC12-GP
DIS_Samsung_M96/Mad
20090902
20090902
DIS_Samsung_M96/Mad
+1.5V_RUN
+1.5V_RUN
R8513
2K1R2F-GP
R8510
2K1R2F-GP
DIS_M96/Mad
DIS_M96/Mad
VRAM2_VREF
C8504
1
R8512
2K1R2F-GP
DIS_M96/Mad
SCD1U16V2ZY-2GP
C8506
DIS_M96/Mad
SCD1U16V2ZY-2GP
DIS_M96/Mad
R8511
2K1R2F-GP
VRAM1_VREF
DIS_M96/Mad
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
GPU-VRAM1,2 (1/4)
Document Number
Rev
A00
Berry
Sheet
1
85
of
95
+1.5V_RUN
+1.5V_RUN
VRAM3
DIS_M96/Mad
DIS_M96/Mad
VRAM3_VREF
VRAM4_VREF
H1
M8
1
2VRAM_ZQ3 L8
DIS_M96/Mad
R8603
243R2F-2-GP
VREFDQ
VREFCA
ZQ
(81,85) MAA0
(81,85) MAA1
(81,85) MAA2
(81,85) MAA3
(81,85) MAA4
(81,85) MAA5
(81,85) MAA6
(81,85) MAA7
(81,85) MAA8
(81,85) MAA9
(81,85) MAA10
(81,85) MAA11
(81,85) MAA12
(81,85) MAA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
(81,85) A_BA0
(81,85) A_BA1
(81,85) A_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
(81) CKEA1
K9
(81) DQMA5
(81) DQMA4
D3
E7
R8607
56R2J-4-GP
R8608
DIS_M96/Mad56R2J-4-GP
DMU
DML
(81) W EA1#
(81) CASA1#
(81) RASA1#
L3
K3
J3
WE#
CAS#
RAS#
DIS_M96/Mad
SCD01U50V2KX-1GP
C8615
SC1U6D3V2KX-GP
2
1
C8616
SC1U6D3V2KX-GP
2
1
C7
B7
C8624
SC1U6D3V2KX-GP
2
1
DQSU
DQSU#
C8617
C8619
DIS_M96/Mad
DIS_M96/Mad
QSAP_5 (81)
QSAN_5 (81)
DQSL
DQSL#
F3
G3
QSAP_4 (81)
QSAN_4 (81)
ODT
K1
ODTA1 (81)
CS#
RESET#
L2
T2
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
VRAM4_VREF
VRAM3_VREF
CSA1#_0 (81)
MEM_RST (81,85,87,88)
K8
K2
N1
R9
B2
D9
G7
R1
N9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A8
A1
C1
C9
D2
E9
F1
H9
H2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
H1
M8
1
2VRAM_ZQ4 L8
DIS_M96/Mad
R8604
243R2F-2-GP
VREFDQ
VREFCA
ZQ
(81,85) MAA0
(81,85) MAA1
(81,85) MAA2
(81,85) MAA3
(81,85) MAA4
(81,85) MAA5
(81,85) MAA6
(81,85) MAA7
(81,85) MAA8
(81,85) MAA9
(81,85) MAA10
(81,85) MAA11
(81,85) MAA12
(81,85) MAA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
(81,85) A_BA0
(81,85) A_BA1
(81,85) A_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
(81) CKEA1
K9
CKE
(81) DQMA6
(81) DQMA7
D3
E7
DMU
DML
(81) W EA1#
(81) CASA1#
(81) RASA1#
L3
K3
J3
WE#
CAS#
RAS#
(81) CLKA1
(81) CLKA1#
K4W 1G1646E-HC12-GP
MDA[32..63] (81)
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDA61
MDA57
MDA63
MDA60
MDA59
MDA56
MDA62
MDA58
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDA50
MDA55
MDA49
MDA52
MDA48
MDA54
MDA51
MDA53
DQSU
DQSU#
C7
B7
QSAP_6 (81)
QSAN_6 (81)
DQSL
DQSL#
F3
G3
QSAP_7 (81)
QSAN_7 (81)
ODT
K1
ODTA1 (81)
CS#
RESET#
L2
T2
CSA1#_0 (81)
MEM_RST (81,85,87,88)
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
K4W 1G1646E-HC12-GP
DIS_Samsung_M96/Mad
DIS_Samsung_M96/Mad
20090902
20090902
20090902
+1.5V_RUN
+1.5V_RUN
R8605
2K1R2F-GP
R8601
2K1R2F-GP
DIS_M96/Mad
DIS_M96/Mad
1
R8606
2K1R2F-GP
C8626
C8605
DIS_M96/Mad
SCD1U16V2ZY-2GP
DIS_M96/Mad
2
SCD1U16V2ZY-2GP
2
1
C8601
SCD1U16V2ZY-2GP
2
1
1
2
R8602
2K1R2F-GP
VRAM4_VREF
VRAM3_VREF
DIS_M96/Mad
C8603
GPU_CLKA1_T
MDA46
MDA43
MDA45
MDA40
MDA44
MDA41
MDA47
MDA42
CKE
(81) CLKA1
(81) CLKA1#
D7
C3
C8
C2
A7
A2
B8
A3
SC10U6D3V5MX-3GP
2
1
C8608
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
DIS_M96/Mad
DIS_M96/Mad
DY
DY
DY
DIS_M96/Mad
SC10U6D3V5MX-3GP
2
1
SC10U6D3V5MX-3GP
2
1
SC10U6D3V5MX-3GP
2
1
C8606
MDA36
MDA38
MDA33
MDA39
MDA32
MDA34
MDA35
MDA37
C8625
SC1U6D3V2KX-GP
2
1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
E3
F7
F2
F8
H3
H8
G2
H7
C8622
SC1U6D3V2KX-GP
2
1
A8
A1
C1
C9
D2
E9
F1
H9
H2
VRAM4
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
C8623
SC1U6D3V2KX-GP
2
1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C8618
SC1U6D3V2KX-GP
2
1
DY
DY
K8
K2
N1
R9
B2
D9
G7
R1
N9
1.5V, 350mA
MDA[32..63] (81)
C8621
SC1U6D3V2KX-GP
2
1
C8613
SC1U6D3V2KX-GP
2
1
C8614
SC1U6D3V2KX-GP
2
1
DY
C8611
SC1U6D3V2KX-GP
2
1
DY
C8612
SC1U6D3V2KX-GP
2
1
DY
C8609
SC1U6D3V2KX-GP
2
1
DIS_M96/Mad
C8610
SC1U6D3V2KX-GP
2
1
C8607
SC1U6D3V2KX-GP
2
1
C8602
SC1U6D3V2KX-GP
2
1
1.5V, 350mA
DIS_M96/Mad
DIS_M96/Mad
DIS_M96/Mad
1120-3
<Core Design>
Wistron Corporation

Title
Size
A3
Date:
5
GPU-VRAM3,4 (2/4)
Document Number
Rev
A00
Berry
Sheet
1
86
of
95
+1.5V_RUN
+1.5V_RUN
VRAM5
VRAM5_VREF
VRAM6_VREF
R8704
20090902
DIS
VRAM_ZQ5
243R2F-2-GP
(81,88) MAB0
(81,88) MAB1
(81,88) MAB2
(81,88) MAB3
(81,88) MAB4
(81,88) MAB5
(81,88) MAB6
(81,88) MAB7
(81,88) MAB8
(81,88) MAB9
(81,88) MAB10
(81,88) MAB11
(81,88) MAB12
(81,88) MAB13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
(81,88) B_BA0
(81,88) B_BA1
(81,88) B_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
(81) CLKB0
(81) CLKB0#
DIS
2
R8708
56R2J-4-GP
DIS
2
R8707
56R2J-4-GP
(81) CKEB0
K9
(81) DQMB3
(81) DQMB1
D3
E7
DMU
DML
(81) W EB0#
(81) CASB0#
(81) RASB0#
L3
K3
J3
WE#
CAS#
RAS#
1
2
SCD01U50V2KX-1GP
DIS
DQSL
DQSL#
F3
G3
ODT
K1
CS#
RESET#
L2
T2
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
VREFDQ
VREFCA
ZQ
(81,88) MAB0
(81,88) MAB1
(81,88) MAB2
(81,88) MAB3
(81,88) MAB4
(81,88) MAB5
(81,88) MAB6
(81,88) MAB7
(81,88) MAB8
(81,88) MAB9
(81,88) MAB10
(81,88) MAB11
(81,88) MAB12
(81,88) MAB13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
(81,88) B_BA0
(81,88) B_BA1
(81,88) B_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
(81) CKEB0
K9
CKE
(81) DQMB0
(81) DQMB2
D3
E7
DMU
DML
(81) W EB0#
(81) CASB0#
(81) RASB0#
L3
K3
J3
WE#
CAS#
RAS#
QSBP_3 (81)
QSBN_3 (81)
DY
DY
C8718
C8725
SC1U6D3V2KX-GP
2
1
H1
M8
L8
C8724
SC1U6D3V2KX-GP
2
1
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
C8722
SC1U6D3V2KX-GP
2
1
DIS
DY
C7
B7
CKE
GPU_CLKB0_T
C8703
DQSU
DQSU#
A8
A1
C1
C9
D2
E9
F1
H9
H2
C8723
SC1U6D3V2KX-GP
2
1
DIS
VREFDQ
VREFCA
ZQ
MDB26
MDB27
MDB30
MDB24
MDB31
MDB25
MDB29
MDB28
C8721
SC1U6D3V2KX-GP
2
1
H1
M8
L8
D7
C3
C8
C2
A7
A2
B8
A3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
SC10U6D3V5MX-3GP
2
1
DIS
C8708
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
K8
K2
N1
R9
B2
D9
G7
R1
N9
SC10U6D3V5MX-3GP
2
1
DIS
SC10U6D3V5MX-3GP
2
1
DIS
SC10U6D3V5MX-3GP
2
1
DIS
C8706
MDB14
MDB13
MDB12
MDB15
MDB11
MDB8
MDB9
MDB10
DY
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
E3
F7
F2
F8
H3
H8
G2
H7
C8720
SC1U6D3V2KX-GP
2
1
DIS
A8
A1
C1
C9
D2
E9
F1
H9
H2
VRAM6
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DY
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C8715
SC1U6D3V2KX-GP
2
1
K8
K2
N1
R9
B2
D9
G7
R1
N9
1.5V, 350mA
MDB[0..31] (81)
C8717
SC1U6D3V2KX-GP
2
1
DY
C8714
SC1U6D3V2KX-GP
2
1
C8713
SC1U6D3V2KX-GP
2
1
DIS
C8711
SC1U6D3V2KX-GP
2
1
DIS
DY
C8712
SC1U6D3V2KX-GP
2
1
DIS
DY
C8709
SC1U6D3V2KX-GP
2
1
DY
C8710
SC1U6D3V2KX-GP
2
1
C8707
SC1U6D3V2KX-GP
2
1
C8702
SC1U6D3V2KX-GP
2
1
DIS
1.5V, 350mA
C8719
VRAM6_VREF
VRAM5_VREF
QSBP_1 (81)
QSBN_1 (81)
R8706
DIS
VRAM_ZQ6
243R2F-2-GP
ODTB0 (81)
CSB0#_0 (81)
MEM_RST (81,85,86,88)
(81) CLKB0
(81) CLKB0#
K4W 1G1646E-HC12-GP
E3
F7
F2
F8
H3
H8
G2
H7
MDB16
MDB18
MDB20
MDB19
MDB22
MDB17
MDB23
MDB21
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB1
MDB5
MDB2
MDB4
MDB3
MDB7
MDB0
MDB6
DQSU
DQSU#
C7
B7
QSBP_0 (81)
QSBN_0 (81)
DQSL
DQSL#
F3
G3
QSBP_2 (81)
QSBN_2 (81)
ODT
K1
ODTB0 (81)
CS#
RESET#
L2
T2
CSB0#_0 (81)
MEM_RST (81,85,86,88)
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
K4W 1G1646E-HC12-GP
DIS_Samsung
DIS_Samsung
20090902
20090902
+1.5V_RUN
+1.5V_RUN
R8701
2K1R2F-GP
R8703
2K1R2F-GP
DIS
DIS
C8701
R8705
2K1R2F-GP
SCD1U16V2ZY-2GP
DIS
C8705
SCD1U16V2ZY-2GP
DIS
DIS
DIS
R8702
2K1R2F-GP
VRAM6_VREF
VRAM5_VREF
MDB[0..31] (81)
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
<Core Design>
Wistron Corporation

Title
GPU-VRAM5,6 (3/4)
Size
A3
Date:
5
Document Number
Rev
Berry
A00
Sheet
1
87
of
95
+1.5V_RUN
+1.5V_RUN
VRAM7
DIS
VRAM7_VREF
VRAM8_VREF
R8803
20090902
DIS
VRAM_ZQ7
243R2F-2-GP
(81,87) MAB0
(81,87) MAB1
(81,87) MAB2
(81,87) MAB3
(81,87) MAB4
(81,87) MAB5
(81,87) MAB6
(81,87) MAB7
(81,87) MAB8
(81,87) MAB9
(81,87) MAB10
(81,87) MAB11
(81,87) MAB12
(81,87) MAB13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
(81,87) B_BA0
(81,87) B_BA1
(81,87) B_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
K9
CKE
(81) CLKB1
(81) CLKB1#
R8807
56R2J-4-GP
R8808
56R2J-4-GP
DIS
2
DIS
VREFDQ
VREFCA
ZQ
(81) CKEB1
(81) DQMB4
(81) DQMB5
D3
E7
DMU
DML
(81) W EB1#
(81) CASB1#
(81) RASB1#
L3
K3
J3
WE#
CAS#
RAS#
SCD01U50V2KX-1GP
DIS
C8803
GPU_CLKB1_T
CS#
RESET#
L2
T2
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
DY
DY
C8817
DIS
QSBP_4 (81)
QSBN_4 (81)
C8825
SC1U6D3V2KX-GP
2
1
DIS
ODT
ODTB1 (81)
DY
QSBP_5 (81)
QSBN_5 (81)
K1
C8824
SC1U6D3V2KX-GP
2
1
DQSL
DQSL#
F3
G3
C8823
SC1U6D3V2KX-GP
2
1
C7
B7
C8822
SC1U6D3V2KX-GP
2
1
DIS
DQSU
DQSU#
DY
MDB36
MDB35
MDB39
MDB32
MDB37
MDB33
MDB38
MDB34
C8821
SC1U6D3V2KX-GP
2
1
DIS
D7
C3
C8
C2
A7
A2
B8
A3
C8820
SC1U6D3V2KX-GP
2
1
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
C8819
SC1U6D3V2KX-GP
2
1
DIS
MDB40
MDB43
MDB47
MDB44
MDB41
MDB45
MDB42
MDB46
C8818
DIS
VRAM8_VREF
VRAM7_VREF
R8804
CSB1#_0 (81)
MEM_RST (81,85,86,87)
DIS
VRAM_ZQ8
243R2F-2-GP
K8
K2
N1
R9
B2
D9
G7
R1
N9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A8
A1
C1
C9
D2
E9
F1
H9
H2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
H1
M8
L8
VREFDQ
VREFCA
ZQ
(81,87) MAB0
(81,87) MAB1
(81,87) MAB2
(81,87) MAB3
(81,87) MAB4
(81,87) MAB5
(81,87) MAB6
(81,87) MAB7
(81,87) MAB8
(81,87) MAB9
(81,87) MAB10
(81,87) MAB11
(81,87) MAB12
(81,87) MAB13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
(81,87) B_BA0
(81,87) B_BA1
(81,87) B_BA2
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
(81) CKEB1
K9
CKE
(81) DQMB7
(81) DQMB6
D3
E7
DMU
DML
(81) W EB1#
(81) CASB1#
(81) RASB1#
L3
K3
J3
WE#
CAS#
RAS#
(81) CLKB1
(81) CLKB1#
E3
F7
F2
F8
H3
H8
G2
H7
MDB53
MDB51
MDB55
MDB49
MDB54
MDB48
MDB52
MDB50
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDB61
MDB62
MDB58
MDB59
MDB63
MDB56
MDB57
MDB60
DQSU
DQSU#
C7
B7
QSBP_7 (81)
QSBN_7 (81)
DQSL
DQSL#
F3
G3
QSBP_6 (81)
QSBN_6 (81)
ODT
K1
ODTB1 (81)
CS#
RESET#
L2
T2
CSB1#_0 (81)
MEM_RST (81,85,86,87)
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
K4W 1G1646E-HC12-GP
K4W 1G1646E-HC12-GP
DIS_Samsung
20090902
MDB[32..63] (81)
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DIS_Samsung
20090902
+1.5V_RUN
+1.5V_RUN
R8801
2K1R2F-GP
R8805
2K1R2F-GP
DIS
DIS
C8801
R8806
2K1R2F-GP
SCD1U16V2ZY-2GP
DIS
C8804
SCD1U16V2ZY-2GP
DIS
DIS
DIS
R8802
2K1R2F-GP
VRAM8_VREF
VRAM7_VREF
H1
M8
L8
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
E3
F7
F2
F8
H3
H8
G2
H7
SC10U6D3V5MX-3GP
2
1
C8807
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
SC10U6D3V5MX-3GP
2
1
DIS
A8
A1
C1
C9
D2
E9
F1
H9
H2
VRAM8
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
1.5V, 350mA
MDB[32..63] (81)
C8816
SC1U6D3V2KX-GP
2
1
C8814
SC1U6D3V2KX-GP
2
1
DIS
DY
C8806
K8
K2
N1
R9
B2
D9
G7
R1
N9
SC10U6D3V5MX-3GP
2
1
DY
C8813
SC1U6D3V2KX-GP
2
1
SC10U6D3V5MX-3GP
2
1
DY
C8812
SC1U6D3V2KX-GP
2
1
DY
C8811
SC1U6D3V2KX-GP
2
1
C8810
SC1U6D3V2KX-GP
2
1
C8809
SC1U6D3V2KX-GP
2
1
DIS
C8808
SC1U6D3V2KX-GP
2
1
DIS
C8802
SC1U6D3V2KX-GP
2
1
DIS
1.5V, 350mA
<Core Design>
Wistron Corporation

Title
GPU-VRAM7,8 (4/4)
Size
A3
Date:
5
Document Number
Rev
Berry
A00
Sheet
1
88
of
95
RT8208AGQW for +VCC_GFX_CORE
SSID = Video.PWR.Regulator
PC8907
SCD1U25V2KX-GP
PC8911
SCD1U25V2KX-GP
1
2
1
1
SC10P50V2JN-4GP
DIS
1
2
PTC8903 C
DY
+GFX_CORE_EN_R
11/9
PR8909
150KR2F-L-GP
DIS
+GFX_CORE_FB
PC8912
SCD1U10V2KX-4GP
DIS
PR8911
49K9R2F-L-GP
PR8912
49K9R2F-L-GP
DIS
DIS_PowerPlay
B
PWRCNTL_1#
PWRCNTL_0#
M96 Power Table
Park Power Table
PWRCNTL_0
PWRCNTL_1
+VCC_GFX_CORE
PWRCNTL_0
PWRCNTL_1
0.9V
0.9V
0.95V
0.95V
1.05V
1.05V
1.1V
1.12V
+VCC_GFX_CORE
PR8912=49.9KR
64.44225.6DL
PR8912=49.9KR
64.49925.6DL
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.6mohm/1.8mohm Isat=25Arms 68.R5610.10D
O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms Panasonic/ 79.33719.L01
DIS
PTC8902
2 10KR2J-3-GP
DY
DIS
2 0R2J-2-GP
PM_SLP_S3#
DY
PR8920 1
(21,37,41,42,49,52)
PR8921 1
SC10P50V2JN-4GP
DIS
0210-1
(37) GFX_CORE_EN
DY
PR8908
PC8910
10KR2F-2-GP
SC330P50V2KX-3GP
DIS
PTC8901
PC8913
DY
+GFX_CORE_VOUT
PC8917
Change to RT8208B(Pin to Pin)
DIS_65MOS
DIS
PC8915
SCD1U10V2KX-4GP
2
1
1
5
6
7
8
DIS_65MOS
RT8208BGQW -GP
1120-8
4
3
2
1
+GFX_CORE_VOUT
PG8920
GAP-CLOSE-PWR-3-GP
PR8906
2D2R5F-2-GP
VOUT
DY
GND
PU8904
1VGA_CORE_DIV
EM/DEM
17
PU8903
PW RCNTL_1 (82)
PW RCNTL_1#
PW RCNTL_0#
S
S
S
G
PC8904
SC1U10V2KX-1GP
2
1
PC8918
15
PW RCNTL_0 (82)
+GFX_CORE_FB
S
S
S
G
SCD1U10V2KX-5GP
2
1
7
3
14
5
6
SE330U2VDM-L-GP
G0
FB
G1
D1
D0
DIS
DIS
1
2
COIL-D56UH-2-GP
SE330U2VDM-L-GP
DIS
PGOOD
CS
12
11
8
D
D
D
D
0225-3 +GFX_CORE_EN_R
4
10
UGATE
PHASE
LGATE
+VGA_CORE
PL8901
D
D
D
D
1
DIS 2+GFX_CORE_CS
PR8905 6K98R2-GP
VDD
0114-1
PR8902
PC8906
+GFX_CORE_BOOT
2
1 DIS
2
DIS 1+GFX_CORE_BOOT_C
1R3J-L1-GP
+GFX_CORE_UGATE
SCD1U25V3KX-GP
+GFX_CORE_PHASE
+GFX_CORE_LGATE
SE330U2VDM-L-GP
(49,51,52,90) RUNPW ROK
13
SIR460DP-T1-GE3-GP
4
3
2
1
+GFX_CORE_VDD
BOOT
Vout=0.75V*(R1+R2)/R2
24.14A<OCP< 28.53A
SIR460DP-T1-GE3-GP
4
3
2
1
1
DIS
10R2F-L-GP
TON
VDDP
DIS
S
S
S
G
PU8901
16
9
DIS
1117-6
DIS_65MOS
249KR2F-GP
PR8903
PR8910
1
DIS 2
+GFX_CORE_TON
DIS
DIS
SC10U25V6KX-1GP
PC8905
5
6
7
8
PU8902
SI7686DP-T1-GP
5
6
7
8
PC8908
SC1U10V2KX-1GP
D
D
D
D
5V, 1.25mA
DIS
DIS
+5V_ALW
PC8903
SC10U25V6KX-1GP
PC8914
SC10U25V6KX-1GP
+PW R_SRC
<Core Design>
Wistron Corporation

Title
RT8208B_+VCC_GFXCORE
Size
A3
Date:
5
Document Number
Rev

Sheet
1
89
A00
of
95
APL5930 for +1.8V_RUN_VGA
+3.3V_RUN_VGA
+1.8V_RUN_VGA_P
+1.8V_RUN_VGA
1
R9001
DIS_Park/Mad
2
0R2J-2-GP
+3.3V_RUN_VGA
Q9001
FB
DIS
SO-8-P
+1.8V_RUN_VGA
DIS
1
1
DIS
100R2J-2-GP
DIS_M96
3.3V_RUN_VGA_1
PC9007
DY
PR9006
13K3R2F-L1-GP
DIS
2
10R2J-2-GP
1208-1
1.8V_DIS 1
R9005
DIS
PC9006
R9004
DIS_M96
84.27002.F3F
PC9005
PR9003
GND
1
APL5930KAI-TRG-GP
3
4
5912_1.8V_DELAY_FB
4
3
DIS
1
SC4700P50V2KX-1GP
2
1
1
1.8V_DIS_GATE
DY
PQ9001
2N7002EDW -GP
VOUT#3
VOUT#4
84.27002.F3F
DIS
PC9001
Q9002
+1.8V_RUN_VGA_P
SC22U6D3V5MX-2GP
EN
5
9
SC22U6D3V5MX-2GP
VIN#5
VIN#9
SC68P50V2JN-1GP
PR9002
0R0402-PAD
POK
16K5R2F-2-GP
21.8V_VGA_RUN_EN_C
(37,52) 1.8V_VGA_RUN_EN
Vo=0.8*(1+(R1/R2))
Id: 2A
Rds: 0.15ohm
3.3V_ALW _1
(49,51,52,89) RUNPW ROK
R9006
100KR2J-1-GP
DIS
DIS_M96
2N7002EDW -GP
PU9001
VCNTL
GAP-CLOSE-PW R
DIS
D
DIS_M96
SI2301CDS-T1-GE3-GP
DIS
+5V_ALW
GAP-CLOSE-PW R
DY
GAP-CLOSE-PW R
PG9004
2
1
R9002
100KR2J-1-GP
DIS
PC9004
DIS
PC9003
DIS
SC1U10V2KX-1GP
SC10U6D3V5MX-3GP
PC9002
SC10U6D3V5MX-3GP
PG9001
2
1
+3.3V_RUN
GAP-CLOSE-PW R
PG9003
1
2
DIS
+1.8V_RUN_VGA_VIN
+5V_RUN
5V, 1.5mA
+1.8V_RUN_VGA_VIN
+3.3V_RUN
PG9002
1
2
1.8V_VGA_RUN_EN
APL5930KAI for +1.0V_RUN_VGA
Will be Change to +1.0V_RUN_VGA

+5V_ALW
+1.5V_SUS
APL5930KAI-TRG-GP
SO-8-P
1.0V_DIS 1
R9010
2
10R2J-2-GP
1
2
PC9013
DIS
PC9012
DIS
PC9014
DY
2
PR9009
DIS
5930_1.0VRUN_FB
+1.0V_RUN_VGA
DIS
+1.0V_RUN_VGA
PR9011
<Core Design>
32K4R2F-1-GP
DIS
Wistron Corporation
84.27002.F3F
+1.0V_RUN_VGA
FB
PQ9002
2N7002EDW -GP
DIS
3
4
SCD01U16V2KX-3GP
2
1
VOUT#3
VOUT#4
5
9
DIS
VIN#5
VIN#9
SC4700P50V2KX-1GP
2
1
1.0V_DIS_GATE
DY
EN
PC9010
DY
SC10U6D3V3MX-GP
PC9011
POK
DIS
SC10U6D3V3MX-GP
PR9007
0R0402-PAD
12KR2F-L-GP
21.0V_RUN_VGA_EN_C
VCNTL
(49,51,52,89) RUNPW ROK
DIS
GND
PU9002
R9007
100KR2J-1-GP
PC9009
+3.3V_ALW
1
2
DIS
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
PC9008
SC1U10V2KX-1GP
5V, 1.5mA
1.0V_RUN_VGA_EN

Title
DISCRETE VGA POWER

5
Size
A3
Document Number
Date:
Tuesday, March 09, 2010
Rev
Berry
A00
Sheet
1
90
of
95
POWER SEQUENCE
+PWR_SRC
+3.3V_RTC_LDO
VBAT(+RTC_CELL)
KBC_ROM_STRAPS
S5_ENABLE
+3.3V_ALW
+5V_ALW
WAKE#(PCIE_WAKE#)
RSMRST#(KBC_RSMRST#)
S5_ROM_STRAPS
PWR_BTN#(PM_PWRBTN#)
PM_SLP_S3#/PM_SLP_S5#
+3.3V_RUN, +5V_RUN
+1.5V_SUS
+0.75V_DDR_VTT
+1.8V_RUN
+VGA_CORE
+2.5V_RUN
1.5V_RUN_EN, 1.0V_RUN_VGA_EN
+1.5V_RUN, +1.0V_RUN_VGA
1.8V_VGA_RUN_EN
+1.8V_RUN_VGA
3.3V_RUN_VGA_EN
B
+3.3V_RUN_VGA
RUNPWROK
+CPU_VDDR
IMVP_VR_ON
+VCC_CORE, +VDDNB
IMVP_PWRGD
+1.1V_RUN
VDDC_PWRGD
SB_PWRGD
S0_ROM_STRAPS
<Core Design>
NB_PWRGD
Wistron Corporation

LDT_PG(CPU_LDT_PWRGD)
Title
Size
A3
Date:
5
POWER SEQUENCE
Document Number
Rev
A00

Sheet
1
91
of
95
Change notes - Page 1

VERSON
DATE
X01
11/6
11/9
ITEM
PAGE
Modify List
10
Add C1002 10uF, C1007, EC1001 0.1uF, C1008 10pF.
Insure signal quality.
Issue Description
OWNER
EE
13
Change R1314 to 4.7K.
Meet CRB.
EE
51
Swap PU5101 pin3, pin4.
Correct input voltage level.
EE
82
Add R8210 0R.
Reserve GPU clock input source.
EE
30
Change C3014 to 2.2uF.
Reduce package size.
EE
69
Change C6903 to 0.1uF.
Reduce package size.
EE
49
Add PR4916 100KR.
To prevent leakage in S3 status.
EE
18,19
Change DIMM socket Part Number.
Request by ME.
ME
37
Add R3754 100KR.
To detect leakage current.
EE
11/11
10
Modify R1028 pull-up to +1.5V_RUN.
Solve leakage in S3 status.
EE
11/12
20
Change C2011 to 18pF, C2012 to 15pF.
Set accurate clock frequency.
EE
37
Add C3717 10pF.
Stable singal level.
EE
57
Delete RN5711, RN5705.
Redundant parts.
EE
13
Delete R1331, R1332, R1308.
Redundant parts.
EE
77
Add Pi-filter.
Cure EMI.
EMC
20
Change X2001 P/N.
Request by Sourcer.
Sourcer
11/10
11/13
11/16
11/17
Change R713 to 47R.
Fine tune damping.
EE
82
Add R8211 80.6R, R8220 150R.
Set a voltage divider to 1.8V level swing.
EE
21
Add R2133 1KR.
For UMA VRAM vendor selection.
EE
22
Delete RN2203 pin 4, pin 5 connection.
Solve S5 leakage.
EE
51
Change PR5105 pull-up to +3.3V_RUN.
Prevent leakage.
EE
21
Add C2103, C2104 0.1uF.
For signal stability.
EE
37
Add C3718 0.1uF.
EE
41
Add C4101, C4102 0.1uF.
EE
49
Add PC4923 0.1uF.
EE
66
Add C6601, C6602 0.1uF.
EE
77
Add RN7713 150R.
Move impedance matching resistor from CRT/B to M/B.
EMC
78
Change CARDBD1 pin 2 link to PLTRST#_LAN_WAN.
Change card reader chip to RTS5159 to solve EMI.
EMC
30
Add R3014, R3017, R3020 0R to link AGND and GND.
Issue for pop noise when system boot.
EE
42,48,50
Merge 1.1V power solution on main board.
Save components.
EE, Power
77
Modify CRTBD1 pin define.
Relief EMI.
EMC
79
Add some decoupled capacitors.
Request by EMC.
EMC
37
Change R3737 to 33R, stuff C3715 10pF.
Request by EMC.
EMC
62,89
Sutff EC6203 22pF, PC8911, PC8907 0.1uF.
Request by EMC.
EMC
45,46,47
Stuff EC4502 0.1uF, PC4605, PC4609, PC4738 0.1uF.
Request by EMC.
EMC
<Core Design>
Wistron Corporation

Title
Change notes
Size
A3
Date:
Document Number
Rev
A00

Sheet
1
92
of
95

VERSON
DATE
X01
11/17
Delete R904.
Remove redundant layout trace.
EE
11/18
81
Swap R8105, C8103 location.
Meet CRB.
EE
79
Add some decoupled capacitor.
By RF team request.
RF
49
Change PR4903 to 620KR.
Change to common part.
Power
All
Synchronize with DJ schematic.
Schematic standardlize.
EE
48
Change P/N for PU4802, PU4803, PU4804, PU4805.
Rquest by Power team
Power
All
Review all capacitors tolerance.
Total review for deratig.
EE
11/19
11/20
ITEM
PAGE
Modify List
Issue Description
OWNER
21
Add RN2105 0R.
Reserve to fine tune signal quality.
EE
21
Change RN2101 to 4.7KR.
Fine tuned value for signal.
EA
37
Add RN3705, R3755 0R.
To isolate layout trace to DB1 connector.
EA
49
Change PC4908 to 2.2uF.
Changed by EA report.
EA
54
Modify R5408 connection.
To synchronize with DJ.
EE
57
Add D7701.
To prevent leakage from RGB monitor.
EE
86
Add C8626 0.1uF.
By EA report.
EA
37
Add R3756 10KR, C3720 0.1uF.
Synchronize with DJ.
EE
37
Delete RN3705, R3755.
For more layout space.
EE
X02
13
Delete TP1303, TP1304.
EE
49
Delete PR4905.
EE
89
Add PC8918 0.1uF.
Stable signal quality.
EE
11/24
46,49
Change PU4601, PU4901 Power components.
Request by Power team.
Power
11/25
1 46,47,49,89 Change power components.
Request by Power team.
Power
11/29
10
Change C1008 to 10pF.
Fine tuned signal slew rate to meet specification.
EE
30
Change R3007 to 2.2KR.
By FAE suggestion.
EE
81
Set BOM mark R8104, R8106, R8107, R8110, R8111, R8112.
Implement co-layout Madison and M96.
EE
82,84
Add R8407, R8408 0R.
EE
Add R8016 10KR.
EE
Set BOM mark.
EE
EE
12/04
80
83,84
83
Add L8306, L8307,
12/05
37
Change R3756, C3720 connection.
Correct soft-start for EC power.
EE
12/08
90
Set BOM mark.
EE
12/15
15
Delete RN1501, Add G1501~G1504.
Synchronize with DJ and supply sufficient power rail.
EE
62
Add R6207 100KR.
Insure SPI Write-Protect pin signal level.
EE
66
Change C6602 net name.
Correct signal name.
EE
81
Add R8122 1KR, RN8101 4.7KR.
Meet M96 schematic check list.
EE
82
Swap CLK_VGA_27M_NSS and CLK_VGA_27M_SS connection.
Solve external RGB display tremble issue.
EE
C8397, R8301, R8302, R8303.
<Core Design>
Wistron Corporation

Title
Change notes
Size
A3
Date:
Document Number
Rev
A00

Sheet
1
93
of
95
VERSON
DATE
X02
12/16
ITEM
PAGE
Modify List
Issue Description
OWNER
66
Change R6605 to 0R.
Assure power button level set to low.
EE
37,76
Add net "8103_GPO".
Implement LAN DSM hardware function.
EE
12/17
37
Add U3703.
To solve SPI WP signal malfunction on EC.
EE
12/18
82
Add R8222 1MR.
Assure crystal resonant clock stable.
EE
81
Set VRAM reset circuit.
Follow M96 reset circuit and reseve BOM option.
EE
18
Change TC1801 to 330uF, 2V tolerance.
Implement common part for 1.5V power rail.
EE
46
Change PR4603 to 127KR.
Set 5V current limitation.
Power
46
Empty PR4618 and stuff PR4619.
Set Ultra-sonic mode to keep +15V_ALW voltage level.
Power
10
Set RN1006 PU to +1.5V_SUS.
Follow AMD check list and cure +1.5V_RUN leakage.
EE
62
Change R6206 to 1KR.
According to Safety request, verified OK.
Safety
51
Change PR5102 1KR, PR5106 8.2KR, PR5107 5.62KR.
Set VDDR low voltage level to 0.9V.
EE
10,37
Add Q1005, R1039, R1040.
Request by AMD to set CPU into HTC mode in DOS.
EE
47
Change PR4720 93.1KR, PR4721 24KR.
Set power OCP value.
Power
ALL
Change some resistors as short-pad or resistor array.
Save component counts.
EE
ALL
Change some capacitors with smaller value or empty.
Save component counts.
EE
01/04
15
Change R1507,R1508,R1509,R1510,R1511 to bead.
Filter power noise.
EMC
01/05
Combine R707,R721 as RN711.
EE
81
Delete TP8101,TP8102.
Remove useless test point for more layout space.
EE
7,80
Delete R716,R8020, combine R8009,R8010 as RN8001.
Redundant part.
EE
R3747,R4104 short pad, delete R3722,R3904.
Redundant part.
EE
12/25
12/29
12/31
01/06
01/07
01/08
37,39,41
46
Change PR4620 as short pad.
Redundant part.
EE
51
Change PQ5101 with ESD protector.
Change to common part.
Power
54
Empty R5405 and Stuff R5408.
Avoid LCD white panel.
EE
62
Change R6205 to 0R.
Already have one 1KR ahead.
EE
50
Add PR5004 10KR and empty PR5002.
Avoid +1.1V_ALW leakage in South Bridge.
EE
13
Change R1342 to size 0603.
Synchronous schematic w/DJ.
EE
79
Add R7921 and R7922.
Reserved RF team solution.
RF
Add RN712,C722,C723
Reserve for SMBus signal quality tuning.
EE
60
Change EC6007,EC6008 to 0.01uF.
According FAE Request.
IDT FAE
39
Add Q3904.
According thermal team request.
Thermal
Change location RN2105 to RN1801, add C1823,C1824.
For SMBus signal quality fine tune.
EE
Remove C3912,TP8301,TP8302,TP8213.
Remove dummy part for more layout space.
EE
21,18
39,82,83
76
Reserve C7601, C7602.
Fine tune USB signal quality.
EE
79
Reserve EC7925,EC7926,EC7927.
Reserve by EMC team.
EMC
77
Change RN7711 to 0R, L7701,L7702,L7703 to bead 22R.
According EMC measurement result.
EMC
0108
<Core Design>
Wistron Corporation

Title
Change notes
Size
A3
Date:
Document Number
Rev
A00

Sheet
1
94
of
95

VERSON
DATE
X02
01/08
OWNER
37
Reserve C3721,C3722.
Prevent signal cross talk.
EE
ALL
Change capacitors value and add C3723.
Ensure signal quality.
EE
01/11
68
Change KB1 P/N.
According ME request.
ME
66
Change R6601,R6602,R6604,R6606 to 1KR, R6603 to 470R.
Decrease LED brightness.
EE
01/12
37
Add C3724, R3757.
To set accurate current detection in EC.
EE
10
Add R1041 0R.
Add 0R for level shift off.
EE
01/13
21,37
Add C3725, C2105.
Reserve for singal quality.
EE
01/14
Power
Modify power team componets.
Request by Power Team.
Power
Change RN712 to 22R.
Fine tuned damping resistor value.
EE
66
Reserve R6609, R6610 1KR.
Add for future LED brightness balance.
EE
68
Add keyboard back light circuit, remove R5403.
Add for keyboard with back light module.
EE
69
Change HALLSW1 footprint for co-layout.
Change for co-layout different kind of HALLSW1.
EE
Add AFTP7701, AFTP7702, AFTP7703.
Add AFTP test point for factory test.
EE
Update Obsolete parts.
Update obsolete parts due to policy.
Power
79
Change HBT1 part number.
Change HBT1 part number to match ME EMN file.
ME
47
Add PTC4710.
Add to solve board accoustic issue.
EE
54
Remove co-layout pad.
As factory requst.
EE
42
Add C4217, C4401, C4402.
Ensure signal quality.
EE
48
Delete Power Gap.
Request by Power Team.
Power
02/23
ALL
Change to short pad.
Change most of 0-ohm resistors to short pad.
EE
02/24
7,68,79
Reserve C724, C725, C6806, C6807, EC7928-EC7932.
As EMC team request.
EMC
02/25
13
Add TP1309.
As factory requset to add.
Factory
7,68
Rename EMC capacitor to EC704,EC705,EC6801,EC6802.
Meet schematic standardization.
EE
49,89
Change PR4913 to 3.9R, PR8905 to 6.98KR.
PR4913 for snubber, PR8905 for OCP.
Power
21
Change R2133 to 0R.
Set GPIO input level from 0.5V to 0V.
EE
02/10
02/22
18,19
Issue Description
EE
02/08
Modify List
Reduce V_REF ripple by EA team result.
PAGE
Add C1825,C1922.
A00
ITEM
77
Power
79
02/26
39,42
Remove EC7928.
Layout space limitation.
EE
Empty R3906 and Change R4202 from 0R to 1KR.
It is for solving T8 shutdown issue.
EE
03/03
60
Change SPK1 part number.
Request by ME.
ME
03/05
20,24,37
Empty R2029,R2404,R3751.
Saving unused components.
EE
03/08
48
Stuff PU4803 and empty PU4804.
Place the H/S and L/S MOS at the same surface.
Power
0308-1
<Core Design>
Wistron Corporation

Title
Change notes
Size
A3
Document Number
Berry
Date:
Rev
A00
Sheet
95
of
95

Dell n5010 - Wistron Berry Amd Discrete Uma - Rev A00

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5

Berry Discrete/UMA Schematics Document

AMD Danube CPU S1g4

Berry AMD Discrete/UMA

Date: Monday, March 08, 2010

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

DDR III 1333

DDR III 1333

Berry DG15 Discrete/UMA Block Diagram

Project code :91.4HH01.001

LVDS, CRT I/F

AMD RS880M CORE

AMD SB820M S5 POWER

PCIE x 2& USB 2.0 x 2

14 USB 2.0 ports

High Definition Audio

DDR III SUS&VTT

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Berry AMD Discrete/UMA

AMD GPU CORE

Internal Analog MIC

DDR III SUS&VTT

Power Block Diagram

Power Block Diagram

Berry AMD Discrete/UMA

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

KBC SMBus Block Diagram

SB820M SMBus Block Diagram

Berry AMD Discrete/UMA

SMBUS BLOCK DIAGRAM

Thursday, March 04, 2010

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Thermal Block Diagram

Audio Block Diagram

System sensor, put

THERMAL/AUDIO BLOCK DIAGRAM

Berry AMD Discrete/UMA

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

External clock mode: Use 100-MHz PCIeR

Indicates if memory side-port is available or not

Defines clock generator

Capture from 46113_rs880m_ds_nda_1.03

Embedded Controller (EC)

Selects loading of strap values from EEPROM.

3.3V Integrated clock mode: Use 25-MHz crystal

clock and generate both internal and external clocks

Set PCIe to Gen II mode

0V Force PCIe interface at Gen I mode

Not Applicable to SB820M but provision for

0V Disable the boot fail timer function

Disable Debug Straps.

CPU/NB HT Clock Selection

Slow down core clock for low power platform.

USB0 (I/O Board/ESATA)

USB1 (I/O Board)

USB2 (CRT Board)

USB3 (CRT Board)

CAMERA (LVDS CONN)

Berry AMD Discrete/UMA

Thursday, March 04, 2010

Need External PU Resistor

(76) CLK_PCIE_W LAN

+3.3V_CLK_VDD (40 mils)

RED: Connected to GND through two separate 133- 1%