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Compal Confidential
2

NAWA1 Schematics Document


AMD Tigris: Caspian Processor with RS880M/SB710/Park-S3 & M93-S3

2009-11-26

www.diendanlaptop.org
www.diendanlaptop.org

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Cover Page
Size
B
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009

Sheet
E

of

49

Tigris

Compal Confidential

AMD S1G3 Processor

VRAM 512MB
64M16 x 4

Model Name : NAWA1

Fan Control

page 19

page 37

Memory BUS(DDRII)

uPGA-638 Package
Caspian page 4,5,6,7

Dual Channel

200pin DDRII-SO-DIMM X2
page 8,9

BANK 0, 1, 2, 3

1.8V DDRII 667 (800)

DDR3 800MHz

ATI PARK-S3 & M93-S3


uFCBGA-631

LCD (LED BL)


page 21

Page 14,15,16,17,18

PCI-Express 16x
Gen2

5 in 1 socket

page 29

Thermal Sensor

ATI RS880M

CRT

ADM1032

WINBOND

page 22

page 6

Clock Generator
Card Reader

SLG8SP626VTR

page 20

RTS5138

uFCBGA-528
PCI-Express 1x

MINI Card x1
WLAN
port 2

page 29

page 10,11,12,13

page 32

A link Express2

LAN(10/100)/1000
AR8131/AR8132

page 31
2

Hyper Transport Link


16 x 16

page 30

port 3

ATI SB710

page 31

Mini
card
(WL)X1

Bluetooth
Conn

USB
conn
X1

USB port 0,1

USB port 7

USB port 8

USB port 3

USB port 5

USB port 2
2

USB

3.3V 24.576MHz/48Mhz

page 23,24,25,26,27

page 32

CMOS
Camera

HD Audio

uFCBGA-528

page 30

page 31

USB
conn
X2
3.3V 48MHz

RJ45

page 32

S-ATA

HDA Codec
CX20671
page 36
LPC BUS

SATA HDD
Conn. page 28

CDROM
Conn.
page 28

port 0

port 1

MIC
page 36

Phone Jack x2
page 36

ENE KB926
page 33

Int.KBD

Touch Pad

page 34

page 34

Power Board
BIOS

page 35

page 34

DC/DC Interface.

www.diendanlaptop.org
www.diendanlaptop.org

page 38

Power Circuit
4

page 39,40,41,42,43,
44,45,46,47,48

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Block Diagrams
Size
B
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009

Sheet
E

of

49

Voltage Rails

BTO Option Table

Power Plane

Description

S1

S3

VIN

Adapter power supply (19V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE_0

Core voltage for CPU (0.7-1.2V)

ON

OFF

OFF

+CPU_CORE_1

Core voltage for CPU (0.7-1.2V)

ON

OFF

OFF

+CPU_CORE_NB

Voltage for On-die Northbridge of CPU(0.8-1.1V) ON

OFF

OFF

+0.9V

0.9V switched power rail for DDR terminator

ON

OFF

ON

S5

+1.1VS

1.1V switched power rail for NB VDDC & VGA

ON

OFF

OFF

+1.2V_HT

1.2V switched power rail

ON

OFF

OFF

+VGA_CORE

0.95-1.2V switched power rail

ON

OFF

OFF

+1.5VS

1.5V power rail for PCIE Card

ON

OFF

OFF

+1.8V

1.8V power rail for CPU VDDIO and DDR

ON

ON

OFF

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+2.5VS

2.5V for CPU_VDDA

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+3V_LAN

3.3V power rail for LAN

ON

ON

ON

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

+VSB

VSB always on power rail

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

BTO Item
Discrete
PARK
M93
HDT debug
UMA
Wireless LAN
Blue Tooth
Camera
New Card
VRAM
UNPON

BOM Structure
VGA@
PARK@
M93@
HDT@
UMA@
WLAN@
BT@
CMOS@
New Card@
X76@
@

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Full ON

+VALW

+V

+VS

Clock

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

ON

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

NAWA1_UMA : UMA@/WLAN@/BT@/CMOS@/NEW CARD@


NAWA1_DIS : VGA@/M93@/WLAN@/BT@/NEW CARD@/CMOS@/X76@

PARK-S3 power on sequence

+3VS_VGA
+VGA_CPRE
+1.1VS_VGA
2

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

+1.8VS_VGA

RS880M power on sequence

External PCI Devices


Device

SIGNAL

STATE

IDSEL#

REQ#/GNT#

Interrupts

+3VS
(AVDD, VDD33)
+1.8VS
+1.1VS PLL Rails
(PLLVDD, IOPLLVDD)
+NB_CORE

EC SM Bus1 address

EC SM Bus2 address

Device

Address

HEX

Smart Battery

0001 011X b

16H

Device

Address

HEX

ADI ADM1032 (CPU)

1001 100X b

98H

GMT G781-1 (GPU)

1001 101X b

9AH

SB-Temp Sensor

SB710
SM Bus 0 address

9CH

SB710
SM Bus 1 address

Device

Address

Clock Generator
(SILEGO SLG8SP626)

1101 001Xb

HEX

D2

DDR DIMM1

1001 000Xb

90

DDR DIMM2

1001 010Xb

94

Device

Address

New card

www.diendanlaptop.org
www.diendanlaptop.org

Mini card
4

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Notes List
Size
B
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009

Sheet
E

of

49

VLDT CAP.

+1.2V_HT

250 mil
1
H_CADIP[0..15]

(10) H_CADIP[0..15]

H_CADOP[0..15]

H_CADIN[0..15]

(10) H_CADIN[0..15]

H_CADON[0..15]

H_CADOP[0..15]
H_CADON[0..15]

(10)

C755
10U_0805_6.3V4Z

(10)

C727
10U_0805_6.3V4Z

C666
10U_0805_6.3V4Z

C725
0.22U_0603_16V4Z

C726
0.22U_0603_16V4Z

C722
180P_0402_50V8J

C668
180P_0402_50V8J

Near CPU Socket


+1.2V_HT

+1.2V_HT
JCPU1A

VLDT=1.5A
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

HT LINK

D1
D2
D3
D4

VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3

E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5

L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

AE2
AE3
AE4
AE5

1
C664

L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15

AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

2
10U_0805_6.3V4Z

(10)
(10)
(10)
(10)

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

J3
J2
J5
K5

L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1

L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1

Y1
W1
Y4
Y3

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

(10)
(10)
(10)
(10)

(10)
(10)
(10)
(10)

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

N1
P1
P3
P4

L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1

L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1

R2
R3
T5
R5

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

(10)
(10)
(10)
(10)

6090022100G_B

ME@

www.diendanlaptop.org
www.diendanlaptop.org

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

AMD CPU S1G3 HT I/F


Size Document Number
Custom
Date:

Rev
1.0

LA-5971P

Thursday, December 10, 2009

Sheet
E

of

49

Processor DDR2 Memory Interface

PLACE CLOSE TO PROCESSOR


WITHIN 1.2 INCH

JCPU1C

(9) DDRB_SDQ[63..0]

MEM:DATA

DDRA_CLK0
+1.8V

DDRA_CLK0#

R78
1K_0402_1%

C888
1.5P_0402_50V9C

R79
1K_0402_1%

C177
1000P_0402_25V8J

C178
0.1U_0402_16V4Z

DDRA_CLK1
+MCH_REF
1

DDRA_CLK1#

C891
1.5P_0402_50V9C

DDRB_CLK0
1

DDRB_CLK0#

C890
1.5P_0402_50V9C

DDRB_CLK1
1

DDRB_CLK1#

C889
1.5P_0402_50V9C

+0.9V

+0.9V
JCPU1B

VTT=0.75A
Place them close to CPU within 1"

+1.8V

R77
1
1
R76

39.2_0402_1%
2
2
39.2_0402_1%

D10
C10
B10
AD10

VTT1
VTT2
VTT3
VTT4

AF10
AE10

MEMZP
MEMZN

H16
(8) DDRA_ODT0
(8) DDRA_ODT1

(8) DDRA_SCS0#
(8) DDRA_SCS1#

(8) DDRA_CKE0
(8) DDRA_CKE1

(8) DDRA_CLK0
(8) DDRA_CLK0#
(8) DDRA_CLK1
(8) DDRA_CLK1#
3

(8) DDRA_SMA[15..0]

(8) DDRA_SBS0#
(8) DDRA_SBS1#
(8) DDRA_SBS2#
(8) DDRA_SRAS#
(8) DDRA_SCAS#
(8) DDRA_SWE#

DDRA_ODT0
DDRA_ODT1

DDRA_SCS0#
DDRA_SCS1#

DDRA_CKE0
DDRA_CKE1

DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#

T19
V22
U21
V19
T20
U19
U20
V20
J22
J20
N19
N20
E16
F16
Y16
AA16
P19
P20

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15

N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19

DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#

R20
R23
J21

DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#

R19
T22
T24

MEM:CMD/CTRL/CLK VTT5
VTT6
VTT7
VTT8
VTT9

RSVD_M1
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
MA_CKE0
MA_CKE1

VTT_SENSE
MEMVREF
RSVD_M2
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB_CKE0
MB_CKE1

MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CLK_H2
MA_CLK_L2
MA_CLK_H3
MA_CLK_L3

MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CLK_H2
MB_CLK_L2
MB_CLK_H3
MB_CLK_L3

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

MA_BANK0
MA_BANK1
MA_BANK2

MB_BANK0
MB_BANK1
MB_BANK2

MA_RAS_L
MA_CAS_L
MA_WE_L

MB_RAS_L
MB_CAS_L
MB_WE_L

W10
AC10
AB10
AA10
A10
Y10
W17

VTT_SENSE

PAD

T4

+MCH_REF

B18
W26
W23
Y26

DDRB_ODT0
DDRB_ODT1

V26
W25
U22

DDRB_SCS0#
DDRB_SCS1#

J25
H26

DDRB_CKE0
DDRB_CKE1

P22
R22
A17
A18
AF18
AF17
R26
R25

DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15

R24
U26
J26

DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#

U25
U24
U23

DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#

DDRB_ODT0 (9)
DDRB_ODT1 (9)
DDRB_SCS0# (9)
DDRB_SCS1# (9)
DDRB_CKE0 (9)
DDRB_CKE1 (9)

DDRB_CLK0 (9)
DDRB_CLK0# (9)
DDRB_CLK1 (9)
DDRB_CLK1# (9)
(9) DDRB_SDM[7..0]
DDRB_SMA[15..0] (9)

DDRB_SBS0# (9)
DDRB_SBS1# (9)
DDRB_SBS2# (9)

(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)

DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#

DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7

A12
B16
A22
E25
AB26
AE22
AC16
AD12

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#

C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

DDRB_SRAS# (9)
www.diendanlaptop.org
DDRB_SCAS# (9)
www.diendanlaptop.org
DDRB_SWE# (9)

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

E12
C15
E19
F24
AC24
Y19
AB16
Y13

DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#

DDRA_SDQ[63..0]

(8)
1

DDRA_SDM[7..0]

(8)

DDRA_SDQS0 (8)
DDRA_SDQS0# (8)
DDRA_SDQS1 (8)
DDRA_SDQS1# (8)
DDRA_SDQS2 (8)
DDRA_SDQS2# (8)
DDRA_SDQS3 (8)
DDRA_SDQS3# (8)
DDRA_SDQS4 (8)
DDRA_SDQS4# (8)
DDRA_SDQS5 (8)
DDRA_SDQS5# (8)
DDRA_SDQS6 (8)
DDRA_SDQS6# (8)
DDRA_SDQS7 (8)
DDRA_SDQS7# (8)

6090022100G_B
ME@

6090022100G_B
ME@

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

AMD CPU S1G3 DDRII I/F


Size Document Number
Custom
Date:

Rev
1.0

LA-5971P

Thursday, December 10, 2009

Sheet
E

of

49

+2.5VDDA
L63
1
2
MBK1608221YZF_0603

+2.5VS

+
C918
150U_B2_6.3VM_R35M

1
C941

1
C938

+1.8V

close to L35

LDT_RST#
H_PWRGD
LDT_STOP#

(20) CLK_CPU_BCLK#

1
C724

2
3900P_0402_50V7K

+1.8VS

+1.8V
+1.8V

+1.2V_HT

R557
300_0402_5%

(23)

R82
R89

1
1 390_0402_5%
390_0402_5%

(47) CPU_VDD1_FB_H
(47) CPU_VDD1_FB_L

+1.8VS

R558
300_0402_5%
1

CPU_VDD1_FB_H
Y6
CPU_VDD1_FB_L AB6
G10
AA9
AC9
AD9
AF9

VDDNB_FB_H
VDDNB_FB_L

DBRDY
TMS
TCK
TRST_L
TDI
TEST23
TEST18
TEST19

T37 PAD
T33 PAD

CPU_TEST25H
CPU_TEST25L

T2

CPU_TEST21
CPU_TEST20
CPU_TEST24
CPU_TEST22
CPU_TEST12
CPU_TEST27

R227 2 0_0402_5%
1
CPU_TEST6
PAD

AB8
AF7
AE7
AE8
AC8
AF8
C2
AA6
A3
A5
B3
B5
C1

CPU_SVC (47)
CPU_SVD (47)

R556
300_0402_5%

(11,23) LDT_STOP#
1

Q9
1

R65

2
0_0402_5%

H_THERMTRIP# (24)

1
R69

+1.8V

2
300_0402_5%

CPU_THERMTRIP#_R
H_PROCHOT#

AF6
AC7
AA8

H_PROCHOT#

R68

2
0_0402_5%

H_PROCHOT_R# (23,33)

THERMDC_CPU
THERMDA_CPU

W7
W8

DBREQ_L
TDO

TEST21
TEST20
TEST24
TEST22
TEST12
TEST27

E10

CPU_DBREQ#

CPU_VDDNB_FB_H (47)
CPU_VDDNB_FB_L (47)

CPU_TDO

AE9

TEST17
TEST16
TEST15
TEST14

D7
E7
F7
C7

CPU_TEST17
CPU_TEST16
CPU_TEST15
CPU_TEST14

TEST7
TEST10

C3
K8

CPU_TEST7
CPU_TEST10

C4

CPU_TEST8

TEST29_H
TEST29_L

(43)

T5

CPU_VDDNB_FB_H
CPU_VDDNB_FB_L

CPU_TEST28_H_PLLCHRZ_P
CPU_TEST28_L_PLLCHRZ_N

TEST8

TEST9
TEST6

VDDIO
PAD

H6
G6

J7
H8

TEST28_H
TEST28_L

TEST25_H
TEST25_L

W9
Y9

PAD
PAD
PAD
PAD
PAD
PAD

T34
T36
T32
T38

PAD
PAD

T31
T18

PAD

T67

CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N

C9
C8

PAD
PAD

T24
T21

+1.8V

CPU_SVC
CPU_SVD

T39
T35

R456 1
1
R549

2 1K_0402_5%
2
1K_0402_5%

+1.8V
@
1
R144
CPU_TEST25L 1
R143
CPU_TEST10
1
R101@
CPU_TEST18
1
R950@
CPU_TEST19
1
R951@
CPU_TEST22
1
R952@
CPU_TEST21
1
R75
CPU_TEST24
1
R74
CPU_TEST20
1
R73
CPU_TEST23
1
R72
CPU_TEST25H 1
R136
CPU_TEST25L 1
R135
CPU_TEST25H

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

RSVD10
RSVD9
RSVD8
RSVD7
RSVD6

H18
H19
AA7
D5
C5

+1.8VS

VDDIO_FB_H
VDDIO_FB_L

VDD1_FB_H
VDD1_FB_L

H10
G9

T42 PAD
T3 PAD
T41 PAD

THERMDC
THERMDA

VDD0_FB_H
VDD0_FB_L

CPU_TEST18
CPU_TEST19

E9
E8

THERMTRIP_L
PROCHOT_L
MEMHOT_L

CPU_SVC
CPU_SVD

A6
A4

MMBT3904_NL_SOT23-3

M11
W18

HT_REF0
HT_REF1

T25 PAD
T26 PAD

T43 PAD

C720
0.01U_0402_16V7K
@

F6
E6

SVC
SVD

SIC
SID
ALERT_L

AD7

H_PWRGD

R6
P6

CPU_VDD0_FB_H
CPU_VDD0_FB_L

KEY1
KEY2

RESET_L
PWROK
LDTSTOP_L
LDTREQ_L

CPU_TEST23

T44 PAD

AF4
AF5
AE6

CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

C721
0.01U_0402_16V7K
@

(23) H_PWRGD

CPU_SIC
CPU_SID

2 44.2_0402_1% CPU_HTREF0
2 44.2_0402_1% CPU_HTREF1

1
1

(47) CPU_VDD0_FB_H
(47) CPU_VDD0_FB_L

LDT_RST#

LDT_RST#

2
R70 2
R71 @

CLKIN_H
CLKIN_L

B7
A7
F10
C6

R455
169_0402_1%

VDDA1
VDDA2

A9
A8

CPU_THERMTRIP#_R

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

2 3900P_0402_50V7K

1
C723

F8
F9

JCPU1D

(20) CLK_CPU_BCLK

2
10K_0402_5%
2
300_0402_5%

R66
1
R67

C880
0.22U_0603_16V4Z

4.7U_0805_10V4Z
C296
2 180P_0402_50V8J

VDDA=0.25A

3300P_0402_50V7K

6090022100G_B
ME@

LDT_STOP#
C719
0.01U_0402_16V7K
@

2
510_0402_5%
2
510_0402_5%
2
0_0603_5%
2
0_0603_5%
2
0_0603_5%
2
0_0603_5%
2
300_0402_5%
2
300_0402_5%
2
300_0402_5%
2
300_0402_5%
2
510_0402_5%
2
510_0402_5%

C206
2

MP(Remove)

U10
1

VDD

THERMDA_CPU

THERMDC_CPU
C194
1
2
3300P_0402_50V7K

D-

THERM#

D+

EC_SMB_CK2

SDATA

EC_SMB_DA2

ALERT#

GND

SCLK

EC_SMB_CK2 (33)

R140 2
@
0_0402_5%

+3VS

MP(Remove)
U15
HDT_RST#

B
A

SAMTEC_ASP-68200-07

LDT_RST#

2
1

SB_PWRGD (11,24,33)4

NC7SZ08P5X_NL_SC70-5
@

MP(mask)

2008/10/06

Issued Date

1001 100X b

Compal Electronics, Inc.

Compal Secret Data

Security Classification

ADM1032ARMZ_MSOP8

Address

EC_SMB_DA2 (33)

2
4
6
8
10
12
14
16
18
20
22
24
26

1
3
5
7
9
11
13
15
17
19
21
23

0.1U_0402_16V4Z

JP1

www.diendanlaptop.org
www.diendanlaptop.org
CPU_DBREQ#
CPU_DBRDY @
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

+3VS

+1.8V

2
1
220_0402_5%R117
2
1
220_0402_5%R118
2
1
220_0402_5%R119
2
1
300_0402_5%R120
1
2
300_0402_5%R555

+1.8V

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

Title

AMD CPU S1G3 CTRL


Size Document Number
Custom
Date:

Rev
1.0

LA-5971P

Thursday, December 10, 2009

Sheet
E

of

49

VDD0 = 18A

VDD(+CPU_CORE) decoupling.
+CPU_CORE_0

+CPU_CORE_0

C939
330U_X_2VM_R6M

G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11

+CPU_CORE_1

C661
330U_X_2VM_R6M

1
C96
330U_X_2VM_R6M

C643
330U_X_2VM_R6M

Near CPU Socket


VDDNB=4A
(For Tigris)
+CPU_CORE_0

VDDNB=3A

+CPU_CORE_1

+CPU_CORE_NB
1

C914
22U_0805_6.3V6M

C911
22U_0805_6.3V6M

C273
22U_0805_6.3V6M

C915
22U_0805_6.3V6M

C214
22U_0805_6.3V6M

C238
22U_0805_6.3V6M

+CPU_CORE_0

C227
22U_0805_6.3V6M

K16
M16
P16
T16
V16

C215
22U_0805_6.3V6M

+1.8V

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17

+CPU_CORE_1

VDDIO=3A
1

C887
0.22U_0603_16V4Z

C276
0.01U_0402_16V7K

C921
180P_0402_50V8J

C882
0.22U_0603_16V4Z

C9
0.01U_0402_16V7K

C230
180P_0402_50V8J

Under CPU Socket


2

VDD1 =18A
JCPU1E

JCPU1F
AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4

+CPU_CORE_1

VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12

VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

+1.8V

6090022100G_B
Athlon 64 S1
Processor Socket

VDDIO decoupling.

ME@

+CPU_CORE_NB

decoupling.

+1.8V
+CPU_CORE_NB
1

C195
22U_0805_6.3V6M

C228
22U_0805_6.3V6M

C222

0.22U_0603_16V4Z
2

C886

0.22U_0603_16V4Z
2

C919

C274

180P_0402_50V8J 180P_0402_50V8J
2
2

C207
22U_0805_6.3V6M

C910
22U_0805_6.3V6M

C913
22U_0805_6.3V6M

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

6090022100G_B

Under CPU Socket

Athlon 64 S1
Processor Socket

ME@

Between CPU Socket and DIMM


+1.8V

+0.9V

C301
0.22U_0603_16V4Z

C302
0.22U_0603_16V4Z

C303
0.22U_0603_16V4Z

+1.8V

C309
0.01U_0402_16V7K

C307
0.01U_0402_16V7K

C300
0.22U_0603_16V4Z

C218
180P_0402_50V8J

C: Change to NPO CAP


1

C912
22U_0805_6.3V6M

C308
180P_0402_50V8J

C310
180P_0402_50V8J

+1.8V

+0.9V

C219
1
180P_0402_50V8J

C943
4.7U_0805_10V4Z

C945
4.7U_0805_10V4Z

C883
0.22U_0603_16V4Z

C885
0.22U_0603_16V4Z

C893
1000P_0402_25V8J

C892
1000P_0402_25V8J

C920
180P_0402_50V8J

C922
180P_0402_50V8J

Near CPU Socket Right side.

+
2

220U_D2_4VM_R15

180PF Qt'y follow the distance between


CPU socket and DIMM0. <2.5inch>

Near Power Supply


C937

+1.8V

VTT decoupling.

1
C211
4.7U_0805_10V4Z

1
C209
4.7U_0805_10V4Z

1
C208
4.7U_0805_10V4Z

1
+ C226
C210
4.7U_0805_10V4Z
330U_X_2VM_R6M

+0.9V
www.diendanlaptop.org
www.diendanlaptop.org
1

2
2

C942
4.7U_0805_10V4Z

C944
4.7U_0805_10V4Z

C884
0.22U_0603_16V4Z

C881
0.22U_0603_16V4Z

C718
1000P_0402_25V8J

C717
1000P_0402_25V8J

C716
180P_0402_50V8J

C715
180P_0402_50V8J

Near CPU Socket Left side.

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

AMD CPU S1G3 PWR & GND


Size Document Number
Custom
Date:

Rev
1.0

LA-5971P

Thursday, December 10, 2009

Sheet
E

of

49

+1.8V

+1.8V
JDIMM1

DDRA_SDQ10
DDRA_SDQ11

DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2#
DDRA_SDQS2

(5) DDRA_SDQS2#
(5) DDRA_SDQS2

DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27

DDRA_CKE0

(5) DDRA_CKE0

DDRA_SBS2#

(5) DDRA_SBS2#

DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#

(5) DDRA_SBS0#
(5) DDRA_SWE#

DDRA_SCAS#
DDRA_SCS1#

(5) DDRA_SCAS#
(5) DDRA_SCS1#

DDRA_ODT1

(5) DDRA_ODT1

DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4

(5) DDRA_SDQS4#
(5) DDRA_SDQS4

DDRA_SDQ34
DDRA_SDQ35
3

DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49

DDRA_SDQS6#
DDRA_SDQS6

(5) DDRA_SDQS6#
(5) DDRA_SDQS6

DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
SB_SMBDATA
SB_SMBCLK

(9,20,24,31) SB_SMBDATA
(9,20,24,31) SB_SMBCLK

+3VS
4

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND

DDRA_SDQ[0..63]

DDRA_SDQ[0..63]

DDRA_SDM0
DDRA_SDM[0..7]

(5)

DDRA_SDM[0..7] (5)

DDRA_SDQ6
DDRA_SDQ7

DDRA_SMA[0..15]

DDRA_SDQ12
DDRA_SDQ13

DDRA_SMA[0..15] (5)

DDRA_SDM1
DDRA_SMA6
DDRA_SMA7
DDRA_SMA15
DDRA_SMA11

DDRA_SDQ14
DDRA_SDQ15

1
C198

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

1
C225
1
C223

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

1
C159
1
C167

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

1
C179
1
C17

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

DDRA_SBS0#
DDRA_SMA10
DDRA_SMA1
DDRA_SMA3

47_0804_8P4R_5%
RP7
8
1
7
2
6
3
5
4

1
C169
1
C15

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

DDRA_SCS1#
DDRA_ODT1
DDRA_SWE#
DDRA_SCAS#

47_0804_8P4R_5%
RP4
8
1
7
2
6
3
5
4

1
C157
1
C142

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

DDRA_SMA13
DDRA_ODT0
DDRA_SCS0#
DDRA_SRAS#

47_0804_8P4R_5%
RP3
1
8
2
7
3
6
4
5

1
C145
1
C18

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

+1.8V

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

C14

DDRA_SDQ20
DDRA_SDQ21

+V_DDR_MCH_REF
DDRA_SDQ22
DDRA_SDQ23

DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQS3#
DDRA_SDQS3

2
DDRA_SDQS3# (5)
DDRA_SDQS3 (5)

DDRA_SDQ30
DDRA_SDQ31
DDRA_CKE1

DDRA_SBS2#
DDRA_CKE0
DDRA_SMA14
DDRA_CKE1

R147
1K_0402_1%

DDRA_SDM2

+V_DDR_MCH_REF

DDRA_SBS1#
DDRA_SMA0
DDRA_SMA2
DDRA_SMA4

R148
1K_0402_1%

DDRA_SMA5
DDRA_SMA8
DDRA_SMA9
DDRA_SMA12

DDRA_CKE1 (5)

DDRA_SMA15
DDRA_SMA14

Check layout place

DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_SMA13

DDRA_SBS1# (5)
DDRA_SRAS# (5)
DDRA_SCS0# (5)
DDRA_ODT0 (5)

1
2
3
4

8
7
6
5

1
C16

47_0804_8P4R_5%
RP13
8
1
7
2
6
3
5
4
47_0804_8P4R_5%
RP8
1
8
2
7
3
6
4
5
47_0804_8P4R_5%
RP9
8
1
7
2
6
3
5
4

47_0804_8P4R_5%
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
3

DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5#
DDRA_SDQS5

DDRA_SDQS5# (5)
DDRA_SDQS5 (5)

DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ52
DDRA_SDQ53

EMI
+1.8V

DDRA_CLK1 (5)
DDRA_CLK1# (5)
DDRA_SDM6

2
0.1U_0402_16V4Z

C13
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7

1
C175
1
C176

www.diendanlaptop.org
DDRA_SDQS7# (5)
www.diendanlaptop.org
DDRA_SDQS7 (5)

@
@

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

DDRA_SDQ62
DDRA_SDQ63
R39
R36

1
1

DIMM1 REV H:5.2mm (BOT)

0.1U_0402_16V4Z
2
2
2.2U_0805_10V6K

2 10K_0402_5%
2 10K_0402_5%
4

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

+1.8V

+0.9V
RP10

DDRA_CLK0 (5)
DDRA_CLK0# (5)

TYCO_292527-4
ME@

+3VS

C936

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201

DDRA_SDQ4
DDRA_SDQ5

DDRA_SDQS1#
DDRA_SDQS1

(5) DDRA_SDQS1#
(5) DDRA_SDQS1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

DDRA_SDQ8
DDRA_SDQ9

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

DDRA_SDQ2
DDRA_SDQ3

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

DDRA_SDQS0#
DDRA_SDQS0

(5) DDRA_SDQS0#
(5) DDRA_SDQS0

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

C923
1U_0402_6.3V4Z

DDRA_SDQ0
DDRA_SDQ1

C894
1000P_0402_25V8J

+V_DDR_MCH_REF

Title

DDRII SO-DIMM 1
Size Document Number
Custom
Date:

Rev
1.0

LA-5971P

Thursday, December 10, 2009

Sheet
E

of

49

+V_DDR_MCH_REF

+1.8V
+1.8V

2.2U_0603_6.3V4Z

1
C933

DDRB_SDQ[0..63]

JDIMM2
DDRB_SDQ0
DDRB_SDQ1

(5) DDRB_SDQS0#
(5) DDRB_SDQS0

DDRB_SDQS0#
DDRB_SDQS0
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9

(5) DDRB_SDQS1#
(5) DDRB_SDQS1

DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11

DDRB_SDQ16
DDRB_SDQ17
(5) DDRB_SDQS2#
(5) DDRB_SDQS2

DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3

DDRB_SDQ26
DDRB_SDQ27
(5) DDRB_CKE0
(5) DDRB_SBS2#

DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1

(5) DDRB_SBS0#
(5) DDRB_SWE#
(5) DDRB_SCAS#
(5) DDRB_SCS1#
(5) DDRB_ODT1

DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#
DDRB_SCAS#
DDRB_SCS1#
DDRB_ODT1
DDRB_SDQ32
DDRB_SDQ33

(5) DDRB_SDQS4#
(5) DDRB_SDQS4

DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35

DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49

(5) DDRB_SDQS6#
(5) DDRB_SDQS6

DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
SB_SMBDATA
SB_SMBCLK

(8,20,24,31) SB_SMBDATA
(8,20,24,31) SB_SMBCLK

+3VS

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDRB_SDM[0..7]

DDRB_SDQ4
DDRB_SDQ5

DDRB_SDQ[0..63]

(5)

DDRB_SDM[0..7] (5)

DDRB_SDM0
DDRB_SMA[0..15]
DDRB_SDQ6
DDRB_SDQ7

DDRB_SMA[0..15] (5)

DDRB_SDQ12
DDRB_SDQ13
DDRB_SDM1
DDRB_CLK0 (5)
DDRB_CLK0# (5)

+1.8V

+0.9V

DDRB_SDQ14
DDRB_SDQ15

RP6
DDRB_SRAS#
DDRB_SMA0
DDRB_SMA2
DDRB_SMA4

1
2
3
4

DDRB_SDQ20
DDRB_SDQ21

8
7
6
5

2
C171
1
C201

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C180
1
C20

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C200
1
C231

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
1
C197

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C146
1
C19

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C122
1
C117

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

2
C147
1
C118

1
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

47_0804_8P4R_5%
RP12
DDRB_SMA6
DDRB_SMA7
DDRB_SMA11
DDRB_SMA14

DDRB_SDM2
DDRB_SDQ22
DDRB_SDQ23

1
2
3
4

8
7
6
5

47_0804_8P4R_5%
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQS3#
DDRB_SDQS3

RP14
DDRB_CKE0
DDRB_SBS2#
DDRB_SMA15
DDRB_CKE1

DDRB_SDQS3# (5)
DDRB_SDQS3 (5)

8
7
6
5

DDRB_SDQ30
DDRB_SDQ31
DDRB_CKE1

1
2
3
4

47_0804_8P4R_5%
RP11

DDRB_CKE1 (5)

DDRB_SMA8
DDRB_SMA5
DDRB_SMA9
DDRB_SMA12

DDRB_SMA15
DDRB_SMA14
DDRB_SMA11
DDRB_SMA7
DDRB_SMA6

8
7
6
5

1
2
3
4

C21

47_0804_8P4R_5%
RP5

DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_SMA13

DDRB_SBS0#
DDRB_SMA10
DDRB_SMA3
DDRB_SMA1
DDRB_SBS1# (5)
DDRB_SRAS# (5)
DDRB_SCS0# (5)

8
7
6
5

1
2
3
4

47_0804_8P4R_5%
RP1
DDRB_ODT1
DDRB_SCS1#
DDRB_SWE#
DDRB_SCAS#

DDRB_ODT0 (5)

DDRB_SDQ36
DDRB_SDQ37

8
7
6
5

1
2
3
4

47_0804_8P4R_5%
RP2

DDRB_SDM4

DDRB_SMA13
DDRB_ODT0
DDRB_SCS0#
DDRB_SBS1#

DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5

1
2
3
4

8
7
6
5

47_0804_8P4R_5%

DDRB_SDQS5# (5)
DDRB_SDQS5 (5)

DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ52
DDRB_SDQ53
DDRB_CLK1 (5)
DDRB_CLK1# (5)
DDRB_SDM6
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQS7#
DDRB_SDQS7

www.diendanlaptop.org
www.diendanlaptop.org
DDRB_SDQS7# (5)
DDRB_SDQS7 (5)

DDRB_SDQ62
DDRB_SDQ63
R37
R35

1
1

2 10K_0402_5%
2 10K_0402_5%

+3VS
4

FOX_AS0A426-NARN-7F~N
ME@

DIMM2 REV H:9.2mm (BOT)

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

DDRII SO-DIMM 2
Size Document Number
Custom
Date:

Rev
1.0

LA-5971P

Thursday, December 10, 2009

Sheet
E

of

49

(14) PCIE_GTX_C_MRX_P[0..15]
(14) PCIE_GTX_C_MRX_N[0..15]

PCIE_GTX_C_MRX_P[0..15]

PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]

PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15] (14)
PCIE_MTX_C_GRX_N[0..15] (14)

U20B

(31)
(31)
(30)
(30)

PCIE_PTX_C_IRX_P1
PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P2
PCIE_PTX_C_IRX_N2

(31) PCIE_PTX_C_IRX_P4
(31) PCIE_PTX_C_IRX_N4

(23)
(23)
(23)
(23)
(23)
(23)
(23)
(23)

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

PART 2 OF 6

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5

PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)

AC8
AB8

PCIE I/F GPP

PCIE I/F SB

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15

C646 1
C648 1
C650 1
C652 1
C356 1
C657 1
C365 1
C641 1
C636 1
C635 1
C632 1
C360 1
C627 1
C623 1
C624 1
C361 1

PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P4
PCIE_ITX_PRX_N4

SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C

C352
C609
C38
C33
C37
C32
C610
C616

R32 1
R267 1

WLAN@
WLAN@
C614 1
2
C362
1
2
C357 1
2
C618
1
2
C964 1
C965
1
NEWCARD@
NEWCARD@
1
1
1
1
1
1
1
1
2
2

2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P0


PCIE_MTX_C_GRX_N0
2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
VGA@
0.1U_0402_10V7K
2
PCIE_MTX_C_GRX_N12
2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
2 VGA@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

C358 1
2 VGA@ 0.1U_0402_10V7K
C649 1
2 VGA@ 0.1U_0402_10V7K
C651 1
2 VGA@ 0.1U_0402_10V7K
C653 1
2 VGA@ 0.1U_0402_10V7K
C366 1
VGA@
0.1U_0402_10V7K
2
C876 1
2 VGA@ 0.1U_0402_10V7K
C658 1
2 VGA@ 0.1U_0402_10V7K
C364 1
2 VGA@ 0.1U_0402_10V7K
C638 1
VGA@
0.1U_0402_10V7K
2
C637 1
2 VGA@ 0.1U_0402_10V7K
C634 1
2 VGA@ 0.1U_0402_10V7K
C631 1
2 VGA@ 0.1U_0402_10V7K
C629 1
2 VGA@ 0.1U_0402_10V7K
C363 1
2 VGA@ 0.1U_0402_10V7K
C359 1
2 VGA@ 0.1U_0402_10V7K
C621 1
2 VGA@ 0.1U_0402_10V7K

2
2
2
2
2
2
2
2

0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K

2
2

PCIE_ITX_C_PRX_P1
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P2
PCIE_ITX_C_PRX_N2

(31)
(31)
(30)
(30)

WLAN
LAN

PCIE_ITX_C_PRX_P4 (31)
PCIE_ITX_C_PRX_N4 (31)

New Card

(4) H_CADOP[0..15]
(4) H_CADON[0..15]

0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K

1.27K_0402_1%
2K_0402_1%

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

(23)
(23)
(23)
(23)
(23)
(23)
(23)
(23)

H_CADIP[0..15]
H_CADIN[0..15]

H_CADIP[0..15]

(4)

H_CADIN[0..15]

(4)

U20A

+1.1VS

RS880M_FCBGA528
RS780M Display Port Support (muxed on GFX)
GFX_TX0,TX1,TX2 and TX3
DP0
AUX0 and HPD0
3

H_CADOP[0..15]
H_CADON[0..15]

GFX_TX4,TX5,TX6 and TX7


DP1
AUX1 and HPD1

(4)
(4)
(4)
(4)

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

(4)

H_CTLOP0

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
T22
T23
AB23
AA22

H_CTLOP0
H_CTLON0

(4)
H_CTLON0
H_CTLOP1
www.diendanlaptop.org
(4)
H_CTLOP1
H_CTLON1
www.diendanlaptop.org
(4)
H_CTLON1
1

R56

M22
M23
R21
R20
C23
A24

301_0402_1%

0718 Place within 1"


layout 1:2
4

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

PART 1 OF 6

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HYPER TRANSPORT CPU I/F

D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3

PCIE I/F GFX

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7

F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

H24
H25
L21
L20

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

M24
M25
P19
R18

HT_RXCALP
HT_RXCALN

HT_TXCALP
HT_TXCALN

B24
B25

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

(4)
(4)
(4)
(4)

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

(4)
(4)
(4)
(4)

R51

301_0402_1%

0718 Place within 1"


layout 1:2

RS880M_FCBGA528

SA00002DR30 S IC 216-0674026 A13 RS780MN FCBGA 0FA


SA000032710 S IC 216-0752001 A11 RS880M FCBGA528 0FA

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

RS880-HT/PCIE
Size Document Number
Custom
Date:

Rev
1.0

LA-5971P

Thursday, December 10, 2009

Sheet
E

10

of

49

For RS780M A13


RED: Connected to GND through two separate 140ohm 1% resistor
GMCH_CRT_R
2
140_0402_1%
GMCH_CRT_G
2
150_0402_1%
GMCH_CRT_B
2
150_0402_1%

UMA@ 1
R45
UMA@ 1
R49
UMA@ 1
R50
1

+1.8VS

C22
0.1U_0402_16V4Z

+1.8VS

PLLVDD18=20mA
+NB_HTPVDD

+AVDDQ
2
1
FBMA-L11-160808-221LMT_0603
1

L13
2
1
FBMA-L11-160808-221LMT_0603
1
1
C93
2.2U_0603_6.3V4Z

C935
2.2U_0603_6.3V4Z

C84
1U_0402_6.3V4Z

AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)

C875
1U_0402_6.3V4Z
2 @

E17
F17
F15

C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)

G18
G17
E18
F18
E19
F19

RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)

GMCH_CRT_R

(22) GMCH_CRT_R

VDDA18HTPLL=20mA
+1.8VS

(22) GMCH_CRT_G

+VDDA18HTPLL

C86
1U_0402_6.3V4Z

2
R283

H17

VDDA18HTPLL

+VDDA18PCIEPLL

D7
E7

C25
C24

(20) CLK_NBHT
(20) CLK_NBHT#
CLK_NB_14.318M

(20) CLK_NB_14.318M
+1.1VS

R477
100_0402_5%
@

1
2
R564
4.7K_0402_5%

1
2
R566
4.7K_0402_5%

E11
F11
T2
T1

(20) CLK_NBGFX
(20) CLK_NBGFX#

U1
U2

(20) CLK_SBLINK_BCLK
(20) CLK_SBLINK_BCLK#

C854
100P_0402_50V8J
@

GMCH_LCD_CLK
GMCH_LCD_DATA
GMCH_HDMI_DATA_R2
GMCH_HDMI_CLK_R2
GMCH_HDMI_CLK
GMCH_HDMI_DATA

(21) GMCH_LCD_CLK
(21) GMCH_LCD_DATA

POWER_SEL

(45) POWER_SEL

(13)

Strap pin

+3VS
2 4.7K_0402_5% GMCH_LCD_CLK
2 4.7K_0402_5% GMCH_LCD_DATA

HIGH

1.0V

LOW

1.1V

UMA@
R451
10K_0402_5%
@

VDDA18PCIEPLL1
VDDA18PCIEPLL2
SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP
HT_REFCLKP
HT_REFCLKN
REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)
GFX_REFCLKP
GFX_REFCLKN
GPP_REFCLKP
GPP_REFCLKN

VDDLTP18(NC)
VSSLTP18(NC)

GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)

B9
A9
B8
A8
B7
A7

I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

A22
B22
A21
B21
B20
A20
A19
B19

GMCH_TXOUT0+ (21)
GMCH_TXOUT0- (21)
GMCH_TXOUT1+ (21)
GMCH_TXOUT1- (21)
GMCH_TXOUT2+ (21)
GMCH_TXOUT2- (21)

B18
A18
A17
B17
D20
D21
D18
D19

VDDLTP18=15mA

B16
A16
D16
D17

GMCH_TXCLK+ (21)
GMCH_TXCLK- (21)

C665
1U_0402_6.3V4Z@
A13
B13

+VDDLTP18

A15
B15
A14
B14

+VDDLT18

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

C14
D15
C16
C18
C20
E20
C22

LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)

E9
F7
G12

MIS.

SUS_STAT#(PWM_GPIO5)

C90
0.1U_0402_16V4Z

L12
1
2
MBK1608221YZF_0603

R744
1

C644
2.2U_0603_6.3V4Z

+VDDLT18
1

L56
2
1
+1.8VS
FBMA-L11-160808-221LMT_0603

VDDLT18=0.3A

R469
4.7K_0402_5%

TMDS_HPD(NC)
HPD(NC)

+VDDLTP18
1

+1.8VS

C95
4.7U_0805_10V4Z

0_0402_5%
2
UMA_ENVDD_R (21)
UMA_VARIBL (21,33)
ENBKL
(33)

D9
D10
D12

THERMALDIODE_P
THERMALDIODE_N

AE8
AD8

TESTMODE

D13

AUX_CAL(NC)

1
2
R106 0_0402_5%

SUS_STAT# (24)
SUS_STAT_R# (13)

Strap pin

1
2
R279
1.8K_0402_5%

RS880M_FCBGA528

POWER_SEL

UMA@
R563 1
R565 1

+3VS

TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

V4
V3

C8

AUX_CAL

TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)

DAC_RSET(PWM_GPIO1)

+VDDA18HTPLL

1
300_0402_5%

CLK_NB_14.318M

DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)

PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)

NB_RESET#
D8
NB_PWRGD_R A10
NB_LDTSTOP#
C10
NB_ALLOW_LDTSTOP C12

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)

PART 3 OF 6

A12
D14
B12

R107
0_0402_5%
1
2
1
2
R511 @
0_0402_5%

(13,14,23,30,31,33) PLT_RST#
(24) NB_PWRGD
+1.8VS

+NB_PLLVDD
+NB_HTPVDD

Y
3

C87
2.2U_0603_6.3V4Z

NB_PWRGD
(6,24,33) SB_PWRGD

2 715_0402_1% G14

+NB_PLLVDD
+NB_HTPVDD

+VDDA18PCIEPLL
L14
2
1
FBMA-L11-160808-221LMT_0603
1
1

R42

+1.8VS
U42
NC7SZ08P5X_NL_SC70-5

VDDA18PCIEPLL=0.12A
+1.8VS

GMCH_CRT_HSYNC A11
GMCH_CRT_VSYNC B11
GMCH_CRT_CLK
F8
GMCH_CRT_DATA E8

(13,22) GMCH_CRT_HSYNC
(13,22) GMCH_CRT_VSYNC
(22) GMCH_CRT_CLK
(22) GMCH_CRT_DATA

C924
1U_0402_6.3V4Z

C934
2.2U_0603_6.3V4Z

GMCH_CRT_G
GMCH_CRT_B

(22) GMCH_CRT_B

L9
2
1
FBMA-L11-160808-221LMT_0603
1
1

U20C
F12
E12
F14
G15
H15
H14

AVDDQ=4mA

L8

C94
2.2U_0603_6.3V4Z

@
1 R441
2
1.27K_0402_1%
@
1 R29
2
1.27K_0402_1%

C663
1U_0402_6.3V4Z

C874
1U_0402_6.3V4Z@
2
+AVDD2
2
1
FBMA-L11-160808-221LMT_0603
1
L10

C645
2.2U_0603_6.3V4Z

AVDDDI=20mA

+1.8VS

CRT/TVOUT

2
1
FBMA-L11-160808-221LMT_0603
1
1

PLL PWR
LVTM

L59

PM

L15
+AVDD1
2
1
FBMA-L11-160808-221LMT_0603
1

+NB_PLLVDD

CLOCKs

+3VS

PLLVDD=65mA
+1.1VS

AVDD=0.11A

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www.diendanlaptop.org

+1.8VS
POWER_SEL
2

R1004
2K_0402_5%

NB_LDTSTOP#

R60
1K_0402_5%

0_0402_5%
1
2
R280

(6,23) LDT_STOP#

(23) ALLOW_LDTSTOP

R59
1

0_0402_5%
2

NB_ALLOW_LDTSTOP

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

RS880 VEDIO/CLK GEN


Size Document Number
Custom
Date:

Rev
1.0

LA-5971P

Thursday, December 10, 2009

Sheet
E

11

of

49

U20F

VDDHTRX+VDDHT=1.3A

1
C50

1
C342

1
C925

2
2
2
2
2
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

+1.8VS

0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE

C45
4.7U_0805_10V4Z

1
C47

1
C40

1
C51

1
C48

2
2
2
2
4.7U_0805_10V4Z 0.1U_0402_16V4Z

1
C345
2
0.1U_0402_16V4Z

VDD18=10mA

F9
G9
AE11
AD11

+1.8VS

C89
1U_0402_6.3V4Z

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)

VDD33_1(NC)
VDD33_2(NC)

+NB_CORE

NB_CORE=10A

1
+
2

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

RS780M_FCBGA528

AE10
AA11
Y11
AD10
AB10
AC10

VDD33=60mA

H11
H12

+3VS
1

RS880M_FCBGA528

330U_D2E_2.5VM

MBK2012221YZF_0805

J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

C27

FOR Version A11 pop 1.35VS A12


use 1.2V_HT
VDDA18PCIE=0.7A
L5

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11

PART 6/6

C338
0.1U_0402_16V4Z

1
C24

U20D

0.1U_0402_16V4Z

PAR 4 OF 6

2
3

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AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)

AD16
AE17
AD17

MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)

SBD_MEM/DVO_I/F

1
C49

C44

1
C31

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

2
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z

C88
C339

C36

MBK2012221YZF_0805

AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17

2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z

1
1

10U_0805_10V4Z

0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX

2 4.7U_0805_10V4Z

1
1

C25

VDDHTTX=0.68A

L4
2

+1.2V_HT

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

C930
C929

10U_0805_10V4Z

2
2
2
2
4.7U_0805_10V4Z 0.1U_0402_16V4Z

H18
G19
F20
E21
D22
B23
A23

C29

0.1U_0402_16V4Z

C931

2 10U_0805_10V4Z
2 10U_0805_10V4Z

C26

C85

1
1

C340

C336

+1.1VS

C30
C28

0.1U_0402_16V4Z

C940

+VDDA11PCIE

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

0.1U_0402_16V4Z

PART 5/6

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

C43

MBK2012221YZF_0805

VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

C337

+VDDHTRX

0.1U_0402_16V4Z

J17
K16
L16
M16
P16
R16
T16

C34

VDDHTRX=0.7A
0.1U_0402_16V4Z

L11
2

L3
1
2
FBMA-L11-201209-221LMA30T_0805

VDDPCIE=2.5A

U20E

2
2
2
0.1U_0402_16V4Z

C23

2
4.7U_0805_10V4Z

1
C928

0.1U_0402_16V4Z

1
C341

0.1U_0402_16V4Z

1
C344

C35

1
C612

0.1U_0402_16V4Z

MBK2012221YZF_0805

VDDHT=0.6A

0.1U_0402_16V4Z

+VDDHT

C343

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

0.1U_0402_16V4Z

L71
2

+1.1VS

POWER

VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27

GROUND

A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25

W12
Y12
AD18
AB13
AB18
V14

MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)

V15
W14

MEM_CKP(NC)
MEM_CKN(NC)

AE12
AD12

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
IOPLLVDD18(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)

MEM_COMPP(NC)
MEM_COMPN(NC)

MEM_VREF(NC)

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

Y17
W18
AD20
AE21
W17
AE19

15mA

AE23
AE24

+1.8VS
+1.1VS

26mA

AD23
AE18

RS780M_FCBGA528

+1.8VS=W/S=20/10mil For Memory PLL power


+1.1VS=W/S=20/10mil For Memory PLL power

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

RS880 PWR/GND
Size Document Number
Custom
Date:

Rev
1.0

LA-5971P

Thursday, December 10, 2009

Sheet
E

12

of

49

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
2
R560
2
R559 @

(11,22) GMCH_CRT_VSYNC
1

1
3K_0402_5%
1
3K_0402_5%

Enables the Test Debug Bus using GPIO. (VSYNC)


1 : Disable (RS880m)
0 : Enable (RS880M)

+3VS

DFT_GPIO1: LOAD_EEPROM_STRAPS
1
2
@ R284
150_0402_1%
D29
@ CH751H-40_SC76
2
1

(11) AUX_CAL

RS780 DFT_GPIO1

(11) SUS_STAT_R#

Selects Loading of STRAPS from EPROM


1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

PLT_RST# (11,14,23,30,31,33)

RS780 use HSYNC to enable SIDE PORT


RS780 use HSYNC to enable SIDE PORT
2
R281
@
2
R282

(11,22) GMCH_CRT_HSYNC

1
3K_0402_5%
1
3K_0402_5%

+3VS

RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)


0.
Enable (RS880M)
1 : Disable(RS880M)

www.diendanlaptop.org
www.diendanlaptop.org

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

RS880 STRAPS
Size Document Number
Custom
Date:

Rev
1.0

LA-5971P

Thursday, December 10, 2009

Sheet
E

13

of

49

(10)
(10)
(10)
(10)

U40A

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0

AF30
AE31

PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1

AE29
AD28

PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2

AD30
AC31

PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3

AC29
AB28

PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6

AA29
Y28
Y30
W31

PCIE_GTX_MRX_P0
PCIE_GTX_MRX_N0

C131
0.1U_0402_10V7K
VGA@
1
2
VGA@
1
2
C102 0.1U_0402_10V7K

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

AG29
AF28

PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N1

C126
0.1U_0402_10V7K
VGA@
1
2
VGA@
1
2
C130 0.1U_0402_10V7K

PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

AF27
AF26

PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N2

C101
0.1U_0402_10V7K
VGA@
1
2
VGA@
1
2
C107 0.1U_0402_10V7K

PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2

PCIE_TX3P
PCIE_TX3N

AD27
AD26

PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N3

C112
0.1U_0402_10V7K
VGA@
1
2
VGA@
1
2
C129 0.1U_0402_10V7K

PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3

PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N

PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7

W29
V28

PCIE_RX7P
PCIE_RX7N

PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8

V30
U31

PCIE_RX8P
PCIE_RX8N

PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9

U29
T28

PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11

AB30
AA31

AH30
AG31

T30
R31
R29
P28

PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N

PCIE_TX4P
PCIE_TX4N

PCI EXPRESS INTERFACE

PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4

PCIE_TX0P
PCIE_TX0N

PCIE_RX0P
PCIE_RX0N

PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N

AC25
AB25

PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N4

Y23
Y24

PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N5

AB27
AB26

PCIE_GTX_MRX_P6
PCIE_GTX_MRX_N6

C124
0.1U_0402_10V7K
VGA@
1
2
VGA@
1
2
C83 0.1U_0402_10V7K

PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4

C123
0.1U_0402_10V7K
VGA@
1
2
VGA@
1
2
C98 0.1U_0402_10V7K

PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5

C103
0.1U_0402_10V7K
VGA@
1
2
VGA@
1
2
C105 0.1U_0402_10V7K

PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6

PCIE_TX7P
PCIE_TX7N

Y27
Y26

PCIE_GTX_MRX_P7
PCIE_GTX_MRX_N7

C110
0.1U_0402_10V7K
VGA@
1
2
VGA@
1
2
C125 0.1U_0402_10V7K

PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7

PCIE_TX8P
PCIE_TX8N

W24
W23

PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N8

C133
0.1U_0402_10V7K
VGA@
1
2
VGA@
1
2
C135 0.1U_0402_10V7K

PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8

PCIE_TX9P
PCIE_TX9N

V27
U26

PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N9

C128
0.1U_0402_10V7K
VGA@
1
2
VGA@
1
2
C132 0.1U_0402_10V7K

PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10

T26
T27

PCIE_GTX_MRX_P11 C127
0.1U_0402_10V7K
VGA@
1
2
PCIE_GTX_MRX_N11
VGA@
1
2
C99 0.1U_0402_10V7K

PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11

PCIE_TX12P
PCIE_TX12N

T24
T23

PCIE_GTX_MRX_P12 C134
0.1U_0402_10V7K
VGA@
1
2
PCIE_GTX_MRX_N12
VGA@
1
2
C104 0.1U_0402_10V7K

PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12

U24
U23

PCIE_TX11P
PCIE_TX11N

PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12

P30
N31

PCIE_RX12P
PCIE_RX12N

PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13

N29
M28

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

P27
P26

PCIE_GTX_MRX_P13 C109
0.1U_0402_10V7K
VGA@
1
2
PCIE_GTX_MRX_N13
VGA@
1
2
C136 0.1U_0402_10V7K

PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13

PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14

M30
L31

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

P24
P23

PCIE_GTX_MRX_P14 C106
0.1U_0402_10V7K
VGA@
1
2
PCIE_GTX_MRX_N14
VGA@
1
2
C111 0.1U_0402_10V7K

PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14

PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

L29
K30

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

M27
N26

PCIE_GTX_MRX_P15 C97
0.1U_0402_10V7K
VGA@
1
2
PCIE_GTX_MRX_N15
VGA@
1
2
C100 0.1U_0402_10V7K

PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

CLOCK
CLK_PCIE_VGA
CLK_PCIE_VGA#

(20) CLK_PCIE_VGA
(20) CLK_PCIE_VGA#

R293
2
A

PLT_RST#

23,30,31,33) PLT_RST#

LVDS CONTROL

VARY_BL
DIGON

VGA@1 R292
2
10K_0402_5%
AB11 VGA@1 R128
2
0_0402_5%
AB12

VGA_VARIBL (21,33)
VGA_ENVDD (21)

VGA@1 R907
2
10K_0402_5%

add at 8/11

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

AH20
AJ19

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

AL21
AK20

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

AH22
AJ21

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

AL23
AK22

TXOUT_U3P
TXOUT_U3N

AK24
AJ23

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

AL15
AK14

VGA_TXCLK+ (21)
VGA_TXCLK- (21)

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

AH16
AJ15

VGA_TXOUT0+ (21)
VGA_TXOUT0- (21)

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

AL17
AK16

VGA_TXOUT1+ (21)
VGA_TXOUT1- (21)

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

AH18
AJ17

VGA_TXOUT2+ (21)
VGA_TXOUT2- (21)

TXOUT_L3P
TXOUT_L3N

AL19
AK18

change at 8/11

M9X-S2/S3 + Park-S3
PARK@

U40

CALIBRATION

N10
AL27

PWRGOOD

PCIE_CALRP

Y22 1.27K_0402_1%
1 VGA@

2R159

PCIE_CALRN

AA22

2K_0402_5%
1 VGA@

2R333

M93-S3
M93@

+VGA_PCIE

www.diendanlaptop.org
www.diendanlaptop.org
Compal Secret Data

Compal Electronics, Inc.

Security Classification

PERSTB

Issued Date

M9X-S2/S3 + Park-S3

2008/10/06

Deciphered Date

2009/10/06

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PARK@

U40F

PCIE_REFCLKP
PCIE_REFCLKN

PARK@
10K_0402_5%
1

1 R127
2
@ 0_0402_5%

(44) VGA_PWROK

AK30
AK32

LVTMDP

PCIE_GTX_MRX_P10 C108
0.1U_0402_10V7K
VGA@
1
2
PCIE_GTX_MRX_N10
VGA@
1
2
C113 0.1U_0402_10V7K

PCIE_TX10P
PCIE_TX10N

PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]

PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]

PARK-S3 PCIE/LVDS
Size
B
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009

Sheet
1

14

of

49

1
2
TX2P_DPA0P
TX2M_DPA0N
TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N

DPB

TX4P_DPB1P
TX4M_DPB1N

AK3
AK1

C1021
2 22P_0402_50V8J

DPC_VDD10#1/DVPDAT15
DPC_VDD10#2/DVPDAT17

DVPDATA_7 / TX0P_DPC2P
DVPDATA_1 / TX0M_DPC2N
DVPCNTL_MV1 / TX1P_DPC1P
DVPDATA_9 / TX1M_DPC1N

DPC_VSSR#1 / DVPCLK
DPC_VSSR#2 / DVPDAT5
DPC_VSSR#3 / GND
DPC_VSSR#4 / GND
DPC_VSSR#5/ DVPCNTL_MV0

DVPDATA_13 / TX2P_DPC0P
DVPCNTL_1 / TX2M_DPC0N
VDDR4 / DPCD_CALR

PCIE TRANSMITTER DE-EMPHASIS ENABLED

C1022
2 22P_0402_50V8J

BIF_GEN2_EN_A

GPIO2

PCIE GNE2 ENABLED

VGA@

AK6
AM5

GPIO8
BIF_VGA DIS

+3VS_VGA

STRAPS

AK8
AL7

GPIO9

GPU_GPIO0
GPU_GPIO1
GPU_GPIO2

R232
@ R228
@ R215

2 VGA@
2
2

1 10K_0402_5%
1 10K_0402_5%
1 10K_0402_5%

GPU_GPIO8
GPU_GPIO9
GPIO21_BBEN

@ R233
@ R231
@ R216

2
2
2

1 10K_0402_5%
1 10K_0402_5%
1 10K_0402_5%

BIOS_ROM_EN
ROMIDCFG(2:0)

W3
V2
Y4
W5
AA3
Y2

GPU_GPIO11
GPU_GPIO12
GPU_GPIO13

R217
@ R236
@ R234

2 VGA@
2
2

1 10K_0402_5%
1 10K_0402_5%
1 10K_0402_5%

VGA_CRT_HSYNC
VGA_CRT_VSYNC
VGA_CRT_VSYNC2
VGA_CRT_HSYNC2
GPU_GPIO8

@ R229
@ R230
@ R235
@ R108

2
2
2
2
2

1
1
1
1
1

R1014

HSYNC

10K_0402_5%

AUD[0]

VSYNC

+VREFG_GPU
VGA@
1

C58

C953

249_0402_1%
VGA@

0.1U_0402_10V6K

1U_0402_6.3V4Z

C952

C951

10U_0603_6.3V6M

VGA@
1

+DPLL_PVDD

AC16

120mA

@
R582 2
1 82.5_0402_1% CLK_XTALIN
XTALOUT_XTL1 R842
CLK_XTALOUT
2
@ 0_0402_5%

XTALOUT_XTL 3

XOUT

VSS
MODOUT

XIN/CLKIN
@

R160
100_0402_1%
@

+3VS_VGA

REFOUT

VDD

AM28
AK28

AC22
AB22

DDC1CLK
DDC1DATA
AUX1P
AUX1N
DDC2CLK
DDC2DATA
AUX2P
AUX2N
DDCCLK_AUX5P
DDCDATA_AUX5N

THERMAL
GPU_THERMAL_D+
GPU_THERMAL_D-

T4
T2

AH12
AM10
AJ9

2
@

VGA@
1

C1042

@
1

0.1U_0402_10V6K

@
1

1U_0402_6.3V4Z

C1041

C949
0.1U_0402_10V6K
C950
1U_0402_6.3V4Z

C1040

R_27M_SSC
R841 2
1
33_0402_1% @

10U_0603_6.3V6M

T69 PAD

L100
2
1
BLM15BD121SN1D_0402
PARK@

C1006

0.1U_0402_10V6K

C1005

+A2VDDQ
PARK@ PARK@ PARK@
1
1
1

VGA_PWRSEL

R302
R305
R294
R299
R298
R483
R341
R342

2@ 10K_0402_5%
2@ 10K_0402_5%
2@ 10K_0402_5%
2@ 10K_0402_5%
2@ 10K_0402_5%
2@ 5.11K_0402_1%
1 4.7K_0402_5%
1 4.7K_0402_5%

GPIO24_TRSTB
GPIO25_TDI
GPIO26_TCK
GPIO27_TMS
GPIO28_TDO
TEST_EN
VGA_LCD_DATA
VGA_LCD_CLK

1
1
1
1
1
1
2 VGA@
2 VGA@

+1.8VS_VGA

1U_0402_6.3V4Z

C999

+VDD1DI
VGA@
1

GPU_GPIO3
GPU_GPIO4

2@ 10K_0402_5%

R315
10K_0402_5%
VGA@
1

VGA@
1

2@ 10K_0402_5%
2@ 10K_0402_5%

R287 1

+3VS_VGA
B

DDC6CLK
DDC6DATA
NC/DDCCLK_AUX3P
NC/DDCDATA_AUX3N

1
VGA_SMB_CK2_R

VGA_SMB_DA2_R

AE19

add at 8/11
AG13

AE6
AE5

Q54A
2N7002DW-T/R7_SOT363-6
VGA@

VGA_SMB_DA2

(33)

VGA@ VGA@ VGA@

VGA Thermal Sensor G781-1P8F

VGA_CRT_CLK
VGA_CRT_DATA

Closed to GPU

VGA_CRT_CLK (22)
VGA_CRT_DATA (22)

www.diendanlaptop.org
www.diendanlaptop.org
add at 8/11

+3VS_VGA

C137

AC11
AC13

AE16
AD16

(33)

Q54B
VGA@
2N7002DW-T/R7_SOT363-6

1 R908
2 VGA@
715_0402_1%

AD2
AD4

AD13
AD11

VGA_SMB_CK2

R308 1
2
150_0402_1%

+A2VDDQ

VGA_CRT_B
R309 1
2
150_0402_1%

2
+A2VDD

VGA_CRT_G

R713
10K_0402_5%
VGA@

1.5mA

R714
10K_0402_5%
VGA@
2

130mA

+VDD2DI
PARK@ PARK@ PARK@
1
1
1

2
1
BLM15BD121SN1D_0402
PARK@

+3VS_VGA

R311 1
2
150_0402_1%

AE17

+1.8VS_VGA

+VDD2DI

0.1U_0402_10V6K

AE20

50mA

C1009

AD19
AC19

L99

1U_0402_6.3V4Z

VGA_CRT_HSYNC2
VGA_CRT_VSYNC2

AL13
AJ13

0.1U_0402_16V4Z
VGA@

1
U26

+VGA_PCIE
L101
2
1
BLM15BD121SN1D_0402
VGA@

AC1
AC3

GPU_THERMAL_D+
VGA@
1

AD20
AC20

DPLUS
DMINUS

+DPLL_VDDC
VGA@
1

VGA@
1

GPU_THERMAL_D-

2
C708VGA@
1
2

2200P_0402_50V7K

VDD1

SCLK

D+

SDATA

D-

ALERT#

THERM#

GND

VGA_SMB_CK2_R

VGA_SMB_DA2_R

6
THM_ALERT#

G780P81U_MSOP8

2
4.7K_0402_5%

VGA@

1
R340

+3VS_VGA

VGA@

+1.8VS_VGA

ASM3P2872AF-06OR_TSOT-23-6

08/11
Spread Spectrum For EMI

VGA@
1

AK10
AL9

M92-S2/M93-S3

DPLL_PVDD
DPLL_PVSS

L97
2
1
BLM15BD121SN1D_0402
VGA@

C1012

+1.8VS_VGA

R303 1
R297 1

0.1U_0402_10V6K

AL11
AJ11

+A2VDD
PARK@ PARK@ PARK@
1
1
1

C1011

AM12
AK12

+AVDD
VGA@
1
0.1U_0402_10V6K

1U_0402_6.3V4Z

+VDD1DI

VGA@
1

C1003

45mA

VGA@
1

C998

+AVDD

2
1
BLM15BD121SN1D_0402
PARK@

+3VS_VGA

L96
2
1
BLM15BD121SN1D_0402
VGA@

VGA_CRT_R
H2SYNC
V2SYNC

VREFG

NC#2/XO_IN
NC#1/XO_IN2

+1.8VS_VGA

+3VS_VGA

L98

0.1U_0402_10V6K

C / NC
Y / NC
COMP / NC

A2VDDQ / NC

XTALIN
XTALOUT

GENERICC

GPIO21_BB_EN
(22)
(22)

DAC2

HPD1

DPLL_VDDC

(22)

VGA_CRT_HSYNC
VGA_CRT_VSYNC

1U_0402_6.3V4Z

AE23
AD23

2 VGA@

VGA_CRT_B

C1002

B2 / NC
B2B / NC

DDC/AUX
AD14

11

PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

C1000

AG24
AE22

1 R482

70mA499_0402_1%

(22)

10U_0603_6.3V6M

AD22

VGA_CRT_G

C1001

G2 / NC
G2B / NC

PLL/CLOCK
AF14
AE14

VGA_CRT_HSYNC
VGA_CRT_VSYNC

AH26
AJ27

(22)

10U_0603_6.3V6M

R2 / NC
R2B / NC

VDD2DI / NC
VSS2DI / NC

1
1

AH24
AG25

VGA_CRT_B

27MCLK_SSIC

VGA_CRT_G

VGA_CRT_R

M92-S2/M93-S3

GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4

M92-S2/M93-S3

+DPLL_PVDD

R332

U46

VDD1DI
VSS1DI

A2VSSQ

300mA
27MCLK_SSIC
1 R843
2
@ 0_0402_5%
(20)
27M_CLK

AVDD
AVSSQ

R2SET / NC

+DPLL_VDDC
CLK_XTALIN

RSET

A2VDD / NC

add at 8/11
VGA@
1

HSYNC
VSYNC

2
499_0402_1%
VGA@

0.1U_0402_10V6K

VGA@
1

B
BB

DAC1

AL25
AJ25

R481

+1.8VS_VGA

+1.8VS_VGA
L83
2
1
BLM15BD121SN1D_0402
VGA@

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
TESTEN

G
GB

VGA_CRT_R

C1008

AC14

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB

AM26
AK26

C1007

AB13
W8
W9
W7
AD10

0
AUD[1] AUD[0]
0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected
1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI

H2SYNC
R
RB

10U_0603_6.3V6M

(16) TEST_EN

L6
L5
L3
L1
K4
AF24

GENERICC

I2C

C1013

GPIO24_TRSTB
GPIO25_TDI
GPIO26_TCK
GPIO27_TMS
GPIO28_TDO
TEST_EN

AUD[1]

0.1U_0402_10V6K

(17) GPIO21_BBEN

IGNORE VIP DEVICE STRAPS

AMD RESERVED CONFIGURATION STRAPS

C1014

(44) VGA_PWRSEL
(20) 27M_SSC

001

V2SYNC

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

1U_0402_6.3V4Z

ACIN

U6
U10
T10
U8
U7
T9
T8
T7
P10
P4
P2
GPU_GPIO11
N6
GPU_GPIO12
N5
GPU_GPIO13
N3
Y9
VGA_PWRSEL
N1
1 R840
2R_27M_SSC M4
THM_ALERT#
@ 0_0402_5%
R6
W10
1 R301
2 @
M2
10K_0402_5%
P8
GPIO21_BBEN
P7
N8
N7

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

R310
150_0402_1%
VGA@

C1015

(25,33,39)

GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
1 R300 @2
GPU_GPIO3
10K_0402_5%
GPU_GPIO4
D4
1
2
@
RB751V_SOD323
VGA_ENBKL
(33) VGA_ENBKL
GPU_GPIO8
GPU_GPIO9

GPIO[13:11]

SCL
SDA

GENERAL PURPOSE I/O

+3VS_VGA

0
ENABLE EXTERNAL BIOS ROM

AA12

10U_0603_6.3V6M

R1
R3

H2SYNC

2
VGA_LCD_CLK
VGA_LCD_DATA

(21) VGA_LCD_CLK
(21) VGA_LCD_DATA

VGA ENABLED

GPIO_22_ROMCSB

VIP_DEVICE_STRAP_ENA

V4
U5

DPC
C

GPIO21

AJ7
AH6

VGA@

EMI request
add at 8/17

AK5
AM3

1U_0402_6.3V4Z

U1
W1
U3
Y6
AA1

GPIO1

VGA@

M92-S2/M93-S3
DVPDATA_3/TXCCP_DPC3P
DVPCNTL_2/TXCCM_DPC3N

TX_DEEMPH_EN

AA5
AA6

DPC_VDD18#1/DVPDAT10
DPC_VDD18#2/DVPDAT23

27MHZ_20P_7A27000010
AH3
AH1

C1004

AC6
AC5

DPC_PVDD / DVPDATA_11
DPC_PVSS / GND

PCIE FULL TX OUTPUT SWING

10U_0603_6.3V6M

W6
V6

RECOMMENDED SETTINGS

GPIO0

C1010

+DPC_PVDD

DESCRIPTION OF DEFAULT SETTINGS

TX_PWRS_ENB

10U_0603_6.3V6M

C55

TX1P_DPA1P
TX1M_DPA1N

PIN

STRAPS

Y6
AG3
AG5

M93-S3/M92-S2

+DPC_PVDD
VGA@
1
20mA

TX0P_DPA2P
TX0M_DPA2N

DPA

TX5P_DPB0P
TX5M_DPB0N

0.1U_0402_10V6K

1U_0402_6.3V4Z

C696

C323

VGA@
1

TXCAP_DPA3P
TXCAM_DPA3N

DVO

+DPC_VDD10
VGA@
1
10U_0603_6.3V6M

L24
2
1
BLM15BD121SN1D_0402
VGA@

DVCNTL_0/ DVPDATA_18
DVCNTL_1 / NC
DVCNTL_2 / TESTEN#2
DVDATA_12 / DVPDATA_16
DVDATA_11 / DVPDATA_20
DVDATA_10 / DVPDATA_22
DVDATA_9 / DVPDATA_12
DVDATA_8 / DVPDATA_14
DVDATA_7 / DVPCNTL_0
DVDATA_6 / DVPDATA_8
DVDATA_5 / DVPDATA_6
DVDATA_4 DVPDATA_4
DVDATA_3 / DVPDATA_19
DVDATA_2 / DVPDATA_21
DVDATA_1 / DVPDATA_2
DVDATA_0 / DVPDATA_0

C57

AE9
L9
N9
AE8
AD9
AC10
AD7
AC8
AC7
AB9
AB8
AB7
AB4
AB2
Y8
Y7

C56

0.1U_0402_10V6K

1U_0402_6.3V4Z

C694

VRAM_ID2
VRAM_ID1
VRAM_ID0

VRAM_ID2
VRAM_ID1
VRAM_ID0

+DPC_VDD18

+1.8VS_VGA

R972
1M_0402_5%
VGA@
CLK_XTALOUT

AF2
AF4

(16)
(16)
(16)
+DPC_VDD10
VGA@
1
200mA

VGA@
1

10U_0603_6.3V6M

C324

VGA@
1

0.1U_0402_10V6K

L23
2
1
BLM15BD121SN1D_0402
VGA@

1U_0402_6.3V4Z

C322

10U_0603_6.3V6M

2
D

+VGA_PCIE

C695

+DPC_VDD18
PARK@ PARK@ PARK@
1
1
1
130mA

2
1
BLM15BD121SN1D_0402
PARK@

+1.8VS_VGA

M93-S3/M92-S2

RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

U40B

L40

CONFIGURATION STRAPS

CLK_XTALIN

R5
AD17
AC17

TS_FDO
TSVDD
TSVSS

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

M9X-S2/S3 + Park-S3

2008/10/06

Deciphered Date

2009/10/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PARK@

Title

PARK-S3 Main Generic/MSIC


Size
C
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009
1

Sheet

15

of

49

+1.8VS_VGA

MVREFDA

R163
100_0402_5%
VGA@

C295
0.1U_0402_16V4Z
VGA@

+1.8VS_VGA

MVREFSA

R166
100_0402_5%
VGA@

R165
100_0402_5%
VGA@

R485

R486

C313
0.1U_0402_16V4Z
VGA@

R312

C311

C312

4.7K_0402_5% 4.7K_0402_5% 240_0402_1%0_0402_5%


M93@

M93@

M93-S3
R330
R130
R312
R331

M93@

M93@

PARK-S3

NC

240

NC

0/short

240

150

NC

240

M93-S3
A

M93@

0_0402_5%

PARK-S3

R485

4.7K

51.1

R486

4.7K

51.1

C311

0/short

0.1uF

C312

0/short

0.1uF
5

K27
J29
H30
H32
G29
F28
F32
F30
C30
F27
A28
C28
E27
G26
D26
F25
A25
C25
E25
D24
E23
F23
D22
F21
E21
D20
F19
A19
D18
F17
A17
C17
E17
D16
F15
A15
D14
F13
A13
C13
E11
A11
C11
F11
A9
C9
F9
D8
E7
A7
C7
F7
A5
E5
C3
E1
G7
G6
G1
G3
J6
J1
J3
J5

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

MVREFDA
MVREFSA

K26
J26

1
1R330
(15)
R130
1
1R312
R331
DRAM_RST
PARK@
PARK@
1R486 51.1_0402_1%
2
1C311
1
2
1
R485 51.1_0402_1%
C312
PARK@
PARK@
+1.8VS_VGA
TEST_EN

PARK@
2
J25
240_0402_1%
2
K7
0_0402_5% PARK@
PARK@J8
2
150_0402_1%
2
K25
240_0402_1%
PARK@
L10
20.1U_0402_16V4Z K8
2
L7
0.1U_0402_16V4Z

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13/BA2
MAA_14/BA0
MAA_15/BA1

K17
J20
H23
G23
G24
H24
J19
K19
J14
K14
J11
J13
H11
G11
J16
L15

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_BA2
M_BA0
M_BA1

DQMA_0
DQMA_1
DQMA_2
DQMA_3
DQMA_4
DQMA_5
DQMA_6
DQMA_7

E32
E30
A21
C21
E13
D12
E3
F4

M_DQM0
M_DQM1
M_DQM2
M_DQM3
M_DQM4
M_DQM5
M_DQM6
M_DQM7

RDQSA_0
RDQSA_1
RDQSA_2
RDQSA_3
RDQSA_4
RDQSA_5
RDQSA_6
RDQSA_7

H28
C27
A23
E19
E15
D10
D6
G5

M_DQS0
M_DQS1
M_DQS2
M_DQS3
M_DQS4
M_DQS5
M_DQS6
M_DQS7

WDQSA_0
WDQSA_1
WDQSA_2
WDQSA_3
WDQSA_4
WDQSA_5
WDQSA_6
WDQSA_7

H27
A27
C23
C19
C15
E9
C5
H4

M_DQS#0
M_DQS#1
M_DQS#2
M_DQS#3
M_DQS#4
M_DQS#5
M_DQS#6
M_DQS#7

ODTA0
ODTA1

L18
K16

M_ODT0
M_ODT1

CLKA0
CLKA0B

H26
H25

M_CLK0
M_CLK#0

CLKA1
CLKA1B

G9
H9

M_CLK1
M_CLK#1

RASA0B
RASA1B

G22
G17

M_RAS#0
M_RAS#1

CASA0B
CASA1B

G19
G16

M_CAS#0
M_CAS#1

CSA0B_0
CSA0B_1

H22
J22

M_CS#0

CSA1B_0
CSA1B_1

G13
K13

M_CS#1

MVREFDA
MVREFSA

CKEA0
CKEA1

K20
J17

M_CKE0
M_CKE1

MEM_CALRN0
NC/TESTEN#2

WEA0B
WEA1B

G25
H10

M_WE#0
M_WE#1

+1.8VS_VGA
R834
R835
R836
R837
R838
R839

M_BA2
M_BA0
M_BA1

(19)
(19)
(19)

1
1
1
1
1
1

2
2
2
2
2
2

MEM_CALRP1/DPC_CALR
MEM_CALRP0

PX_EN

DRAM_RST
CLKTESTA
CLKTESTB

Hynix

G14

RSVD#3

G20

VRAM_ID0

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

Vendor

VRAM_ID0 (15)

VRAM_ID1

VRAM_ID1 (15)

VRAM_ID2

VRAM_ID0

VRAM_ID2 (15)

VRAM_ID1

Samsung K4W1G1646E-HC12

M93-S3

M_ODT0 (19)
M_ODT1 (19)
M_CLK0 (19)
M_CLK#0 (19)
M_CLK1 (19)
M_CLK#1 (19)
M_RAS#0 (19)
M_RAS#1 (19)

R306

NA

10K

R579

0/short

680

R320

2.2K

C287

2.2nF

R579

(19)

M_CS#1

(19)

NA
68pF

C287

M_CAS#0 (19)
M_CAS#1 (19)
M_CS#0

PARK-S3

+VGA_CORE

0_0402_5%
M93@

2200P_0402_50V7K
M93@

R320
2.2K_0402_5%
M93@

M_CKE0 (19)
M_CKE1 (19)

R579
DRAM_RST

M_WE#0 (19)
M_WE#1 (19)

1 PARK@ 2
680_0402_5%
R306
10K_0402_5%
PARK@

DRAM_RST# (19)
1

C287
68P_0402_50V8J
PARK@

M_MA13
A

M9X-S2/S3 + Park-S3
PARK@

www.diendanlaptop.org
www.diendanlaptop.org
Compal Secret Data

Compal Electronics, Inc.

Security Classification
Issued Date

2008/10/06

Deciphered Date

2009/10/06

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

VRAM_ID2

H5TQ1G63BFR-12C

AB16

RSVD#2

H@
S@
S@
H@
@

M_DQS#[7..0]

(19) M_DQS#[7..0]
D

M_DA0
M_DA1
M_DA2
M_DA3
M_DA4
M_DA5
M_DA6
M_DA7
M_DA8
M_DA9
M_DA10
M_DA11
M_DA12
M_DA13
M_DA14
M_DA15
M_DA16
M_DA17
M_DA18
M_DA19
M_DA20
M_DA21
M_DA22
M_DA23
M_DA24
M_DA25
M_DA26
M_DA27
M_DA28
M_DA29
M_DA30
M_DA31
M_DA32
M_DA33
M_DA34
M_DA35
M_DA36
M_DA37
M_DA38
M_DA39
M_DA40
M_DA41
M_DA42
M_DA43
M_DA44
M_DA45
M_DA46
M_DA47
M_DA48
M_DA49
M_DA50
M_DA51
M_DA52
M_DA53
M_DA54
M_DA55
M_DA56
M_DA57
M_DA58
M_DA59
M_DA60
M_DA61
M_DA62
M_DA63

M_DQS[7..0]

(19) M_DQS[7..0]

M_DQM[7..0]

(19) M_DQM[7..0]

M_MA[13..0]

MEMORY INTERFACE

M_DA[63..0]

(19) M_DA[63..0]
(19) M_MA[13..0]

R164
100_0402_5%
VGA@

U40C

PARK-S3 MEM Interface


Size
B
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009

Sheet
1

16

of

49

+1.8VS_VGA

Park-S3: TMDS/DP=110mA@1.0V : LVDS=120mA@1.0V


M9X-S2/S3: TMDS/DP=170mA@1.1V LVDS=100mA@1.1V

L84

C326

DPB_VDD10#1
DPB_VDD10#2

AF23
AG23
AM20
AM22
AM24

DPF_VSSR#1
DPF_VSSR#2
DPF_VSSR#3
DPF_VSSR#4
DPF_VSSR#5

DPB_VSSR#1
DPB_VSSR#2
DPB_VSSR#3
DPB_VSSR#4
DPB_VSSR#5

AF10
AG9
AH8
AM6
AM8

AF17

DPEF_CALR

DPAB_CALR

AE10

@
1

20mA

R844
0_0402_5%
1 VGA@ 2
AG19 DPF_PVDD
1
2
AF20
R845VGA@ 0_0402_5% DPF_PVSS

20mA

20mA

AG8
AG7

DPB_PVDD
DPB_PVSS

AG10
AG11

+DPA_PVDD

C329

+1.8VS_VGA

S
3

1 R168

2
@
100K_0402_5%

+5VS

Q37B
2N7002DW T/R7_SOT-363-6
@

www.diendanlaptop.org
www.diendanlaptop.org
Compal Secret Data

Issued Date

2008/10/06

Deciphered Date

2009/10/06

C91

1U_0402_6.3V4Z

2 R992
1 M93@
0_0402_5%

+DPA_PVDD

+VPB_VDD10

2 R847
1 VGA@
0_0603_5%

+DPA_VDD10

+DPB_VDD18

2 R848
1 PARK@ +DPA_VDD18
0_0603_5%

+DPA_PVDD

2 R849
1 PARK@
0_0402_5%

+DPB_PVDD

2 R850
1 PARK@
0_0402_5%
add

at 8/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R289
10K_0402_5%
@

+DPB_PVDD

Compal Electronics, Inc.

Security Classification

(15) GPIO21_BBEN

L29
2
1
BLM15BD121SN1D_0402
@
1

2
G

2N7002DW T/R7_SOT-363-6

Q7
3 AO3413_SOT23-3
@

0.1U_0402_10V6K

Q37A

0.02A

+DPB_PVDD
@

0_0402_5%

0_0402_5%

2
1
M93@ BLM15BD121SN1D_0402
M93@
1

+1.8VS_VGA

1 VGA@ 2

M93@

+DPE_PVDD

1 @
+BBP

M93@

M9X-S2/S3 + Park-S3
PARK@

R846

+1.8VS_VGA
L27

C59

+DPE_VDD18

DPA_PVDD
DPA_PVSS

0.02A
C405

20mA

add at 8/11

1
@

1U_0402_6.3V4Z

C331

DP PLL POWER

DPE_PVDD
DPE_PVSS

+VGA_CORE

add at 8/11

L28

VGA@1 R313
2
150_0402_1%

C330

AG18
AF19

VGA@
1
10U_0603_6.3V6M

0.1U_0402_10V6K

C65

1U_0402_6.3V4Z

VGA@
1

0.1U_0402_10V6K

VGA@
1

C403

2
1
BLM15BD121SN1D_0402

R131

@
1

VGA@

L26

@
1

2
1
BLM15BD121SN1D_0402
@

1U_0402_6.3V4Z

R314 1
2
150_0402_1%

VGA@

DPF_VDD10#1
DPF_VDD10#2

AF8
AF9

@
1

+VGA_PCIE

PARK-S3 1.0V@110mA
+VPB_VDD10 M93-S3 1.1V@200mA

C61

+DPE_PVDD
+1.8VS_VGA

AF22
AG22

+DPB_VDD18
@
1

C406

DPB_VDD18#1
DPB_VDD18#2

+DPF_VDD10

0.11A

L85
2
1
BLM15BD121SN1D_0402
@

+DPB_VDD18

10U_0603_6.3V6M

DPF_VDD18#1
DPF_VDD18#2

AE13
AF13

C63

C328

AF16
AG17

1U_0402_6.3V4Z

2
C

C62

C401

0.1U_0402_10V6K

1U_0402_6.3V4Z

MBK1608121YZF_0603

0.11A

+DPF_VDD10
VGA@ VGA@

VGA@

10U_0603_6.3V6M

0.1U_0402_10V6K

VGA@

130mA

+DPE_VDD18

L31

C958

AE1
AE3
AG1
AG6
AH5

2
VGA@
MBK1608121YZF_0603 +1.8VS_VGA

VGA@

1U_0402_6.3V4Z

DPA_VSSR#1
DPA_VSSR#2
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5

VGA@

C956

DPE_VSSR#1
DPE_VSSR#2
DPE_VSSR#3
DPE_VSSR#4
DPE_VSSR#5

VGA@

C60

AF6
AF7

C400

DPA_VDD10#1
DPA_VDD10#2

0.1U_0402_10V6K

AG14
AH14
AM14
AM16
AM18

DPE_VDD10#1
DPE_VDD10#2

+VGA_PCIE

L25

0.1U_0402_10V6K

AG20
AG21

PARK-S3 1.0V@110mA
+DPA_VDD10M93-S3 1.1V@200mA 1

C404

0.12A

+DPA_VDD18

AE11
AF11

+DPF_VDD10

+VGA_PCIE

130mA

1U_0402_6.3V4Z

DPA_VDD18#1
DPA_VDD18#2

10U_0603_6.3V6M

C64

DPE_VDD18#1
DPE_VDD18#2

C325

VGA@
1

DP A/B POWER

10U_0603_6.3V6M

1U_0402_6.3V4Z

C327

10U_0603_6.3V6M
C402

VGA@ VGA@
1
1

AG15
AG16

0.1U_0402_10V6K

200mA

10U_0603_6.3V6M

DP E/F POWER

+DPE_VDD18
L30
2
1
BLM15BD121SN1D_0402
VGA@

C954

+1.8VS_VGA

+DPA_VDD18
PARK@PARK@ PARK@
1
1
1
0.1U_0402_10V6K

2
PARK@
MBK1608121YZF_0603

U40G

10U_0603_6.3V6M
C955

10U_0603_6.3V6M
C957

DPE_VDD10
DPF_VDD10

PARK-S3 DPX Power


Size
B
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009

Sheet
1

17

of

49

+1.5VS

2.2A

+1.8VS_VGA

0.4A
10U_0603_6.3V6M

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

10U_0603_6.3V6M

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

M6
N11
N12
N13
N16
N18
N21
P6
P9
R12
R15
R17
R20
T13
T16
T18
T21
T6
U15
U17
U20
U9
V13
V16
V18
Y10
Y15
Y17
Y20

VGA@
1

1U_0402_6.3V4Z

VGA@
1
1U_0402_6.3V4Z

VGA@
1
1U_0402_6.3V4Z

VGA@
1
1U_0402_6.3V4Z

1U_0402_6.3V4Z

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

VGA@
1

MPV18
SPV18

2A(RMS)/3A(Peak)
VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8

M13
M15
M16
M17
M18
M20
M21
N20

+VDDCI
VGA@
1

VGA@ VGA@
1
1

+VGA_CORE

VGA@
1

10U_0603_6.3V6M

PCIE_PVDD

ISOLATED
CORE I/O

1U_0402_6.3V4Z

0.1U_0402_10V6K

1U_0402_6.3V4Z

VSSRHA

1U_0402_6.3V4Z

0.1U_0402_10V6K

1U_0402_6.3V4Z

10U_0603_6.3V6M

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

1U_0402_6.3V4Z

10U_0603_6.3V6M

M11
M12

VGA@
1

0.1U_0402_10V6K

VGA@
1
1U_0402_6.3V4Z

0.1U_0402_10V6K

SPV10

BBP#1
BBP#2

+3VS

Q8
3 AO3413_SOT23-3
VGA@
2

+MPV18
2
G

(31,33,38,41,44,46)

SUSP#

@
0_0402_5%
1
2
VGA@
R339 174K_0402_1%

SUSP#

0.1U_0402_10V6K

C962

C961

1U_0402_6.3V4Z

VLDT_EN# 1

www.diendanlaptop.org
www.diendanlaptop.org

PARK@ PARK@
1
1

VLDT_EN#

VGA@
0_0402_5%

R923
(38)

+SPV18

R211
100K_0402_5%
VGA@
R132

3VS_VGA_EN

C52
1

0.1U_0402_10V6K

1U_0402_6.3V4Z

C960

PARK@ PARK@
1
1

C959

PARK@ L88
1
2
BLM15BD121SN1D_0402

A32
AM1
AM32

PARK@

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

M9X-S2/S3 + Park-S3
PARK@

+3VS_VGA

GND

A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6
T11
R11

M9X-S2/S3 + Park-S3

120mA

+1.8VS_VGA
PARK@ L87
1
2
BLM15BD121SN1D_0402

GND#56
GND#57
GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84

GND#1
GND#2
GND#3 / EVDDQ#2
GND#4
GND#5
GND#6 / EVDDQ#3
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#85
GND#86

SPVSS

1U_0402_6.3V4Z

10U_0603_6.3V6M

VGA@
1

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31

BACK BIAS
+BBP

C68

C416

add at 8/11

VGA@
1

C69

VGA@
1

C422

C333

VGA@
1

C412

H8
J7

PARK@ L38
1
2
BLM15BD121SN1D_0402
L86
1
2
BLM15BD121SN1D_0402
M93@

VGA@
1

C421

100mA

L8
H7

C420

+SPV10

50mA

VGA@
1

C432

+SPV18

VGA@
1

C375

+MPV18

VGA@
1

C595

75mA

VGA@
1

C437

+VGA_PCIE
+VGA_CORE

VGA@
1

C71

VGA@
1

C415

VGA@
1

AM30

VGA@
1

+VGA_CORE

VGA@
1

C591

+PCIE_PVDD
C335

1
2
BLM15BD121SN1D_0402
VGA@

VGA@
1

VDDRHA

PLL

40mA

VGA@
1

C429

M93@

L32

L16

VGA@
1

C599

+1.8VS_VGA

MEM CLK
L17

VGA@
1

C598

0.04A

VGA@
1

C334

1U_0402_6.3V4Z M93@
2
1C407
L33
+VDDRHA
1
2
BLM15BD121SN1D_0402
M93@
R971
0_0402_5%

+1.5VS

NC#3 / VDDR5
TESTEN#2 / VDDR5

VGA@
1

C379

V11
U11

NC#1 / VDDR4
DVCLK / VDDR4

VGA@
1

C373

AA11
Y11

+VGA_CORE

C380

+VDDR

VDDR4#1 / VDDR5
VDDR4#2
VDDR4#3 / VDDR5

C594

9A(RMS)/14A(Peak)
AA15
N15
N17
R13
R16
R18
Y21
T12
T15
T17
T20
U13
U16
U18
V21
V15
V17
V20
Y13
Y16
Y18
R21
U21

C382

V12
Y12
U12

VGA@

C597

C72

VGA@
C428

C370

+VGA_PCIE

C426

VGA@

I/O

AA27
AB24
AB32
AC24
AC26
AC27
AD25
AD32
AE27
AF32
AG27
AH32
K28
K32
L27
M32
N25
N27
P25
P32
R27
T25
T32
U25
U27
V32
W25
W26
W27
Y25
Y32

add at 8/11

VGA@
1

C438

+1.8VS_VGA
C

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

VGA@
1

C427

AA17
AA18
AB17
AB18

VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#20
VDDC#21
VDDC#22
VDDC#23 /BIF_VDDC
VDDC#19/BIF_VDDC
CORE

POWER

M93-S3/M92-S2

VGA@
1

C417

LEVEL
TRANSLATION
VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

+PCIE_VDDC
VGA@
VGA@
1
1

C436

AA20
AA21
AB20
AB21

U40E

2A
L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22

C590

17mA

VGA@
1

C414

VGA@
1

C600

C413

C383

VGA@
1

L93
1
2
MBK1608221YZF_0603
VGA@

VGA@
1

C378

+VDDC_CT
VGA@
1

C435

0.06A

C433

+3VS_VGA

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26

C439

1U_0402_6.3V4Z

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8

C423

10U_0603_6.3V6M

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17

VGA@
1

C377

H13
H16
H19
J10
J23
J24
J9
K10
K23
K24
K9
L11
L12
L13
L20
L21
L22

VGA@
1

C369

C67

C596

C418

C332

add at 8/11

VGA@
1

C371

C381

L94
1
2
VGA@
VGA@
VGA@
BLM15BD121SN1D_0402 VGA@
VGA@
1
1
1
1

0.136A

+1.8VS_VGA

VGA@
1

C372

VGA@
1

+VDDC_CT

VGA@
1

C409

PCIE

C424

C408

MEM I/O

10U_0603_6.3V6M

+1.5VS
D

C434

+PCIE_GDDR
VGA@
VGA@
1
1

U40D

1U_0402_6.3V4Z

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

VGA@
1

C66

VGA@
1

C70

VGA@
1

C74

C73

C374

VGA@ VGA@ VGA@


1
1
1

C376

VGA@
1

C592

VGA@
1

C431

VGA@
1

C410

VGA@
1

C593

C419

C425

C411

C430

VGA@ VGA@ VGA@ VGA@


1
1
1
1

Q36
VGA@
S 2N7002_SOT23

2
G

2
0.1U_0402_25V5K

+VDDR

0.1U_0402_10V6K

1U_0402_6.3V4Z

C997

PARK@ PARK@
1
1

C996

PARK@ L95
1
2
BLM15BD121SN1D_0402

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

add at 8/11

2008/10/06

Deciphered Date

2009/10/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PARK-S3 Power
Size
C
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009
1

Sheet

18

of

49

(16) M_DA[63..0]

M_DQM[7..0]

(16) M_DQM[7..0]

M_DQS[7..0]

(16) M_DQS[7..0]

M_DQS#[7..0]

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

A1
A11
T1
T11

NC
NC
NC
NC

B2
B10
D2
D9
E3
E9
F10
G2
G10

J2
L2
J10
L10

R326
240_0402_1%
VGA@

1
R348
4.99K_0402_1%
VGA@

VGA@
2

C78

ZQ/ZQ0

K2
L3
J4
K4
L4

M_DQS6
M_DQS7

F4
C8

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

M_DQM6
M_DQM7

E8
D4

M_DQS#6
M_DQS#7

G4
B8

DRAM_RST# T3
L9

J2
L2
J10
L10

R328
240_0402_1%
VGA@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

A1
A11
T1
T11

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC
NC
NC
NC

B2
B10
D2
D9
E3
E9
F10
G2
G10

J2
L2
J10
L10

R327
240_0402_1%
VGA@

A1
A11
T1
T11

100-BALL
SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA
H@

+1.5VS

VREFD_Q2
1

VGA@

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

+1.5VS

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

VGA@

NC
NC
NC
NC

B2
B10
D2
D9
E3
E9
F10
G2
G10

R350

R352

4.99K_0402_1%
VGA@

4.99K_0402_1%
VGA@

R353

VGA@

+1.5VS

R359

VREFD_Q3

4.99K_0402_1%
VGA@

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

+1.5VS

VREFC_A3
R358
4.99K_0402_1%
VGA@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

100-BALL
SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA
H@

+1.5VS

R354
4.99K_0402_1%
VGA@

R349
4.99K_0402_1%
VGA@

ODT/ODT0
CS
RAS
CAS
WE

4.99K_0402_1%
VGA@

VREFC_A4
1

R357
4.99K_0402_1%
VGA@

VGA@

VREFD_Q4
1

R344
4.99K_0402_1%
VGA@

VGA@

0.1U_0402_10V6K

RESET

M_ODT1
M_CS#1
M_RAS#1
M_CAS#1
M_WE#1

0.1U_0402_10V6K

C80

DQSL
DQSU

A2
A9
C2
C10
D3
E10
F2
H3
H10

0.1U_0402_10V6K

G4
B8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

0.1U_0402_10V6K

B2
B10
D2
D9
E3
E9
F10
G2
G10

0.1U_0402_10V6K

DML
DMU

L9

VREFC_A2
0.1U_0402_10V6K

VGA@

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

DRAM_RST# T3

R351
4.99K_0402_1%
VGA@

VREFC_A1
R347
4.99K_0402_1%
VGA@

E8
D4

+1.5VS

R345
4.99K_0402_1%
VGA@

0.1U_0402_10V6K

0.1U_0402_10V6K

VGA@

NC
NC
NC
NC

1
2

R355
4.99K_0402_1%
VGA@

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

+1.5VS

VREFD_Q1
R346
4.99K_0402_1%
VGA@

M_DQM4
M_DQM5

100-BALL
SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA
H@

+1.5VS

R356
4.99K_0402_1%
VGA@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

A1
A11
T1
T11

100-BALL
SDRAM DDR3
64MX16 H5TQ1G63BFR-12C FBGA
H@

+1.5VS

F4
C8

M_DQS#4
M_DQS#5

ZQ/ZQ0

M_DQS4
M_DQS5

ODT/ODT0
CS
RAS
CAS
WE

CK
CK
CKE/CKE0

B3
D10
G8
K3
K9
N2
N10
R2
R10

C77

RESET

L9

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

K2
L3
J4
K4
L4

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

DQSL
DQSU

M_ODT1
M_CS#1
M_RAS#1
M_CAS#1
M_WE#1

+1.5VS

BA0
BA1
BA2

G4
B8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

J2
L2
J10
L10

R329
240_0402_1%
VGA@

DML
DMU

DRAM_RST# T3

ZQ/ZQ0

E8
D4

M_DQS#3
M_DQS#1

M_ODT1
M_CS#1
M_RAS#1
M_CAS#1
M_WE#1

J8
K8
K10

M_DA57
M_DA58
M_DA60
M_DA61
M_DA63
M_DA62
M_DA56
M_DA59

D8
C4
C9
C3
A8
A3
B9
A4

RESET

L9

M_DQM3
M_DQM1

(16)
(16)
(16)
(16)
(16)

M_CLK1
M_CLK#1
M_CKE1

+1.5VS

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

M_DA54
M_DA52
M_DA53
M_DA49
M_DA51
M_DA50
M_DA55
M_DA48

E4
F8
F3
F9
H4
H9
G3
H8

T3

(16) DRAM_RST#

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

DQSL
DQSU

A2
A9
C2
C10
D3
E10
F2
H3
H10

M3
N9
M4

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

C75

DQSL
DQSU

F4
C8

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

CK
CK
CKE/CKE0

M_BA0
M_BA1
M_BA2

B3
D10
G8
K3
K9
N2
N10
R2
R10

VREFCA
VREFDQ

G4
B8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M_DQS3
M_DQS1

ODT/ODT0
CS
RAS
CAS
WE

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

DML
DMU

K2
L3
J4
K4
L4

+1.5VS

BA0
BA1
BA2

M_CLK1
J8
M_CLK#1 K8
M_CKE1 K10

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

E8
D4

M_DQS#2
M_DQS#0

M_ODT0
M_CS#0
M_RAS#0
M_CAS#0
M_WE#0

M_CLK1
M_CLK#1
M_CKE1

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13

M_DQM2
M_DQM0

DQSL
DQSU

A2
A9
C2
C10
D3
E10
F2
H3
H10

(16)
(16)
(16)
+1.5VS

M3
N9
M4

M_DA44
M_DA42
M_DA47
M_DA40
M_DA45
M_DA43
M_DA46
M_DA41

M9
H2

F4
C8

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

CK
CK
CKE/CKE0

M_BA0
M_BA1
M_BA2

B3
D10
G8
K3
K9
N2
N10
R2
R10

D8
C4
C9
C3
A8
A3
B9
A4

VREFC_A4
VREFD_Q4

C81

M_DQS2
M_DQS0

ODT/ODT0
CS
RAS
CAS
WE

J8
K8
K10

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

M_DA38
M_DA34
M_DA33
M_DA37
M_DA35
M_DA39
M_DA32
M_DA36

K2
L3
J4
K4
L4

M_CLK0
M_CLK#0
M_CKE0

+1.5VS

+1.5VS

BA0
BA1
BA2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E4
F8
F3
F9
H4
H9
G3
H8

M_ODT0
M_CS#0
M_RAS#0
M_CAS#0
M_WE#0

M3
N9
M4

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

M_ODT0
M_CS#0
M_RAS#0
M_CAS#0
M_WE#0

CK
CK
CKE/CKE0

M_BA0
M_BA1
M_BA2

B3
D10
G8
K3
K9
N2
N10
R2
R10

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13

U24

VREFCA
VREFDQ

(16)
(16)
(16)
(16)
(16)

M_CLK0
J8
M_CLK#0 K8
M_CKE0 K10

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

M_DA14
M_DA10
M_DA15
M_DA11
M_DA12
M_DA8
M_DA13
M_DA9

M9
H2

M_CLK0
M_CLK#0
M_CKE0

+1.5VS

BA0
BA1
BA2

D8
C4
C9
C3
A8
A3
B9
A4

VREFC_A3
VREFD_Q3

(16)
(16)
(16)

M3
N9
M4

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

M_DA25
M_DA27
M_DA24
M_DA31
M_DA26
M_DA30
M_DA28
M_DA29

S@

M_BA0
M_BA1
M_BA2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E4
F8
F3
F9
H4
H9
G3
H8

C79

S@

M_BA0
M_BA1
M_BA2

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

SAMSUNG VRAM SAMSUNG VRAM

(16)
(16)
(16)

M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13

U23

VREFCA
VREFDQ

S@

U24

M_DA0
M_DA4
M_DA1
M_DA6
M_DA3
M_DA7
M_DA2
M_DA5

M9
H2

S@

U23

D8
C4
C9
C3
A8
A3
B9
A4

VREFC_A2
VREFD_Q2

SAMSUNG VRAM SAMSUNG VRAM

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

M_DA16
M_DA23
M_DA19
M_DA21
M_DA17
M_DA18
M_DA22
M_DA20

C76

X76S@

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E4
F8
F3
F9
H4
H9
G3
H8

Samsung

U22

N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
M8

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

X76H@

X76-S
M_MA0
M_MA1
M_MA2
M_MA3
M_MA4
M_MA5
M_MA6
M_MA7
M_MA8
M_MA9
M_MA10
M_MA11
M_MA12
M_MA13

U22

VREFCA
VREFDQ

C82

Hynix

U21

M9
H2

U21
VREFC_A1
VREFD_Q1

(16) M_DQS#[7..0]

ZZZ2

M_MA[13..0]

(16) M_MA[13..0]

M_DA[0..63]

+1.5VS
+1.5VS

+1.5VS

2
2
2
2
2
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z

C54
0.01U_0402_16V7K
VGA@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/10/06

Deciphered Date

2009/10/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PARK-S3 DDR3 VRAM


Size
C
Date:

C678

C605

C677

C603

C679

C680

C608

C685

2
2
2
2
2
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z

C675

1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
1
1
1
1
1
1
1
1
1
1
C684

C602

C607

C686

C681

C384

2
2
2
10U_0603_6.3V6M10U_0603_6.3V6M

C120

2
56_0402_1%

C388

C385
2

C606

M_CLK#11
R575 VGA@
C53
0.01U_0402_16V7K
VGA@

C389

2
10U_0603_6.3V6M

C676

1
A

C387
2

C601

M_CLK#01
2
R489 VGA@ 56_0402_1%

2
56_0402_1%

10U_0603_6.3V6M
VGA@ 1
VGA@ 1

C682

C386
M_CLK1 1
R574 VGA@

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www.diendanlaptop.org

10U_0603_6.3V6M
VGA@ 1
VGA@ 1

C604

M_CLK0 1
2
R576 VGA@ 56_0402_1%

10U_0603_6.3V6M
VGA@ 1
VGA@ 1

1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
1
1
1
1
1
1
1
1
1
1

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009
1

Sheet

19

of

49

+3VS_CLK
L68
1

+3VS

FBMA-L11-201209-221LMA30T_0805

+VDDCLK_IO

+1.2V_HT

C483

C476

0.1U_0402_16V4Z
1
C480

10U_0805_6.3V4Z

2
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1
C479

C526

2
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1
C511

C498

2
0.1U_0402_16V4Z

C477

2
0.1U_0402_16V4Z

remove C508 & C528 at 8/12

C474
1U_0402_6.3V4Z

L66
1

FBMA-L11-201209-221LMA30T_0805

0.1U_0402_16V4Z
1
C471

C909

0.1U_0402_16V4Z
1
C516

C475

0.1U_0402_16V4Z
1
C529

2
2
10U_0805_6.3V4Z

2
0.1U_0402_16V4Z

1U CLOSE PIN 69

C530

2
0.1U_0402_16V4Z

remove C527 at 8/12

L67
1

+3VS

+3VS_CLKVDDA

FBMA-L11-201209-221LMA30T_0805

49
48

100mA
+3VS_CLK
Y1
2

33P_0402_50V8J
2

100mA

33P_0402_50V8J

+3VS_CLK

100mA

R175 8.2K_0402_5%
1
2

Routing the trace at least 10mil

R176 8.2K_0402_5%
1
2

+3VS_CLK

L70
1

Mini Card1

SB_SRC_SLOW#

12
18
28
37
53

VDDSRC_IO
VDDSRC_IO
VDDATIG_IO
VDDSB_SRC_IO
VDDCPU_IO

CPUKG0T_LPRS
CPUKG0C_LPRS

56
55

HTT0T_LPRS / 66 M
HTT0C_LPRS / 66 M

60
59

3
17
29
38
44
54
61
69

VDDDOT
VDDSRC
VDDATIG
VDDSB_SRC
VDDSATA
VDDCPU
VDDHTT
VDD48

51
50

(31) MINI1_CLKREQ#

43
42

CLK_NB_14.318M

For Tigris

27M_SEL

1.1V 158R/90.0R

SEL_SATA
2
1
R185 33_0402_5%
CLK_14.318M
1
2
R201
158_0402_1%

(23) SB710_CLK_14M
(11) CLK_NB_14.318M
1
R187

63
64
65

35
34

ATIG0T_LPRS
ATIG0C_LPRS

33
32

ATIG1T_LPRS
ATIG1C_LPRS

31
30

ATIG2T_LPRS
ATIG2C_LPRS

26
25

CLKREQ0 #
CLKREQ1#
CLKREQ2#
CLKREQ3#

(29) CLK_48M_CR
(24) CLK_48M_USB

1
R676
1
R209

CLK_XTAL_IN

67

CLK_XTAL_OUT

68

REF2/SEL_27

R198
8.2K_0402_5%
1

R200
8.2K_0402_5%
@

SEL_SATA

SRC1T_LPRS
SRC1C_LPRS

REF0/SEL_HTT66

SRC2T_LPRS
SRC2C_LPRS

48MHz_0

SRC3T_LPRS
SRC3C_LPRS

+3VS_CLK

2 0_0402_5%
2 0_0402_5%

CLK_NBGFX (11)
CLK_NBGFX# (11)

NB GFX

R957 1 VGA@ 2 0_0402_5%


R958 1
2 0_0402_5%
VGA@

CLK_PCIE_VGA (14)
CLK_PCIE_VGA# (14)

VGA

23
22

R959 1
R960 1

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_LAN (30)
CLK_PCIE_LAN# (30)

LAN

21
20

R961 1 @
R962 1
@

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_EXP (31)
CLK_PCIE_EXP# (31)

16
15

R963 1
R964 1

2 0_0402_5%
2 0_0402_5%

SRC_SLOW

CLK_PCIE_MINI1 (31)
CLK_PCIE_MINI1# (31)

MiniCard_1

R177
8.2K_0402_5%

NB CLOCK INPUT TABLE


NB CLOCKS

14
13

RS740

SRC5T_LPRS
SRC5C_LPRS
SRC6T/SATAT_LPRS
SRC6C/SATAC_LPRS
SRC7T_LPRS/27MHz_SS
SRC7C_LPRS/27MHz_NS

RS780

HT_REFCLKP
R965 1
R966 1

10
9

2 0_0402_5%
2 0_0402_5%

CLK_SBLINK_BCLK (11)
CLK_SBLINK_BCLK# (11)

8
7
R967 1
R968 1

46
45
5
4

CLK_SRC7T
CLK_SRC7C

2 0_0402_5%
2 0_0402_5%

R210 1 @
R461 1
@

CLK_SBSRC_BCLK (23)
CLK_SBSRC_BCLK# (23)

2 0_0402_5%
2 0_0402_5%

27M_SSC (15)
27M_CLK (15)

NC

100M DIFF
100M DIFF

100M DIFF
100M DIFF

REFCLK_N

14M SE (3.3V)
NC

14M SE (1.8V)
NC

14M SE (1.1V)
vref

GFX_REFCLK

100M DIFF

100M DIFF

100M DIFF(IN/OUT)*

GPP_REFCLK

NC

100M DIFF

NC

100M DIFF

100M DIFF

HT_REFCLKN

NB A LINK

X1
X2

RX780

66M SE(SINGLE END)

SRC4T_LPRS
SRC4C_LPRS

GNDDOT
GNDSRC
GNDSRC
GNDATIG
GNDSB_SRC
GNDSATA
GNDCPU
GNDHTT
GND48
GNDPAD

R178
8.2K_0402_5%

SB RCLK

REFCLK_P

GPPSB_REFCLK 100M DIFF

VGA (Spread spectrum)


VGA (Non spread spectrum)

+3VS_CLK
PD#
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@
57

2
R573
R986 1

1
8.2K_0402_5%
2 0_0402_5%

SLG8SP626VTR_QFN72_10x10
R979
8.2K_0402_5%
@

1st (SILEGO) : SA00001Z310 S IC SLG8SP626VTR QFN 72P CLK GEN


2nd (ICS) : SA000023H10 S IC ICS9LPRS488CKLFT MLF 72P CLK GEN

CPU

CLK_NBHT (11)
CLK_NBHT# (11)

48MHz_1

27M_SEL

R186
8.2K_0402_5%

2 0_0402_5%
2 0_0402_5%

R955 1
R956 1

REF1/SEL_SATA

+3VS_CLK
6
11
19
27
36
47
52
58
72
73

R953 1
R954 1

CLKREQ4#

2
90.9_0402_1%
2 CLK_48MHZ 71
47_0402_5%
2 CLK_48M
70
47_0402_5%

CLK_CPU_BCLK (6)
CLK_CPU_BCLK# (6)

40
39

SB_SRC1T_LPRS
SB_SRC1C_LPRS

SRC0T_LPRS
SRC0C_LPRS

RS780

41

SB_SMBCLK (8,9,24,31)
SB_SMBDATA (8,9,24,31)

SRC_SLOW

SB_SRC0T_LPRS
SB_SRC0C_LPRS

FBMA-L11-160808-601LMT 0603

(31) EXP_CLKREQ#

SB_SMBCLK
SB_SMBDATA

1
2

VDDREF
GNDREF

24

NEW CARD

SMBCLK
SMBDAT

62
66

1
0.1U_0402_16V4Z

+VDDCLK_IO

14.31818MHZ_20P_6X14300202
1
C517

C518

2
C500

ICS 9LPRS488
VDDA
GNDA

100mA

C473
0.1U_0402_16V4Z

CLK_XTAL_IN

U5

C463

10U_0805_6.3V4Z

1
CLK_XTAL_OUT

single-ended 66MHz HTT output

0*

differential 100MHz HTT output

NON SPREAD 100M SATA SRC6 output

0*

SPREAD 100M SATA SRC6 output

1 * NON SPREAD 27M and SPREAD 27M output


27M_SEL
0

differential spread SRC_7 output

* default
5

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

SEL_HTT66

SEL_SATA

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

Clock generator
Size Document Number
Custom
Date:

Rev
1.0

LA-5971P

Thursday, December 10, 2009

Sheet
1

20

of

49

LCD POWER CIRCUIT


+UMA_LCDVDD

+DIS_LCDVDD
+3VS

+3VALW

+3VS

+3VALW

W=60mils

W=60mils

IN

AO3413_SOT23-3
Q34
VGA@
+DIS_LCDVDD

2
2

62K_0402_5%
VGA@

C163
VGA@
4.7U_0805_10V4Z

C160
0.1U_0402_16V4Z
VGA@

W=60mils

Q66
DTC124EKAT146_SC59-3
VGA@

R508
2.7K_0402_5%
UMA@

1
1

VGA@
R695 0_0402_5%
1
2

(14) VGA_ENVDD

Q65
DTC124EKAT146_SC59-3
UMA@

2
1
2
G

OUT

C578
0.1U_0402_16V4Z
UMA@

Q64
2N7002_SOT23
VGA@ S

GND

OUT
IN

GND

2
R701

3
2
2

62K_0402_5%
UMA@

UMA@
R512 0_0402_5%
1
2
1

(11) UMA_ENVDD_R

AO3413_SOT23-3
Q33
UMA@
+UMA_LCDVDD

2
G

R698
100K_0402_5%
VGA@

2
R253

C579
UMA@
4.7U_0805_10V4Z

R252
100K_0402_5%
UMA@

Q63
2N7002_SOT23
UMA@
S

W=60mils
1

R702
150_0603_1%
VGA@

R254
150_0603_1%
UMA@

R699
10K_0402_5%
@

+3VS

R255
10K_0402_5%
UMA@

BKOFF#

BKOFF#

R691
10K_0402_5%
VGA@

D13
RB751V_SOD323

D24
RB751V_SOD323
(33)

+3VS

UMA_DISPOFF#

(33)

UMA@

BKOFF#

VGA_DISPOFF#

VGA@

BKOFF#

1
C1026
1
DAC_BRIG C1027
1
C587
PANEL_PWM
1
C586
UMA_DISPOFF# 1
C588
VGA_DISPOFF# 1
C1023

R996 1

20_0402_5%

CLOSE TO JLVDS1

@
+3VS

2
@
2
@
2

R690
10K_0402_5%
VGA@

220P_0402_50V7K
2

R256
10K_0402_5%
UMA@

220P_0402_50V7K
220P_0402_50V7K

220P_0402_50V7K
2
UMA@ 220P_0402_50V7K
2
VGA@ 220P_0402_50V7K

R995 1

20_0402_5%

CLOSE TO JLVDS2

@
+3VS

A
@

R998 1

UMA_PWM

Y
A
@

VGA_PWM

+UMA_LCDVDD
1
+3VS
C114
C46
UMA@
UMA@
4.7U_0805_10V4Z
0.1U_0402_25V6
(11)
GMCH_TXCLK2
2
(11) GMCH_TXCLK+
(11) GMCH_TXOUT0(11) GMCH_TXOUT0+
(11) GMCH_TXOUT1(11) GMCH_TXOUT1+
(11) GMCH_TXOUT2(11) GMCH_TXOUT2+

700mA

JLVDS1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

+LCDVDD_L

GMCH_TXCLKGMCH_TXCLK+
GMCH_TXOUT0GMCH_TXOUT0+
GMCH_TXOUT1GMCH_TXOUT1+
GMCH_TXOUT2GMCH_TXOUT2+

32

NC7SZ08P5X_NL_SC70-5

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

GNDGND

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

20_0402_5%
VGA@

700mA

FBMA-L11-201209-221LMA30T_0805
L42 1
2
VGA@
(60 MIL)

+UMA_LEDVDD

+DIS_LCDVDD
DAC_BRIG
UMA_PWM
UMA_DISPOFF#

+3VS
DAC_BRIG (33)

1
+3VS
C164
C162
VGA@
VGA@
4.7U_0805_10V4Z
0.1U_0402_25V6
(14)
VGA_TXCLK2
2
(14) VGA_TXCLK+
(14) VGA_TXOUT0(14) VGA_TXOUT0+
(14) VGA_TXOUT1(14) VGA_TXOUT1+
(14) VGA_TXOUT2(14) VGA_TXOUT2+

VGA_TXCLKVGA_TXCLK+
VGA_TXOUT0VGA_TXOUT0+
VGA_TXOUT1VGA_TXOUT1+
VGA_TXOUT2VGA_TXOUT2+

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GMCH_LCD_DATA
GMCH_LCD_CLK

GMCH_LCD_DATA (11)
GMCH_LCD_CLK (11)

31

280mA (60 MIL)

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

GNDGND

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

VGA@

700mA
+DIS_LEDVDD
+3VS
DAC_BRIG (33)

DAC_BRIG
VGA_PWM
VGA_DISPOFF#

VGA_LCD_DATA
VGA_LCD_CLK

VGA_LCD_DATA (15)
VGA_LCD_CLK (15)

31

ACES_87142-3041-BS
ME@

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
UMA@

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

+UMA_LEDVDD

FBMA-L11-201209-221LMA30T_0805
2
1
B+
L17
1
UMA@
C858
4.7U_0805_25V6-K

JLVDS2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32

ACES_87142-3041-BS
ME@

400mA

FBMA-L11-201209-221LMA30T_0805
2
1
B+
L41
1
VGA@
C166
4.7U_0805_25V6-K

R997 1

LCD/PANEL BD. Conn.

20_0402_5%
UMA@

(60 MIL)

+DIS_LEDVDD

U50

NC7SZ08P5X_NL_SC70-5

700mA

FBMA-L11-201209-221LMA30T_0805
L16 1
2
UMA@

(14,33) VGA_VARIBL

P
Y
G

(11,33) UMA_VARIBL

(33) PANEL_PWM

(33) PANEL_PWM

U49

(60 MIL)
B

Title

LVDS Connector
Size
B
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009

Sheet
1

21

of

49

CRT CONNECTOR
+5VS

+R_CRT_VCC
D25

W=40mils

+CRT_VCC

F1

D28
D27
D26
DAN217_SC59 DAN217_SC59 DAN217_SC59
@
@
@

2
1

RB491D_SC59-31.1A_6VDC_FUSE
C622
0.1U_0402_16V4Z

+5VS

JCRT1
CRT_R

(11) GMCH_CRT_G

2 UMA@ 1
R277
0_0402_5%

CRT_G

CRT_R_1

FCM2012C-800_0805
2

CRT_G_1

FCM2012C-800_0805
1
2

CRT_B_1

L54
1
L52

(15) VGA_CRT_G

2 VGA@ 1
R495
0_0402_5%

(15) VGA_CRT_B

2 VGA@ 1
R494
0_0402_5%

UMA@

C640

C662

10P_0402_50V8J

2 VGA@ 1
R493
0_0402_5%

C633

10P_0402_50V8J

(15) VGA_CRT_R

R273

10P_0402_50V8J

DVT

R276

2
1
150_0402_1%

R285

2
1
150_0402_1%

CRT_B

2 UMA@ 1
R274
0_0402_5%

2
1
140_0402_1%

(11) GMCH_CRT_B

1
C948
2

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

DDCDATA
HSYNC

1
C660
2

1
C639
2

+CRT_VCC

10P_0402_50V8J

2 UMA@ 1
R439
0_0402_5%

10P_0402_50V8J

(11) GMCH_CRT_R

FCM2012C-800_0805
1
2

10P_0402_50V8J

L57

VSYNC
DDCCLK

G
G

16
17

ALLTO_C10534-91507-L
ME@

R285
2

150_0402_1%
VGA@

Place closed to chipset

+3VS_VGA

R938
0_0402_5%
VGA@

1
2
C628
0.1U_0402_16V4Z
(11,13) GMCH_CRT_VSYNC

1 UMA@ 2
R513 0_0402_5%

(15) VGA_CRT_VSYNC

1 VGA@ 2
R492 0_0402_5%

DDCDATA

R57

DDCDATA_R

33_0402_5%
DDCCLK

R44

DDCCLK_R

VSYNC_L

U27
SN74AHCT1G125GW_SOT353-5

2 R939
1
VGA@
0_0402_5%

Q57A
2N7002DW-T/R7_SOT363-6
VGA@
3

33_0402_5%
L51
1

R48
10K_0402_5%
VGA@
2

FCM1608C-121T_0603
HSYNC
2

R55
10K_0402_5%
VGA@

U25
SN74AHCT1G125GW_SOT353-5

L50
1

R46
2.2K_0402_5%
2

5
1
P
OE#
G

HSYNC_L

1 VGA@ 2
R490 0_0402_5%

5
1

(15) VGA_CRT_HSYNC

P
OE#

1 UMA@ 2
R491 0_0402_5%

R54
2.2K_0402_5%

1K_0402_5%

(11,13) GMCH_CRT_HSYNC

R775
1

+CRT_VCC
1
2
C351
0.1U_0402_16V4Z

DVT

+CRT_VCC

2 R940

VGA_CRT_CLK (15)

0_0402_5%
VGA@

Q57B
2N7002DW-T/R7_SOT363-6
VGA@

FCM1608C-121T_0603
VSYNC
2

VGA_CRT_DATA (15)

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www.diendanlaptop.org

2 R941
1
UMA@
0_0402_5%

GMCH_CRT_DATA (11)

2 R942
1
0_0402_5%
UMA@

GMCH_CRT_CLK (11)

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

CRT Connector
Size
B
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009

Sheet
E

22

of

49

U30A

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

PCIE_CALRP=W/S=4/8(55ohm impedance), <1"


PCIE_CALRN=W/S=4/8(55ohm impedance), <1"

2
2
2
2
2
2
2
2

0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K

SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C

SB700
A_RST#

Part 1 of 5

V23
V22
V24
V25
U25
U24
T23
T22

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N

U22
U21
U19
V19
R20
R21
R18
R17

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N

R572
562_0402_1% T25
2
1
R173
2.05K_0402_1% T24
2
1
+PCIE_VDDR
L78
PCIE_PVDD=43mA +SB_PCIEVDD
2
1
P24
+1.2V_HT
FBMA-L11-160808-221LMT_0603
1
1
P25
C757
C762
2.2U_0603_6.3V4Z
1U_0402_6.3V4Z
2
2

PCIE_CALRP
PCIE_CALRN
PCIE_PVDD
PCIE_PVSS

U29

P
Y

PLT_RST#

PLT_RST# (11,13,14,30,31,33)

NC7SZ08P5X_NL_SC70-5

(20) CLK_SBSRC_BCLK
(20) CLK_SBSRC_BCLK#

R426
8.2K_0402_5%
@

1
R980@

2
0_0603_5%

N25
N24

PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN

K23
K22

NB_DISP_CLKP
NB_DISP_CLKN

M24
M25

NB_HT_CLKP
NB_HT_CLKN

P17
M18
M23
M22
J19
J18
L20
L19
M19
M20
C853 @ 100P_0402_50V8J @
2
1
2
R470

1
100_0402_5%

N22
P22
L18

(20) SB710_CLK_14M
3

For Tigris

J21

Close to SB
@ R380 20M_0402_5%
1
2

J20

PCI INTERFACE

CPU_HT_CLKP
CPU_HT_CLKN
SLT_GFX_CLKP
SLT_GFX_CLKN
GPP_CLK0P
GPP_CLK0N
GPP_CLK1P
GPP_CLK1N
GPP_CLK2P
GPP_CLK2N

CLOCK GENERATOR

A_RST#

GPP_CLK3P
GPP_CLK3N
25M_48M_66M_OSC
25M_X1

25M_X2

C779
SB_32KHI

X1

OUT

NC

IN

NC

SB_32KHO

B3

X2

32.768KHZ_12.5P_1TJS125BJ4A421P

LPC

SB_32KHO

(11) ALLOW_LDTSTOP
(6,33) H_PROCHOT_R#
(6)
H_PWRGD
(6,11) LDT_STOP#
(6)
LDT_RST#

H_PROCHOT_R#

F23
F24
F22
G25
G24

ALLOW_LDTSTP
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#

INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
SERIRQ
RTCCLK

P4
P3
P1
P2
T4
T3

PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5

N1

PAD

U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2
AA2
AB4
AA1
AB3
AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28

PAD
PAD

H_PWRGD_L (47)

2008/10/06

STRAP PIN

+RTCBATT

2
510_0402_5%

W=20mils
1

1 C794
1U_0402_6.3V4Z

STRAP PIN

for Clear CMOS

J7
JOPEN
@

Compal Electronics, Inc.


2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

level shift to ISL6265


A

RTC_CLK (27)
+RTCBATT

Compal Secret Data

Security Classification
Issued Date

0.1U_0402_16V4Z

C795 1

1
1
FDV301N_NL_SOT23-3

CLK_PCI_DB (31)
CLK_PCI_EC (27,33)
LPCCLK1 (27)

SERIRQ (33)

1
R400

2
22_0402_5%
CLK_PCI_EC
2
0_0402_5%

LPC_AD0 (31,33)
LPC_AD1 (31,33)
LPC_AD2 (31,33)
LPC_AD3 (31,33)
LPC_FRAME# (31,33)

C3
C2
B2

SA000030740 S IC 218-0660017 A14 SB710 FCBGA HF 0FA

Q35

T12
T11

1
R973 @
1
R551

CLK_LPC_EC

G22
E22
H24
H23
J25
J24
H25
H22
AB8
AD7
V15

@
1
2
INTRUDER_ALERT#
R403
1M_0402_5%
www.diendanlaptop.org
VBAT
www.diendanlaptop.org

H_PWRGD

(27)
(27)
(27)
(27)
(27)
(27)

SA00001S570 S IC 218S7EBLA12FG SB700 BGA 528P SB 0FA

R567
4.7K_0402_5%

AD3
AC4
AE2
AE3

218S7EALA11FG_BGA528_SB700

+3VS
+1.8VS
4

(27)
(27)
(27)
(27)

T68

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PAD T10
PAD T9

RTC

12P_0402_50V8J

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/GPIO70
REQ4#/GPIO71
GNT0#
GNT1#
GNT2#
GNT3#/GPIO72
GNT4#/GPIO73
CLKRUN#
LOCK#

CPU

A3

RTC XTAL

R382
20M_0603_5%
C787

SB_32KHI

Y4

15P_0402_50V8J

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5/GPIO41

PCIRST#

0.1U_0402_16V4Z
2

1
1
1
1
1
1
1
1

+3VALW

C798
2

C468
C465
C459
C354
C355
C353
C460
C464

(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)

PCI CLKS

N2

PCI EXPRESS INTERFACE

A_RST#

Title

SB710-PCIE/PCI/ACPI/LPC/RTC
Size Document Number
Custom
Date:

Rev
1.0

LA-5971P

Thursday, December 10, 2009

Sheet
E

23

of

49

U30D

demo circuit LID use RI#

R1005
10K_0402_5%
@

SUS_STAT#

(33)
(33)
(33)
(33)

H_THERMTRIP#
NB_PWRGD
EC_RSMRST#

D3

SUS_STAT#

(31) SB_PCIE_WAKE#
EC_RSMRST#
2
2.2K_0402_5%
GPU_SEL
2
10K_0402_5%

1
R404
1
R1016 @

(6) H_THERMTRIP#
(11) NB_PWRGD
(33) EC_RSMRST#

USBCLK/14M_25M_48M_OSC
USB_RCOMP

USB MISC

2
4.7K_0402_5%

1
R405

+3VS

PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
SB_PWRGD
SUS_STAT#
T14 PAD
T13 PAD
T15 PAD
GATEA20
KB_RST#
EC_SCI#
EC_SMI#

PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S2/GPM9#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST2
TEST1
TEST0
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
WAKE#/GEVENT8#
BLINK/GPM6#
SMBALERT#/THRMTRIP#/GEVENT2#
NB_PWRGD

USB 1.1

(33)
(33)
(33)
(6,11,33)
(11)

E1
E2
H7
F5
G1
H2
H1
K3
H5
H4
H3
Y15
W15
K4
K24
F1
J2
H6
F2
J6
W14

USB_HSD8P
USB_HSD8N

R183 1

2 2.2K_0402_5% SB_SMBCLK

R179 1

2 2.2K_0402_5% SB_SMBDATA

AE18
AD18
GPU_SEL
AA19
W17
V17
W20
W21
(36) SB_SPKR
SB_SMBCLK
AA18
(8,9,20,31) SB_SMBCLK
SB_SMBDATA W18
(8,9,20,31) SB_SMBDATA
K1
SB_SPKR=W/S=4/4(55ohm impedance)
K2
AA20
Y18
C1
Y19
G5

SATA_IS0#/GPIO10
CLK_REQ3#/SATA_IS1#/GPIO6
SMARTVOLT1/SATA_IS2#/GPIO4
CLK_REQ0#/SATA_IS3#/GPIO0
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
SCL1/GPOC2#
SDA1/GPOC3#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
LLB#/GPIO66
SMARTVOLT2/SHUTDOWN#/GPIO5
DDR3_RST#/GEVENT7#

USB_HSD7P
USB_HSD7N

USB 2.0

+3VALW

1
R970
(36) HDA_SYNC_AUDIO

(32)
(32)

10K_0402_5%
2
HDA_BITCLK
2
HDA_SDOUT
2

USB_OC#1
USB_OC#0

USB_OC#1
USB_OC#0

33_0402_5%

HDA_SDIN0

HDA_SYNC

(36) HDA_RST_AUDIO#

R408

33_0402_5%

M1
M2
J7
J8
L8
M3
L6
M4
L5

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO42
AZ_SDIN1/GPIO43
AZ_SDIN2/GPIO44
AZ_SDIN3/GPIO46
AZ_SYNC
AZ_RST#
AZ_DOCK_RST#/GPM8#

AMD (un-used)

2
10K_0402_5%

@
R412

USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GPM5#
USB_OC4#/IR_RX0/GPM4#
USB_OC3#/IR_RX1/GPM3#
USB_OC2#/GPM2#
USB_OC1#/GPM1#
USB_OC0#/GPM0#

(27) HDA_RST#

H19
H20
H21
F25
D22
E24
E25
D23

IMC_GPIO0
IMC_GPIO1
SPI_CS2#/IMC_GPIO2
IDE_RST#/F_RST#/IMC_GPO3
IMC_GPIO4
IMC_GPIO5
IMC_GPIO6
IMC_GPIO7

INTEGRATED uC

STRAP PIN

E11
F11

USB20_P10
USB20_N10

A11
B11

USB20_P9
USB20_N9

C10
D10

USB20_P8
USB20_N8

G11
H12

USB20_P7
USB20_N7

C12
D12

USB_HSD4P
USB_HSD4N

B12
A12

USB_HSD3P
USB_HSD3N

G12
G14

USB20_P3
USB20_N3

USB_HSD2P
USB_HSD2N

H14
H15

USB20_P2
USB20_N2

IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25
IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41

2
R370

H11
J10

USB_HSD5P
USB_HSD5N

IMC_GPIO8
IMC_GPIO9
IMC_PWM0/IMC_GPIO10
SCL2/IMC_GPIO11
SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
IMC_PWM1/IMC_GPIO15
IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17

HDA_RST#

USB_RCOMP 1
11.8K_0402_1%

E12
E14

USB_HSD0P
USB_HSD0N

USB OC

B9
B8
A8
A9
E5
F8
E4

INTEGRATED uC

R969
1
R414
33_0402_5%
1
R416
33_0402_5%
1

(36) HDA_BITCLK_AUDIO
(36) HDA_SDOUT_AUDIO
(36) HDA_SDIN0

USB_OC#6
EC_LID_OUT#

(32)
USB_OC#6
(33) EC_LID_OUT#

CLK_48M_USB (20)

USB_HSD6P
USB_HSD6N

USB_HSD1P
USB_HSD1N

GPU_SEL
2
10K_0402_5%
SB_PCIE_WAKE#
2
10K_0402_5%
EC_LID_OUT#
2
100K_0402_5%

HD AUDIO

1
R1015
@
1
R388
@
1
R379

F7
E8

RSMRST#

GPIO

+3VS

USB_FSD12P
USB_FSD12N

USB_HSD9P
USB_HSD9N

SB700 has internal PD

G8

E6
E7

USB_HSD10P
USB_HSD10N

2 100P_0402_50V8J
1

C8

USB_FSD13P
USB_FSD13N

USB_HSD11P
USB_HSD11N

@
C775 1
2
100_0402_5%

1
R376

Part 4 of 5

SB700

ACPI / WAKE UP EVENTS

+3VALW

USB20_P5
USB20_N5

USB20_P10 (32)
USB20_N10 (32)

USB-10 Int USB

USB20_P9 (31)
USB20_N9 (31)

USB-9 New Card

USB20_P8 (31)
USB20_N8 (31)

USB-8 Bluetooth

USB20_P7 (32)
USB20_N7 (32)

USB-7 USB Camera

USB20_P5 (31)
USB20_N5 (31)

USB-5 MiniCard(WLAN)

USB20_P3 (32)
USB20_N3 (32)

USB-3 Int USB

USB20_P2 (29)
USB20_N2 (29)

USB-2 USB Card reader

USB20_P0 (32)
USB20_N0 (32)

USB-0 Int USB

A13
B13
B14
A14

USB20_P0
USB20_N0

A18
B18
F21
D21
F19
E20
E21
E19
D19
E18

GPIO16 (27)
GPIO17 (27)

STRAP PIN
STRAP PIN

G20
G21
D25
D24
C25
C24
B25
C23

B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18

www.diendanlaptop.org
www.diendanlaptop.org
218S7EALA11FG_BGA528_SB700

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

SB710 USB/HD audio


Size Document Number
Custom
Date:

Rev
1.0

LA-5971P
Sheet

Thursday, December 10, 2009


E

24

of

49

U30B
1

Close chip

C522 1
C519 1

(28) SATA_STX_C_DRX_P1
(28) SATA_STX_C_DRX_N1

ODD

SATA_STX_DRX_P1
SATA_STX_DRX_N1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

(28) SATA_DTX_C_SRX_N1
(28) SATA_DTX_C_SRX_P1

SATA_TX0P
SATA_TX0N

AB10
AC10

SATA_RX0N
SATA_RX0P

AE10
AD10

SATA_TX1P
SATA_TX1N

AD11
AE11

SATA_RX1N
SATA_RX1P

AB12
AC12
AE12
AD12
AD13
AE13
AB14
AC14
AE14
AD14

25MHZ_20PF_7A25000012

DVT
SATA_CAL=W/S=9/20(35ohm impedance), <1"

R371
10M_0402_5%

Y3
2

27P_0402_50V8J

SATA_X1

1 C770
1

1 C772

SATA_CAL
1
1K_0402_1%
SATA_X1

2
R375

SATA_X2

SATA_TX3P
SATA_TX3N
SATA_RX3N
SATA_RX3P
SATA_TX4P
SATA_TX4N
SATA_RX4N
SATA_RX4P
SATA_TX5P
SATA_TX5N

AE16
AD16

SATA_RX5N
SATA_RX5P
SATA_CAL

Y12

SATA_X1

SATA_X2 AA12

SATA_X2

W11

AA11
W12

C783
0.1U_0402_16V4Z

+3VS
L81

XTLVDD_SATA=6mA

2
1
FBMA-L11-160808-221LMT_0603

C777
1U_0402_6.3V4Z
3

+XTLVDD_SATA
2
1

C776
0.1U_0402_16V4Z

SPI_DI/GPIO12
SPI_DO/GPIO11
SPI_CLK/GPIO47
SPI_HOLD#/GPIO31
SPI_CS1#/GPIO32
LAN_RST#/GPIO13
ROM_RST#/GPIO14

PLLVDD_SATA
XTLVDD_SATA

FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52
TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63
TEMPIN3/TALERT#/GPIO64

HW MONITOR

C784
2.2U_0603_6.3V4Z

SATA PWR

+PLLVDD_SATA

PLLVDD_SATA=93mA

AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23

FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49

SATA_ACT#/GPIO67

L82
2
1
FBMA-L11-160808-221LMT_0603

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23
IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

V12

2 10K_0402_5%

+3VS
(35) SATA_LED#

+1.2V_HT

SATA_RX2N
SATA_RX2P

AB16
AC16

27P_0402_50V8J
R377 1

SATA_TX2P
SATA_TX2N

AD15
AE15

IDE_IORDY
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_DACK#
IDE_DRQ
IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#

AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24

Part 2 of 5

ATA 66/100/133

(28) SATA_DTX_C_SRX_N0
(28) SATA_DTX_C_SRX_P0

SB700

AD9
AE9

SPI ROM

(28) SATA_STX_C_DRX_P0
(28) SATA_STX_C_DRX_N0

HDD

SATA_STX_DRX_P0
SATA_STX_DRX_N0

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SERIAL ATA

C504 1
C507 1

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

AVDD
AVSS

SB_SPI_DI
SB_SPI_DO
SB_SPI_CLK
SB_SPI_HOLD#
SB_SPI_CS1#

G6
D2
D1
F4
F3
U15
J1
M8
M5
M7
P5
P8
R8
C6
B6
A6
A5
B5
A4
B4
C4
D4
D5
D6
A7
B7

EC_THERM# (33)
2
D30

1
RB751V_SOD323

R369 2
R374 2

+3VALW

F6

ACIN

1 100K_0402_5%

+3VALW

1 100K_0402_5%

+3VS

(15,33,39)

AVDD=5mA

G7

218S7EALA11FG_BGA528_SB700
C1043 1

+3VALW

Primary master

SATA controler

Port 1

Secondary master

SATA controler

Port 2

Primary slave

SATA controler

Port 3

Secondary slave

SATA controler

Port 4

Primary (Secondary) master

PATA controler

Port 5

Primary (Secondary) slave

PATA controler

2 0.1U_0402_16V4Z

@
+SB_SPI_VCC

+3VALW

1K_0402_5% 1
@
SB_SPI_CS1#
SB_SPI_DI
10K_0402_5%1
@
2 R1006

2 R1013

www.diendanlaptop.org
www.diendanlaptop.org

U51
1
2
3
4

CS#
SO
WP#
GND

VCC
HOLD#
SCLK
SI

8
7
6
5

MX25L1605AM2C-12G_SO8
@

4.7K_0402_5%
1
SB_SPI_CLK
SB_SPI_DO

R1009
22_0402_5%
@
C1044
33P_0402_50V8K

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

@
SB_SPI_HOLD# R1007 2
@
1
2
R1008 0_0402_5%

Port 0

SATA drive controlled by

Port Number

Pri/SEC,Mas/Slave assignment

Title

SB710 SATA/IDE/SPI
Size Document Number
Custom
Date:

Rev
1.0

LA-5971P

Thursday, December 10, 2009

Sheet
E

25

of

49

U30C
+3VS
2
22U_0805_6.3V6M

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

PCIE_VDDR=0.6A

Y20
AA21
AA22
AE25

VDD33_18_1
VDD33_18_2
VDD33_18_3
VDD33_18_4

+PCIE_VDDR

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

AVDD_SATA=567mA

PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7

+1.2V_SATA

1
1
1
1
1

2
2
2
2
2

22U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

AA14
AB18
AA15
AA17
AC18
AD17
AE17

AVDD_SATA_1
AVDD_SATA_4
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7

SATA I/O

MBK2012221YZF_0805

L21
L22
L24
L25

+1.2V_HT

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7

A17
A24
B17
J4
J5
L1
L2

S5_1.2V_1
S5_1.2V_2

G2
G4

S5_3.3V=32mA

+S5_3V

2.2U_0603_6.3V4Z

C769

2.2U_0603_6.3V4Z

C486
+1.2VALW

S5_1.2V=113mA

+S5_1.2V

+1.2VALW
L80
1
2
MBK1608221YZF_0603
C771 1
2 10U_0805_10V4Z

USB_PHY_1.2V_1
USB_PHY_1.2V_2

AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20

A10
B10

10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z

2 0.1U_0402_16V4Z

AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDTX_5
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVDDRX_5

V5_VREF
AVDDCK_3.3V

PLL

A16
B16
C16
D16
D17
E17
F15
F17
F18
G15
G17
G18

USB I/O

C481 1

1 1U_0402_6.3V4Z
1 1U_0402_6.3V4Z

A15
B15
C14
D8
D9
D11
D13
D14
D15
E15
F12
F14
G9
H9
H17
J9
J11
J12
J14
J15
K10
K12
K14
K15

1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24

+AVDD_USB

1
2
2
2
2

C797 2
C796 2

USB_PHY_1.2V=197mA
+1.2_USB

L65
2

MBK2012221YZF_0805
C461 1
C469 1
C495 1
C485 1

T10
U10
U11
U12
V11
V14
W9
Y9
Y11
Y14
Y17
AA9
AB9
AB11
AB13
AB15
AB17
AC8
AD8
AE8

C478
C487
C494
C482

1
1
1
1

+1.2V_CKVDD

C773 2
C774 2

AVDDTX/RX=658mA
+3VALW

2
2
2
2

+3VALW

L79
2

C764
C766
C765
C767
C768

1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

SB700

2
+1.2V_HT
0_0805_5%
C467
2

AVDDCK_1.2V
AVDDC

V5_VREF=1mA

AE7

+V5_VREF

J16

+AVDDCK_3.3V

K17

+AVDDCK_1.2V

E9

+AVDDC

1K_0402_5% 2
1 R386
+5VS
D31
1
2
+3VS
C786
1U_0402_6.3V4Z CH751H-40PT_SOD323-2

AVDDC=17mA

H18
J17
J22
K25
M16
M17
M21
P16

L69
2
1
+3VALW
FBMA-L11-160808-221LMT_0603

218S7EALA11FG_BGA528_SB700

2.2U_0603_6.3V4Z

C484

0.1U_0402_16V4Z

C496

F9

PCIE_CK_VSS_1
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_4
PCIE_CK_VSS_5
PCIE_CK_VSS_6
PCIE_CK_VSS_7
PCIE_CK_VSS_8
AVSSC

GROUND

P18
P19
P20
P21
R22
R24
R25

2 4.7U_0805_10V4Z
2 1U_0402_6.3V4Z

C759 1
C497 1

+1.2V_HT

1
R171
10U_0805_10V4Z

MBK2012221YZF_0805
C466 1
C763 1

CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4

3.3V_S5 I/O

U30E

+1.2V_SB_CORE

POWER

L64
+1.2V_HT

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

L15
M12
M14
N13
P12
P14
R11
R15
T16

VDD=138mA

VDD33=71mA
+3VS

CLKGEN I/O

2
2
2

CORE S5

1
1
1

Part 3 of 5

IDE/FLSH I/O

C489
C499
C493

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12

A-LINK I/O

1
C472
1

VDD=0.51A

SB700
CORE S0

L9
M9
T15
U9
U16
U17
V8
W7
Y6
AA4
AB5
AB21

PCI/GPIO I/O

VDDQ=131mA

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50

PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21

Part 5 of 5

AVSSCK

A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24

P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25
L17

218S7EALA11FG_BGA528_SB700

AVDDCK_1.2V=62mA
+AVDDCK_1.2V

L77
2
1
+1.2V_HT
FBMA-L11-160808-221LMT_0603

2.2U_0603_6.3V4Z

C758

0.1U_0402_16V4Z

C761

AVDDCK_3.3V=47mA

L76

2
1
+3VS
FBMA-L11-160808-221LMT_0603
www.diendanlaptop.org
www.diendanlaptop.org
2.2U_0603_6.3V4Z 2
1 C756
+AVDDCK_3.3V

0.1U_0402_16V4Z

1 C760

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

SB710 power/GND
Size Document Number
Custom
Date:

Rev
1.0

LA-5971P

Thursday, December 10, 2009

Sheet
E

26

of

49

REQUIRED STRAPS

NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

PCI_CLK3

PCI_CLK4

PCI_CLK5

BOOTFAIL
TIMER
ENABLED

USE
DEBUG
STRAPS

RESERVED

RESERVED

LPC_CLK0

CLK_PCI_EC LPC_CLK1
ENABLE PCI
MEM BOOT

CLKGEN
ENABLED

RTC_CLK AZ_RST_CD#
INTERNAL
RTC

EC
ENABLED

DEFAULT

BOOTFAIL
TIMER
DISABLED

IGNORE
DEBUG
STRAPS

DISABLE PCI
MEM BOOT

DEFAULT

DEFAULT

DEFAULT

R411
10K_0402_5%
2
1

+3VALW

R401
10K_0402_5%
2
1

+3VALW

R361
10K_0402_5%
2
1

+3VALW

R453
10K_0402_5%
2
1

+3VALW

R421
10K_0402_5%
2
1

+3VS

DEFAULT

R423
10K_0402_5%
2
1

+3VS

EC
DISABLED

R425
10K_0402_5%
2
1

+3VS

DEFAULT

(23)
PCI_CLK2
(23)
PCI_CLK3
(23)
PCI_CLK4
(23)
PCI_CLK5
(23,33) CLK_PCI_EC
(23)
LPCCLK1
(23)
RTC_CLK
(24)
HDA_RST#
(24)
GPIO17
(24)
GPIO16

H,H = Reserved
1

L,H = LPC ROM (Default L,NC)


L,L = FWH ROM

+3VALW

+3VALW

R366
2.2K_0402_5%
2
1

R410
10K_0402_5%
2
1

R402
2.2K_0402_5%
2
1

R452
10K_0402_5%
2
1

R398
10K_0402_5%
2
1

R454
10K_0402_5%
2
1

R420
10K_0402_5%
2
1

R422
10K_0402_5%
2
1

R424
10K_0402_5%
2
1

GP16

Internal pull up

H,L = SPI ROM

EXT. RTC
(PD on X1,
apply
32KHz to
RTC_CLK)

R427
10K_0402_5%
2
1

+3VS

CLKGEN
DISABLED

GP17

R367
2.2K_0402_5%
2
1

PCI_CLK2

PULL
LOW

R363
2.2K_0402_5%
2
1

PULL
HIGH

R362
2.2K_0402_5%
2
1

DEBUG STRAPS

PULL
LOW

PCI_AD24

PCI_AD23

USE IDE
PLL

USE DEFAULT
PCIE STRAPS

RESERVED

DEFAULT

DEFAULT

DEFAULT

DEFAULT

DEFAULT

USE
SHORT
RESET

BYPASS
PCI PLL

BYPASS
ACPI
BCLK

BYPASS IDE
PLL

USE EEPROM
PCIE STRAPS

R399
2.2K_0402_5%
2
1

R396
2.2K_0402_5%
2
1

PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
R392
2.2K_0402_5%
2
1

(23)
(23)
(23)
(23)
(23)
(23)

PCI_AD25

USE ACPI
BCLK

R389
2.2K_0402_5%
2
1

PCI_AD26

USE PCI
PLL

R395
2.2K_0402_5%
2
1

PCI_AD28
PULL
HIGH

PCI_AD27

USE
LONG
RESET

R393
2.2K_0402_5%
2
1

SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

www.diendanlaptop.org
www.diendanlaptop.org
@

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

SB710 STRAPS
Size Document Number
Custom
Date:

Rev
1.0

LA-5971P

Thursday, December 10, 2009

Sheet
E

27

of

49

SATA ODD Conn.

JSATA1
1
2
3
4
5
6
7

SATA_STX_C_DRX_P1
SATA_STX_C_DRX_N1

(25) SATA_STX_C_DRX_P1
(25) SATA_STX_C_DRX_N1
C513
C510

(25) SATA_DTX_C_SRX_N1
(25) SATA_DTX_C_SRX_P1

SATA_DTX_SRX_N1
SATA_DTX_SRX_P1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

1
1

8
9
10
11
12
13

+5VS

2A
0.1U_0402_16V4Z
1

GND
GND

14
15

DP
+5V
+5V
MD
GND
GND

OCTEK_SLS-13SD1G_NR
ME@

Placea caps. near ODD CONN.

+5VS

GND
A+
AGND
BB+
GND

C491

10U_0805_10V4Z

C492

C505
2

C490

1000P_0402_25V8J

1U_0402_6.3V4Z

SATA HDD Conn.


JSATA2
SATA_STX_C_DRX_P0
SATA_STX_C_DRX_N0

(25) SATA_STX_C_DRX_P0
(25) SATA_STX_C_DRX_N0
C515
C521

(25) SATA_DTX_C_SRX_N0
(25) SATA_DTX_C_SRX_P0

1
1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_SRX_N0
SATA_DTX_SRX_P0

Close conn
+3VS

+5VS

+5VS

10U_0805_10V4Z
0.1U_0402_16V4Z

+3VS
1
1

C556

C554

C557

C555

1A
C552

C792
2

0.1U_0402_16V4Z

1000P_0402_25V8J

C551

1U_0402_6.3V4Z
0.1U_0402_16V4Z

www.diendanlaptop.org
www.diendanlaptop.org

0.1U_0402_16V4Z

1
2
3
4
5
6
7

GND
A+
AGND
BB+
GND

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
VCC12

23
24

G1
G2

OCTEK_SAT-22SB1G_RV
ME@
JALA0
(CL 9.2mm)

for ESD issue

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/10/06

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

HDD & ODD Connector


Size
B

Document Number

Rev
1.0

LA-5971P

Date:

Thursday, December 10, 2009


G

Sheet

28
H

of

49

2 100P_0402_50V8J

@
1 R851

R682

U7
1 6.19K_0402_1%

2
+3VALW
1

400mA

Trace width:20mil

(24)
(24)

REFE

2
3

DM
DP

4
5
6

3V3_IN
CARD_3V3
V18

XD_CD#

XD_CD#

R677 1XD_RDY_SD_WP_MS_CLK
2
0_0402_5%
XD_RE#_MS_INS#
XD_CE#_SD_D1
XD_CLE_SD_D0_MS_D7
XD_ALE_SD_D7_MS_D3

8
9
10
11
12

C752

SP1
SP2
SP3
SP4
SP5

25

C751
10U_0805_10V4Z

C747

XD_RDY_SD_WP_MS_CLK_R

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C746

@
1

22_0402_5%

1
USB20_N2
USB20_P2

USB20_N2
USB20_P2

+VCC_3IN1
1

add at 8/11
EMI reserved
Close to U7 pin24

GPIO0

17

CLK_IN

24

XD_D7

23

SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6

22
21
20
19
18
16
15
14
13

EPAD

C748 1

CLK_48M_CR

C963
2
33P_0402_50V8K

CLK_48M_CR

(20)

XD_D7
XD_D6_MS_BS
XD_D5_SD_D2_MS_D5
XD_D4_SD_D3_MS_D1
XD_D3_SD_D4_MS_D4
XD_D2_SD_CMD
XD_D1_SD_D5_MD_D0
XD_D0_SD_CLK_MS_D2
XD_WP_SD_D6_MS_D6
XD_WE#_SD_CD#

R678
2

XD_D0_SD_CLK_MS_D2_R

0_0402_5%

RTS5138-GR_QFN24_4X4

EMI reserved

Close to JP1

XD_D0_SD_CLK_MS_D2_R

Card reader(XD/SD/MMC/MS/MS-Pro HD SD)

@
R681
10_0402_5%
@
C750
10P_0402_50V8J

XD_RDY_SD_WP_MS_CLK_R

@
R680
10_0402_5%
@
C749
10P_0402_50V8J

7 in 1 Card Reader

+VCC_3IN1

400mA

Trace width:20mil

R679
2

100K_0402_1%
JP2
3

XD-VCC

XD_D0_SD_CLK_MS_D2
XD_D1_SD_D5_MD_D0
XD_D2_SD_CMD
XD_D3_SD_D4_MS_D4
XD_D4_SD_D3_MS_D1
XD_D5_SD_D2_MS_D5
XD_D6_MS_BS
XD_D7

32
10
9
8
7
6
5
4

XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

XD_WE#_SD_CD#
XD_WP_SD_D6_MS_D6
XD_ALE_SD_D7_MS_D3
XD_CD#
XD_RDY_SD_WP_MS_CLK
XD_RE#_MS_INS#
XD_CE#_SD_D1
XD_CLE_SD_D0_MS_D7

34
33
35
40
39
38
37
36

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

11
31

7IN1 GND
7IN1 GND

41
42

7 IN 1 CONN

SD-VCC
MS-VCC

21
28

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
SD-CD-SW

20
14
12
30
29
27
23
18
16
25
1

SD-WP-SW

XD_RDY_SD_WP_MS_CLK

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS

26
17
15
19
24
22
13

XD_RDY_SD_WP_MS_CLK_R
XD_D1_SD_D5_MD_D0
XD_D4_SD_D3_MS_D1
XD_D0_SD_CLK_MS_D2
XD_ALE_SD_D7_MS_D3
XD_RE#_MS_INS#
XD_D6_MS_BS

XD_D0_SD_CLK_MS_D2_R
XD_CLE_SD_D0_MS_D7
XD_CE#_SD_D1
XD_D5_SD_D2_MS_D5
XD_D4_SD_D3_MS_D1
XD_D3_SD_D4_MS_D4
XD_D1_SD_D5_MD_D0
XD_WP_SD_D6_MS_D6
XD_ALE_SD_D7_MS_D3
XD_D2_SD_CMD
XD_WE#_SD_CD#

7IN1 GND
7IN1 GND
TAITW_R015-B10-LM_NR

C745
2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1
C744
2

www.diendanlaptop.org
www.diendanlaptop.org

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

2008/10/06

Deciphered Date

2009/10/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

RTS5138 Card Reader


Size Document Number
Custom
Date:

Rev
1.0

LA-5971P

Thursday, December 10, 2009


E

Sheet

29

of

49

Place Close to LAN chip


+3V_LAN
J4
2

+3VALW

@
1 JOPEN

60mil
1

+3VALW

49.9_0402_1%
2
49.9_0402_1%
2

R480
1
R478
1

49.9_0402_1%
2
49.9_0402_1%
2

8131@ R909
1
8131@ R910
1

49.9_0402_1%
2
49.9_0402_1%
2

8131@ R911
1
8131@ R912
1

49.9_0402_1%
2
49.9_0402_1%
2

MDI0MDI1+

MDI1+AVDD_CEN

+AVDD_CEN
C190
0.1U_0402_16V4Z

AO3414_SOT23-3

Place Close to Pin 2

2
G

C1029
C391
C690
C277
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
2 8131@
2
2
2
1U_0402_6.3V4Z

3 Q5

R479
1
R360
1

MDI0+
L39
+1.8_VDD/LX
1
2
S INDUC_ 4.7UH +-20% SIA4012-4R7M

C390
10U_0805_10V4Z

MDI2+
MDI2-

MDI3+

R337
33K_0402_5%
@

MDI3-

D42
1

2 C181

0.1U_0402_16V4Z

2 C139

0.1U_0402_16V4Z

10/100_LINK_LED

1000_LINK_LED

2 C1016 0.1U_0402_16V4Z

2 C1017 0.1U_0402_16V4Z

8131@

L39 close to U9 pin1, C190 and C390 close to L39

add GIGA LAN resistor at 8/12

+2.5V_VDDH
C689
1U_0402_6.3V4Z

60mil

0.1U_0402_16V4Z

2 EN_WOL
G Q2
2N7002_SOT23
@

EN_WOL

+1.8_VDD/LX

(33)
+3V_LAN

2
C315
2
C314

(10)
(10)
(10)
(10)

+1.2_AVDDL

+AVDD_CEN

0.1U_0402_16V4Z
+2.5V_VDDH

1
0.1U_0402_16V4Z

PLT_RST#

3
7

LAN_WAKE#
C317 1
2 0.1U_0402_10V7K
C316 1
2 0.1U_0402_10V7K

(33) LAN_WAKE#
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P2

85mA

1 R689@ 4.7K_0402_5%
2
+3V_LAN
(11,13,14,23,31,33)
PLT_RST#
R286
10K_0402_5%
1
2
+3V_LAN

PCIE_IRX_C_PTX_N2
PCIE_IRX_C_PTX_P2

LAN_XTALO
LAN_XTALI

R157
1
@

0_0603_5%
2

4
37
38
44
43
9
10
34
35

+AVDDVCO1
1

R158
0_0603_5%

C138
0.1U_0402_16V4Z

31
33

VDDHO/VDD18O/VDD18O

TWSI_DATA
TWSI_CLK
LED_LINK10_100n
LED_ACTn

VDD3V

SPI_CS/LED_DUPLEXn/LED_DUPLEXn
VDD3V/VDDHO/VDDHO
SPI_DI/NC/LED_Link1000n
VDDLO/CTR12/CTR12
REFCLKN
REFCLKP
PERSTn

WAKEn
TX_N
TX_P
RX_N
RX_P

Atheros

AR8121/8131

XTLO
XTLI

AVDDL0
AVDDL1
AVDDL2
DVDDL/AVDDL/AVDDL
AVDDL3
AVDDL4
AVDDL5

TESTMODE
NC

SMCLK
SMDATA

DVDDL0
AVDDL/DVDDL/DVDDL
DVDDL1
SPI_CLK/DVDDL/DVDDL

49

L18

GND
SPI_DO/AVDDH/AVDDH
AVDDH0
AVDDH1

+AVDDVCO2

2
1

0_0603_5%

R323 1

2 2.37K_0402_1%

0.1U_0402_16V4Z
C192

12

TXN0/TXN0/TRXN0
TXP0/TXP0/TRXP0
RXN1/RXN1/TRXN1
RXP1/RXP1/TRXP1
NC/NC/TRXN2
NC/NC/TRXP2
NC/NC/TRXN3
NC/NC/TRXP3

VAUX_AVL/VBG1P18/VBG1P18

C138 close to Pin11 of U9

C689 close to U9 pin15


C189 close to U9 pin19
C845 close to U9 pin25

8131@

U9
C182
@

RBIAS

30
29
48
47

0.1U_0402_16V4Z
1
1
C189
C845
0.1U_0402_16V4Z

10/100_LINK_LED
ACTIVITY#
1 R693
2
4.7K_0402_5%

27
26

1000_LINK_LED

40
41

C8441
C8431

14
13
18
17
21
20
24
23

MDI0MDI0+
MDI1MDI1+
MDI2MDI2+
MDI3MDI3+

+3V_LAN

20.1U_0402_10V7K
20.1U_0402_10V7K

C688, C184 close to U9 pin8


C187 close to U9 pin16
C140 close to U9 pin22
C141 close to U9 pin36
C846 close to U9 pin39

CLK_PCIE_LAN# (20)
CLK_PCIE_LAN (20)

+1.2_AVDDL

0.1U_0402_16V4Z
1

C688
42
39
36
22
16
11
8

+AVDDVCO2
+1.2_AVDDL

46
45
32
28

+1.2_DVDDL

25
19
15

+2.5V_VDDH

C184
2

0.1U_0402_16V4Z0.1U_0402_16V4Z
1

C187
2

1U_0402_6.3V4Z

1
C140

2
0.1U_0402_16V4Z

C141
2

C846
2

2
0.1U_0402_16V4Z

+AVDDVCO1
+1.2_AVDDL

C687 close U9 pin46


C193 close U9 pin45
C183 close U9 pin28
C185 close U9 pin32
+1.2_DVDDL
1
C687
1U_0402_6.3V4Z

0.1U_0402_16V4Z
1
C193

2
0.1U_0402_16V4Z

C183
2

S IC AR8132-AL1E_QFN48P_6X6
8132@

C192 close to Pin11 of U42

LINK_LED

CHP202UPT_SOT323-3

C185
0.1U_0402_16V4Z

If overclocking, R157 , L18 stuffed and R158 removed.


LAN_XTALI

If not overclocking, R158 , L18 suffed and R157 removed.


AR8131:L18=0ohm (more power saving mode)

LAN_XTALO

U9

RJ45 CONN
Y5
1

JRJ45
R335

ACTIVITY#

+AVDD_CEN

C806
27P_0402_50V8J

C805
27P_0402_50V8J

12
510_0402_5%
1

220P_0402_50V7K
C810

MDO3-

MDO3+

MDO1-

MDO2-

MDO2+

MDO1+

MDO0-

MDO0+
510_0402_5%
1

R688
0_0603_5%
2 1U_0603_10V4Z

C191 close to R688


C191 1

Amber LED-

11

add signal at 8/12

5.1K_0402_5%
1

25MHZ_20P

R694

AR8131
8131@

C810 close to U9

2 0.1U_0402_16V4Z
8131@

1
MDI3+

C1018 close to Pin1

TCT1
TD1+

MCT1
1:1

MX1+

24

MCT3

23

MDO3+

R913 2 8131@

1 75_0402_5%
R334
LINK_LED

MDI3C1019 1

2 0.1U_0402_16V4Z
8131@

C1019 close to Pin4

C186 1

MDI2+

MDI2-

2 0.1U_0402_16V4Z

7
MDI1+

C186 close to Pin7

TD1-

MX1-

TCT2
TD2+

MCT2
1:1

MX2+

TD2-

MX2-

TCT3

MCT3

TD3+

1:1

MX3+

22

MDO3-

21

MCT2

20

MDO2+

19

MDO2-

18

MCT1

17

MDO1+

C811
220P_0402_50V7K

1 75_0402_5%

www.diendanlaptop.org
www.diendanlaptop.org

16

15

PR3PR3+
PR2+
PR1SHLD2

14

PR1+

10

Green LED-

SHLD1

13

Green LED+
FOX_JM36113-P2221-7F
ME@

C811 close to JRJ45


RJ45_PR

R581 2

SHLD3

PR2-

+3V_LAN
R914 2 8131@

SHLD4

PR4PR4+

U41
C1018 1

Amber LED+

1 75_0402_5%

1
2
C318
1000P_1206_2KV7K

MDI1C188 1

2 0.1U_0402_16V4Z

9
10

U41

C188 close to Pin10

NS892404
8132@

MDI0+

11

MDI0-

12

TD3-

MX3-

TCT4
TD4+

MCT4
1:1

TD4350uH_NS892406
8131@

MX4+

MX4-

16

MDO1-

15

MCT0

14

MDO0+

13

MDO0-

R580 2

1 75_0402_5%

RJ45_PR

change to GIGA LAN transformer at 8/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/04/16

Deciphered Date

2009/04/16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Atheros AR8132 & LAN CONN


Size
C
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009
D

Sheet

30

of

49

For Wireless LAN

4.7U_0805_10V4Z

WLAN@

C841
0.1U_0402_16V4Z

WLAN@

C813
0.1U_0402_16V4Z

WLAN@

C825
4.7U_0805_10V4Z

C808
0.1U_0402_16V4Z

C823

(35)

BT_LED#

0.1U_0402_16V4Z

+3VS
+3VALW

(33) EC_TX_P80_DATA
(33) EC_RX_P80_CLK

1
2
R709 1 WLAN@ 2 0_0402_5%
R710 1 WLAN@ 2 0_0402_5%
R711 1 @
2 0_0402_5%
0_0402_5%
R712
WLAN@
0_0402_5%
EC_TX_P80_DATA_R
R432 1
2
EC_RX_P80_CLK_R
1
2
R935 0_0402_5%
R936
100K_0402_5%
@

(MINI1_LED#)

1
2
R547 WLAN@ 0_0402_5%

Normal

+3VS

1000

750

+3V

330

250

250 (wake enable)

+1.5VS

500

375

5 (Not wake enable)

+3VS_BT
Q43
30mils
1 AO3413_SOT23-3
BT@
1

R257
100K_0402_1%
BT@
1 R1010 2
100K_0402_1%
BT@

BT_OFF#

WLAN_LED# (35)

IN
BT@

LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
CLK_PCI_DB

R974
R975
R976
R977
R978

1
1
1
1
1

@
@
@
@
@

2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

add at 8/11

change pin define


for new symbol (JP22)
on C test

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

LPC_FRAME# (23,33)
LPC_AD3 (23,33)
LPC_AD2 (23,33)
LPC_AD1 (23,33)
LPC_AD0 (23,33)
CLK_PCI_DB (23)

+3VS

+1.5VS_UMA

C985
@
0.1U_0402_16V4Z

@
C986
0.1U_0402_16V4Z

JEXP1

1
U48
12
14

0_1206_5%
1

R904
+1.5VS_UMA

1.5Vin
1.5Vin

C988
0.1U_0402_16V4Z
2 NEWCARD@

+3VALW

+3VS

(33,38,43) SYSON

(18,33,38,41,44,46) SUSP#

C992
0.1U_0402_16V4Z
2 NEWCARD@

+3VALW

2
4

3.3Vin
3.3Vin

R905 1

PLT_RST#

AUX_IN

SYSON

20

SUSP#

SHDN#

2 @ 100K_0402_5% 10
CPUSB#

3.3Vout
3.3Vout
AUX_OUT

SYSRST#

OC#
PERST#

STBY#

NC

CPPE#

GND

CPUSB#
PAD

18

1.5Vout
1.5Vout

11
13

40mil
+3VS_CARD1

17
(11,13,14,23,30,33) PLT_RST#

+3VALW

+1.5VS_CARD1

NEWCARD@

(8,9,20,24) SB_SMBCLK
(8,9,20,24) SB_SMBDATA
+1.5VS_CARD1

Imax = 0.75A

+3VS

RCLKEN
P2231NL_QFN20

3
5

1
(24) SB_PCIE_WAKE#
+3VALW_CARD1

C987
0.1U_0402_16V4Z
2 NEWCARD@

(20) EXP_CLKREQ#

+3VS_CARD1

40mil

PERST#

NEWCARD@
C990
10U_0805_10V4Z

(10) PCIE_ITX_C_PRX_N4
(10) PCIE_ITX_C_PRX_P4

C991
0.1U_0402_16V4Z
2 NEWCARD@

(10) PCIE_PTX_C_IRX_N4
(10) PCIE_PTX_C_IRX_P4

16
7
21

CPUSB#

(20) CLK_PCIE_EXP#
(20) CLK_PCIE_EXP

Imax = 1.35A
1

19

PERST#

+3VS_CARD1

60mil

+3VALW_CARD1

15

NEWCARD@
C989
10U_0805_10V4Z

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

USB20_N9
USB20_P9
CPUSB#

(24) USB20_N9
(24) USB20_P9

+1.5VS_CARD1

C1045
0.1U_0402_16V4Z
BT@

Q42
DTC124EKAT146_SC59-3

add at 8/11

+1.5VS_UMA

ACES_88231-08001
ME@

C488
0.1U_0402_16V4Z
2
BT@

Normal

Express Card Power Switch

Reserve for SW mini-pcie debug card.


Series resistors closed to KBC side.

1
2
3
4
5
6
7
8
GND1
GND2

(9~16mA)

Auxiliary Power (mA)

Peak

3
(33)

ME@

Primary Power (mA)

R1012
100K_0402_1%
@

USB20_N5 (24)
USB20_P5 (24)

Mini Card Power Rating


Power

WL_OFF# (33)
PLT_RST# (11,13,14,23,30,33)
+3VS
+3VALW

SB_SMBCLK (8,9,20,24)
SB_SMBDATA (8,9,20,24)

TAITW_PFPET0-AFGLBG1ZZ4N0

add at 8/13

+3VS

54

GND

@
@

SB_SMBCLK
SB_SMBDATA

+5VALW +5VS

GND

2 0_0603_5%
2 0_0603_5%

53

WL_OFF#
PLT_RST#
+3V_WLAN
R458 1
R459 1

+1.5VS_UMA

(24) USB20_P8
(24) USB20_N8

OUT

(10) PCIE_ITX_C_PRX_N1
(10) PCIE_ITX_C_PRX_P1

1
LPC_FRAME#_R
JOPEN
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R

BT@

(10) PCIE_PTX_C_IRX_N1
(10) PCIE_PTX_C_IRX_P1

2
J3

GND

0_0402_5%
2 PLT_RST#_R
CLK_PCI_DB

+3VS

PLT_RST#
R983 1

WAKE#
3.3V
NC
GND
NC
1.5V
CLKREQ#
NC
GND
NC
REFCLKNC
REFCLK+
NC
GND
NC
NC
GND
NC
NC
GND
PERST#
PERn0
+3.3Vaux
PERp0
GND
GND
+1.5V
GND
SMB_CLK
PETn0 SMB_DATA
PETp0
GND
GND
USB_DNC
USB_D+
NC
GND
NC
LED_WWAN#
NC
LED_WLAN#
NC
LED_WPAN#
NC
+1.5V
NC
GND
NC
+3.3V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

JP30
1
2
3
4
5
6
7
8
9
10

BTON_LED
WLAN_ACTIVE
BT_ACTIVE
USB20_P8
USB20_N8

(20) CLK_PCIE_MINI1#
(20) CLK_PCIE_MINI1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

@
2 0_0402_5%
2 @ 0_0402_5%
2 @ 0_0402_5%

SB_PCIE_WAKE# R457 1
BT_ACTIVE
R103 1
WLAN_ACTIVE R102 1
(20) MINI1_CLKREQ#

BT MODULE CONN

IN

GND

JP22
(24) SB_PCIE_WAKE#

Q41
DTC124EKAT146_SC59-3

C842

+1.5VS_UMA

OUT

+3VS

27
28

+3VALW_CARD1

Imax = 0.275A

www.diendanlaptop.org
1
1
@
www.diendanlaptop.org
C993
C994
2

NEWCARD@

10U_0805_10V4Z

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND

GND
GND
SANTA_130801-5_RT
ME@

0.1U_0402_16V4Z
2 NEWCARD@

(NEW)

C995
0.1U_0402_16V4Z
2 NEWCARD@

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

MINI CARD/BT/ NEW CARD


Size
B
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009

Sheet
E

31

of

49

CMOS Camera Conn

150mA

+5VS
D

Q48
1 AO3413_SOT23-3
CMOS@

3
1

2
1
OUT
3

GND

IN

(24)

USB20_N0

(24)

USB20_P0

(24)

C550
0.1U_0402_16V4Z

USB20_N0

USB20_P0

USB20_P0_R

USB20_N10

(24)

USB20_P10

USB20_P10 1

USB20_P10_R

(24)

USB20_P3

USB20_P3_R

(24)

USB20_N3

USB20_P3

USB20_N3

CMOS@
1

Q49
DTC124EKAT146_SC59-3
CMOS@

JP31

CMOS@
C553
10U_0805_10V4Z

1
2
3
4
5
6
7

USB20_P0

1
2
3
4
5
GND1
GND2

USB20_N10
USB20_P10
USB20_N3

EMI request
add at 8/14

ACES_88266-05001
ME@

1
L103
L104
1

@2

USB20_P3

USB20_N10_R

USB20_N3_R

3
4WCM-2012-900T_4P
3
@
R944
1
R945
1
R946
1
R947
1
R948
1
R949
1

USB20_N0

@
C1047
0.1U_0402_16V4Z
2 USB20_N7
USB20_P7

USB20_N0_R

WCM-2012-900T_4P
3
4
3

1 1
2
@2
L102
USB20_N10 4 WCM-2012-900T_4P 3
4
3

(33) CMOS_OFF#

R259
100K_0402_5%
R1011
CMOS@
1
2
100K_0402_5%
CMOS@
1
CMOS@
C1046
0.1U_0402_16V4Z
2
(24)
USB20_N7
(24)
USB20_P7

0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2

USB20_N0_R
USB20_P0_R
USB20_N10_R
USB20_P10_R
USB20_N3_R
USB20_P3_R

JUSB3
8
7
6
5
4
3
2
1

+USB_VCCC
USB20_P3_R
USB20_N3_R

GND
GND
GND
GND
4
3
2
1
SUYIN_020173MR004S558ZL
ME@

+5VALW
D43
+USB_VCCC

C501 0.1U_0402_16V4Z
2
1
USB_ON#

(33)

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

8
7
6
5

1
+

C503
150U_B2_6.3VM_R35M

USB_OC#1 (24)

USB20_P3_R

1
PJDLC05_SOT23-3
@

+USB_VCCA

C545
470P_0402_50V7K
2 @

APL3510BKI-TRGSO8

EMI request
add at 8/14

U43
1
2
3
4

USB20_N3_R

+USB_VCCA

W=80mils

W=80mils

C502
@ 1000P_0402_25V8J

2
2

C947

C946
2

470P_0402_50V7K

470P_0402_50V7K

+5VALW
JUSB2
JUSB1

+USB_VCCA
USB20_N0_R
USB20_P0_R

U45
C546 0.1U_0402_16V4Z
2
1
USB_ON#

(33)

1
2
3
4

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

1
2
3
4

8
7
6
5

1
+
USB_OC#6 (24)

APL3510BKI-TRGSO8

USB_OC#0 (24) 2
1

C549
www.diendanlaptop.org
5 GND1
470P_0402_50V7K
6 GND2
www.diendanlaptop.org
2
7

5
6
7
8

C548
150U_B2_6.3VM_R35M

8
@

C547
@ 1000P_0402_25V8J

GND3
GND4

SUYIN_020173MR004G579ZR
ME@
D44

USB20_N0_R

USB20_P0_R

EMI request
add at 8/14

2008/10/06

Issued Date

GND1
GND2
GND3
GND4

USB20_P10_R

PJDLC05_SOT23-3
@

Compal Electronics, Inc.


2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

EMI request
add at 8/14

PJDLC05_SOT23-3
@

VCC
DD+
GND

SUYIN_020173MR004G579ZR
ME@
D45
USB20_N10_R

Compal Secret Data

Security Classification

1
2
3
4

USB20_N10_R
USB20_P10_R

VCC
DD+
GND

Title

BlueTooth / Int USB x2 /eSATA


Size
B
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009

Sheet
E

32

of

49

+3VALW

+3VALW

+EC_AVCC

+3VS
2

1
C731
0.1U_0402_16V4Z

1
C733
0.1U_0402_16V4Z

1
C732
0.1U_0402_16V4Z

1
C730
0.1U_0402_16V4Z

1
C734
1000P_0402_25V8J

C735
1000P_0402_25V8J

U6
R700
10K_0402_5%

AVCC

R595
10K_0402_5%

VCC
VCC
VCC
VCC
VCC
VCC

@
@

67

9
22
33
96
111
125

+3VS

2
R591
100K_0402_5%
2

(24) EC_SCI#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

KSO[0..15]

KSO1
(34)
KSO2

KSO[0..15]
KSI[0..7]

(34)

KSI[0..7]

LID_SW#

2
4.7K_0402_5%
Ver02:add pull high resister
EC_SMB_CK1
2
4.7K_0402_5%
EC_SMB_DA1
2
4.7K_0402_5%

1
R610
1
R607
+3VS

EC_SMB_CK2
4.7K_0402_5%
EC_SMB_DA2
4.7K_0402_5%
FAN_SPEED1
2
10K_0402_5%
SSD_DET#
2
10K_0402_5%
MUTE_BTN#
2
10K_0402_5%
VOLUME_UP#
2
10K_0402_5%
VOLUME_DOWN#
2
10K_0402_5%
DGPU_BTN#
2
10K_0402_5%

R596
R600
1
R592
1
R928
1
R929
1
R930
1
R931
1
R932

(40)
(40)
(6)
(6)

(24) PM_SLP_S3#
(24) PM_SLP_S5#
(24)
EC_SMI#

EC_SEL
2
10K_0402_5%
@

(31) EC_TX_P80_DATA
(31) EC_RX_P80_CLK
(35)
ON/OFF#
(6,23) H_PROCHOT_R#
(35) NUM_LED#

2
0_0402_5%

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

77
78
79
80

@ 1
R987

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

XCLKI
XCLKO

122
123

EC_SMI#
VOLUME_UP#
VOLUME_DOWN#
EC_SEL
VGATE
PANEL_PWM
FAN_SPEED1
DGPU_BTN#
EC_TX_P80_DATA
EC_RX_P80_CLK

(21) PANEL_PWM
(37) FAN_SPEED1

add at 8/13
1
R1001

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PS2 Interface

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

SPI Flash ROM

GPIO
SM Bus

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

GPI

1
R933
1
R934
1
R1002

2
10K_0402_5%

X1
32.768K_1TJS125BJ4A421P

11
24
35
94
113

C740
27P_0402_50V8J

DAC_BRIG (21)
EN_FAN1 (37)
IREF
(41)
CHGVADJ (41)

R594
10K_0402_5%

EC_MUTE# (36)

USB_ON#

WL_OFF#

119
120
126
128

FRD#SPI_SO
FWR#SPI_SI
SPI_CLK_R
FSEL#SPICS#

100
101
102
103
104
105
106
107
108
110
112
114
115
116
117
118

BATT_TEMP

TP_CLK (34)
TP_DATA (34)

97
98
99
109

73
74
89
90
91
92
93
95
121
127

BATT_OVP

USB_ON# (32)
05/25

TP_CLK
TP_DATA

LID_SW#

1
2
R1000 @
0_0402_5%
CHARGE_LED0#
CAPS_LED#
CHARGE_LED1#
2 VR_ON
0_0402_5%

VGA_VARIBL (14,21)

SB_PWRGD_EC

UMA_VARIBL (11,21)
FSTCHG (41)
CHARGE_LED0# (35)
CAPS_LED# (35)
CHARGE_LED1# (35)
PWR_LED_SC# (35)
SYSON (31,38,43)
VR_ON (47)
ACIN
(15,25,39)

BKOFF# (21)
BT_OFF# (31)

RB751V_SOD323
1
2

SB_PWRGD

SB_PWRGD (6,11,24)

@
1
R609

ENBKL_R
1 UMA@ 2
R984
0_0402_5%
EC_THERM#
SUSP#
PBTN_OUT#
EC_PME#

2
0_0402_5%

@
+3VS
R599
2.2K_0402_5%
Ver02 :change from 4.7K to 2.2K

VLDT_EN (38,44,45,46)
ENBKL (11)
EAPD
(36)
EC_THERM# (25)
SUSP#
(18,31,38,41,44,46)
PBTN_OUT# (24)

20mil

AGND

(47)

EC_SEL

VGATE

VGATE

1
D7

(42,43)

SPOK

2
100P_0402_50V8J

SPI_CLK (34)

D8

MUTE_BTN#

1
C736

C739
10P_0402_50V8J

EC_RSMRST# (24)
EC_LID_OUT# (24)
EC_ON
(35)
CMOS_OFF# (32)

EC_LID_OUT#
EC_ON

124

2
100P_0402_50V8J
2
100P_0402_50V8J

close to EC pin126 for RF request


FRD#SPI_SO (34)
FWR#SPI_SI (34)
SPI_CLK
1
2
R602
FBMA-10-100505-101T_0402
1
FSEL#SPICS# (34)

R9991 @
20_0402_5%
SSD_DET#

SYSON
1
R988

ACIN

1
C737
1
C738

WL_OFF# (31)
EN_WOL (30)
BATT_SEL_EC (41)
LID_SW# (34)

+3VS
ENBKL_R 1 VGA@ 2
R985
0_0402_5%

VGA_ENBKL (15)

C743
4.7U_0805_10V4Z

R990
10K_0402_5%
@

G3 state ICH_POK
www.diendanlaptop.org
www.diendanlaptop.org
D6
@ CH751H-40PT_SOD323-2

VOUTX
VOUTY

83
84
85
86
87
88

69

GND
GND
GND
GND
GND
2

C741
27P_0402_50V8J

KSO3

KSO2

SUSP#

1
R989
@

2
10K_0402_5%

SB_PWRGD
SB_PWRGD (6,11,24)

2
G

Q62
2N7002_SOT23
@

@ CH751H-40PT_SOD323-2
2

VR_ON

C1030
0.1U_0402_16V4Z
2 @

05/25

add at 8/13

C728
0.1U_0402_16V4Z

ECAGND
2
FCM1608CF-121T03_2P

1
L20

ECAGND

R697

IN

@
1

1
OUT

@
1

R696

NC

R589

KB926QFE0_LQFP128
SYSON

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
V18R

SUSP#

NC

2
100K_0402_5%
2
100K_0402_5%
2
100K_0402_5%
2
100K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

XCLK1
XCLK0

TP_DATA

1
R590

TP_CLK

2
4.7K_0402_5%
2
4.7K_0402_5%

DAC_BRIG
EN_FAN1
IREF

SPI Device Interface

+5VS
1
R605
1
R604

68
70
71
72

BATT_TEMP (40)
BATT_OVP (41)
ADP_I
(41)

VOUTX
VOUTY

+EC_AVCC
2

+3VALW
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

DA Output

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

BATT_TEMP
BATT_OVP

2
FCM1608CF-121T03_2P

R991
100K_0402_5%
@
2

1
R608
+5VALW

AD

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

C729
0.1U_0402_16V4Z

+3VALW
2
47K_0402_5%
2
47K_0402_5%

12
13
37
20
38

EC_RST#
EC_SCI#

63
64
65
66
75
76

1
L19

+3VALW

2
47K_0402_5%

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

ACOFF

1
R613

+3VALW

PWM Output

KILL_SW# (34)
BEEP#
(36)
NOVO#
(35)
ACOFF
(39,41)

BEEP#

13,14,23,30,31) PLT_RST#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

21
23
26
27

2
1
2
R603@
33_0402_5%
@
22P_0402_50V8J
ver 01:for EMC request

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

1
C742

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

(23)
SERIRQ
(23,31) LPC_FRAME#
(23,31) LPC_AD3
(23,31) LPC_AD2
(23,31) LPC_AD1
(23,31) LPC_AD0

(23,27) CLK_PCI_EC

1
R611
1
R612

1
2
3
4
5
7
8
10

GATEA20

KB_RST#

(24)
(24)

(15) VGA_SMB_DA2

2 VGA@ 1
0_0402_5%
R993
2 VGA@ 1
0_0402_5%
R994

EC_SMB_CK2
EC_SMB_DA2

R593
10K_0402_5%
@

CLOSE TO U6

Compal Secret Data

Security Classification
Issued Date

2009/04/23

Deciphered Date

2009/05

Title

(30) LAN_WAKE#

1
R587

2
0_0402_5%

EC_PME#

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.


BIOS & EC I/O Port

(15) VGA_SMB_CK2

+3VALW

Size Document Number


Custom
Date:

Thursday, December 10, 2009

Rev
1.0
Sheet

33

of

49

11mA

+5VS

BIOS(SYS / EC / VGA)
(33)
(33)
U52
FSEL#SPICS#
FRD#SPI_SO
SPI_WP#

1
2
3
4

CS#
DO
WP#
GND

VCC
HOLD#
CLK
DIO

8
7
6
5

JP27
1
2
3
4
5
6
7
8

TP_CLK
TP_DATA
SW/L
SW/R

TP_CLK
TP_DATA

SPI_HOLD#
SPI_CLK_R
FWR#SPI_SI

ACES_85201-06051
ME@

MX25L2005CMI-12G SOP
@
+5VS
C512 1

+3VALW

1
2
3
4
5
6
GND
GND

2 0.1U_0402_16V4Z

TP_DATA C560 1

2 @ 100P_0402_50V8J

TP_CLK

2 @ 100P_0402_50V8J

C558 1

C559
+SPI_VCC
0.1U_0402_16V4Z
U38
(33) FRD#SPI_SO
R207 1

+3VALW

1
2
3
4

2 4.7K_0402_5% SPI_WP#

CS#
SO
WP#
GND

VCC
HOLD#
SCLK
SI

8
7
6
5

SPI_HOLD#
4.7K_0402_5% 2
1 R204
SPI_CLK_R
1
2
R208 0_0402_5%

SPI_CLK (33)
FWR#SPI_SI (33)

TP_CLK

TP_DATA

MX25L1605AM2C-12G_SO8

FSEL#SPICS#

(33) FSEL#SPICS#

D40
PJDLC05_SOT23-3
@

R206
22_0402_5%
@

C524
33P_0402_50V8K

SW/L

INT_KBD Conn.

6
5

6
5

SW/R

SW3
EVQPLHA15_4P

3
SW2
EVQPLHA15_4P

JP26
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND2
GND1

KSI[0..7]

KSI[0..7]

KSO[0..15]

(33)

KSO[0..15] (33)

Kill Switch
SW4
2
R18

+3VALW
(33)

26
25

1
100K_0402_5%

3
2

KILL_SW#

KILL_SW#
1

E-T_6905-E24N-01R
ME@

C446 1

KSO12

C445 1

KSI0

C451 1

KSO11

C444 1

KSO10

C443 1

KSI1

C452 1

KSI2

C453 1

KSO9

C442 1

KSI3

C454 1

KSO8

C441 1

2
@
2
@
2
@
2
@

100P_0402_50V8J

KSO7

C440 1

100P_0402_50V8J

KSO6

C907 1

100P_0402_50V8J

KSO5

C905 1

100P_0402_50V8J

KSO4

C906 1

2
@
2
@
2
@
2
@

100P_0402_50V8J

KSO3

C903 1

100P_0402_50V8J

KSI4

C455 1

100P_0402_50V8J

KSO2

C904 1

100P_0402_50V8J

KSO1

C902 1

2
@
2
@
2
@
2
@

100P_0402_50V8J

KSO0

C901 1

100P_0402_50V8J

KSI5

C456 1

100P_0402_50V8J

KSI6

C457 1

100P_0402_50V8J

KSI7

C458 1

2
@
2
@
2
@
2
@

100P_0402_50V8J

2
@
2
@
2
@
2
@

100P_0402_50V8J

2
@
2
@
2
@
2
@

100P_0402_50V8J

100P_0402_50V8J
100P_0402_50V8J

Lid Switch

100P_0402_50V8J

100P_0402_50V8J
+3VALW

100P_0402_50V8J
100P_0402_50V8J

1
R317

+VCC_LID

2
0_0402_5%

R318 1

KSO13

www.diendanlaptop.org
www.diendanlaptop.org

100P_0402_50V8J

C561
0.1U_0402_16V4Z

100P_0402_50V8J

OUTPUT
2

100P_0402_50V8J

Issued Date

2008/10/06

Deciphered Date

LID_SW# (33)
2

U39
1

C562
10P_0402_50V8J

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2 100K_0402_5%

A3212ELHLT-T_SOT23W-3

VDD

C447 1

GND

C448 1

KSO14

1BS003-1211L_3P

KSO15

2009/10/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

BIOS, I/O Port & K/B Connector


Size
B
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009

Sheet

34

of

49

Power Button
Switch Board Conn.

+5VS
2

ON/OFF switch

J5
2
J6

1
@ JOPEN

ME@
ACES_85201-06051

D10

R14
0_0603_5%

+3VALW
ON/OFFBTN#

NOVO_BTN#

ON/OFFBTN#
NOVO_BTN#

R8

1
@ JOPEN

PJSOT24C_SOT23-3

100K_0402_5%
D3

ON/OFFBTN#

ON/OFF#

(33)

51_ON#

(39)

CAPS_LED#
NUM_LED#

(33) CAPS_LED#
(33) NUM_LED#

Bottom Side

8
7
6
5
4
3
2
1

TOP Side

GND
GND
6
5
4
3
2
1
JP33

done

DAN202UT106_SC70-3

Name change at 8/12


2

D1

S 2N7002_SOT23

ON/OFFBTN#
Q1

2
G

NOVO_BTN#

1
1

C584

10K_0402_5%

0.1U_0402_25V6

R6

RLZ20A_LL34
@

0.1U_0402_25V6
C589

EC_ON

1
EC_ON

(33)

1000P_0402_25V8J
@1

C897

remove C585 at 8/12

+3VALW

LED

+5VALW +5VS

R265

Green

100K_0402_5%
D41

1
(33)

NOVO#

(39)

51_ON#

NOVO#

2
51_ON#

NOVO_BTN#

3
DAN202UT106_SC70-3
LED2

1
R249

2
2
300_0402_5%

1
R244

2
432_0402_1%

1 BT@

BT_LED# (31)

WLAN_LED# (31)

2
0_0402_5%
2
R25
WLAN@
0_0402_5%
19-213A-T1D-CP2Q2HY-3T_WHITE
R24

LED3
2

SATA_LED# (25)

19-213A-T1D-CP2Q2HY-3T_WHITE
LED4
1
R246

2
432_0402_1%

1
2
R247
432_0402_1%
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www.diendanlaptop.org

PWR_LED_SC# (33)

LED5
19-213A-T1D-CP2Q2HY-3T_WHITE
Blue CHARGE_LED0#
2
1

7.3mA

+3VALW
R245
1
2
499_0402_1%

CHARGE_LED0# (33)

19-213A-T1D-CP2Q2HY-3T_WHITE
LED6
2

Amber CHARGE_LED1#

CHARGE_LED1# (33)

S LED 19-217/S2C-FM2P1VY/3T 0603 ORANGE


4

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Power BTN/LED
Size
B
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009

Sheet
E

35

of

49

10

2 R122
1
R17

1
2

38
37

SPK_L2+
SPK_L1-

11
13

SPK_R2+
SPK_R1-

16
14

Internal SPEAKER

BIT_CLK
SYNC
SDATA_IN
SDATA_OUT

PORTB_R
PORTB_L
B_BIAS
C_BIAS
PORTC_R
PORTC_L
GPIO0/EAPD#
GPIO1/SPK_MUTE#

DMIC_CLK
DMIC_1/2

NC
NC
NC

LEFT+
LEFTAVEE
FLY_P
FLY_N

RIGHT+
RIGHT-

CX20671-11Z_QFN40_6X6

HDA_BITCLK_AUDIO

2
R121

1
22P_0402_50V8J
C803

22P_0402_50V8J
C804

MIC_INR
MIC_INL

+MICBIASC

C707
C705

2 5.11K_0402_1%

R213
R338

1
1

2 10K_0402_1%
2 39.2K_0402_1%

2 2.2U_0603_10V7K
2 2.2U_0603_10V7K

1
1

1
1

2
2

15_0402_5%
15_0402_5%

Port C
Port A

R161

100_0402_1% EXT_MIC_R
EXT_MIC_L
100_0402_1%

2
1U_0603_10V4Z

SPK_R1SPK_R2+
SPK_L1SPK_L2+

1
1
1
1

2
2
2
2

SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN

FBMA-L11-160808-121LMA30T
FBMA-L11-160808-121LMA30T
FBMA-L11-160808-121LMA30T
FBMA-L11-160808-121LMA30T

C706

2 2.2U_0603_10V7K
@

MIC_INL

220P_0402_50V7K

2
MIC_INR

@ R316
1K_0402_5%

Headphone

C799

@ R319
1K_0402_5%
GNDA

GNDA
JHP1

SM010022410
PL-OUT
1
2
R584
FBMA-L10-160808-121LMT
PR-OUT
1SM010022410
2
R586
FBMA-L10-160808-121LMT

HP_OUTL

1
2
6
3

PLUG_IN

4
2

R212
10K_0402_1%
2

EXT_MIC_L
1C698

1
2

R214
10K_0402_1%

1 1

2
B
E

EXT_MIC_R
PC_BEEP

C807
47P_0402_50V8J
2GNDA

Q4
2SC2411KT146_SOT23-3

R487

JMIC1

MIC_JD

4
4

GNDA 5

10P_0402_50V8J

C320
@

FOX_JA6333L-B3S0-7F
ME@

2
GNDA
2
1

1 1

560_0402_5%

D5 @
RB751V_SOD323

R307
10K_0402_5%

2008/10/06

Deciphered Date

2009/10/06

Title

HD Audio Codec ALC888S-VC

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size
C
Date:

MIC IN

1
2
6
3

C321
10P_0402_50V8J
2GNDA
@

R325
20K_0402_5%
1

1U_0603_10V4Z

ICH Beep

C
2

1U_0603_10V4Z

SB_SPKR

R488

560_0402_5%

C703
(24)

1U_0603_10V4Z
1

Audio Jack

EXT_MIC_L-2

C285
@ 0.1U_0402_16V4Z

C697
2

C699
2

2PC_BEEP1
20K_0402_5%

SM010022410
1
2
R583
FBMA-L10-160808-121LMT
1

C826
@ C319
47P_0402_50V8J
10P_0402_50V8J
2GNDA
2GNDA
SM010022410
EXT_MIC_R-2
1
2
R585
FBMA-L10-160808-121LMT
1
1

R324

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www.diendanlaptop.org

1U_0603_10V4Z

BEEP#

FOX_JA6333L-B3S0-7F
ME@

R1003
0_0402_5%
@

+3VS

C800
1

0_0603_5%
1
2 R981

2 2.2U_0603_10V7K

1
2
C704

HP_OUTR

1
2
3
4
G5
G6

ACES_85205-04001

Audio Jack

EC Beep

1
2
3
4
5
6

ME@

WM-64PCY_2P
45@

PC Beep

1000P_0402_25V8J

JSPK1
L37
L35
L36
L34

220P_0402_50V7K

GNDA

1000P_0402_25V8J
C1039

External MIC

HP_OUTR
HP_OUTL

wide 20MIL
1
C701

GNDA

+MICBIASC

GNDA

(33)

Sense resistors must be


connected same power
that is used for VAUX_3.3

R343
4.7K_0402_5%

1
2

Headphone

add at 8/12

24
25
39

+VAUX_3.3
MIC_JD
PLUG_IN

2.2K_0402_5%
2.2K_0402_5%

R162
23
22

R484

R321
R322

R919
R920

0_0603_5%

C1036

SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN

+5VS

Internal MIC

+MICBIASB

32
31
30

Please bypass caps very close to device.

36
35
34
33

EMI
1 R15

2200P_0402_50V7K

1000P_0402_25V8J
C1035

10U_0805_10V4Z
C1034

10U_0805_10V4Z
C396

0.1U_0402_16V4Z
C397

C284
C292

0.1U_0402_16V4Z
C280

0.1U_0402_16V4Z

12
15
17

21
19
20

1
22P_0402_50V8J
C801

22P_0402_50V8J
C802

1000P_0402_25V8J
C1033

3300P_0402_50V7K
C1032

2200P_0402_50V7K
C1031

+MICBIASB

MIC1

GND

2
1

0.1U_0402_16V4Z

AVDD_3.3
AVDD_5V
AVDD_HP

SENSE_A

1
0_0402_5%

EMI

PC_BEEP

41

C278
1
2
0_0402_5%
R126
1
2
0_0402_5%
R124
1
2
0_0402_5%
R123
1
2
0_0402_5%

27
28
26

29
FILT_1.65

LPWR_5.0
RPWR_5.0
CLASS-D_REF

GND

C283
1
2
0_0402_5%

RESET#

2.5A

PORTA_R
PORTA_L
40
1

C290
1
2
0_0402_5%

EMI

HDA_SDOUT_CODEC

10U_0805_10V4Z

5
8
6
4

C282
1
2
0_0402_5%

C395

C394

0_0402_5%
EC_MUTE#
0_0402_5%

EAPD
EC_MUTE#

U8

PC_BEEP

FILT_1.8
VDD_IO
VAUX_3.3
DVDD_3.3

HDA_RST_AUDIO#

+5VS

3
7
2
18

0.1U_0402_16V4Z

Layout Note:Path from +5VS to LPW R_5.0


RPW R_5.0 must be very low
resistance (<0.01 ohms)

C286

(33)
(33)

0.1U_0402_16V4Z
C393

10U_0805_10V4Z
C809

2
1

HDA_BITCLK_AUDIO
HDA_SYNC_CODEC
33_0402_5%
1 R336
2
HDA_SDOUT_CODEC

EAPD active low


0=power down ex AMP
1=power up ex AMP

J8

10K_0402_5%
C398

(24) HDA_BITCLK_AUDIO
(24) HDA_SYNC_AUDIO
(24) HDA_SDIN0
(24) HDA_SDOUT_AUDIO

@ JUMP_43X118

EMI

AVDD_3.3 pinis output of


internal LDO. NOT connect
to external supply.

10K only needed if supply to VAUX_3.3


is removed during system re-start.

0.1U_0402_16V4Z

1U_0603_10V4Z
C294

C700

(24) HDA_RST_AUDIO#

30mA

R133

R291

0_0402_5%

0.1U_0402_16V4Z

10U_0805_10V4Z
C281

+LDO_OUT_3.3V
1

0.1U_0402_16V4Z

C702

0.1U_0402_16V4Z

C392

10U_0805_10V4Z
C291

1U_0603_10V4Z
C289

0.1U_0402_16V4Z

C399

60mA

10U_0805_10V4Z
C293

+3VS

+3VS

R155

To suuport Wake-on-Jack or Wake-on-Ring, the CODEC


VAUX_3.3 & VDD_IO pins must be powerd by a rail that
is not removed unless AC power is removed.
*DSH page42 has more detail.

HDA_SYNC_CODEC

+VAUX_3.3

0_0402_5%

HDA_RST_AUDIO#

0.1U_0402_16V4Z
C279

+3VS

B+

CX20671
High Definition Audio Codec SoC
With Integrated Class-D Stereo
Amplifier.
An integrated 5 V to 3.3 V Low-dropout
voltage regulator (LDO).
An integrated 3.3 V to 1.8V Low-dropout
voltage regulator (LDO).
1

1000P_0402_25V8J
C1038

1000P_0402_25V8J
C1037

10U_0805_10V4Z
C288

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009

Sheet

36
H

of

49

FAN1 Conn
+5VS
+5VS

10U_0805_10V4Z
2

C908
1
U31

BAS16_SOT23-3
C121
10U_0805_10V4Z
1
2

C350
0.1U_0402_16V4Z
+3VS

C119
1000P_0402_25V8J
1
2

R450
10K_0402_5%
H21
H_3P0

H10
H_3P0

H22
H_3P3

H23
H_3P2

H5
H_3P0

H13
H_4P2

H16
H17
H_3P6N H_3P0

H1
H_3P0

H15
H_3P0

H18
H_3P6X6P1N

H11
H_3P6X6P1N

@
FD1

FIDUCIAL_C40M80

FIDUCIAL_C40M80
@

FD4

FD3

FD2

FIDUCIAL_C40M80

H2
H_3P0

H3
H_3P0

H4
H_3P0

H12
H_3P0

H20
H_3P0

H9
H_4P2

H14
H_4P2

H7
H_4P2

ACES_85205-03001
ME@

C670
1000P_0402_25V8J

1
2
3

JP13

(33) FAN_SPEED1

40mil
+VCC_FAN1

D12
1
@

APL5605KI-TRL SOP 8P

+VCC_FAN1
1
1K_0402_5%

D11
1SS355_SOD323-2
@

8
7
6
5

2
R62

GND
GND
GND
GND

EN_FAN1

VEN
VIN
VO
VSET

(33)

1
2
3
4

FIDUCIAL_C40M80

www.diendanlaptop.org
www.diendanlaptop.org

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/10/06

Deciphered Date

2009/10/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

FAN & Screw Hole


Size
B
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009

Sheet

37

of

49

+5VALW

+5VALW

+5VS

+1.2VALW

4.305A

C577

0.1U_0603_25V7K
VLDT_EN# 2
Q23G
2N7002_SOT23

1
1

Q21
2N7002_SOT23

+5VALW

C506
0.1U_0603_25V7K
1
C1028

add at 8/12

2
@

R242
100K_0402_5%
220P_0402_50V7K

SUSP

SUSP

Q30
2N7002_SOT23

+3VALW TO +3VS

2
G

(18,31,33,41,44,46) SUSP#

+3VALW

2
2 VLDT_EN#
G
Q22
2N7002_SOT23
@

2
G

R174
100K_0402_5%

1.2VS_GATE

SYSON

(31,33,43) SYSON

SYSON#

SYSON#

2
10U_0805_10V4Z

2
1
R196
200K_0402_5%

B+

10U_0805_10V4Z
C462
2
2
1U_0402_6.3V4Z

R197
470_0603_5%
@

2 R921
1 SUSP
0_0402_5%
@
C1020
@
0.1U_0603_25V7K

(43)

SUSP

2
Q29G
2N7002_SOT23

SI4800BDY_SO8

Q28
S
2N7002_SOT23
@

2 R943
1
0_0402_5%

C470

2
G
5VS_GATE

2
1
R239
49.9K_0402_1%

B+

C509

1
2
3
4

S
S
S
G

R202
1K_0402_5%

D
D
D
D

10U_0805_10V4Z
2
2
10U_0805_10V4Z

8
7
6
5

DVT

R238
470_0603_5%
@

2
1

C573
10U_0805_10V4Z
2
2
1U_0402_6.3V4Z

SI4800BDY_SO8
1

C570

C576

U37

1
2
3
4

S
S
S
G

C571

D
D
D
D

R169
100K_0402_5%

+1.2V_HT

3.265A

U34
8
7
6
5

+1.2VALW TO +1.2V_HT

+5VALW TO +5VS

R248
10K_0402_5%

+3VS

4.121A
U33
1
2
3
4

2
C572

SI4800BDY_SO8

C569
10U_0805_10V4Z
2
2
1U_0402_6.3V4Z

10U_0805_10V4Z
2
2
10U_0805_10V4Z

+5VALW

R167
100K_0402_5%

2
G

B+

SUSP
VLDT_EN#

(18) VLDT_EN#

Q27 S
2N7002_SOT23
@

3VS_GATE

2
1
R982
100K_0402_5%

R243
470_0603_5%
@

S
S
S
G

Q3
2N7002_SOT23

0.1U_0603_25V7K
R290
10K_0402_5%

2
G

(33,44,45,46) VLDT_EN

C1024

SUSP

2
Q61G
2N7002_SOT23

C574

D
D
D
D

C575

1 1

8
7
6
5

+1.8V to +1.8VS
+1.8V

+1.8V

+1.8VS

+1.8VS_VGA

6.988A

4.556A

SI4800BDY_SO8

1
SUSP

2
G

C565
VGA@

10U_0805_10V4Z

1.8VS_GATE

2
1
R271
150K_0402_5%

B+

2
10U_0805_10V4Z

R570
470_0603_5%
@

10U_0805_10V4Z
C709
2
2
1U_0402_6.3V4Z

10U_0805_10V4Z

2 SUSP
G
Q46
2N7002_SOT23
@

B+
@
VLDT_EN#1
R924
SUSP 1
R407

C711

Q47
0.1U_0603_25V7K
2N7002_SOT23 2

C563

2
10U_0805_10V4Z

2
0_0402_5%
1.8VS_VGE_EN
2
2
G
20K_0402_5%

VGA@

S
S
S
G

1
2
3
4

C367

10U_0805_10V4Z
C368
2
VGA@ 2
1U_0402_6.3V4Z
VGA@

SI4800BDY_SO8
VGA@

VGA@

VGA@
2
1
R154
200K_0402_5%

D
D
D
D

8
7
6
5

R115
470_0603_5%
@
3

C712

1.8VS_VGA_GATE

1
2
3
4

1
1

S
S
S
G

C710

D
D
D
D

8
7
6
5

C714

U32

U36

2 1.8VS_VGE_EN
G
Q14
2N7002_SOT23
@

C564
0.1U_0603_25V7K
2 VGA@
Q19
2N7002_SOT23
VGA@

C852
0.1U_0402_16V4Z
2
VGA@

add at 8/13

2
G
Q18
2N7002_SOT23
@

2
G
Q11
2N7002_SOT23
@

SYSON#

2
G
Q12
2N7002_SOT23
@

SYSON#

2
G
Q26
2N7002_SOT23
@

SUSP

SUSP

R925
470_0603_5%
PARK@

R113
470_0603_5%
@

R112
470_0603_5%
@

R153
470_0603_5%
@

+VGA_PCIE

R241
470_0603_5%
@

+1.8V

+0.9V

+2.5VS

+1.5VS_UMA

www.diendanlaptop.org
www.diendanlaptop.org

@
1
R926

2 VLDT_EN#
0_0402_5%

SUSP
2
1
2
G
R927PARK@0_0402_5%
Q60
2N7002_SOT23
PARK@

add at 8/13
A

2008/10/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/10/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

Title

DC Interface
Size
B
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009

Sheet
E

38

of

49

ACIN

PQ101
TP0610K-T1-E3_SOT23-3

PR102
1K_1206_5%
1
2

PD101
2

VIN

PR103
1K_1206_5%
1
2
PR104
100K_0402_1%
2
1

LL4148_LL34-2

Max.
18.384V
17.728V

VIN

VS

(33,41)

ACOFF

PQ102

3
PR113
2.2M_0402_5%
2
1

VL

2
1
PR116
499K_0402_1%

2
1
PR117
100K_0402_1%

PR123
200_0603_5%
CHGRTCP 1
2

2
1
PR119
499K_0402_1%

1
2

1
PR118
205K_0402_1%

PR125
47K_0402_5%
1

PACIN (41)

1
IN
GND

PC116
10U_0603_6.3V6M

PQ106
DTC115EUA_SC70-3

+RTCBATT

+CHGRTC

RB751V-40_SOD323-2
4

RTC Battery

2CHGRTCIN
1

OUT

@ MAXEL_ML1220T10

PC117
1U_0805_25V4Z

Compal Electronics, Inc.

Compal Secret Data

Security Classification

+5VALW

PD106

3.3V

www.diendanlaptop.org
PR129
- JRTC
+ 560_0603_5%
www.diendanlaptop.org

Issued Date

2009/01/06

Deciphered Date

2010/01/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

2
G

PR128
200_0603_5%

PU102
G920AT24U_SOT89-3

PR130
560_0603_5%
1
2

PQ105
SSM3K7002F_SC59-3

VS

+CHGRTC

PC115
0.1U_0603_25V7K

51ON-3

RTCVREF
4

PR124
10K_0402_5%
2
1

RTCVREF

PC114
0.22U_0603_25V7K

1
2

PR127
22K_0402_1%
1
2

S
51ON-2

PR126
100K_0402_1%

(35) 51_ON#

PR122
68_1206_5%
2

PR121
PQ104
68_1206_5%
TP0610K-T1-E3_SOT23-3

51ON-1
1

PD105
LL4148_LL34-2
2
1

BATT+

PD104
LL4148_LL34-2

PC113
0.1U_0603_25V7K

PU101B
LM393DG_SO8

PC111
1000P_0402_50V7K

8
7

ACON

(41)

VIN

PD103
RB715F_SOT323-3
2
1
3

(40,42) MAINPWON

(41)

PACIN

3.3V

RTCVREF

3
(15,25,33)

PD102
LLZ4V3B_LL34-2
PR115
10K_0402_5%
2
1

B+
PQ103

PC112
0.01U_0402_25V7K

1
PR109
10K_0805_5%

PACIN

PU101A
LM393DG_SO8

DTC115EUA_SC70-3
2

DTC115EUA_SC70-3
ACIN

1
PR114
10K_0402_5%

PR110
10K_0402_1%
1
2

1
+

8
3

1
2

PC109
0.1U_0402_16V7K

PR112
20K_0402_1%

VINDE-3

PR111
22K_0402_1%
1
2

VINDE-1

PR108
84.5K_0402_1%

PC108
0.068U_0603_16V7K
2
1

PC107
0.01U_0402_25V7K

PRG++ 2

VINDE-2
VIN

PR107
1M_0402_1%
1
2

1 2

Vin Detector
Min.
typ.
L-->H 17.430V 17.901V
H-->L 16.976V 17.262V

PR101
1K_1206_5%
1
2

1
2

PC106
1000P_0402_50V7K

1
2

PC105
100P_0402_50V8J

PC104
@ 0.1U_0603_25V7K

1
2

@ 4602-Q04C-09R 4P P2.5
JDCIN

PC103
100P_0402_50V8J

PL101
SMB3025500YA_2P
1
2

PF101
7A_24VDC_429007.W RML
1
2 APDIN1

PC102
1000P_0402_50V7K

APDIN

PC101
@ 0.1U_0603_25V7K

PR105
100K_0402_1%
2
1

DC030006J00

BATT ONLY
Precharge detector
Min.
typ.
Max.
L-->H 7.196V 7.349V 7.505V
H-->L 6.138V 6.214V 6.056V

Precharge detector
Min.
typ.
Max.
L-->H 14.991V 15.381V 15.782V
H-->L 13.860V 14.247V 14.621V

VIN

PR106
100K_0402_1%

Title

DCIN & DETECTOR


Size Document Number
Custom
Date:

Rev
1.0

Thursday, December 10, 2009


D

Sheet

39

of

49

VMB

VS

2
PC207

PR202
47K_0402_1%

TM-2

@ 0.01U_0402_25V7K

TM-1

3
2

O
-

PQ201
SSM3K7002FU_SC70-3

VL

PR208
100K_0402_1%
PR210
100K_0402_1%

A/D

PC204
1000P_0402_50V7K

PR207
15.4K_0402_1%

PC206

2
G

PU201A
LM393DG_SO8

O
G

BATT_TEMP (33)

TM-3

1
2
PR211
10K_0402_5%

+3VALW

PC203
0.22U_0603_25V7K
2
1

1
2
PR209
6.49K_0402_1%

EC_SMB_DA1 (33)

@ 0.01U_0402_25V7K

TM_REF1

EC_SMB_CK1 (33)

MAINPW ON (39,42)
2

PR205
13.7K_0402_1%
1
2

PR203
47K_0402_1%
1

PH201
100K_0402_1%_TSM0B104F4251RZ

VL

PC202
0.01U_0402_25V7K

1
2

PC201
1000P_0402_50V7K

TYCO_1775789-1
@

2
1
PR206
100_0402_1%

EC_SMCA
EC_SMDA

VL

BATT+

PL201
SMB3025500YA_2P
1
2

1
2
3
4
5
6
7
8
9

2
1
PR204
100_0402_1%

1
2
3
4
5
6
7
GND
GND

PF201
12A_65V_451012MRL
1
2

JBATT

PC205
0.01U_0402_25V7K

VMB2

PH1 under CPU botten side :


CPU thermal protection at 92 degree C
Recovery at 56 degree C

PU201B
LM393DG_SO8

www.diendanlaptop.org
www.diendanlaptop.org

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/01/06

Deciphered Date

2010/01/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

BATTERY CONN / OTP


Size
Date:

Document Number

Rev
1.0

Thursday, December 10, 2009


D

Sheet

40

of

49

B+

P3
P2

PR302
0.15_1206_1%

8
7
6
5

CHG_B+
PJ301

PR304
47K_0402_1%
1
2

1 1
ICOMP

CSIN

20

VCOMP

CSIP

19

ICM

PHASE

18

Vcell

CHGVADJ

(33) CHGVADJ

CHG
1

PACIN

PQ309
2N7002KW _SOT323-3

BATT+

ACLIM

VDDP

15

11

VADJ

LGATE

14

12

GND

PGND

13

PC317
0.1U_0603_25V7K
BST_CHGA 2
1

DL_CHG

PD303
RB751V-40TE17_SOD323-2

6251_VDDP

26251_VDD

PR323
4.7_0402_5%
PC323
4.7U_0805_6.3V6K

PR325
15.4K_0402_1%
1
2

PC320
10U_1206_25V6M
2
1

BOOT

10

PR320
0_0402_5%
BST_CHG 1
2

PC319
10U_1206_25V6M
2
1

CHLIM

16

PC318
10U_1206_25V6M
2
1

DH_CHG

17

PR319
@ 4.7_1206_5%

UGATE

VREF

0V

2
2

100K_0402_1%
1

PQ315
DTC115EUA_SC70-3

FSTCHG

SUSP#

PD304
RB715F_SOT323-3

FSTCHG (33)

2007/6/22

Issued Date

PQ313B
2N7002KDW -2N_SOT363-6

Compal Electronics, Inc.


2008/6/22

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1
PR331
0_0402_5%

Compal Secret Data

Security Classification

SUSP# (18,31,33,38,44,46)

PR336
@ 105K_0402_1%

PR337

(33) BATT_SEL_EC
PQ313A
2N7002KDW -2N_SOT363-6

1
+

PC324
@0.01U_0402_25V7K

2
8

www.diendanlaptop.org
(33) BATT_OVP
www.diendanlaptop.org

2
1
PC325
@0.01U_0402_25V7K

PU302A
@ LM358DT_SO8
1 0

PR330
@ 0_0402_5%

PR332
@ 499K_0402_1%

6251_DCIN

PR334
@ 10K_0402_1%
1
2

PU302B
@ LM358DT_SO8
7 0

Per cell=3.5V

3
PR335
100K_0402_1%
2
1

P3

PR333
10_0603_5%
1
2

BATT-OVP=0.1112*VMB

VS

PQ314 TP0610K-T1-E3_SOT23-3

LI-3S :13.5V----BATT-OVP=1.5012V

VCHLIM need over 95mV

DIS CP mode
Vaclim=2.39*(3.9K/(3.9K+16.9K))=0.478V
Iinput=(1/0.015)((0.05*Vaclim)/2.39+0.05)
where Vaclim=0.478V, Iinput=4A

IREF=0.254V~3.048V

PR328
100K_0402_1%
1

CELLS

IREF=1.016*Icharge

2
PR327
100K_0402_1%

PR329
@ 340K_0402_1%

VS

6251_VDD

CC=0.25A~3A

VMB2

3.2935V

6251_VDD

PR326
31.6K_0402_1%

UMA CP mode
Vaclim=2.39*(1.4K/(1.4K+13.7K))=0.2376V
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05)
where Vaclim=0.2376V, Iinput=2.75A

1.882V

4.35V

4.2V

4V

2
G
S

PL301
PR317
10U_LF919AS-100M-P3_4.5A_20% 0.02_1206_1%
1

ISL6251AHAZ-T_QSOP24

CSOP

VIN

21

PC311
0.1U_0603_25V7K
2
1

CSOP

PR308
200K_0402_1%
1
2

CELLS

CSON

PC310
0.047U_0402_16V7K
1
2
PR311
20_0402_5%
2
1
PR312
PC313
20_0402_5%
0.1U_0402_16V7K
1
2
PR315
2.2_0402_5%
LX_CHG

PQ308
SIS412DN-T1-GE3_PAK1212-8

22

3
2
1

CSON

PD302
RB715F_SOT323-3

EN

PR310
20_0402_5%
1
2

PR324
3.9K_0402_1%

Connect to EC A/D Pin.

CHGVADJ=(Vcell-4)/0.10627

ACOFF

PC322
@ 680P_0603_50V7K

1
2

PR322
100K_0402_1%

1
2
PC316
0.1U_0402_16V7K
PR321
16.9K_0402_1%
6251_VREF 1
2

23

PQ312
SI7716ADN-T1-GE3 _PAK1212-8

IREF

1
2
PR316
100_0402_1%
6251_VREF

ACSET ACPRN

(33)
ACOFF

ACOFF

ADP_I
PR318
154K_0402_1%
2
1

3
1

PQ306
DTC115EUA_SC70-3

3
2
1

1
2
PC315
@ 100P_0402_50V8J

PC321
0.01U_0402_25V7K
2
1

(33)

6.81K_0402_1%
2

0.01U_0402_25V7K

ACON
PQ311
DTC115EUA_SC70-3

(33,39)

PR314
1

24

PC314
1
2

2
G

6800P_0402_25V7K
2

DCIN

PC312
1

VDD

PQ310
D 2N7002KW _SOT323-3

PACIN

CELLS

PR313
3K_0402_1%
1
2

6251_EN

PC309
0.1U_0603_25V7K
6251_DCIN2
1

PU301

2
G
3

PR307
2

PQ307
D 2N7002KW _SOT323-3

2
PC308
0.1U_0402_16V7K
PR309
150K_0402_1%

(39)

VIN

(33) FSTCHG

PR305
10K_0402_1%

PC307
2.2U_0603_6.3V6K
2
1

PR306
10K_0402_1%
2
1
100K_0402_1%

PQ305
DTC115EUA_SC70-3

PACIN

2
PD301
RB751V-40TE17_SOD323-2
6251_VDD
1
2

1
2

(39)

8
7
6
5
4

PC305
2200P_0402_50V7K

CSIN
CSIP

1
2
3

@ JUMP_43X118

PC304
4.7U_1206_25V6K
1
2

PC301
0.1U_0603_25V7K
2
1
PR303
200K_0402_1%

PQ304

PQ303
FDS6675BZ_SO8

PC303
4.7U_1206_25V6K
1
2

PC306
4.7U_1206_25V6K
1
2

1
PR301
47K_0402_5%

DTA144EUA_SC70-3

1
2
3

VIN

PQ302
FDS6675BZ_SO8
1
2
3

PC302
470P_0603_50V8J

PQ301
FDS6675BZ_SO8
8
7
6
5

Title

CHARGER
Size
Date:

Document Number

Rev
1.0

Thursday, December 10, 2009

Sheet
1

41

of

49

ISL6237_B+

30

VOUT2

DRVL1

18

LG5

PGND

22

VOUT1

10

FB1

11

VSW

VREF2

LDOREFIN

PD401

5V_SKIP

29

NC

PGOOD2

28

EN_LDO

PGOOD1

13

TRIP1

12

ILM1

TRIP2

31

ILIM2

14

EN1

3/5V_EN2

27

EN2

21

2VREF_ISL6237

PC422
0.1U_0402_25V6
2
1

PC413
220U_6.3V_M

SPOK

(33,43)

2
1
PR414
301K_0402_1%
2
1

SN0806081RHBR_QFN32_5X5

PR415
301K_0402_1%
B

13/5V_TON

PR416
0_0402_5%

1 PR411 2
0_0402_5%
2 PR421 1
@ 0_0402_5%

+
2

VL

VL

PR420
0_0402_5%

PJ402

+3VALWP

+3VALW

@ JUMP_43X118
2VREF_ISL6237

PC418
1U_0603_10V6K
2
13/5V_NC

0_0402_5%
(39,40)

PR419
@ 47K_0402_1%

MAINPW ON

2VREF_ISL6237

PR418
2

PC420
0.047U_0402_16V7K
2
1

RB751V-40_SOD323-2

PC419
0.047U_0402_16V7K

PR417

PD403

806K_0603_1%

VL

PR410
2
1
@ 0_0402_5%

3/5V_EN1

GND

PC417
0.22U_0603_25V7K

EN_LDO

VREF3

LLZ5V1B_LL34-2

EN_LDO-1

PR413
200K_0402_1%
1
2

20

TONSE

RB751V-40_SOD323-2
PR412
100K_0402_1%
1
2

PC406
2200P_0402_50V7K
2
1

FB5

SKIPSEL

PD402
1

PC404
10U_1206_25V6M
2
1

REFIN2

PC416
0.22U_0603_25V7K

VS

PC415
330P_0402_50V7K

PQ404
SI7716ADN-T1-GE3_PAK1212-8

PC412
0.1U_0603_25V7K

PR422

32

16

1
PR407
@ 61.9K_0402_1%
1
2

DRVL2

LL1

LL2

23

SW 5

3
2
1

25

LG3

VL

PR404
4.7_1206_5%

1BST5A-1
PR405
2.2_0603_5%

PR409
0_0402_5%
1
2

BST5A2

+5VALWP

HG5

17

15V_SNB
2

15

VBST1

2VREF_ISL6237
1

3
2
1

DRVH1

VBST2

7
LDO

DRVH2

SW 3

FB3

19

PR403
2.2_0603_5%
PC411 <BOM Structure>
0.1U_0603_25V7K

V5FILT

24

VIN

26

4.7U_0805_6.3V6K

PC409
2
1

PC408
3/5V_VCC
1
2
3

1U_0603_10V6K

3/5V_VIN

2
1

UG3
BST3A

PC410
1U_0603_10V6K
1
2

V5DRV

PQ402
SIS412DN-T1-GE3_PAK1212-8
PL402
4.7UH_PCMC063T-4R7MN_5.5A_20%
2
1

100K_0402_1%

PQ403
SI7716ADN-T1-GE3_PAK1212-8

PR408
10K_0402_1%

TP

2
PC414
330P_0402_50V7K

33

1
2
3

BST3A-1

13V_SNB
2

PU401

PR402
4.7_1206_5%

PR406
0_0402_5%

VL

1
2
3

PL401
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2

+3VALWP

PC407
0.1U_0603_25V7K

PQ401
4 SIS412DN-T1-GE3_PAK1212-8

PC403
2200P_0402_50V7K
2
1

PC401
10U_1206_25V6M
2
1

PR401
0_0402_5%
1
2

PC423
0.1U_0402_25V6
2
1

PC405
330P_0402_50V7K
2
1

PJ401
@ JUMP_43X118
2 2
1 1

PC421
220U_6.3V_M

ISL6237_B+

B+

PJ403

+5VALWP

www.diendanlaptop.org
www.diendanlaptop.org

+5VALW

@ JUMP_43X118

2009/01/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/01/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

3VALW/5VALW

Size Document Number


Custom
Date:

Rev
1.0

Thursday, December 10, 2009

Sheet
1

42

of

49

PJ501
1.2V_IN

LG_1.2V

SI4634DY-T1-E3_SO8
4

TP

PU501
TPS51117RGYR_QFN14_3.5x3.5

PQ502

+
2

DRVL

PR504
4.7_1206_5%

10

+5VALW

V5DRV

1.2V_TRIP
1
2
PR506
10K_0402_1%

PC507
10U_0603_6.3V6M

1.2V_SW

11

+1.2VALW P

PC506
220U_B2_2.5VM_R15M

12

5
6
7
8

LL
TRIP

PC510
4.7U_0805_6.3V6K

PR507
100K_0402_1%

UG_1.2V

3
2
1

PGOOD

13

DRVH

VFB
PGND

1.2V_FB

14

15

1
EN_PSV

V5FILT

GND

VOUT

PC509
@ 47P_0402_50V8J
1
2

3
1.2V_V5FILT

1
PC508
4.7U_0603_6.3V6K

TON

PL501
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2

1.2V_SNB

+3VALW

0.1U_0603_25V7K
PC501
@0.01U_0402_25V7K

PR505
100_0603_1%
1
2

+5VALW

B+

3
2
1

PR503
PC505
0_0603_5%
BST_1.2V 1
2BST_1.2V-1
1
2

1.2V_EN

VBST

SPOK

(33,42)

2
1
PC504
2200P_0402_50V7K

1.2V_TON
PR501
0_0402_5%
1
2

SI4686DY-T1-E3_SO8
4

2
1
PC503
0.1U_0402_25V6

2
1
PC502
10U_1206_25V6M

5
6
7
8
PQ501
PR502
240K_0402_1%
1
2

@ JUMP_43X118

PC511
680P_0402_50V7K

1.2V_PW ROK

PR508
13.7K_0402_1%
1
2

PR509
20.5K_0402_1%

PJ502
1.8V_IN

PC522
@0.1U_0402_16V7K

15

LG_1.8V

DRVL

+5VALW
PQ504
SI4634DY-T1-E3_SO8
4
1

PGND

GND

PR516
@ 100K_0402_1%
1

PC521
@ 47P_0402_50V8J
1
2

PC520
4.7U_0603_6.3V6K

@
2
1
PC515
2200P_0402_50V7K

2
1
PC514
0.1U_0402_25V6

V5DRV

10

1.8V_TRIP
1
2
PR515
8.45K_0402_1%

PR513
4.7_1206_5%

PU502
TPS51117RGYR_QFN14_3.5x3.5

1
+
2

PC523
4.7U_0805_6.3V6K

PGOOD

1.8V_SW

11

12

PC518
220U_6.3V_M

VFB

LL
TRIP

1.8V_SNB 2

+1.8VP

1.8V_FB

UG_1.8V

V5FILT

13

5
6
7
8

VOUT

DRVH

3
1.8V_V5FILT

PL502
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2

3
2
1

TON

TP

PR514
100_0603_1%
1
2

+5VALW

EN_PSV

PC517
@0.1U_0402_16V7K

2BST_1.8V-1
1
2
PC516
0.1U_0603_25V7K

B+

PC519
10U_0603_6.3V6M

BST_1.8V 1
PR512
2.2_0603_5%

3
2
1

1.8V_EN
1

(31,33,38) SYSON

1.8V_TON

PR511
0_0402_5%
1
2

14

VDDIO

SI4686DY-T1-E3_SO8
4

VBST

(6)

PR510
240K_0402_1%
1
2

2
1
PC513
10U_1206_25V6M

PQ503
PR522
@ 0_0402_5%
1
2

JUMP_43X79

2
1
PC512
@ 10U_1206_25V6M

5
6
7
8

PC524
820P_0402_25V7

1.8V_PGOOD

PR517
31.6K_0402_1%
1
2

PR518
22.1K_0402_1%
+1.8VP

PJ503
2

+1.2VALWP
1
2

PU503
VIN

VCNTL

GND

NC

VREF

NC

VOUT

NC

TP

2
5

+1.2VALW

+1.8V

@ JUMP_43X118

PC526
1U_0402_6.3V6K
PJ506
2

+0.9VP

+0.9V

@ JUMP_43X79

G2992F1U_SO8

+0.9VP

PC529
10U_0603_6.3V6M

2009/01/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

1
PC527
0.1U_0402_16V7K
2

PR521
1K_0402_1%

S PQ505
@ SSM3K7002FU_SC70-3

1
PC528
@ 0.1U_0402_16V7K

2
G

SYSON#

PJ505
2

+1.8VP

+3VALW

PR519
1K_0402_1%

0.9V_REF

(38)

www.diendanlaptop.org
www.diendanlaptop.org

PR520
@ 0_0402_5%
1
20.9V_EN

1
2

PJ504
@ JUMP_43X79

0.9V_IN

PC525
4.7U_0805_6.3V6K

@ JUMP_43X118

2010/01/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

1.2V/1.8V/0.9V
Size
Date:

Document Number

Rev
1.0

Thursday, December 10, 2009

Sheet
1

43

of

49

PJ601
1.5V_IN

PC611
@0.1U_0402_16V7K

LG_1.5V

@
1.5V_SNB 2

PU601
TPS51117RGYR_QFN14_3.5x3.5

PC612
4.7U_0805_6.3V6K

15

2
1
PC605
2200P_0402_50V7K
+
2

+1.5VS

PC613
@ 470P_0402_50V7K

PQ602
SI7716ADN-T1-GE3_PAK1212-8

1.5V_PGOOD

PR608
21K_0402_1%
1
2

10

PR604
@ 4.7_1206_5%

+5VALW

V5DRV

1.5V_TRIP
1
2
PR606
17.8K_0402_1%

PC608
10U_0603_6.3V6M

1.5V_SW

11

PC607
220U_B2_2.5VM_R15M

12

DRVL

2
1
PC604
0.1U_0402_25V6

LL
TRIP

+1.5VSP

@ JUMP_43X79

1
2

PGOOD

PJ602
+1.5VSP

1,5
v

2
1
PC603
10U_1206_25V6M

2
1
PC602
@ 10U_1206_25V6M

5
VFB

UG_1.5V
5

13

3
2
1

1.5V_FB

DRVH

B+

PL601
2.2UH_PCMC063T-2R2MN_8A_20%
1
2

V5FILT

PR607
@ 100K_0402_1%

TP

1
VOUT

1
PC610
@ 47P_0402_50V8J
1
2

PC609
4.7U_0603_6.3V6K

EN_PSV

3
1.5V_V5FILT

TON

GND

PR605
100_0603_1%
1
2

+5VALW

PC601
@0.1U_0402_16V7K

2BST_1.5V-1
1
2
PC606
0.1U_0603_25V7K

3
2
1

BST_1.5V 1
PR603
0_0603_5%
14

1.5V_EN

VBST

SUSP#

(18,31,33,38,41,46)

PGND

1.5V_TON
PR601
0_0402_5%
1
2

JUMP_43X79

PQ601
SIS412DN-T1-GE3_PAK1212-8
PR602
240K_0402_1%
1
2

PR609
21K_0402_1%
C

PQ603
PR613
PC617
0_0603_5%
BST_VGA 1
2BST_VGA-1
1
2

PC616
@ 0.1U_0402_16V7K

PC615
10U_1206_25V6M

VGA_EN

100K_0402_1%

PD601
1SS355_SOD323-2
1
2
+5VALW

SUSP#

PJ603
VGA_IN

PR612
(18,31,33,38,41,46)

PR610
205K_0402_1%
1
2

VGA_TON

5
6
7
8

(33,38,45,46) VLDT_EN

PR611
@ 10K_0402_5%
1

PR622
@ 0_0402_5%
2
1

PC614
10U_1206_25V6M

+3VS

B+

@ JUMP_43X79

SI4686DY-T1-E3_SO8

PU602
TPS51117RGYR_QFN14_3.5x3.5

PC623
4.7U_0805_6.3V6K

PC626
@ 47P_0402_50V8J
1
2

PC625
@ 0.1U_0402_16V7K

1
2

PC622
10U_0805_6.3V6M

PC621
10U_0805_6.3V6M

2
PR621
2.67K_0402_1%
1
2
PR623
10K_0402_1%

PC620
10U_0805_6.3V6M

+VGA_COREP

PC618
330U_D2_2.5VY_R15M

PR615
4.7_1206_5%

LG_VGA

1VGA_SNB
2

DRVL

+5VALW

VGA_TRIP
1
2
PR617
9.1K_0402_1%

PQ605
SI4634DY-T1-E3_SO8

V5DRV

10

3
2
1

SW _VGA

11

5
6
7
8

12

5
6
7
8

3
2
1

14

LL
TRIP

PQ604
SI4634DY-T1-E3_SO8

PGOOD

UG_VGA

3
2
1

13

VFB

VBST

EN_PSV

PL602
0.88UH +-20% PCMC104T-R88MN 20A
1
2

PC624
680P_0402_50V7K

V5FILT

1
(14) VGA_PW ROK

@ 100K_0402_1%

2
PR619

1
PC619
4.7U_0603_6.3V6K

VGA_FB

VOUT

DRVH

+3VS

PGND

VGA_V5FILT

PR616
100_0603_1%
1
2

+5VALW

TON

GND

TP

15

0.1U_0603_25V7K

+3VALW

1PWRSEL-2
1

PR627

www.diendanlaptop.org
M93
www.diendanlaptop.org
VGA_PWRSEL

Core Voltage Level

PJ604

S PQ606
2N7002KW _SOT323-3

1.2 V

0.95 V

+VGA_CORE

@ JUMP_43X118
PJ605
2

@ JUMP_43X118
PC627
0.022U_0402_16V7K

2009/01/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/01/06

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

+VGA_COREP

2
G
3

2
1PW RSEL-1
10K_0402_1%

PR625

10K_0402_1%

2
1
PR629

1
PR630
2

@ 10K_0402_1%

2
1 2
10K_0402_1% G

(15) VGA_PWRSEL

PR624
20K_0402_1%

@ 10K_0402_1%

2N7002KW_SOT323-3

PQ607
PR628

1
PR626
2
A

@ 10K_0402_1%

+3VALW

Title

1.5V/VGA_CORE
Size
Date:

Document Number

Rev
1.0

Thursday, December 10, 2009

Sheet
1

44

of

49

PJ701
NB_CORE_IN

2
1
PC705
2200P_0402_50V7K

2
1
PC704
0.1U_0402_25V6

+
2

PC712
4.7U_0805_6.3V6K

PC713
@ 470P_0402_50V7K

PU701
TPS51117RGYR_QFN14_3.5x3.5

PR704
@ 4.7_1206_5%

LG_NB_CORE

SI4634DY-T1-E3_SO8
4
1

PGND

PQ702

PC711
@0.1U_0402_16V7K

DRVL

+5VALW

PC708
10U_0603_6.3V6M

V5DRV

10

NB_CORE_TRIP
1
2
PR706
10K_0402_1%

PC707
220U_B2_2.5VM_R15M

NB_CORE_SW

11

NB_CORE_SNB
2

12

LL
TRIP

+NB_COREP

PJ702

+NB_COREP

+NB_CORE

@ JUMP_43X118

11

PR710
PR711
261K_0402_1% 91K_0402_1%

D
PR712
2
1PW RSEL-1
2
10K_0402_1% G
S PQ703
2N7002KW _SOT323-3

PJ703

@ JUMP_43X118

1
2

PGOOD

UG_NB_CORE
5
6
7
8

13

3
2
1

15

TP

VBST

DRVH

B+

NB_CORE_PGOOD

PR708
31.6K_0402_1%
1
2

10K_0402_1%

PR709
2
1
3

2N7002KW_SOT323-3

2
G
0.01U_0402_25V7K

PC714
2
1

11) POWER_SEL

PR707
@ 100K_0402_1%

GND

1
PC710
@ 47P_0402_50V8J
1
2

+5VALW

PR713
2
1
0_0402_5%

VFB

PC709
4.7U_0603_6.3V6K

PQ704

V5FILT

1.1V

VOUT

NB_CORE_FB 5

LOW

PL701
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2

1.0V

TON

NB_CORE_V5FILT4

HIGH

PR705
100_0603_1%
1
2

+5VALW

EN_PSV

POWER_SEL

PC701
0.1U_0402_16V7K

2BST_NB_CORE-1
1
2
PC706
0.1U_0603_25V7K

3
2
1

BST_NB_CORE
1
PR703
0_0603_5%
14

NB_CORE_EN

(33,38,44,46) VLDT_EN

NB_CORE_TON
PR701
34.8K_0402_1%
1
2

2
1
PC703
10U_1206_25V6M

2
1
PC702
10U_1206_25V6M

5
6
7
8
PQ701
SI4686DY-T1-E3_SO8
4

PR702
240K_0402_1%
1
2

@ JUMP_43X118

PC715
0.1U_0402_25V6

www.diendanlaptop.org
www.diendanlaptop.org

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/01/06

Issued Date

Deciphered Date

2010/01/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

+NB_CORE
Size Document Number
Custom
Date:

Rev
1.0

Thursday, December 10, 2009

Sheet
1

45

of

49

+1.2VALW

1
6

1
PC805
2

2
PR802
1.15K_0402_1%

APL5912-KAC-TRL_SO8

PC804
0.01U_0402_25V7K

22U_0805_6.3V6M

VIN

+1.1VSP

VCNTL

2
FB

GND

EN

@
PR803
47K_0402_5%

@ PC801
1U_0603_10V6K

PR801
0_0402_5%

VIN
VOUT
VOUT

@ RB751V-40_SOD323-2
1
2
1

VLDT_EN

POK

(33,38,44,45)

PU801
7

1
VLDT_EN

PR815
@ 0_0402_5%
1
2

+5VALW

PD801

PC803
4.7U_0805_6.3V6K

PJ801 @
JUMP_43X79

PC802
1U_0402_6.3V6K

+5VALW

PR804
3K_0402_1%

+1.8V

+5VALW

PJ802
2

+1.1VSP

PJ803
@ JUMP_43X79

PC806
@ 1U_0402_6.3V6K

+1.1VS

PJ804

PC808
@ 0.01U_0402_25V7K

+1.5VS_UMA

@ JUMP_43X79

1
1

PR806
@ 1.54K_0402_1%

VIN

@ APL5915KAI-TRL_SO8

+1.5VSP_UMA

+1.5VSP_UMA
1

FB

GND

EN

PR807
@ 47K_0402_5%

PC807
@ 4.7U_0805_6.3V6K

PC810
@ 0.1U_0402_16V7K

8
1

SUSP#

VOUT
VOUT

(18,31,33,38,41,44)

VIN

PC809
@ 22U_0805_6.3V6M

PR805
@ 10K_0402_1%
1
2

POK

PU802
@ 0_0402_5%
1
2

+5VALW

VCNTL

PR816

@ JUMP_43X118

PJ805
2

+2.5VSP

+2.5VS

@ JUMP_43X79

PR808
@ 1.74K_0402_1%

PJ807
2

+1.0VSP

+VGA_PCIE

@ JUMP_43X118

PU803
APL5508-25DC-TRL_SOT89-3
3

Park

1
2

PC811
4.7U_0805_6.3V6K

GND
PC812
1U_0402_6.3V6K

+2.5VSP

M93

VGA_PCIE

1.0V

1.1 V

PR811

4.53K

3K

OUT

@ PR809
150_1206_5%

IN

+3VS

+1.2VALW

vcc
VREF
shdw= Control,onLDO
LDO
En
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www.diendanlaptop.org

PC816
1U_0402_6.3V6K

FB
VIN

PC817
2

EN

2
9

APL5912-KAC-TRL_SO8

PR812
1.15K_0402_1%

PC813
0.01U_0402_25V7K

22U_0805_6.3V6M

PR810
@ 47K_0402_5%

+1.0VSP

PD803
RB751V-40_SOD323-2
1
2
PC814
1U_0603_10V6K

SUSP#

PC815
4.7U_0805_6.3V6K

SUSP#

(18,31,33,38,41,44)

VOUT
VOUT

15K_0402_5%
1
2

POK

VIN

PR813

VCNTL

VLDT_EN

GND

VLDT_EN

(33,38,44,45)

PU804

1
PR817
@ 0_0402_5%

PR814
@ 0_0402_5%
1
2

PD802
@ RB751V-40_SOD323-2
1
2

PJ806
JUMP_43X79
@

+5VALW

+5VALW

PR811
4.53K_0402_1%

Compal Secret Data

Security Classification

Issued Date

2009/01/06

Deciphered Date

2010/01/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

1.1V/1.5V/2.5V/1.0V
Size
Date:

Compal Electronics, Inc.


Document Number

Rev
1.0

Thursday, December 10, 2009


1

Sheet

46

of

49

CPU_B+

PL901
HCB4532KF-800T90_1812
1
2

PR902
2_0603_5%
1
2

1
2

PHASE0

PC914
2200P_0402_50V7K
2
1

PC913
10U_1206_25V6M
2
1

3
2
1

PR922
16.2K_0402_1%

5
6
7
8

PC917
0.22U_0603_10V7K
PQ902

PR920
4.7_1206_5%

PQ904
4

+5VS

UGATE1

25

BOOT1

0.1U_0402_16V7K

CPU_B+

PQ905
SI7686DP-T1-E3_SO8
UGATE1

+CPU_CORE_0
Design Current: 12.6A
Max current: 18A
OCP_min:24A

PL904
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
2

3
2
1

PR932
2.2_0603_1%
BOOT1 1
2 1

PC925
0.22U_0603_10V7K

PQ906
SI4634DY-T1-E3_SO8

PQ907
SI4634DY-T1-E3_SO8

DIFF_0

PR934
4.7_1206_5%
1 2

@ PR938 1K_0402_1%
2
1
+1.8V

DIFF_1

PC926
680P_0603_50V7K

3
2
1

PR939
10_0402_5%
1

3
2
1

VSEN1

VW0

+CPU_CORE_1

PR936
16.2K_0402_1%

+CPU_CORE_1

PHASE1

RTN1
PR935 10K_0402_1%
2
1

(6) CPU_VDD1_FB_H

PC919
2
1

ISP0

PHASE1

26

1 PR923 2
4.02K_0402_1%

LGATE0

PC922
10U_1206_25V6M
2
1

27

PC920
1U_0603_10V6K

PC918
680P_0603_50V7K

28

PC921
10U_1206_25V6M
2
1

LGATE1

29

3
2
1

30

3
2
1

LGATE0

31

PC924
2200P_0402_50V7K
2
1

32

SI4634DY-T1-E3_SO8

1 2

SI4634DY-T1-E3_SO8

ISN0

33

+CPU_CORE_0

34

UGATE0

BOOT0

PL903
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
2

2
5
6
7
8

35

PR917
2.2_0603_1%
BOOT0 1
2 1

TP

ISN1
24
ISN1

ISP1
23
ISP1

22

VW1

COMP1

FB1

21

PC915
10U_1206_25V6M
2
1

38

39

37
UGATE_NB

PHASE_NB

40

LGATE_NB

41

PGND_NB

OCSET_NB

43

44

45

42
RTN_NB

VSEN_NB

BOOT_NB

10_0402_5%
1

BOOT1

36

RTN0

5
6
7
8

(6) CPU_VDD0_FB_L

5
6
7
8

PR928
2
1
10_0402_5%

0_0402_5%
PR929
1
2

20

ISP0

14

13
ISP0
ISN0

(6) CPU_VDD1_FB_L

FSET_NB

46

UGATE1

VW0

VSEN0

PR933
2

FB_NB

COMP0

+CPU_CORE_0

COMP_NB

VCC

PGND1
PHASE1

VDIFF1

12

PVCC

FB0

19

11

LGATE0

LGATE1

ISL6265IRZ-T_QFN48_6X6~D

VDIFF0

10

(6) CPU_VDD0_FB_H

PQ903
SI7686DP-T1-E3_SO8
UGATE0

49

(6)

PC916
0.01U_0402_25V7K
2
1

5
CPU_VDDNB_FB_L

PC923
0.01U_0402_25V7K
2
1

dam bao chan nay

OCSET

PR926
1
95.3K_0402_1%

PGND0

RBIAS

8
2

PHASE0

ENABLE

2
1
21.5K_0402_1%

UGATE0

SVD
SVC

do
PR925

1 2

1
5

1
0_0402_5%

PWROK

VSEN1

VR_ON

RTN1

(33)

2
PR924

4,5

PC910
220U_D2_4VM

PHASE0

BOOT0

RTN0

CPU_SVC

CPU_B+

BOOT_NB

PGOOD

VSEN0

(6)

1
0_0402_5%

OFS/VFIXEN

15
PR927 0_0402_5%
2
1
16
0_0402_5%
2 PR930 1
17
0_0402_5%
2 PR931 1
18

2
PR921

CPU_SVD

LGATE_NB

PR912
0_0402_5%

ISN0

(6)

(6)

PC911
680P_0603_50V7K

+VDDNB
Design Current: 2.8A
Max current: 4A
OCP_min:5A

PHASE_NB

47

48
VIN

2
E

+CPU_CORE_NB

PR905
4.7_1206_5%

UGATE_NB

PU901

+
2

PHASE_NB

PR915
10_0402_5%

PR918 0_0402_5%
1
2
1
2
PR919 0_0402_5% @

(23) H_PWRGD_L

CPU_VDDNB_FB_H

PR909
11.3K_0402_1%
2
1

do

VGATE

PC909
0.22U_0603_10V7K

PR911
@ 105K_0402_1%

PR916
@ 105K_0402_1%

2
(33)

+CPU_CORE_NB

PR914
@ 10K_0402_1%

PR913
105K_0402_1%

PC912
0.1U_0603_16V7K

PR906
10_0402_5%
1
2

PR908
0_0402_5%

PR910
0_0402_5%

PL902
3.3UH_SIQB74B-3R3PF_5.9A_20%
1
2

PR903
0_0603_5%
BOOT_NB 1
2 1

PR907
2_0603_5%

+3VS

+5VS

1
2
3
4

D2
D2
G1
S1

PHASE_NB

PR904
22K_0402_1%
2
1

PC908
0.1U_0603_16V7K

CPU_B+

G2
S2/D1
S2/D1
S2/D1

AO4932_SO8
PC907
1000P_0402_50V7K
2
1

8
7
6
5

+5VS

UGATE_NB

PC902
1200P_0402_50V7K

B+
PC906
220U_25V_M

PR901
44.2K_0402_1%

PC905
2200P_0402_50V7K
2
1

PC903
10U_1206_25V6M
2
1

PQ901
2

PC904
0.01U_0402_25V7K
2
1

LGATE_NB
PC901
33P_0402_50V8J
2
1

1 PR937 2
4.02K_0402_1%

PC927
2
1
0.1U_0402_16V7K

VW1

COMP0

PC929
180P_0402_50V8J
PR942
1K_0402_5%
2
1

PR943
2

PC934
2
1

PR941
PC931
255_0402_1% 4700P_0402_25V7K
FB_1
2
1 2
1

PC930
1000P_0402_50V7K

COMP1

PC932
180P_0402_50V8J

PR944
6.81K_0402_1%
2
1

PR945
1K_0402_5%
2
1

54.9K_0402_1% 1200P_0402_50V7K

ISP1

PR940
PC928
255_0402_1% 4700P_0402_25V7K
FB_0
2
1 2
1

+CPU_CORE_1
Design Current: 12.6A
Max current: 18A
OCP_min:24A

PC933
1000P_0402_50V7K

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PR946

PC935
2
1

ISN1

LGATE1

PR947
6.81K_0402_1%
2
1

54.9K_0402_1% 1200P_0402_50V7K

Compal Secret Data

Security Classification

2009/01/06

Issued Date

Deciphered Date

2010/01/06

Title

CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size
Date:

Compal Electronics, Inc.

Document Number
Thursday, December 10, 2009

Rev
1.0
Sheet

47
1

of

49

Version change list (P.I.R. List)


Item
D

Page 1 of 1
for PWR

Reason for change

PG#

Adjust power sequence for VGA_PCIE by HW request

Change PC108 from 1000pF to 0.068uF for issue solution

Add snubber R & C and modify

Adjust power sequence

P46

boost resistor for 1.8VP

Modify List
PR831=15K

Date

Phase

2009.10.27

EVT

2009.11.17

PVT

P39

PC108=0.068uF

P43

PR512=2.2 ohm;PR513=4.7 ohm;PC524=820pF

2009.11.17

PVT

P45

PR701=34.8K,PC701=0.1uF
Un-pop PR520,PQ505

2009.12.03

PVT

5
6
C

9
10

11

12
13
14

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15
16
A

17

2009/01/06

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2009/01/06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PIR (PWR)
Size Document Number
Custom

Rev
1.0

LA-5971P

Date:

Thursday, December 10, 2009

Sheet
1

48

of

49

1. change component AP2301GN to AO3413


2. remove R521, R517, R520 and R518, and reserve U49 , U50, R995, R996, R997 and R998 for experiment Vari-bright function.
3. U6.18 add a pull up resistor R1001 and pull down resistor R1002 for check ENE KB926 version.
4. reserve R999 and R1000 for Vari-bright test.
D

5. add J8, C1031, C1032, C1033, C1034, C1035, C1036, C1037, C1038 and C1039 for EMI request.
6. Change R583, R584, R585 and R586 Bead from SM010018110 to SM010022410.
7. reserve R1003 for EMI request.
8. Change C633, C640, C662, C948, C660 and C639 to 10pF for EMI rquest.

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Compal Secret Data

Compal Electronics, Inc.

Security Classification
Issued Date

2008/10/06

Deciphered Date

2009/10/06

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

HW PIR
Size
B
Date:

Document Number

Rev
1.0

LA-5971P
Thursday, December 10, 2009

Sheet
1

49

of

49

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