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Contents:
Instruction execution timing,
Assembler instruction format,
Data transfer instructions,
Arithmetic instructions, branch instructions, looping instructions,
NOP and HLT instructions, flag manipulation instructions, logical
instructions, shift and rotate instructions,
directives and operators, programming examples.
• 20 address lines
• 16 data lines
• 4-10 control lines.
• The contents of the CS are shifted left by four. Bit 15 moves to the
Bit 19 position. The lowest four bits are filled with zeros. The
resulting value is added to the Instruction Pointer contents to make
up a 20-bit physical address. The CS makes up a segment base
address and the IP is looked as an offset into this segment.
• This segmented model also applies to all the other general registers
and segment registers in the8086 device. For example, the SS and
SP are combined in the same way to address the stack area in
physical memory.
• This scheme applies even when16-bit memories are used. It allows the 8086
to access byte data. Similar schemes allow 32-bit processors like the 80386
to access byte data.
MN/MX
CLK M/IO
8284A
READY
CLOCK INTA
RESET
GENE-
RD
RATOR
WR
8282
DT/R
LATCH
DEN
ALE ADDR
WAIT STATE
GENERATOR AD0-
AD15
A16-A19
8286
TRAN-
ADDR/DATA CEIVER
DATA
CLK
M/IO
ALE
MEMORY ACCESS TIME
ADDR/ RESERVED VALID
A15-A0
DATA FOR DATA D15-D0
ADDR/ A19-A16
STATUS
RD/INTA
READY
DT/R
DEN
15/07/08 Institute of Technology and Management, Gurgaon
WRITE CYCLE
Here we will see the activities carried out on
8086 bus at various time instants when it
writes to a port or a memory location.
Assumption that the 8086 is operated in is
minimum mode.
CLK
M/IO
ALE
ADDR/
A15-A0 DATA OUT (D15-D0)
DATA
ADDR/ A19-A16
STATUS
WR
READY
DT/R
DEN
15/07/08 Institute of Technology and Management, Gurgaon
Wait States
• Wait States are used to help interface to slow memory or I/O devices.
• The READY input signal on the 8086 is used to insert wait states into
the processor bus cycle, so that the processor stretches out its read or
write cycle, to accommodate the slow device.
Generating Wait States
• The normal memory or I/O cycle on an 8086 is 4 clocks long – T1 to
T4. Wait states , called Tw can be inserted in the bus cycle as
followsThe 8086 READY line is sampled at the rising edge of T3. If
READY is low, a WAUT state is inserted.
• During the WAIT state the READY is sampled again at the next rising
edge of the clock, and another
• WAIT is inserted if READY is still low. A number of further WAIT
states can be inserted in this way.
ODD EVEN
CS CS
BHE A1---A19 A0
D15-D8 D7-D0