VERILOG CODE FOR PARALLEL IN PARALLEL OUT SHIFT

REGISTER:
module pipo(din,clk,rst,dout);
input [3:0] din;
input clk,rst;
output [3:0] dout;
wire [3:0] din;
wire clk,rst;
reg [3:0] dout;
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
dout <= 4'b0;
end
else
begin
dout <= din;
end
end
endmodule
TEST BENCH:
module t_pipo;
reg [3:0] din;
reg clk,rst;
wire [3:0] dout;
pipo pipo_ins(din,clk,rst,dout);
initial
begin
rst = 1'b0;
clk = 1'b0;
end
always
begin
#40 clk = ~clk;
end
initial
begin
#50 rst = 1'b1;
#15 din = 4'b1010;
#95 din = 4'b1110;
#5000 $finish;
end
endmodule
FIG 4.2 WAVEFORM FOR PARALLEL IN PARALLEL OUT SHIFT REGISTER

FIG 4.3 SCHEMATIC VIEW FOR PARALLEL IN PARALLEL OUT SHIFT

REGISTER