Compal LA-8862P PDF

A
QCLA4,5
Eureka 14" & 15"
LA-8862P REV 0.2 Schematic

Intel Processor(Ivy Bridge / Sandy Bridge)
PCH(Panther Point)
2011-11-24 Rev 0.2
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/01/31
Issued Date
Deciphered Date
2012/12/31
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Cover Page
Document Number
Rev
0.2
QCLA4,5
Thursday, February 16, 2012
Sheet
E
of
48
Intel CPU
Ivy Bridge
Sandy Bridge
eDP Conn.
Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2
rPGA-989
page 13
37.5mm*37.5mm
Dual Channel
page 5,6,7,8,9,10
CRT
page 14
FDI X8
DMI X4
2.7GT/s
5GT/s
USB Right
5V 5GT/s
USB20 port 2,3

USB30 port 3,4
page 25
USB20 4x
LVDS Conn.
FingerPrinter
USB20 3x
5V 480MHz
page 15
page 40
USB20 port 0,1

USB30 port 1,2
page 30
Int. Camera
USB port 8
page 29
USB port 11
page 13
HDMI Conn.
Intel PCH
Panther Point
page 15
RJ45
USB Left
5V 480MHz
page 13
2
HDMI-CEC
page 11,12
BANK 0, 1, 2, 3
1.5V DDRIII 1066/1333/1600 MT/s
USB30 4x
EC SMBus
RTL8105E-VD 10/100M
RTL8111F-VB 1G
5V 480MHz
PCIe Gen1 1x
PCIeMini Card
WiMax USB port 9
page 27
1.5V 5GT/s
PCIe Gen1 1x
SATA Gen3 port 1
1.5V 5GT/s
5V 6GHz(600MB/s)
page 31
PCIe port 1
USB20 3x
FCBGA-989
PCIeMini Card
WLAN PCIe port 2
PCIeMini Card
3G/TV#1
TV#2
USB port 12
USB port 10
page 27
mSATA
SATA port 1
page 27
page 27
B-CAS
page 26
25mm*25mm
Cardreader
RTS5229
PCIe port4
PCIe Gen1 1x
1.5V 5GT/s
page 29
SATA Gen3 port 0
5V 6GHz(600MB/s)
SATA port 2
SATA ODD
SIM
page 27
page 16,17,18,19,20,21,22,23,24
5V 3GHz(300MB/s)
SATA port 2
page 23
SATA HDD
SATA port 0
page 23
PCIe Gen2 2x
1.5V 5GT/s
LPC BUS
HD Audio
3.3V 33 MHz
3.3V 24MHz
USB3.0 Right-side
UPD720202
HDA Codec
SPI ROM
(4MB + 2MB)
page 16
Debug Port
page 36
ALC280
ENE KB930/KB9012
USB3.0 Left-side
UPD720202
PCIe port5
page 31
PCIe port6
page 32
page 33
page 35
RTC CKT.
page 16
SPK Conn
JPIO
(HP &page
MIC)
34
page 34
DC/DC Interface CKT.
Touch Pad
page 37
page 38
Int.KBD
page 36
EC ROM
(128KB)
page 36
CIR
page 35
G-Sensor
page 36
EC SMBus
Power Circuit DC/DC

page 39,40,41,42,43,
44,45,46,47,48,49
Finger Printer/B
page 26
Power On/Off CKT.

page 37
Compal Secret Data
2010/09/03
Issued Date
Power/B
Deciphered Date
2012/12/31
Title
Size
page 37
Date:
Block Diagram
Document Number
Rev
0.2
QCLA4,5
Sheet

E
of
48
DESIGN CURRENT 0.1A

DESIGN CURRENT 0.1A
+3VL
+5VL
B+
Ipeak=10.63A, Imax=7.44A, Iocp min=12.3A
DESIGN CURRENT 11A
+5VALW
DESIGN CURRENT 1.8A
+1.8VS
DESIGN CURRENT 6.5A
+5VS
SUSP#
SY8033BDBC
SUSP
D
N-CHANNEL
BCPWON
SI4800
DESIGN CURRENT 0.1A
+5VS_L_BCAS
DESIGN CURRENT 0.4A
+5VS_LED
DESIGN CURRENT 0.3A
+3VS_HDP
DESIGN CURRENT 1.6A
+5VS_ODD
P-CHANNEL
AO-3413
KB_LED
TPS51125
P-CHANNEL
AO-3413
+5VS
LDO
G9191
ODD_EN#
P-CHANNEL
AO-3413
SYSON
Ipeak=6A, Imax=4.2A, Iocp min=8A DESIGN CURRENT 13.5A
SY8036
+1.5V
SUSP
N-CHANNEL
DESIGN CURRENT 5A
+1.5V_CPU
FDS6676AS
SUSP
C
N-CHANNEL
DESIGN CURRENT 1.5A
+1.5VS
FDS6676AS
0.75VR_EN#
DESIGN CURRENT 1A
+0.75VS
DESIGN CURRENT 6A
+VCCSA
DESIGN CURRENT 0.3A
+16VS
DESIGN CURRENT 7.5A
+3VALW
DESIGN CURRENT 0.1A
+3V_LAN
G2992
VCCPPWRGD
Ipeak=6A, Imax=4.A, Iocp min=8
SY8037
LNB EN
Imax=0.3A, Iocp min=0.8A
APW7137
Ipeak=5A, Imax=3.5A, Iocp min=6.2A

WOL_EN
P-CHANNEL
AO-3413
SUSP
N-CHANNEL
B
DESIGN CURRENT 6A
+3VS
DESIGN CURRENT 2A
+LCD_VDD
UMA_ENVDD
SI4800
P-CHANNEL
AO-3415
FELICA_PWR
DESIGN CURRENT 0.1A
P-CHANNEL
AO-3413
VR_ON
NCP6132A
+FLICA_VCC
DESIGN CURRENT 94A
+CPU_CORE
DESIGN CURRENT 50A
+GFX_CORE
DESIGN CURRENT 15A
+1.05VS_VCCP
SUSP#
TPS51212
Ipeak=14A, Imax=9.8A, Iocp min=16.92A
Issued Date
Compal Secret Data
2010/09/03
2012/12/31
Deciphered Date
5
Title
Power Tree
Size
Document Number
Rev
0.2
QFKAA
Date:
Sheet
1
of
48
Voltage Rails
( O MEANS ON
+RTCVCC
X MEANS OFF )
B+
+5VL
+5VALW
+3VL
+3VALW
+1.5V
+5VS
+3VS
+1.8VS
+VSB
power
plane
+1.5VS
1
+1.05VS
BTO Option Table
+0.75VS
+CPU_CORE
+VGA_CORE
+VTT
State
HDMI
Camera & Mic
TPM
description
HDMI
Camera & Mic
TPM
explain
HDMI
Digital MIC
Analog MIC
SLB 9635
SLB 9655
WIMAX
BTO
HDMI@
CAM@
AMIC@
TPM9635@
TPM9655@
WIMAX@
Function
+GFX_CORE
+VRAM_1.5VS
+3VS_DGPU
+1.05VS_DGPU
S1
S3
S5 S4/AC
X
X
S5 S4/ Battery only
S5 S4/AC & Battery

don't exist
Half Card
SPI ROM
Green CLK
USB 3.0
Sleep & Charge
LAN
description SPI ROM
Green CLK
USB 3.0
Sleep & Charge
LAN
Function
S0
MINI PCI-E SLOT
explain
WIN8
BTO
WIN8@
Green CLK
GCLK@
NOGCLK
NOGCLK@
Internal
10/100M
IUSB30@
Giga
8105ELDO@
8111FVB@
PCH SM Bus Address
Power
Device
HEX
+3VS
DDR SO-DIMM 0
A0 H
1010 0000 b
+3VS
DDR SO-DIMM 1
A4 H
1010 0100 b
+3VS
Clock Generator
D2 H
1101 0010 b
+3VS
New Card
+3VS
WLAN/WIMAX
+3VS
Clock Generator
+3VS
3G
Address
SIGNAL
STATE
EC SM Bus1 Address
EC SM Bus2 Address
SLP_S3# SLP_S4# SLP_S5#

HIGH
HIGH
Power
Device
HEX
Address
Power
Device
HEX
Address
S1(Power On Suspend)
HIGH
HIGH
HIGH
+3VL
Smart Battery
16 H
0001 0110 b
+3VS
PCH
96 H
1001 0110 b
S3 (Suspend to RAM)
LOW
HIGH
HIGH
+3VL
HDMI-CEC
34 H
0011 0100 b
+3VS
NVIDIA GPU
9A H
1001 1010 b
+3VS
G-Sensor
40 H
0100 0000 b
S4 (Suspend to Disk)
LOW
LOW
HIGH
+3VS
Light Sensor
52 H
0101 0010 b
S5 (Soft OFF)
LOW
LOW
LOW
G3
LOW
LOW
LOW
Power
Device
+3VL
Cap. Sensor
HEX
Address
Full ON
HIGH
Virtual I2C
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
Title
Size Document Number
Custom
Date:
Notes List
Rev
0.2
QFKAA
Sheet

E
of
48
JCPUB
100 MHz
1000P_0402_50V7K
1 CC63
PM_DRAM_PWRGD_R
1 CC62
H_PWRGOOD_R
H_SNB_IVB#
11,21 H_SNB_IVB#
C26
PROC_SELECT#
T2
+1.05VS_VCCP
31
RC44
1 62_0402_5%
1 10K_0402_5%
TP_SKTOCC#
PAD
H_PECI
H_PROCHOT#
AN34
H_CATERR#
AL33
H_PECI
AN33
SKTOCC#
CATERR#
PECI
RC159
31 H_PROCHOT#
RC45
PAD
THERMAL
T1
2 H_PROCHOT#_R
56_0402_5%
AL32
PROCHOT#
H_PWRGOOD
H_THERMTRIP#
21 H_THERMTRIP#
AN32
THERMTRIP#
CLOCKS
BCLK
BCLK#
A28
A27
CLK_CPU_DMI
CLK_CPU_DMI#
Stuff RC157 and RC158 if do not support eDP
CLK_CPU_DMI 17
CLK_CPU_DMI# 17
+1.05VS_VCCP
120 MHz
DPLL_REF_CLK
DPLL_REF_CLK#
A16
A15
CLK_CPU_EDP
CLK_CPU_EDP#
CLK_CPU_EDP#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PRDY#
PREQ#
1 CC70
1000P_0402_50V7K
1000P_0402_50V7K
H_PM_SYNC
18 H_PM_SYNC
1 CC71
H_PM_SYNC
1 CC66
BUF_CPU_RST#
AM34
PM_SYNC
RC187
21 H_PWRGOOD
PM_SYS_PWRGD_BUF
Please place near JCPU
1
RC58
2 H_PWRGOOD_R
0_0402_5%
2 PM_DRAM_PWRGD_R
130_0402_5%
AP33
V8
UNCOREPWRGOOD
SM_DRAMPWROK
BUF_CPU_RST#
AR33
RESET#
+3VALW_PCH
+3VALW_PCH
2
10K_0402_5%
2 RC13
1
+3VS
R8
H_DRAMRST#
AK1
A5
A4
SM_RCOMP_0 RC56
SM_RCOMP_1 RC59
SM_RCOMP_2 RC61
TCK
TMS
TRST#
TDI
TDO
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
H_DRAMRST# 7
2
2
2
1 140_0402_1%
1 25.5_0402_1%
1 200_0402_1%
DDR3 Compensation Signals

Layout Note:Place these
resistors near Processor
AP29
AP27
@
1
2
CC34
180P_0402_50V8J
by ESD requestion and place near CPU
AR26
AR27
AP30
XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R
AR28
AP26
XDP_TDI_R
XDP_TDO_R
AL35
1K_0402_5%
PAD
PAD
T4
T5
2
RC55
PAD T6
PAD T7
1
51_0402_5%
Layout request for test point
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
0.1U_0402_10V7K
CC33
UC1
74AHC1G09GW_TSSOP5
2
1
0_0402_5% B
2
A
TYCO_2013620-2_IVY BRIDGE
RC14
200_0402_5%
PM_SYS_PWRGD_BUF
18 DRAMPWROK
1K_0402_5%
1
RC12 @
18,31 PM_PWROK
+1.5V_CPU
DRAMPWROK
1
200_0402_5%
2
RC11
JTAG & BPM
H_PECI
PWR MANAGEMENT
RC158
H_DRAMRST#
1000P_0402_50V7K
1
RC157
CLK_CPU_EDP
SM_DRAMRST#
DDR3
MISC
1000P_0402_50V7K
MISC
SUSP
SUSP
1 2
9,34
RC25
39_0402_5%
@
2 0_0402_5%
1
RC181
2
G
QC2
2N7002_SOT23
@
FAN Control Circuit

Buffered Reset to CPU
+5VS
JFAN
1A
PLT_RST# 20,26,27,28,31,32
+FAN2
3
A
IN
OUT
GND
10mil
BUFO_CPU_RST#
RC35
43_0402_1%
1
2
1000P_0402_50V7K
1
8
7
6
5
4
5
GND
GND
ACES_85204-0300N
R24
10K_0402_5%
1
+3VS
FAN_SPEED1
APL5607KI-TRG_SO8
C17
10U_0805_6.3V6M
BUF_CPU_RST#
FAN_SPEED1
31
C14
0.01U_0402_25V7K
@
74AHC1G125GW_SOT353-5
RC40
0_0402_5%
@
EN_DFAN1
RC38
75_0402_5%
5
2
VCC
OE#
GND
GND
GND
GND
1
2
3
31
UC2
PLT_RST#
EN
VIN
VOUT
VSET
1
U1
1
2
3
4
@
2
C15
C13
10U_0805_6.3V6M
1 0.1U_0402_10V7K
CC36
+1.05VS_VCCP
1
2
3
+FAN2
+3VS
Issued Date
Compal Secret Data
2010/09/03
2012/12/31
Deciphered Date
5
Title
Sandy Bridge_JTAG/XDP/FAN
Size
Document Number
Custom
Date:
Rev
0.2
QFKAA
Sheet
1
of
48
+1.05VS_VCCP
18 DMI_CTX_PRX_N0
18 DMI_CTX_PRX_N1
18 DMI_CTX_PRX_N2
18 DMI_CTX_PRX_N3
18
18
18
18
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
18
18
18
18
18
18
18
18
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
18
18
18
18
18
18
18
18
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
18 FDI_FSYNC0
18 FDI_FSYNC1
18 FDI_INT
18 FDI_LSYNC0
18 FDI_LSYNC1
eDP_COMP signals should be

shorted near balls and
routed with typical
+1.05VS_VCCP
impedance <25m ohm
RC2
+1.05VS_VCCP
1
1
RC3
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
B28
B26
A24
B23
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
G21
E22
F21
D21
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
G22
D22
F20
C21
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
A21
H19
E19
F18
B21
C20
D18
E17
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
A22
G19
E20
G18
B20
C19
D19
F17
FDI_FSYNC0
FDI_FSYNC1
J18
J17
FDI_INT
H20
FDI_LSYNC0
FDI_LSYNC1
J19
H17
2 24.9_0402_1%
2
10K_0402_5%
A18
A17
B16
EDP_COMP
H_EDP_HPD#
C15
D15
Reserve RC3 for HW Review demand
C17
F16
C16
G15
C18
E16
D16
F15
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
eDP_AUX
eDP_AUX#
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
PCI EXPRESS* - GRAPHICS
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
B27
B25
A25
B24
DMI
18
18
18
18
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
Intel(R) FDI
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
eDP
18
18
18
18
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
J22
J21
H22
PEG_COMP
RC1
24.9_0402_1%
JCPUA
PEG_ICOMPI and RCOMPO signals should be

shorted and routed
with - max length = 500 mils - typical
impedance = 43 m ohm (4 mils)
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 m ohm (12 mils)
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
@
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
Title
Custom
Date:
Sandy Bridge_DMI/PEG/FDI
Rev
0.2
QFKAA
Sheet
1
of
48
JCPUC
11 DDR_A_D[0..63]
JCPUD
12 DDR_B_D[0..63]
11
11
11
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
AE10
AF10
V6
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
AB6
AA6
V9
DDRA_CLK0
DDRA_CLK0#
DDRA_CKE0
AA5
AB5
V10
DDRA_CLK1
DDRA_CLK1#
DDRA_CKE1
DDRA_CLK0 11
DDRA_CLK0# 11
DDRA_CKE0 11
DDRA_CLK1 11
DDRA_CLK1# 11
DDRA_CKE1 11
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
DDRA_SCS0#
DDRA_SCS1#
AH3
AG3
AG2
AH2
DDRA_ODT0
DDRA_ODT1
C4
DDR_A_DQS#0
G6 DDR_A_DQS#1
J3
DDR_A_DQS#2
M6 DDR_A_DQS#3
AL6 DDR_A_DQS#4
AM8 DDR_A_DQS#5
AR12 DDR_A_DQS#6
AM15 DDR_A_DQS#7
D4
F6
K3
N6
AL5
AM9
AR11
AM14
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDRA_SCS0#
DDRA_SCS1#
DDRA_ODT0
DDRA_ODT1
11
11
11
11
DDR_A_DQS#[0..7]
SA_CAS#
SA_RAS#
SA_WE#
11
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
SA_BS[0]
SA_BS[1]
SA_BS[2]
AE8
AD9
AF9
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
11 DDR_A_CAS#
11 DDR_A_RAS#
11 DDR_A_WE#
SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
11
11
12
12
12
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
AA9
AA7
R6
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
12 DDR_B_CAS#
12 DDR_B_RAS#
12 DDR_B_WE#
AA10
AB8
AB9
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]
RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]
SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]
DDR SYSTEM MEMORY B
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
DDR SYSTEM MEMORY A
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
AE2
AD2
R9
DDRB_CLK0
DDRB_CLK0#
DDRB_CKE0
AE1
AD1
R10
DDRB_CLK1
DDRB_CLK1#
DDRB_CKE1
DDRB_CLK0 12
DDRB_CLK0# 12
DDRB_CKE0 12
DDRB_CLK1 12
DDRB_CLK1# 12
DDRB_CKE1 12
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
DDRB_SCS0#
DDRB_SCS1#
AE4
AD4
AD5
AE5
DDRB_ODT0
DDRB_ODT1
D7
F3
K6
N3
AN5
AP9
AK12
AP15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
C7
G3
J6
M3
AN6
AP8
AK11
AP14
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDRB_SCS0#
DDRB_SCS1#
DDRB_ODT0
DDRB_ODT1
12
12
12
12
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
12
12
12
H_DRAMRST#
2
5 H_DRAMRST#
RC77
1K_0402_5%
2
SM_DRAMRST#
11,12
BSS138_NL_SOT23-3
2
RC78
4.99K_0402_1%
RC76
1K_0402_5%
QC3
1
DDR3_DRAMRST#_R
RC75
0_0402_5%
1
2
@
+1.5V
1
RC73
1
RC74
11,17 DRAMRST_CNTRL_PCH
31 DRAMRST_CNTRL_EC
2 DRAMRST_CNTRL
0_0402_5%
2
0_0402_5%
Issued Date
Compal Secret Data
CC37
0.047U_0402_25V6K
2010/09/03
2012/12/31
Deciphered Date
Title
Sandy Bridge_DDR3
Size
Document Number
Custom
Date:
Rev
0.2
QFKAA
Sheet

1
of
48
PEG AND DDR
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
SVID
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
1
1
RC90 1
RC88 1
RC92
0.1U_0402_10V7K
1
2
CC49
@
RC89
75_0402_5%
AJ29
AJ30
AJ28
RC91
130_0402_5%
VIDALERT#
VIDSCLK
VIDSOUT
2
2 43_0402_1%
2 0_0402_5%
0_0402_5%
VR_SVID_ALRT# 42
VR_SVID_CLK 42
VR_SVID_DAT 42
Pull high resistor on VR side
+CPU_CORE
Close to CPU
RC93
100_0402_1%
AJ35 VCCSENSE_R
AJ34 VSSSENSE_R
RC94 1
RC95 1
2 0_0402_5%
2 0_0402_5%
42
42
B10
A10
VCCIO_SENSE
VCCIO_SENSE
RC96
10_0402_1%
RC98
10_0402_1%
RC97
100_0402_1%
39
VCCIO_SENSE
VSS_SENSE_VCCIO
+1.05VS_VCCP
Issued Date
Compal Secret Data
2010/09/03
2012/12/31
Deciphered Date
5
VCCSENSE
VSSSENSE
1
VCC_SENSE
VSS_SENSE
Close to CPU
+1.05VS_VCCP
+1.05VS_VCCP
0.1U_0402_10V7K
1
2
CC50
@
SENSE LINES
8.5A
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
CORE SUPPLY
+1.05VS_VCCP
97A
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
POWER
JCPUF
+CPU_CORE
Title
Sandy Bridge_POWER-1
Size
Document Number
Custom
Date:
Rev
0.2
QFKAA
Sheet

1
of
48
+GFX_CORE
+GFX_CORE
POWER
JCPUG
RC105
10_0402_1%
2
1
0_0805_5%
10U_0805_10V6K
+1.8VS_VCCPLL
1
+
CC58
@
2
330U_B2_2.5VM_R15M
CC59
CC60
1U_0402_6.3V6K
B6
A6
A2
SENSE
LINES
VREF
DDR3 -1.5V RAILS
SA RAIL
1.5A
VCC_AXG_SENSE
VSS_AXG_SENSE
VCC_AXG_SENSE
VSS_AXG_SENSE
42
42
1 RC106 2
10_0402_1%
+V_SM_VREF should
have 20 mil trace width
AL1
+1.5V_CPU
RC120
1 1K_0402_0.5%
2
+V_SM_VREF
1 1K_0402_0.5%
2
RC109
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
B4
D1
CC65
0.1U_0402_10V7K
2
+VREF_DQA_M3
+VREF_DQB_M3
+1.5V_CPU Decoupling:
1X 330U (6m ohm), 6X 10U
5A
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
6A
VCCPLL Decoupling:
1X 330U (6m ohm), 1X 10U, 2x1U
RC119
AK35
AK34
+1.5V_CPU
VCCPLL1
VCCPLL2
VCCPLL3
CC61
1U_0402_6.3V6K
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
1 ESR
CC55
CC56
CC51
10U_0805_10V6K
CC57
CC52
10U_0805_10V6K
CC53
6mohm
CC54
@
330U_D2_2VM_R6M
10U_0805_10V6K
C
+VCCSA Decoupling:
1X 330U (6m ohm), 3X 10U
+VCCSA
Bottom Socket Cavity

M27
M26
L26
J26
J25
J24
H26
H25
10U_0805_10V6K
CC40
CC41
CC42
VCCSA_VID0
CC43
1
1 RC189
1
+
Co-lay for Cost Down Plan
10U_0805_10V6K
2
2
10U_0805_10V6K
2+VCCSA_SENSE
0_0402_5%
CC44
@
330U_D2_2VM_R6M
10U_0805_10V6K
Bottom Socket Edge

VCCSA_SENSE
H23
+VCCSA_SENSE
1 RC111
0_0402_5% @
MISC
+1.8VS
VAXG_SENSE
VSSAXG_SENSE
SM_VREF
GRAPHICS
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
1.8V RAIL
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
Close to CPU
33A
VCCSA_VID[0]
VCCSA_VID[1]
VCCIO_SEL
C22
C24
H_VCCSA_VID0
H_VCCSA_VID1
VCCSA_VID1
+VCCSA
0.90 V
0.80 V
0.75 V
0.65 V
For Sandy Bridge
41
H_VCCSA_VID0
H_VCCSA_VID1
41
Please
kindly check whether
41
pull down by 10k in PWR-Side
A19
@
+1.5V_CPU
+1.5V_CPU
+1.5VS
PJ1
+1.5V
JUMP_43X118
+1.5V
Vgs=10V,Id=14.5A,Rds=6mohm
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
CC45 1
2 0.1U_0402_10V7K
RC192
470_0805_5%
CC68
10U_0805_10V6K
8
7
6
5
QC5B
CC69
0.1U_0402_25V6
1U_0402_6.3V6K
1
2
C469
4.7U_0805_10V4Z
RC193
1
2
220K_0402_5%
RC194
820K_0402_5%
+VSB
QC5A
2
1
2
4
SUSP
D
D
D
D
FDS6676AS_SO8
RUN_ON_CPU1.5VS3
2N7002DW-T/R7_SOT363-6
S
S
S
G
2 0.1U_0402_10V7K
CC48 1
3 1
CC47 1
C463
1
2
QC4
1
2
3
4
CC46 1
C464
4.7U_0805_10V4Z
1
2
SUSP
SUSP
5,34
2N7002DW-T/R7_SOT363-6
Issued Date
Compal Secret Data
2010/09/03
2012/12/31
Deciphered Date
5
Title
Sandy Bridge_POWER-2
Size
Document Number
Custom
Date:
Rev
0.2
QFKAA
Sheet

1
of
48
VSS
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29
CFG4
AJ31
AH31
AJ33
AH33
AJ26
F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29
J20
B18
J15
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
(CFG[17:0] internal pull high to VCCIO)
VCC_DIE_SENSE
VSS_DIE_SENSE
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
PAD T3
L7
AG7
AE7
AK2
D
W8
AT26
AM33
AJ27
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
RSVD37
RSVD38
RSVD39
RSVD40
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
1: Normal Operation; Lane #

socket pin map definition
definition matches
0:Lane Reversed
T8
J16
H16
G16
CFG4
RC82
1K_0402_1%
@
RSVD5
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
AH27
AH26
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
CFG Straps for Processor
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
Embedded Display Port Presence Strap

RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
RSVD_NCTF10
RSVD51
RSVD52
BCLK_ITP
BCLK_ITP#
RSVD24
RSVD25
RSVD27
AR35
AT34
AT33
AP35
AR34
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
JCPUE
RESERVED
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
JCPUI
CFG
JCPUH
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
KEY
B34
A33
A34
B35
C35
*
CFG4
1 : Disabled; No Physical Display Port

attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
AJ32
AK32
AN35
AM35
AT2
AT1
AR1
B1
PAD T64
PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
*10: x8, x8 - Device 1 function 1 enabled ; function 2
@
CFG[6:5]
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PEG DEFER TRAINING
CFG7
1: (Default) PEG Train immediately following xxRESETB

de assertion
0: PEG Wait for BIOS for training
Issued Date
Compal Secret Data
2010/09/03
2012/12/31
Deciphered Date
Title
Sandy Bridge_GND/RSVD/CFG
Custom
Date:
Rev
0.2
QFKAA
Sheet
1
10
of
48
+1.5V
JDDR3L
DDRA_CKE0
DDR_A_BS2
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
7
7
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK0
DDRA_CLK0#
DDR_A_BS0
7
7
DDR_A_WE#
DDR_A_CAS#
DDRA_SCS1#
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDRA_SCS1#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
CD25
1
CD26
2.2U_0603_6.3V4Z
+3VS
+0.75VS
RD9
10K_0402_5%
0.1U_0402_10V7K
DDR_A_D58
DDR_A_D59
2
RD8 1
10K_0402_5%
205
207
GND1
BOSS1
GND2
BOSS2
1
2
+VREF_DQA
RD2
1K_0402_1%
2
BSS138_NL_SOT23-3
QC7
3
1
+VREF_DQA_M3
DDR_A_D22
DDR_A_D23
2
@ 1
0_0402_5%
RC115
DDR_A_D20
DDR_A_D21
DDR_A_D28
DDR_A_D29
+VREF_DQA
RH100
2
DDR_A_DQS#3
DDR_A_DQS3
DRAMRST_CNTRL_PCH
7,17
+1.5V
10K_0402_5%
1
DDR_A_D30
DDR_A_D31
+VREF_DQB_M3
RD10
1K_0402_1%
+VREF_DQB
DDRA_CKE1
DDRA_CKE1
DDR_A_MA15
DDR_A_MA14
2
@ 1
0_0402_5%
RC116
DDR_A_MA11
DDR_A_MA7
2
G
QC9
BSS138_NL_SOT23-3
QC8
BSS138_NL_SOT23-3
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
H_SNB_IVB#
+VREF_DQB
C
RD11
1K_0402_1%
5,21
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDRA_CLK1
DDRA_CLK1#
DDR_A_BS1
DDR_A_RAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1
+1.5V
DDRA_CLK1 7
DDRA_CLK1# 7
DDR_A_BS1 7
DDR_A_RAS# 7
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
2
33P_0402_50V8K
1
CD52
2
33P_0402_50V8K
1
CD53
2
33P_0402_50V8K
1
CD54
2
33P_0402_50V8K
1
CD55
2
33P_0402_50V8K
RD6
1K_0402_1%
DDRA_ODT1 7
+VREF_CAA_DIMMA
DDR_A_D36
DDR_A_D37
DDR_A_D44
DDR_A_D45
2
33P_0402_50V8K
1
CD51
DDRA_SCS0# 7
DDRA_ODT0 7
+VREF_CAA
DDR_A_D38
DDR_A_D39
1
CD50
+1.5V
RD7
1K_0402_1%
CD15
CD16
0.1U_0402_10V7K
DDR_A_D40
DDR_A_D41
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
Intel DDR Vref M3
DDR_A_D14
DDR_A_D15
2.2U_0603_6.3V4Z
DDR_A_D34
DDR_A_D35
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
SM_DRAMRST# 7,12
7
7
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
RD1
1K_0402_1%
SM_DRAMRST#
DDRA_CKE0
+1.5V
DDR_A_D12
DDR_A_D13
DDR_A_D26
DDR_A_D27
DDR_A_D6
DDR_A_D7
DDR_A_D24
DDR_A_D25
DDR_A_MA[0..15]
DDR_A_D18
DDR_A_D19
DDR_A_D[0..63]
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_DQS#[0..7]
DDR_A_D16
DDR_A_D17
DDR_A_DQS[0..7]
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D10
DDR_A_D11
DDR_A_D4
DDR_A_D5
DDR_A_DQS#1
DDR_A_DQS1
Close to JDDRL.1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
DDR_A_D8
DDR_A_D9
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
DDR_A_D2
DDR_A_D3
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
Layout Note:
Place near JDDRL
close to JDDRL.126
Layout Note: Place these 4 Caps near

Command and Control signals of DIMMA
Layout Note:
Place near JDDRL1.203 and 204
+1.5V
+1.5V
DDR_A_D52
DDR_A_D53
1
CD7
DDR_A_D54
DDR_A_D55
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DDR_A_D0
DDR_A_D1
2.2U_0603_6.3V4Z
0.1U_0402_10V7K
CD2
CD1
+VREF_DQA
DDR3 SO-DIMM A
Reverse Type
+1.5V
2 10U_0603_6.3V6M
CD9
2 10U_0603_6.3V6M
CD10 1
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
+0.75VS
2
330U_2.5V_M
CD8
CD20 1
2 0.1U_0402_10V7K
CD17 1
2 0.1U_0402_10V7K
CD18 1
2 0.1U_0402_10V7K
CD19 1
2 0.1U_0402_10V7K
2 10U_0603_6.3V6M
CD56 1
2 10U_0603_6.3V6M
CD24 2
1 1U_0402_6.3V6K
CD21 2
1 1U_0402_6.3V6K
CD11 1
2 10U_0603_6.3V6M
CD22 2
1 1U_0402_6.3V6K
CD12 1
2 10U_0603_6.3V6M
CD23 2
1 1U_0402_6.3V6K
CD13 1
2 10U_0603_6.3V6M
PM_SMBDATA
PM_SMBCLK
PM_SMBDATA 12,17,26
PM_SMBCLK 12,17,26
+0.75VS
206
208
Compal Secret Data
2010/09/03
Issued Date
LCN_DAN06-K4406-0103
@
Deciphered Date
2012/12/31
4
Title
DDRIII-SODIMM0
Custom
Date:
Rev
0.2
QFKAA
Sheet
1
11
of
48
+1.5V
+1.5V
JDDR3H
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
Close to JDDRH.1
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDRB_CKE0
DDR_B_BS2
DDRB_CKE0
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
7
7
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK0
DDRB_CLK0#
DDR_B_BS0
7
7
DDR_B_WE#
DDR_B_CAS#
DDRB_SCS1#
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDRB_SCS1#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
2
RD14 1
10K_0402_5%
+3VS
2.2U_0603_6.3V4Z
1
@
CD48
1 RD15
2
10K_0402_5%
CD49
2
0.1U_0402_10V7K
+0.75VS
205
207
GND1
GND2
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
BOSS1
BOSS2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
SM_DRAMRST#
DDR_B_DQS[0..7]
DDR_B_D[0..63]
DDR_B_MA[0..15]
7
7
SM_DRAMRST# 7,11
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDRB_CKE1
DDRB_CKE1
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDRB_CLK1
DDRB_CLK1#
DDR_B_BS1
DDR_B_RAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1
DDRB_CLK1 7
DDRB_CLK1# 7
+1.5V
DDR_B_BS1 7
DDR_B_RAS# 7
DDRB_SCS0# 7
DDRB_ODT0 7
RD12
1K_0402_1%
DDRB_ODT1 7
+VREF_CAB
+VREF_CAB_DIMMB
DDR_B_D36
DDR_B_D37
RD13
1K_0402_1%
CD46
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
CD47
1
3
Layout Note:
Place near JDDRH
Layout Note: Place these 4 Caps near

Command and Control signals of DIMMB
Layout Note:
Place near JDDRH.203 and 204
Close to JDDRH.126
+1.5V
DDR_B_D52
DDR_B_D53
+1.5V
@
CD31 1
DDR_B_D54
DDR_B_D55
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
+0.75VS
2 330U_B2_2.5VM_R15M
CD41 1
2 10U_0603_6.3V6M
CD36 1
2 10U_0603_6.3V6M
CD37 1
DDR_B_D60
DDR_B_D61
CD33 1
2 0.1U_0402_10V7K
CD29 1
2 0.1U_0402_10V7K
CD30 1
2 0.1U_0402_10V7K
CD32 1
2 0.1U_0402_10V7K
2 10U_0603_6.3V6M
CD57 1
2 10U_0603_6.3V6M
CD45 2
1 1U_0402_6.3V6K
CD42 2
1 1U_0402_6.3V6K
CD38 1
2 10U_0603_6.3V6M
CD43 2
1 1U_0402_6.3V6K
CD39 1
2 10U_0603_6.3V6M
CD44 2
1 1U_0402_6.3V6K
CD40 1
2 10U_0603_6.3V6M
PM_SMBDATA
PM_SMBCLK
PM_SMBDATA 11,17,26
PM_SMBCLK 11,17,26
+0.75VS
206
208
Compal Secret Data
2010/09/03
Issued Date
FOX_AS0A626-UASN-7F_204P
@
DDR_B_DQS#[0..7]
DDR_B_D12
DDR_B_D13
0.1U_0402_10V7K
DDR_B_D40
DDR_B_D41
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
Reverse Type
DDR3 SO-DIMM B
DDR_B_D4
DDR_B_D5
2.2U_0603_6.3V4Z
DDR_B_D34
DDR_B_D35
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CD27
0.1U_0402_10V7K
2.2U_0603_6.3V4Z
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
CD28
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DDR_B_D0
DDR_B_D1
+VREF_DQB
Deciphered Date
2012/12/31
B
Title
DDRIII-SODIMM1
Custom
Date:
Rev
0.2
QFKAA
Sheet
E
12
of
48
LCD_TXCLK+
+3VS
3
1
Q17
AO3413_SOT23
5
2
19 UMA_ENVDD
+LCD_VDD
W=80mils
Q1B
2N7002DW-T/R7_SOT363-6
R112
100K_0402_5%
C233
0.1U_0402_10V7K
AZ5125-02S.R7G_SOT23-3
INT_MIC_CLK
INT_MIC_DATA
W=80mils
1 2
1
R110 2LCDPWR_GATE
47K_0402_5%
1
C230
0.01U_0402_25V7K
1
3
D84
@
USB20_N11_R
USB20_P11_R
C228
0.1U_0402_10V7K
JLVDS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
@
C256 47P_0402_50V8J
2
CAM@
0.1U_0402_10V7K
1
2
C225
2
W=20mils
1 CAM@ 2 +3VS_LVDS_CAM
R388
0_0603_5%
+3VS
+3VS
R108
100K_0402_5%
Q1A
2N7002DW-T/R7_SOT363-6
INT_MIC_CLK 30
INT_MIC_DATA 30
2A
+LCD_VDD
LCD_EDID_CLK
LCD_EDID_DATA
+3VS
LCD_TXOUT0LCD_TXOUT0+
C226
0.1U_0402_10V7K
C227
4.7U_0805_10V4Z
C258
47P_0402_50V8J
@
C248
0.1U_0402_10V7K
Reserve for EMI request

2
For RF
LED_PWM
1
D17
2
RB751V40_SC76-2
USB20_P11_R
USB20_N11_R
PCH_PWM 19
R131
47K_0402_5%
BKOFF#_R
1.5A
+LCD_INV
2
@
C257 47P_0402_50V8J
1
2
R78 CAM@ 0_0402_5%
WCM-2012-900T_0805
3
4
3
1
L55 @
USB20_P11 20
USB20_N11 20
1
2
R96 CAM@ 0_0402_5%
LCD_TXCLKLCD_TXCLK+
LED_PWM
BKOFF#_R
1
D15
2
RB751V40_SC76-2
BKOFF# 31
R113
10K_0402_5%
STARC_107K30-000001-G2
GND1
GND2
GND3
GND4
GND5
GND6
LCD_TZCLK-
19 LCD_TZCLK-
For RF
31
32
33
34
35
36
R109
150_0603_5%
LCD_TZCLK+
LCD_EDID_DATA
19 LCD_EDID_DATA
LCD_TZOUT2-
LCD_EDID_CLK
19 LCD_EDID_CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
19 LCD_TZOUT219 LCD_TZCLK+
LCD_TXCLK-
19 LCD_TXCLK-
19 LCD_TZOUT2+
LCD_TZOUT2+
LCD_TXOUT2-
+LCD_VDD
LCD_TZOUT1-
19 LCD_TZOUT1-
19 LCD_TXOUT219 LCD_TXCLK+
19 LCD_TXOUT2+
LCD_TXOUT2+
19 LCD_TXOUT1-
LCD_TZOUT1+
19 LCD_TZOUT1+
LCD_TXOUT1-
LCD_TZOUT0-
19 LCD_TZOUT0-
LCD_TXOUT1+
19 LCD_TXOUT1+
LCD_TZOUT0+
19 LCD_TZOUT0+
LCD_TXOUT0-
19 LCD_TXOUT0-
LCD_TXOUT0+
19 LCD_TXOUT0+
JLVDS1
LVDS cable JLVDS1.2 need to contact GND

LVDS_SEL 17
B+
1.5A
For EMI
+LCD_INV
C234
68P_0402_50V8J
B+
L2
2
1
1 FBMA-L11-201209-221LMA30T_0805
C235
0.1U_0402_25V6
2
1
C247
@
1
C269
@
1
C489
@
1
C490
@
0.1U_0402_25V6
ACES_87036-1001-CP
@
0.1U_0402_25V6
LCD_TZOUT0LCD_TZOUT0+
LCD_TZCLKLCD_TZCLK+
0.1U_0402_25V6
12
11
10
9
8
7
6
5
4
3
2
1
GND
GND
10
9
8
7
6
5
4
3
2
1
0.1U_0402_25V6
Issued Date
Compal Secret Data
2010/09/03
Deciphered Date
2012/12/31
Title
Custom
Date:
LVDS/eDP

G
Rev
0.2
QFKAA
Sheet
of
13
H
48
CRT CONNECTOR
If=1A
+5VS
+CRT_VCC_R
+CRT_VCC
D6
F1
40 mils
1
1
2
RB491D_SOT23-3
1
0.5A_8V_KMC3S050RY
C237
0.1U_0402_10V7K
2
@
19
UMA_CRT_R
19
UMA_CRT_G
1
R189
1
R190
1
R191
19 UMA_CRT_B
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
CRT_R_R
L3
2 NBQ100505T-800Y_0402
CRT_R_L
CRT_G_R
L4
2 NBQ100505T-800Y_0402
CRT_G_L
CRT_B_R
L5
2 NBQ100505T-800Y_0402
CRT_B_L
C240
1
C241
1
C242
1
C243
CRT_R_L
2.2P_0402_50V8C
C239
2.2P_0402_50V8C
1
C238
2.2P_0402_50V8C
2.2P_0402_50V8C
1
C251
@
2.2P_0402_50V8C
2.2P_0402_50V8C
1
C250
@
2.2P_0402_50V8C
2.2P_0402_50V8C
2
1
150_0402_1%
2
1
150_0402_1%
2
1
150_0402_1%
1
C249
@
2.2P_0402_50V8C
JCRT
R138 R139 R140
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
T65 PAD
CRT_DDC_DAT
CRT_G_L
HSYNC
CRT_B_L
+CRT_VCC
VSYNC
CHP3_SERDBG
21 CHP3_SERDBG
By EMI demand
CRT_DDC_CLK
G
G
16
17
+CRT_VCC
SUYIN_070546FR015S251ZR
@
1
C244
2
0.1U_0402_10V7K
2
R141
1
10K_0402_5%
1
L6
D_CRT_HSYNC
19 UMA_CRT_HSYNC
P
OE#
5
1
U6
SN74AHCT1G125GW_SOT353-5
2
10_0402_5%
HSYNC
+CRT_VCC
D98
1
L7
D_CRT_VSYNC
2
10_0402_5%
C245
@
1
C246
@
+CRT_VCC
VSYNC
10P_0402_50V8J
U7
10P_0402_50V8J
19 UMA_CRT_VSYNC
I/O4
I/O2
CRT_B_L
5
1
CRT_R_L
P
OE#
1
2
C252
0.1U_0402_10V7K
CRT_G_L
CRT_DDC_DAT
+3VS
I/O1
CHP3_SERDBG
I/O4
I/O2
VDD
GND
I/O3
I/O1
HSYNC
VSYNC
2/9: Add for ESD request
R159
4.7K_0402_5%
2
5
C282
33P_0402_50V8K
@
I/O3
AZC099-04S.R7G_SOT23-6
R153
4.7K_0402_5%
19 UMA_CRT_DATA
+CRT_VCC
+CRT_VCC
Q205B
4
GND
D97
Q205A
1
VDD
CRT_DDC_CLK
19 UMA_CRT_CLK
CRT_DDC_CLK
2N7002DW-T/R7_SOT363-6
CRT_DDC_DAT
2N7002DW-T/R7_SOT363-6
C285
33P_0402_50V8K
2@
C284
470P_0402_50V8J
@
C283
470P_0402_50V8J
2@
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
Title
Size
Date:
CRT
Document Number
Rev
0.2
QFKAA
Sheet
E
14
of
48
+3VS
+HDMI_5V_OUT
+HDMI_5V_OUT
2 0.1U_0402_10V7K HDMI@
CV305
2 0.1U_0402_10V7K HDMI@
UMA_DVI_TXC1
4
UMA_DVI_TXC+
1
2
@
R157
0_0402_5%
L8
HDMI@
2
1
2
4
1
@
R175
L9
UMA_DVI_TXD03
UMA_DVI_TXD1+
3
19 UMA_HDMI_DATA
UMA_DVI_TXD1-
UMA_DVI_TXD2+
2
0_0402_5%
HDMI@
4
4
UMA_DVI_TXD0+
5
P
C265
0.1U_0402_10V7K
HDMI@
HDMI_SCLK
Q18
BSH111_SOT23-3
HDMI@
HDMI_SDATA
UMA_DVI_TXD2-
HDMI@
2
1
R571
2.2K_0402_5%
HDMI_R_CK+ 1 HDMI@ 2
R195
680_0402_1%
HDMI_R_CK- 1 HDMI@ 2
R197
680_0402_1%
HDMI_R_D1- 1 HDMI@ 2
R198
680_0402_1%
HDMI_R_D1+ 1 HDMI@ 2
R202
680_0402_1%
R201
680_0402_1%
R203
680_0402_1%
R205
680_0402_1%
R206
680_0402_1%
HDMI_R_CK-
D95
HDMI_R_D1- 1 1
HDMI_R_CK+
@
10 9 HDMI_R_D1-
HDMI_R_D1+2 2
9 8
HDMI_R_D2- 4 4
7 7 HDMI_R_D2-
HDMI_R_D2+5 5
6 6
HDMI_R_D1+
HDMI_R_D0HDMI_R_D2+
+3VS
HDMI_HPD
HDMI@
D53
+5VS
HDMI_HPD 19
F2
2
+HDMI_5V_OUT_F 1
+HDMI_5V_OUT
0.5A_8V_KMC3S050RY
1
HDMI@
C259
HDMI@
0.1U_0402_10V7K
2
PMEG2010AEH_SOD123
2
G
+5VS
3 3
2
HDMI@
Q19
BSH111_SOT23-3
HDMI@
WCM-2012HS-670T_0805
1
2
@
R173
0_0402_5%
CV307
2 0.1U_0402_10V7K HDMI@
UMA_DVI_TXD0+
UMA_DVI_TXD0-
2 0.1U_0402_10V7K HDMI@
19 UMA_HDMI_CLK
CV301
UMA_DVI_TXC-
CV303
2 0.1U_0402_10V7K HDMI@
HDMI_HPD_C
R186
100K_0402_5%
HDMI@
HDMI_HPD
2 0.1U_0402_10V7K HDMI@
R185
2.2K_0402_5%
HDMI@
U9
19 UMA_HDMI_TX2-
2 0.1U_0402_10V7K HDMI@
CV302
19 UMA_HDMI_TX119 UMA_HDMI_TX2+
CV306
19 UMA_HDMI_TX1+
CV304
UMA_DVI_TXC+
19 UMA_HDMI_TX0-
2 0.1U_0402_10V7K HDMI@
1
2
19 UMA_HDMI_TX0+
R184
2.2K_0402_5%
HDMI@
G
19 UMA_HDMI_TXC-
CV308
19 UMA_HDMI_TXC+
HDMI@
R145
2
HDMI_HPD_U 1
1K_0402_5%
OE#
C264
0.1U_0402_10V7K
HDMI@
Q24
2N7002_SOT23-3
HDMI@
WCM-2012HS-670T_0805
1
2
@
R180
0_0402_5%
HDMI Connector
HDMI_R_D0+
AZ1045-04F_DFN2510P10E-10-9
JHDMI
HDMI_HPD_C
UMA_DVI_TXD1-
1
2
@
R182
0_0402_5%
L10
HDMI@
1
2
1
2
HDMI_R_D1-
+HDMI_5V_OUT
D94
HDMI_R_CK+1 1
10 9
HDMI_SDATA
HDMI_SCLK
HDMI_R_CK+
D96
HDMI_R_CK- 2 2
4
9 8 HDMI_R_CK-
HDMI_HPD_C
WCM-2012HS-670T_0805
1
2
@
R183
0_0402_5%
UMA_DVI_TXD1+
HDMI_R_D1+
HDMI_R_D0+4 4
7 7
HDMI_R_D0+
HDMI_R_D0- 5 5
6 6
HDMI_R_D0-
+5VS
I/O4
I/O2
VDD
GND
I/O3
I/O1
HDMI_SDATA
HDMI_R_CKHDMI_R_CK+
HDMI_R_D0-
3 3
1
@
R187
L11
UMA_DVI_TXD23
2
UMA_DVI_TXD2+
2
0_0402_5%
HDMI@
4
4
HDMI_R_D0+
HDMI_R_D1-
HDMI_R_D2-
+HDMI_5V_OUT
HDMI_SCLK
HDMI_R_D1+
HDMI_R_D2-
AZ1045-04F_DFN2510P10E-10-9
HDMI_R_D2+
WCM-2012HS-670T_0805
1
2
@
R188
0_0402_5%
20
21
22
23
HDMI_R_D2+
Issued Date
Compal Secret Data
2010/09/03
2012/12/31
Deciphered Date
Title
Size
Date:
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
HONGL_13-13201904CP
@
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HDMI Conn./CEC
Document Number
Rev
0.2
QFKAA
Sheet

1
15
of
48
UH1A
PCH_SPKR
30 AZ_RST_HD#
+RTCVCC
2 33_0402_5%
RH30 1
2 33_0402_5%
2
1M_0402_5%
2
330K_0402_5%
RH33 1
+3VS
N34
AZ_SYNC
L34
PCH_SPKR
T10
AZ_RST#
K34
E34
SM_INTRUDER#
G34
PCH_INTVRMEN
C34
PCH_SPK
High = Enabled (No Reboot)
Low = Disabled (Default)
1
RH36
AZ_BITCLK
AZ_SDIN0_HD
30 AZ_SDIN0_HD
RH12 1
C17
2
1K_0402_5%
PCH_SPKR
+3VALW_PCH
30 AZ_SDOUT_HD
31 PWRME_CTRL
2
RH272
1
1K_0402_5%
RH32 1
2 33_0402_5%
RH25 1
2 0_0402_5%
A34
AZ_SDOUT
A36
C36
N32
HDA_SDO
INTVRMEN
J3
PCH_JTAG_TMS
H7
PCH_JTAG_TDI
K5
PCH_JTAG_TDO
H1
LPC
SERIRQ
HDA_SYNC
SPKR
HDA_RST#
HDA_SDIN0
HDA_SDIN2
HDA_SDIN3
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
HDA_SDIN1
HDA_SDO
HDA_DOCK_EN# / GPIO33
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
HDA_DOCK_RST# / GPIO13
JTAG_TCK
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
JTAG_TMS
SATAICOMPO
JTAG_TDI
JTAG_TDO
JTAG
PCH_JTAG_TCK
LDRQ0#
LDRQ1# / GPIO23
HDA_BCLK
8/30 Change PWRME_CTRL# to HDA_SDO by PCH EDS
ME debug mode,
this signal has a weak internal pull down
= Disable (default)
*Low
High = Enable (flash descriptor security overide)
SATAICOMPI
SATA3RCOMPO
HDA_SYNC
signal has a weak internal pull

*This
H=>On Die PLL is supplied by 1.5V
down
26 PCH_RTCX1_R
L=>On Die PLL is supplied by 1.8V

Need to pull high for Huron River platform
2
RH55
+3VALW_PCH
RH26 GCLK@
1
2
PCH_RTCX1
0_0402_5%
Placement near to YH1
1
1K_0402_5%
2
1M_0402_5%
T3
PCH_SPICS0#
Y14
PCH_SPICS1#
T1
PCH_SPIDI
V4
PCH_SPIDO
U3
SPI_CLK
SATA3RBIAS
D36
LPC_FRAME#
LPC_FRAME# 28,31,32
+3VS
E36
K36
V5
AM3
AM1
AP7
AP5
SERIRQ
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
2
RH31
SERIRQ
SERIRQ 28,31
SATA_PRX_C_DTX_N0 25
SATA_PRX_C_DTX_P0 25
SATA_PTX_DRX_N0 25
SATA_PTX_DRX_P0 25
1
10K_0402_5%
AD7
AD5
AH5
AH4
SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2
SATA_PTX_DRX_N2 25
SATA_PTX_DRX_P2 25
ODD
PCH_GPIO21
RH34 2
1 10K_0402_5%
PCH_GPIO19
RH28 1
2 10K_0402_5%
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
+RTCVCC
+RTCBATT
Y3
Y1
AB3
AB1
Y11
Y10
SATAICOMP
1
RH43
2
37.4_0402_1%
+1.05VS_VCC_SATA
SATA3_COMP
1
RH48
2
49.9_0402_1%
+1.05VS_SATA3
1
RH41
2
750_0402_1%
DH7
RB751V-40_SOD323-2
+RTCBATT
+3VL
AB12
AB13
AH1
RBIAS_SATA3
P3
SATA_LED#
V14
PCH_GPIO21
SPI_MOSI
P1
PCH_GPIO19
If use GCLK, please delet DH1
SPI_CS0#
SPI_CS1#
+3VS
HDD
AM10
AM8
AP11
AP10
+5VS
SATA_LED#
SPI_MISO
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
SATA_LED# 33
PCH_GPIO19
2
10K_0402_5%
1
20K_0402_5%
1
RH29
2
RH35
20
BOOT BIOS Strap Bit 0
PANTHER-POINT_FCBGA989
PCHB0@
1
RH56
QH1
1
3
S
30 AZ_SYNC_HD
2
AZ_SYNC_R
33_0402_5%
PCH_SPICLK
AZ_SYNC
+5VS
1
RH54
SATA3COMPI
SPI
INTRUDER#
30
RH27 1
PCH_INTVRMEN
SRTCRST#
30 AZ_BITCLK_HD
Integrated SUS 1.05V VRM Enable

High - Enable Internal VRs
PCH_INTVRMEN (must be always pulled high)
K22
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
FWH4 / LFRAME#
DH1 NOGCLK@
1
NOGCLK@
G22
SM_INTRUDER#
RTCRST#
28,31,32
28,31,32
28,31,32
28,31,32
CH101
10P_0402_50V8J
PCH_SRTCRST#
RTCX2
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
RB751V-40_SOD323-2
1
15P_0402_50V8J
RTCX1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
CH8
@
CH5 1
1U_0402_6.3V6K
2
CH3
D20
C38
A38
B37
C37
0.1U_0402_10V7K
@
2
C20
PCH_RTCRST#
SATA 6G
JME
1
2PCH_SRTCRST#
PCH_RTCX2
RTC
RH24 1
20K_0402_5%
YH1
32.768KHZ_12.5P_1TJF125DP1A000D
NOGCLK@
AZ_BITCLK_HD
A20
IHDA
iME Setting.
NOGCLK@
PCH_RTCX1
SATA
CH4 1
1U_0402_6.3V6K
NOGCLK@
PCH_RTCRST#
RH2
10M_0402_5%
2
1
1
15P_0402_50V8J
2
RH23 1
20K_0402_5%
+RTCVCC
2
CH2
JCMOS @
1
2
CMOS Setting, near DDR Door
BSS138_NL_SOT23-3
1
@
2
RH274
0_0402_5%
+3VS
SPI ROM for BIOS & ME (4MByte )

1
47P_0402_50V8J
CH19
CH6
@ 0.1U_0402_10V7K
UH3
8
2
3
7
For RF
PCH_SPICLK
PCH_SPIDI
PCH_SPICS0#
1
RH66
1
RH67
2
PCH_SPI0_CLK
33_0402_5%
2
PCH_SPI0_DI
33_0402_5%
6
5
VCC
VSS
4MB ROM P/N:

SA00003K800
SA00004LI00
HOLD
S
C
D
PCH_SPI0_DO
1
RH68
2
PCH_SPIDO
33_0402_5%
MX25L3205DM2I-12G SO8
PCH_SPI0_CLK
for EMI
CH7
10P_0402_50V8J
PCH_JTAG_TDI
RH40
100_0402_1%
RH39
100_0402_1%
PCH_SPI1_CLK
for EMI
1
RH50
RH69
10_0402_5%
WIN8@
2
PCH_JTAG_TCK
51_0402_1%
CH21
10P_0402_50V8J
WIN8@
Issued Date
Compal Secret Data
2010/09/03
Deciphered Date
2012/12/31
Title
PCH_HDA/JTAG/SATA/SPI/LPC
Custom
Date:
RH44
100_0402_1%
2MB ROM P/N:

SA000041N00
SA00003FO10
RH65
10_0402_5%
RH38
200_0402_5%
PCH_JTAG_TDO
MX25L1606EM2I-12G_SO8
WIN8@
PCH_JTAG_TMS
8
7
6
5
VCC
HOLD#
SCLK
SI
CS#
SO
WP#
GND
+3VALW_PCH
RH45
200_0402_5%
1
2
3
4
+3VALW_PCH
RH46
200_0402_5%
UH4
PCH_SPICS1#
PCH_SPIDO 1 WIN8@ 2 PCH_SPI1_DO
RH269
33_0402_5% +3VS
+3VALW_PCH
1
2
@ CH20
0.1U_0402_10V7K
1
2
CH100
WIN8@
RH267 33_0402_5%
1 WIN8@ 2
PCH_SPI1_CLK
PCH_SPICLK
1
2
PCH_SPI1_DI
PCH_SPIDI
RH271 33_0402_5%
WIN8@
SPI ROM for Win8 (2MByte )
Socket: SP07000F500/SP07000H900
Please place U13 & U4 close to U2 PCH,
please place RH66, RH67, RH68 near UH3
Please place RH267 near RH66, Please place RH271 near RH67,
Please place RH269 near RH68. +3VS 47P_0402_50V8J For RF
Rev
0.2
QFKAA
Sheet
1
16
of
48
26
26
26
26
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_C_WLANRX_N2
PCIE_PTX_C_WLANRX_P2
CH14 2
CH17 2
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2
BE34
BF34
BB32
AY32
BG36
BJ36
AV34
AU34
BF36
BE36
AY34
BB34
BG37
BH37
AY36
BB36
BJ38
BG38
AU36
AV36
BG40
BJ40
AY40
BB40
+3VS
RH99 1
2 10K_0402_5% PCH_GPIO20
RH104 1
2 10K_0402_5% CLKREQ_WLAN#
RH95 1
210K_0402_5%
BE38
BC38
AW38
AY38
CLKREQ_LAN#
Intel Spec:
PCIECLK_RQ0# is suspend well,
but we pull high to +3VS
for LAN en/disable function
LAN
27
27
26
26
J2
CLKREQ_LAN#
27 CLKREQ_LAN#
WLAN
Y40
Y39
CLK_LAN#
CLK_LAN
CLK_LAN#
CLK_LAN
AB49
AB47
CLK_WLAN#
CLK_WLAN
CLK_WLAN#
CLK_WLAN
M1
CLKREQ_WLAN#
26 CLKREQ_WLAN#
AA48
AA47
V10
PCH_GPIO20
Y37
Y36
A8
PCH_GPIO25
Y43
Y45
L12
PCH_GPIO26
V45
V46
L14
PCH_GPIO44
PERN1
PERP1
PETN1
PETP1
SMBALERT# / GPIO11
SMBCLK
PERN2
PERP2
PETN2
PETP2
SMBDATA
E12
PCH_SMBALERT#
H14
PCH_SMBCLK
C9
PCH_SMBDATA
2 RH72
1 2.2K_0402_5%
2 RH70
1 2.2K_0402_5%
QH3B
PCH_SMBDATA
QH3A
PERN4
PERP4
PETN4
PETP4
SML0ALERT# / GPIO60
SML0CLK
SML0DATA
A12
DRAMRST_CNTRL_PCH
C8
PCH_SMLCLK0
G12
PCH_SMLDATA0
DRAMRST_CNTRL_PCH
SML1ALERT# / PCHHOT# / GPIO74

SML1CLK / GPIO58
PERN6
PERP6
PETN6
PETP6
SML1DATA / GPIO75
PM_SMBCLK 11,12,26
2N7002DW-T/R7_SOT363-6
7,11
+3VALW_PCH
2 RH78
1 2.2K_0402_5%
2 RH74
1 2.2K_0402_5%
+3VS
PERN8
PERP8
PETN8
PETP8
CL_CLK1
CL_DATA1
PCH_SMLCLK1
M16
PCH_SMLDATA1
LAN_EN 27
PCH_SMLDATA1
QH4A
PCH_SMLCLK1
EC_SMB_DA2 31
2N7002DW-T/R7_SOT363-6
EC_SMB_CK2 31
CLKOUT_PCIE0N
CLKOUT_PCIE0P
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
PCIECLKRQ1# / GPIO18
CLKOUT_DP_N
CLKOUT_DP_P
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_GND1_P
CLKOUT_PCIE3N
CLKOUT_PCIE3P
M7
T11
Control Link only for support Intel IAMT.

+3VALW_PCH
CL_RST1#
PEG_A_CLKRQ# / GPIO47
CLKOUT_PCIE1N
CLKOUT_PCIE1P
LAN_EN
E14
2N7002DW-T/R7_SOT363-6
PERN7
PERP7
PETN7
PETP7
C13
PM_SMBDATA 11,12,26
QH4B
PERN5
PERP5
PETN5
PETP5
4.7K_0402_5%
4.7K_0402_5%
4
2N7002DW-T/R7_SOT363-6
PCH_SMBCLK
PERN3
PERP3
PETN3
PETP3
+3VS
RH102
RH103
BG34
BJ34
AV32
AU32
SMBUS
PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_LANRX_N1
PCIE_PTX_LANRX_P1
Link
1 0.1U_0402_10V7K
1 0.1U_0402_10V7K
Controller
CH13 2
CH11 2
PCI-E*
WLAN
PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_C_LANRX_N1
PCIE_PTX_C_LANRX_P1
27
27
27
27
CLOCKS
LAN
+3VALW_PCH
UH1B
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
CLKIN_SATA_N
CLKIN_SATA_P
CLKOUT_PCIE5N
CLKOUT_PCIE5P
REFCLK14IN
P10
M10
PCH_SMBALERT#
RH262 1
2 10K_0402_5%
DRAMRST_CNTRL_PCH
RH76 1
2 1K_0402_5%
LAN_EN
RH75 1
2 10K_0402_5%
PCH_SMLCLK0
RH73 2
1 2.2K_0402_5%
PCH_SMLDATA0
RH77 2
1 2.2K_0402_5%
PCH_GPIO47
AB37
AB38
2
RH89
1
10K_0402_5%
PCH_CLK_DMI#
PCH_CLK_DMI
RH79 1
RH82 1
2 10K_0402_5%
2 10K_0402_5%
CLKIN_GND1#
CLKIN_GND1
RH85 1
RH86 1
2 10K_0402_5%
2 10K_0402_5%
CLK_DOT#
CLK_DOT
RH80 1
RH81 1
2 10K_0402_5%
2 10K_0402_5%
CLK_SATA#
CLK_SATA
RH83 1
RH84 1
2 10K_0402_5%
2 10K_0402_5%
CLK_14M_PCH
RH87 1
2 10K_0402_5%
PCH_GPIO47
AV22
AU22
CLK_CPU_DMI#
CLK_CPU_DMI
AM12
AM13
BF18
BE18
PCH_CLK_DMI#
PCH_CLK_DMI
BJ30
BG30
CLKIN_GND1#
CLKIN_GND1
G24
E24
CLK_DOT#
CLK_DOT
AK7
AK5
CLK_SATA#
CLK_SATA
K45
CLK_14M_PCH
H45
CLK_PCILOOP
V47
V49
PCH_X1
PCH_X2
Y47
1
XCLK_RCOMP
RH115
K43
CLK_FLEX0
T72
PAD
F47
CLK_FLEX1
T74
PAD
H47
CLK_FLEX2
T73
PAD
K49
DGPU_PRSNT#
From Clock Gen.
For EMI
2
@
RH124
CLK_PCILOOP
CLKIN_PCILOOPBACK
CLK_CPU_DMI# 5
CLK_CPU_DMI 5
CLK_PCILOOP
20
@
2
1
CH28
22P_0402_50V8J
1
10_0402_5%
+3VALW_PCH
RH107 1
210K_0402_5%
RH110 1
210K_0402_5%
AB42
AB40
Please place under DDR SODIMM.

10/25
PCH_GPIO26
E6
JPW
@
210K_0402_5% PCH_GPIO44
RH119 1
210K_0402_5%
RH114 1
210K_0402_5% PASSWORD_CLEAR#
V40
V42
RH112 1
PANEL_SEL
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
XTAL25_IN
XTAL25_OUT
13
T13
LVDS_SEL
LVDS_SEL
V38
V37
K12
PANEL_SEL
AK14
AK13
+3VALW_PCH
1
RH116
2
10K_0402_5%
LVDS_SEL
LVDS_SEL
Channel
XCLK_RCOMP
CLKOUT_PCIE6N
CLKOUT_PCIE6P
2
90.9_0402_1%
26 PCH_X1_R
+1.05VS_VCCDIFFCLKN
Placement near to YH2
CLKOUT_PCIE7N
CLKOUT_PCIE7P
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
CLKOUTFLEX0 / GPIO64
NOGCLK@
RH117 2
1 1M_0402_5%
NOGCLK@
CH26
NOGCLK@
27P_0402_50V8J
Compal common design SW request to

add DGPU_Present on this GPIO67
PANEL_SEL
YH2 25MHZ_20PF_7V25000016
3
GND
GND
PCH_X2
CH27
NOGCLK@
27P_0402_50V8J
DGPU_PRSNT#
PANEL_SEL
Single
(Default)
Dual
Channel
LVDS
EDP
DGPU_PRSNT#
UMA
DIS/OPT
1
DGPU_PRSNT#
RH227
M/B SKU
1 @
RH261
Issued Date
2
10K_0402_5%
2010/09/03

2012/12/31
Deciphered Date
3
+3VS
2
10K_0402_5%
Compal Secret Data
PCH_X1
PCH_X1
PCHB0@
LVDS_SEL
RH37
1
2
0_0402_5%
GCLK@
PEG_B_CLKRQ# / GPIO56
PASSWORD_CLEAR#
PCH_GPIO25
FLEX CLOCKS
Title
PCH_PCI-E/SMBUS/CLK
Size
Document Number
Custom
Date:
Rev
0.2
QFKAA
Sheet
1
17
of
48
UH1C
2
RH234
2
RH157
2
RH155
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
2
RH163
2
RH278
2
RH279
PCH_SUSPWRDN#_R
BC24
BE20
BG18
BG20
6 DMI_CTX_PRX_P0
6 DMI_CTX_PRX_P1
6 DMI_CTX_PRX_P2
6 DMI_CTX_PRX_P3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
BE24
BC20
BJ18
BJ20
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
AW24
AW20
BB18
AV18
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
AY24
AY20
AY18
AU18
6 DMI_PTX_CRX_N0
6 DMI_PTX_CRX_N1
6 DMI_PTX_CRX_N2
6 DMI_PTX_CRX_N3
RI#
PCH_LOW_BAT#
6 DMI_PTX_CRX_P0
6 DMI_PTX_CRX_P1
6 DMI_PTX_CRX_P2
6 DMI_PTX_CRX_P3
1
PCH_RSMRST#
10K_0402_5%
1
PM_PWROK
10K_0402_5%
1
SYS_PWROK
10K_0402_5%
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI
+3VALW_PCH
6 DMI_CTX_PRX_N0
6 DMI_CTX_PRX_N1
6 DMI_CTX_PRX_N2
6 DMI_CTX_PRX_N3
FDI_INT
1
RH126
+1.05VS_PCH
2
DMI_COMP
49.9_0402_1%
BJ24
BG25
1
RH127
2
RBIAS_CPY
750_0402_1%
BH21
DMI_ZCOMP
FDI_FSYNC0
DMI_IRCOMP
FDI_FSYNC1
DMI2RBIAS
FDI_LSYNC0
FDI_LSYNC1
Reserve this signal to EC by SW demand

2011/10/18a
VGATE
PM_PWROK
2
SUSACK#_R
0_0402_5%
XDP_DBRESET#
SYS_PWROK
C12
K3
P12
1
PM_PWROK
RH131
SN74AHC1G08DCKR_SC70-5
2
PM_PWROK_R
0_0402_5%
L22
L10
5 DRAMPWROK
SUSACK#_R
2
@
RH281
SUSACK#
SYS_RESET#
SYS_PWROK
IN2
5,31 PM_PWROK
IN1
@
RH133
RH47
2
1
1K_0402_5%
+3VS
UH5
31,42
31 SUSACK#
0.1U_0402_10V7K
1
2
CH103
C
+3VS
DSWVRMEN
1 PCH_SUSPWRDN#_R
0_0402_5%
31 PCH_RSMRST#
Stuff R137 if EC does not want to

involve in the handshake mechanism
for the DeepSX state entry and exit
31 PCH_SUSPWRDN#
@
RH132
31 PBTN_OUT#
1
RH161
+3VALW_PCH
2
330K_0402_5%
DH2
31,36
ACIN
DRAMPWROK
B13
PCH_RSMRST#
C21
2 PCH_SUSPWRDN#_R
0_0402_5%
PBTN_OUT#
E20
PCH_ACIN
H20
PCH_LOW_BAT#
E10
RI#
A10
APWROK
DRAMPWROK
RSMRST#
DPWROK
WAKE#
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
AW16
FDI_INT
AV12
FDI_FSYNC0
BC10
FDI_FSYNC1
AV14
FDI_LSYNC0
BB10
FDI_LSYNC1
A18
DSWVREN
E22
PCH_DPWROK
B9
EC_SWI#
N3
PCH_GPIO32
G8
SUS_STAT#
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
6
6
6
6
6
6
6
6
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
6
6
6
6
6
6
6
6
FDI_INT
1
RH128
PCH_DPWROK
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
+RTCVCC
DSWVREN
EC_SWI#
RH150
RH151
1 330K_0402_5%
@

2011/10/18a
1 330K_0402_5%
26,27
C
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SUSWARN#/SUSPWRDNACK/GPIO30
SLP_S3#
PWRBTN#
SLP_A#
ACPRESENT / GPIO31
SLP_SUS#
BATLOW# / GPIO72
PMSYNCH
RI#
2
PCH_RSMRST#
0_0402_5%
Stuff R222 if do not support DeepSX state
DSWVREN must be always pulled high to +RTCVCC

T76
PAD
32.768 KHz
N14
CLK_EC
D10
PM_SLP_S5#
H4
PM_SLP_S4#
F4
PM_SLP_S3#
G10
PM_SLP_A#
T77
PAD
G16
PM_SLP_SUS#
T78
PAD
31
PM_SLP_S5#
31
PM_SLP_S4#
31
PM_SLP_S3#
31
DSWVREN - Internal Deep Sleep 1.05V regulator

H Enable
L Disable
Follow EC check list demand,

but don't implement CLKRUN# this fuction
+3VS
PCH_GPIO32
AP14
H_PM_SYNC
K14
PCH_GPIO29
H_PM_SYNC
RH256 1
SLP_LAN# / GPIO29
2 8.2K_0402_5%
2
10K_0402_5%
RH160
CH751H-40PT_SOD323-2
K16
PWROK
System Power Management
0_0402_5%
1 @ RH280 2
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
PCHB0@
+3VALW_PCH
EC_SWI#
RH159 1
2 10K_0402_5%
PCH_GPIO29
RH162 1 @
2 10K_0402_5%
DH5
PM_PWROK
PCH_RSMRST#
DH6
35,37
POK
Issued Date
Compal Secret Data
2010/09/03
2012/12/31
Deciphered Date
5
Title
PCH_DMI/FDI/PM
Size
Document Number
Custom
Date:
Rev
0.2
QFKAA
Sheet

1
18
of
48
UH1D
1
RH143
1
RH125
2
UMA_ENBKL
100K_0402_5%
2
RH145
1
LCTL_CLK
2.2K_0402_5%
2
RH146
1
LCTL_DATA
2.2K_0402_5%
2
RH149
1
LCD_EDID_CLK
2.2K_0402_5%
AF37
AF36
AE48
AE47
13 LCD_TXOUT013 LCD_TXOUT113 LCD_TXOUT213 LCD_TXOUT0+

13 LCD_TXOUT1+
13 LCD_TXOUT2+
2
RH148
1
LCD_EDID_DATA
2.2K_0402_5%
13 LCD_TZCLK13 LCD_TZCLK+
2
RH142
1
UMA_CRT_CLK
2.2K_0402_5%
13 LCD_TZOUT013 LCD_TZOUT113 LCD_TZOUT2-
2
RH144
1
UMA_CRT_DATA
2.2K_0402_5%
1
RH156
2
UMA_CRT_B
150_0402_1%
1
RH152
2
UMA_CRT_G
150_0402_1%
1
RH154
2
UMA_CRT_R
150_0402_1%
13 LCD_TZOUT0+
13 LCD_TZOUT1+
13 LCD_TZOUT2+
14 UMA_CRT_B
14 UMA_CRT_G
14 UMA_CRT_R
14 UMA_CRT_CLK
14 UMA_CRT_DATA
14 UMA_CRT_HSYNC
14 UMA_CRT_VSYNC
2
RH138
LCD_TXCLKLCD_TXCLK+
AK39
AK40
LCD_TXOUT0LCD_TXOUT1LCD_TXOUT2-
AN48
AM47
AK47
AJ48
LCD_TXOUT0+
LCD_TXOUT1+
LCD_TXOUT2+
AN47
AM49
AK49
AJ47
LCD_TZCLKLCD_TZCLK+
AF40
AF39
LCD_TZOUT0LCD_TZOUT1LCD_TZOUT2-
AH45
AH47
AF49
AF45
LCD_TZOUT0+
LCD_TZOUT1+
LCD_TZOUT2+
AH43
AH49
AF47
AF43
UMA_CRT_B
UMA_CRT_G
UMA_CRT_R
N48
P49
T49
UMA_CRT_CLK
UMA_CRT_DATA
T39
M40
UMA_CRT_HSYNC
UMA_CRT_VSYNC
M47
M49
1
CRT_IREF
1K_0402_0.5%
T43
T42
L_DDC_CLK
L_DDC_DATA
SDVO_INTN
SDVO_INTP
AP43
AP45
AP39
AP40
L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG
SDVO_CTRLCLK
SDVO_CTRLDATA
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
+3VS
AM42
AM40
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
T45
P39
SDVO_STALLN
SDVO_STALLP
T40
K47
LCTL_CLK
LCTL_DATA
SDVO_TVCLKINN
SDVO_TVCLKINP
L_BKLTCTL
RH140
2.2K_0402_5%
HDMI@
RH139
2.2K_0402_5%
HDMI@
LCD_EDID_CLK
LCD_EDID_DATA
2
LVDS_IBG
2.37K_0402_1%
T79 PAD
13 LCD_TXCLK13 LCD_TXCLK+
+3VS
P45
13 LCD_EDID_CLK
13 LCD_EDID_DATA
D
PCH_PWM
L_BKLTEN
L_VDD_EN
LVDS
PCH_PWM
J47
M45
Digital Display Interface
13
UMA_ENBKL
UMA_ENVDD
CRT
31 UMA_ENBKL
13 UMA_ENVDD
P38
M39
UMA_HDMI_CLK 15
UMA_HDMI_DATA 15
AT49
AT47
AT40
HDMI_HPD
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
UMA_HDMI_TX2UMA_HDMI_TX2+
UMA_HDMI_TXCUMA_HDMI_TXC+
HDMI_HPD
HDMI_HPD
15
UMA_HDMI_TXCUMA_HDMI_TXC+
15
15
15
15
15
15
15
15
2
1
100K_0402_5%
RH254
HDMI
P46
P42
AP47
AP49
AT38
RH141
1 100K_0402_5%
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
RH255
1 100K_0402_5%
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
PCHB0@
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
Title
PCH_CRT/LVDS/HDMI
Custom
Date:
Rev
0.2
QFKAA
Sheet
1
19
of
48
UH1E
1
RH318
1
RH319
1
RH320
1
RH321
1
RH324
1
RH323
1
RH325
1
RH322
1
RH326
1
RH327
1
RH328
1
RH329
1
RH283
1
RH290
2
PCH_GPIO54
8.2K_0402_5%
2
PCH_GPIO4
8.2K_0402_5%
2
PCI_PIRQB#
8.2K_0402_5%
2
PCI_PIRQC#
8.2K_0402_5%
2
PCH_GPIO52
8.2K_0402_5%
2
PCH_GPIO53
8.2K_0402_5%
2
PCI_PIRQA#
8.2K_0402_5%
2
ODD_DA#
8.2K_0402_5%
2
PCH_GPIO55
8.2K_0402_5%
2
PCH_GPIO2
8.2K_0402_5%
2
PCH_GPIO50
8.2K_0402_5%
2
PCH_GPIO51
8.2K_0402_5%
2
PCI_PIRQD#
8.2K_0402_5%
2
PCH_GPIO5
8.2K_0402_5%
2
22_0402_5%
28 CLK_PCI_TPM_PCH
B21
M20
AY16
BG46
29
29
U3RXDN1_R
U3RXDN2_R
29
29
U3RXDP1_R
U3RXDP2_R
29
29
U3TXDN1
U3TXDN2
29
29
U3RXDP1_R
U3RXDP2_R
U3TXDN1
U3TXDN2
U3TXDP1
U3TXDP2
U3TXDP1
U3TXDP2
1 CLK_PCI_TPM_PCH_R
R314
Add new PCI CLK to TPM

25
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
U3RXDN1_R
U3RXDN2_R
ODD_DA#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
K40
K38
H38
G38
PCH_GPIO50
PCH_GPIO52
PCH_GPIO54
C46
C44
E40
PCH_GPIO51
PCH_GPIO53
PCH_GPIO55
D47
E42
F46
PCH_GPIO2
ODD_DA#
PCH_GPIO4
PCH_GPIO5
G42
G40
C42
D44
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
TP21
TP22
TP23
TP24
RSVD23
DF_TVS RSVD24
RSVD25
RSVD26
RSVD27
USB3Rn1
USB3Rn2
USB3Rn3
USB3Rn4
USB3Rp1
USB3Rp2
USB3Rp3
USB3Rp4
USB3Tn1
USB3Tn2
USB3Tn3
USB3Tn4
USB3Tp1
USB3Tp2
USB3Tp3
USB3Tp4
RSVD28
RSVD29
EHCI 1
PIRQA#
PIRQB#
PIRQC#
PIRQD#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
USB
+3VS
RSVD5
RSVD6
RSVD
RSVD1
RSVD2
RSVD3
RSVD4
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
PCI
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
EHCI 2
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
USBRBIAS#
T80 PAD
5,26,27,28,31,32
22_0402_5% 1
22_0402_5% 1
22_0402_5% 1
31 CLK_PCI_EC
17 CLK_PCILOOP
32 CLK_PCI_DDR
PLT_RST#
@
2
1
CH15
180P_0402_50V8J
PCI_PME#
K10
PLT_RST#
C6
2 RH167 CLK_EC_R
2 RH166 CLK_PCH
2 RH284 CLK_SIO
CLK_PCI_TPM_PCH_R
CH22
47P_0402_50V8J
@
PLT_RST#
1K_0402_5%
1 RH285
PCH_GPIO51
1K_0402_5%
1 RH286
PCH_GPIO19
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
NV_ALE
AT8
AY5
BA2
AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
C33
USBBIAS
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
29
29
29
29
25
25
25
25
USB-LEFT2
NV_ALE
USB-Right1
USB20_N11
USB20_P11
USB20_N8
USB20_P8
USB20_N9
USB20_P9
28
28
26
26
USB20_N11
USB20_P11
1
RH165
High=Endabled
Low=Disable(floating)
USB-Right2
*
+1.8VS
NV_ALE
USB20_N8
USB20_P8
USB20_N9
USB20_P9
Intel Anti-Theft Techonlogy
USB-LEFT1
1 @
RH164
2
1K_0402_5%
Card Reader
WiMax
13
13
Int. Camera
2
22.6_0402_1%
Within 500 mils
B33
PME#
PLTRST#
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
A14
K20
B17
C16
L16
A16
D14
C14
USB_OC#0
USB_OC#1
USB_OC#2
SLP_CHG#
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#0
USB_OC#1
SLP_CHG#
29
25
USB-LEFT
USB-Right
29
+3VALW_PCH
USB_OC#6
1
RH209
1
SLP_CHG#
RH196
1
USB_OC#4
RH200
1
USB_OC#1
RH192
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
1
RH177
1
RH183
1
RH201
1
USB_OC#0
RH188
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
Boot BIOS Strap

PCH_GPIO51
@
1
CH104
USBRBIAS
AT10
BC8
PCHB0@
ODD_DA#
by ESD requestion and place near CPU
2
100P_0402_50V8J
H49
H43
J48
K42
H40
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
AY7
AV7
AU3
BG4
PCH_GPIO19
0
0
1
1
PCH_GPIO19
0
1
0
1
Boot BIOS Loaction
USB_OC#2
LPC
USB_OC#5
Reserved
USB_OC#7
PCI
SPI
16
A16 Swap Override Strap

PCH_GPIO55
1K_0402_5% 2
1 RH287
Low= A16 swap override Enable

High= A16 swap override Disable
PCH_GPIO55
Issued Date
Compal Secret Data
2010/09/03
2012/12/31
Deciphered Date
5
Title
PCH_PCI/USB/NAND
Size
Document Number
Custom
Date:
Rev
0.2
QFKAA
Sheet

1
20
of
48
+3VS
UH1F
+3VALW_PCH
ODD_EN#
EC_SCI#
E38
PCH_GPIO28
PCH_GPIO57
31
EC_SCI#
31
EC_SMI#
EC_SMI#
C10
PCH_GPIO12
C4
EC_LID_OUT#
G2
PCH_GPIO16
U2
D40
T5
BT_DET#
E8
T81 PAD
25 ODD_DETECT#
PCH_GPIO27
E16
PCH_GPIO28
P8
PCH_GPIO34
K1
PCH_GPIO35
K4
ODD_DETECT#
V8
PCH_GPIO37
M5
OPTIMUS_EN#
N2
PCH_GPIO39
M3
PCH_GPIO48
V13
PCH_GPIO49
V3
PCH_GPIO57
D6
A4
A44
A45
A46
A5
A6
B3
B47
BD1
GPIO28
On-Die PLL Voltage Regulator

H: Enable
L: Disable
BD49
3D_DET#
BE1
3D_DET#
BE49
BF1
2 1K_0402_5% PCH_GPIO28
TACH6 / GPIO70
TACH3 / GPIO7
TACH7 / GPIO71
SKU
Non3D
3D
BF49
C40
ODD_EN#
ODD_EN# 34
B41
PCH_GPIO69
C41
PCH_GPIO70
A40
PCH_GPIO71
GATEA20
KB_RST#
PCH_GPIO69
PCH_GPIO70
GPIO8
PCH_GPIO71
LAN_PHY_PWR_CTRL / GPIO12
GPIO15
A20GATE
PECI
SATA4GP / GPIO16
TACH0 / GPIO17
SCLOCK / GPIO22
PROCPWRGD
GPIO24
GPIO27
GPIO28
THRMTRIP#
INIT3_3V#
DF_TVS
TS_VSS1
STP_PCI# / GPIO34
TS_VSS2
GPIO35
TS_VSS3
SATA2GP / GPIO36
TS_VSS4
P4
GATEA20
1
RH288
1
RH182
1
RH184
1
RH291
1
RH315
1
RH203
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
GATEA20 31
AU16
P5
KB_RST#
AY11
H_PWRGOOD
AY10
PCH_THRMTRIP# 1
RH191
KB_RST# 31
H_PWRGOOD 5
2
390_0402_5%
H_THERMTRIP# 5
T14
AY1
NV_CLE
This signal has weak internal

pull-up, can't be pulled low
AH8
AK11
AH10
AK10
SATA3GP / GPIO37
SLOAD / GPIO38
NC_1
P37
SDATAOUT0 / GPIO39
SDATAOUT1 / GPIO48
VSS_NCTF_15
SATA5GP / GPIO49 / TEMP_ALERT#
VSS_NCTF_16
GPIO57
VSS_NCTF_17
VSS_NCTF_1
VSS_NCTF_19
VSS_NCTF_2
VSS_NCTF_20
VSS_NCTF_3
VSS_NCTF_21
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_6
VSS_NCTF_24
VSS_NCTF_7
VSS_NCTF_25
VSS_NCTF_8
VSS_NCTF_26
VSS_NCTF_9
VSS_NCTF_27
VSS_NCTF_10
VSS_NCTF_28
VSS_NCTF_11
VSS_NCTF_29
VSS_NCTF_12
VSS_NCTF_30
VSS_NCTF_13
VSS_NCTF_31
VSS_NCTF_14
VSS_NCTF_32
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
DMI & FDI Termination Voltage
C48
D1
Set to VCC when HIGH
NV_CLE
+1.8VS
E1
E49
Set to VSS when LOW
D49
+1.8VS
F1
RH187
2.2K_0402_5%
F49
RH210
2.2K_0402_5%
RH206
TACH5 / GPIO69
TACH2 / GPIO6
VSS_NCTF_18
Follow Compal ORB

and Intel Check list 460603 V1.5
TACH1 / GPIO1
RCIN#
PCH_GPIO17
2
PCH_GPIO37
10K_0402_5%
1
PCH_GPIO27
10K_0402_5%
TACH4 / GPIO68
H36
BMBUSY# / GPIO0
A42
PCH_GPIO6
PCH_GPIO12
31 EC_LID_OUT#
1
RH198
2
RH199
PCH_GPIO1
EC_SMI#
+3VS
T7
2
PCH_GPIO34
10K_0402_5%
1
CHP3_SERDBG
1K_0402_5%
2
PCH_GPIO1
10K_0402_5%
2
BT_DET#
10K_0402_5%
2
OPTIMUS_EN#
10K_0402_5%
2
ODD_DETECT#
200K_0402_5%
2
PCH_GPIO6
10K_0402_5%
2
PCH_GPIO16
10K_0402_5%
2
EC_SCI#
10K_0402_5%
2
PCH_GPIO39
10K_0402_5%
2
PCH_GPIO48
10K_0402_5%
2
PCH_GPIO49
10K_0402_5%
2
PCH_GPIO17
10K_0402_5%
CHP3_SERDBG
CPU/MISC
1
RH180
2
RH292
1
RH190
1
RH185
1
RH193
1
RH178
1
RH197
1
RH179
1
RH293
1
RH194
1
RH181
1
RH195
1
RH186
14 CHP3_SERDBG
EC_LID_OUT#
GPIO
1
1K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
NCTF
2
RH204
1
RH205
1
RH289
1
RH202
1
RH207
DH54
NV_CLE
PCHB0@
2
RH189
1
1K_0402_5%
H_SNB_IVB#
5,11
PMEG2010AEH_SOD123
GPIO8
OPTIMUS_EN#
Integrated Clock Chip Enable (Removed)

H: Disable
L: Enable
OPTIMUS_EN#
HDD2_DET#
SKU
NonOPT
Optimus
SKU
ONE HDD
TWO HDD
RH298 1
2 1K_0402_5%
EC_SMI#
HDD2_DET#
Integrated clock enable functionality

is achieved by soft-strap
The current default is clock enable
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
Title
Custom
Date:
PCH_CPU/GPIO
Rev
0.2
QFKAA
Sheet
1
21
of
48
UH1G
CH33
CH31
CH34
10U_0603_6.3V6M
1U_0402_6.3V6K
2
1U_0402_6.3V6K
+1.05VS_PCH
AN19
This pin can be left as NC if

On-Die VR is enabled (Default)
PAD
BJ22
T82
AN16
AN17
AN21
AN26
AN27
C
+1.05VS_PCH
AP21
1U_0402_6.3V6K
CH43
CH45
CH46
AP23
1
CH47
AP24
CH44
AP26
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
2
AT24
AN34
+3VS
BH29
1
VSSADAC
U48
U47
AP16
+VCCAFDI_VRM

PAD
BG6
T83
+1.05VS_PCH
AP17
+VCCP_VCCDMI
AU20
0.1U_0402_10V7K
1
CH36
+VCCA_DAC
CH35
0.01U_0402_25V7K
LH1
2+VCCA_DAC_R 2
1
1_0603_1%
BLM18PG181SN1D_0603
1
CH37
10U_0603_6.3V6M
PCH Power Rail Table

Refer to PCH EDS R1.0
Voltage Rail
Voltage
S0 Iccmax
Current (A)
+3VS
V_PROC_IO
1mA
VCCALVDS
VSSALVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
60mA
VCCTX_LVDS[3]
VCCTX_LVDS[4]
AK36
+VCCA_LVDS
1.05
0.001
V5REF
0.001
V5REF_Sus
0.001
2
0_0603_5%
RH208
AK37
+1.8VS
AM37
LH2
AM38
0.01U_0402_25V7K
+VCCTX_LVDS
AP36
CH38
AP370.01U_0402_25V7K
CH39
2
1
BLM18PG181SN1D_0603
Vcc3_3
3.3
0.228
VccADAC
3.3
0.063
VccADPLLA
1.05
0.08
VccADPLLB
1.05
0.08
VccCore
1.05
1.7
VccDMI
1.1
0.047
VccIO
1.05
3.711
VccASW
1.05
0.903
VccSPI
3.3
0.01
VccDSW
3.3
0.001
VccDFTERM
1.8
0.002
VccRTC
3.3
N/A
VccSus3_3
3.3
0.095
VccSusHDA
3.3
0.01
VccVRM
1.5
0.167
VccCLKDMI
1.05
0.07
VccSSC
1.05
0.095
VccDIFFCLKN
1.05
0.055
VccALVDS
3.3
0.001
VccTX_LVDS
1.8
0.04
CH40
22U_0805_6.3V6M
VCCIO[28]
+3VS
VCCAPLLEXP
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCC3_3[6]
V33
1
VCC3_3[7]
V34
CH42
0.1U_0402_10V7K
2
+1.5VS
+VCCAFDI_VRM
VCCIO[18]
VCCIO[19] 3709mA
VCCVRM[3]
AT16
+VCCAFDI_VRM
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
RH221
0_0603_5%
2
+VCCP_VCCDMI
VCCIO[20]
VCCDMI[1]
AT20
RH213 +1.05VS_VCCP
0_0603_5%
1
2
+VCCP_VCCDMI
+1.05VS_PCH
75mA
VCCCLKDMI
RH214
2
1
0_0805_5%
AB36 +1.05VS_VCC_DMI
1
CH48
1U_0402_6.3V6K
CH49
1U_0402_6.3V6K
VCCIO[25]
VCCIO[26]
VCCDFTERM[1]
VCC3_3[3]
CH50
0.1U_0402_10V7K
+3VS
VCCADAC
1U_0402_6.3V6K
AN33
RH299
1mA
CRT
CH32
POWER
1300mA
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
LVDS
JUMP_43X118
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
+1.05VS_PCH
HVCMOS
1U_0402_6.3V6K
DMI
DFT / SPI
VCCVRM[2]
VccAFDIPLL
VCCIO[27]
VCCDMI[2]
FDI
PJ4
2
VCC CORE
+1.05VS_VCCP
VCCIO
PCHB0@
VCCDFTERM[2]
190mA
VCCDFTERM[3]
+1.8VS
AG16
AG17
1
AJ16
2
VCCDFTERM[4]
CH51
0.1U_0402_10V7K
AJ17
+3VS
20mA
VCCSPI
V1
1
CH53
1U_0402_6.3V6K
+3VALW to +3V_PCH
Vgs=-4.5V,Id=3A,Rds<97mohm
+3VALW
+3VALW_PCH
PJ2
2
JUMP_43X79
AO3413_SOT23
D
@
2
RH1
1
47K_0402_5%
2
CH99
CH102
2
RH3
0.1U_0402_25V6
PCH_PWR_EN#
23,34 PCH_PWR_EN#
CH98
0.1U_0402_10V7K~D
1
0.01U_0402_25V7K
1
20K_0402_5%~D
QH2
Issued Date
Compal Secret Data
2010/09/03
2012/12/31
Deciphered Date
5
Title
PCH_POWER-1
Size
Document Number
Custom
Date:
Rev
0.2
QFKAA
Sheet

1
22
of
48
+3VS
+5VALW

QH6
+PCH_VCCDSW
V12
+3VS_VCC_CLKF33
T38
PAD T85
BH23
DCPSUSBYP
VCCIO[32]
0.1U_0402_10V7K
AL24
+VCCSUS
CH54
1U_0402_6.3V6K
@
AA24
1
AA26
CH65
AA27
22U_0805_6.3V6M
2
2
22U_0805_6.3V6M
AA29
AA31
1U_0402_6.3V6K
1
1
CH68
CH69
CH67
+1.05VS_PCH
1U_0402_6.3V6K
LH7
1
BLM18PG181SN1D_2P
2
LH8
1
BLM18PG181SN1D_2P
2
+1.05VS_VCCADPLLB
CH93
CH95
1 10U_0603_6.3V6M
1 10U_0603_6.3V6M
1
1
2
AC26
1
AC27
1U_0402_6.3V6K
2
AC29
AC31
+1.05VS_VCCADPLLA
AD29
AD31
W21
W23
2
2 CH94
1U_0402_6.3V6K
2 CH96
1U_0402_6.3V6K
W24
W26
W29
W31
+1.05VS_PCH
RH244
2
W33
1
+VCCDIFFCLK
0_0603_5%
VCCSUS3_3[8]
VCCIO[14]
VCCSUS3_3[9]
DCPSUS[3]
VCCSUS3_3[10]
VCCASW[1]
VCCASW[2]
VCCIO[34]
1010mA
1mA
VCCASW[3]
VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]
V5REF_SUS
CH79
1U_0402_6.3V6K
+VCCRTCEXT
N16
+VCCAFDI_VRM
Y49
CH78
0.1U_0402_10V7K
CH56
1U_0402_6.3V6K
2
RH4
22,34 PCH_PWR_EN#
1
47K_0402_5%
T27
T29
+3VALW_PCH
VCCASW[15]
V5REF
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
T24
V23
CH60
0.1U_0402_10V7K
VCC3_3[8]
VCCASW[16]
VCC3_3[4]
+5VALW_PCH
V24
P24
T26
CH61
0.1U_0402_10V7K
+3VALW_PCH
RH232
10_0402_5%
DH3
+PCH_V5REF_SUS
+1.05VS_PCH
1
M26
AN23
CH62 1
+VCCA_USBSUS
AN24
P34
2 1U_0402_6.3V6K
2
0.1U_0402_10V7K
+PCH_V5REF_RUN
+3VALW_PCH
+5VS
+3VS
RH237
10_0402_5%
1
N22
P20
CH70
1U_0402_6.3V6K
VCCIO[12]
VCCVRM[4]
VCCIO[13]
+PCH_V5REF_RUN
CH71
1U_0402_6.3V6K
AA16
+3VS
W16
T34
CH72
0.1U_0402_10V7K
2
+3VS
AJ2
+1.05VS_SATA3
1
AF13
2
1
AH13
AH14
+1.05VS_PCH
RH242
CH76
0.1U_0402_10V7K
+1.05VS_SATA3
0_0805_5%
CH77
1U_0402_6.3V6K
2
BD47
+1.05VS_VCCADPLLA
+1.05VS_VCCDIFFCLKN
1
0_0603_5%
CH81
1U_0402_6.3V6K
+1.05VS_VCCADPLLB
BF47
+VCCDIFFCLK
AF17
AF33
AF34
AG34
2
+1.05VS_VCCDIFFCLKN
+1.05VS_PCH
VCCADPLLB
80mA
80mA
1
1
VCCIO[2]
+VCCSST
V16
0.1U_0402_10V7K
+1.05VM_VCCSUS
CH85
T17
V19
VCCSSC
VCCIO[4]
95mA
+1.05VM_VCCSUS
0_0603_5%
CH83
1U_0402_6.3V6K
@
0_0603_5%
CH86
4.7U_0603_6.3V6K
0.1U_0402_10V7K
1
CH87
BJ8
+V_CPU_IO
1
CH88
T86 PAD
+VCCAFDI_VRM
AF11
+VCCAFDI_VRM
AC16
+1.05VS_VCC_SATA
AC17

+1.05VS_VCC_SATA
AD17
+1.05VS_PCH
RH246
2
1
0_0805_5%
CH82
1U_0402_6.3V6K
+1.05VS_PCH
DCPSUS[1]
DCPSUS[2]
VCCASW[22]
1mA
V_PROC_IO
+RTCVCC
VCCASW[23]
VCCASW[21]
T21
+VCCME_22
RH300 2
1 0_0402_5%
V21
+VCCME_23
RH301 2
1 0_0402_5%
T19
+VCCME_21
RH302 2
1 0_0402_5%
+3VALW_PCH
0.1U_0402_10V7K
0.1U_0402_10V7K
2
2
CH89
1U_0402_6.3V6K
CH90
A22
VCCRTC
RTC
RH303 @
2
1
AK1
DCPSST
CPU
RH249
AF14
+1.05VS_VCCP
1
VCCVRM[1]
55mA
VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]
VCCIO[3]
AG33
CH84
1U_0402_6.3V6K
+1.05VS_PCH
VCCAPLLSATA
MISC
VCCIO[6]
VCCADPLLA
SATA
+1.05VS_VCCDIFFCLKN
RH247
PCHB0@
0.1U_0402_10V7K
CH91
HDA
+1.05VS_PCH
10mA
VCCSUSHDA
P32
1
CH92
0.1U_0402_10V7K
Issued Date
Compal Secret Data
2010/09/03
2012/12/31
Deciphered Date
5
1
+3VS
2
DCPRTC
CH63 & CH71 are

different by Intel CRB.
DH4
P22
VCCASW[18]
VCCASW[20]
0.1U_0402_10V7K
+3VALW_PCH
N20
VCCASW[17]
VCC3_3[2]
CH63
+PCH_V5REF_SUS
1
2
CH75
0.1U_0402_10V7K
VCCASW[19]
Change RH232, RH237 to 10 ohm by follow Compal ORB abd Intel CRB
+3VALW_PCH
2
VCC3_3[1]
T23
1
CH66
1mA
@
DCPSUS[4]
VCCSUS3_3[1]
VCCIO[5]
119mA
VCCSUS3_3[6]
AA19
AA21
CH64
VCCAPLLDMI2
Clock and Miscellaneous
+1.05VS_PCH
VCCSUS3_3[7]
USB
AL29
+1.05VS_PCH
VCCIO[33]
P28
VCC3_3[5]
PCI/GPIO/LPC

P26
RH228
20K_0402_5%~D
VCCIO[31]
CH59
0.1U_0402_10V7K~D
VCCIO[30]
VCCIO[29]
3mA
VCCACLK
VCCDSW3_3
AO3413_SOT23
1
T16
N26
T84
CH55
0.1U_0402_10V7K
@
CH58
2
1
"@" Avoid leakage
1
D
AD49
+1.05VS_PCH
POWER
UH1J
PAD
+3VALW_PCH
CH74
1U_0402_6.3V6K
CH73
10U_0603_6.3V6M
CH80
+5VALW_PCH
JUMP_43X39
@ PJ5
2
+3VS_VCC_CLKF33
1
0.1U_0402_25V6
LH5
1
2
10UH_LB2012T100MR_20%
Title
PCH_POWER-2
Size
Document Number
Custom
Date:
Rev
0.2
QFKAA
Sheet

1
23
of
48
UH1I
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
UH1H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
PCHB0@
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
PCHB0@
Issued Date
Compal Secret Data
2010/09/03
2012/12/31
Deciphered Date
5
Title
PCH_GND
Size
Document Number
Custom
Rev
0.2
QFKAA
Date:
Sheet

1
24
of
48
C358
0.1U_0402_10V7K
GND
A+
AGND
BB+
GND
C359
0.1U_0402_10V7K
14
15
JHDD
GND
RX+
RXGND
TXTX+
GND
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V
1
2
3
4
5
6
7
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
C369 1
C367 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
C368 1
C370 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SATA_PTX_DRX_P0 16
SATA_PTX_DRX_N0 16
8
9
10
11
12
13
C376 1
C377 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
C378 1
C375 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
ODD_DETECT#
SATA_PTX_DRX_P2 16
SATA_PTX_DRX_N2 16
21
+5VS_ODD
ODD_DA#
+5VS_ODD
Place components closely ODD CONN.
1.6A
ODD_DA# 20
C355
10U_0805_6.3V6M
@ C354
@C354
10U_0805_6.3V6M
C379
@
1U_0402_6.3V6K
2
1
C380
0.1U_0402_10V7K
C360
0.1U_0402_10V7K
SATA ODD Conn (for 15" 17")

JODDB
+3VS
1
2
3
4
5
6
7
8
9
10
11
12
GND
GND
+5VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SATA_PTX_C_DRX_P2_R
SATA_PTX_C_DRX_N2_R
R79
R80
1
1
2 0_0402_5%
2 0_0402_5%
SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2
SATA_PRX_DTX_N2_R
SATA_PRX_DTX_P2_R
R81
R82
1
1
2 0_0402_5%
2 0_0402_5%
SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
ODD_DETECT#
+5VS_ODD
ODD_DA#
Had confirm with ME that

this symbol is the same as connector list
ODDB demand
ACES_88058-120N
SUYIN_127043FB022G278ZR
C
DP
+5V
+5V
MD
GND1
GND
GND2
GND
SANTA_206001-1
@
SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2
C357
0.1U_0402_10V7K
C356
10U_0805_6.3V6M
Close to JHDD
GND
GND
23
24
JODD
1
2
3
4
5
6
7
Place closely JHDD SATA CONN.
1.2A
SATA ODD Conn (for 14")
SATA HDD
Conn.
+5VS
Power Button & RUSB connector

+5VALW
W=80mils
2.5A
+USB_VCCA
For EMI
U14
29,31 USB_EN#
2
3
4
1
6
7
8
5
IN
OUT
IN
OUT
EN/ENB OUT
GND
OCB
SY6288DCAC_MSOP8
SA00004KB00
SA00003TV00
2
C361
1
1000P_0402_50V7K
delete +USB_VCCA capacitance

(place in SB will be better)
USB_OC#1 20
1
C362
4.7U_0805_10V4Z
2@
R77
1
0_0402_5%
2
L54
B
20
USB20_N2
USB20_N2
20
USB20_P2
USB20_P2
USB20_N2_R
USB20_P2_R
JUSIO
R73
1
2
0_0402_5%
USB20_P2_R
USB20_N2_R
0_0402_5%
2
ON/OFFBTN#
2
+5VS_PWR_ON_LED
R22
+USB_VCCA
390_0402_5%
31,33 ON/OFFBTN#
1
+5VS
L53
20
USB20_N3
USB20_N3
20
USB20_P3
USB20_P3
1
2
3
4
5
6
7
8
9
10
11
12
GND
GND
ACES_88058-120N
@
USB20_P3_R
USB20_N3_R
WCM-2012-900T_0805
1
R88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
USB20_N3_R
USB20_P3_R
WCM-2012-900T_0805
1
R87
2
0_0402_5%
Issued Date
Compal Secret Data
2010/09/03
2012/12/31
Deciphered Date
5
Title
SATA-HDD/ODD/USB
Size
Document Number
Rev
0.2
QFKAA
Date:
Sheet

1
25
of
48
Slot 1 Half PCIe Mini Card-WLAN/ WiMax
WLAN&BT Combo module circuits
+3V_WLAN
5
31
PLT_RST#
WLAN_RST#
WLAN_RST#_R
IN2
3
@
For RF
+1.5VS_WLAN
For isolate Intel Rainbow Peak and

Compal Debug Card.
1
1
PJ33
PAD-OPEN 2x2m
@
CM9
C254
@
47P_0402_50V8J
2
2
@
4.7U_0805_10V4Z
2
CM2
CM3
C253
CM7
CM8
47P_0402_50V8J
@
@
2
2
2
2
@
0.01U_0402_25V7K 4.7U_0805_10V4Z
0.01U_0402_25V7K
2
CM1
+1.5VS_WLAN
+3V_WLAN
+3VALW TO +3V_WLAN
for AOAC and WOWL
JWLAN
18,27
+3V_WLAN
EC_SWI#
EC_SWI#
BT_ON
10_0402_5%2BT_CTRL_R
@ R1443
17 CLKREQ_WLAN#
17
17
CLK_WLAN#
CLK_WLAN
1
3
5
7
9
11
13
15
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
G1
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
G2
2
4
6
8
10
12
14
16
+3VALW
+3VS
+3VALW
1
C266
47P_0402_50V8J
@
1 R327
2 E51_RXD_R
1K_0402_5%
For SED
0.1U_0402_10V7K
1
1
BT_ON
BT_ON
2
0_0402_5%
@
For SED
0.1U_0402_10V7K
1
1
RM19
+1.5VS
40 mils
WLAN/ WiFi
+3V_WLAN
31
31
R16
10_0402_5%2
1
2
0_0402_5%
R17
E51_TXD
E51_RXD
E51_RXD_R
USB20_N9 20
USB20_P9 20
1
C907
0.1U_0402_10V7K
3
AOAC_WLAN_PWR_EN#
PM_SMBCLK 11,12,17
PM_SMBDATA 11,12,17
LED_WIMAX#
47K_0402_5%
2
2
R1457
WiMax
+3V_WLAN
C908
0.01U_0402_25V7K
LED_WIMAX# 33
LED_WIMAX#
PJ30
PAD-OPEN 2x2m
@
AO3413_SOT23
Q210
2
17 PCIE_PTX_C_WLANRX_N2
17 PCIE_PTX_C_WLANRX_P2
R1456
100K_0402_5%
WLAN_OFF#
WLAN_RST#_R
C260
47P_0402_50V8J
@
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
17 PCIE_PRX_WLANTX_N2
17 PCIE_PRX_WLANTX_P2
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
+1.5VS_WLAN
WLAN_RST#
BT_ON#
+3V_WLAN
2
0_0402_5%
Disable
RM21
100K_0402_5%
31
1
RM18
WL_OFF#
BT
on module
Enable
UM5
IN1
5,20,27,28,31,32
4WLAN_OFF#
O
IN2
BT
on module
UM4
IN1
WL_OFF#
+3V_WLAN
31 AOAC_WLAN_PWR_EN#
31
+3V_WLAN
5
RM17
8.2K_0402_5%
need short PJ30 if system

don't support AOAC or WOWL
WIMAX@
2
+5VS
100K_0402_5%
WIMAX@
1
2
RM181
200K_0402_5%
1
RM7
Debug card using

@
BELLW_80003-7041
Green Clock
0.1U_0402_10V7K
+3VL
1
CCL8
GCLK@
1 GCLK@ 2 PCH_X1_R
PCH_X1_R_R
RCL1
0_0402_5%
2
UCL1
2
15
+3VALW
+3VL
CCL2
GCLK@
8
3
+3V_LAN
+1.05VS_VCCP
CLK_X2
CLK_X1
1
16
4
7
13
17
+1.05VS_VCCP
1
CCL3
GCLK@
VDD
+V3.3A
GCLK@
VBAT
NC
VDDIO_25M_A
VDDIO_25M_B
XTAL_OUT
XTAL_IN
VSS
VSS
VSS
Thermal Pad
32K
NC
25M_B
25M_A
VDD_RTC_OUT
SLG3NB244VTR_TQFN16_2X3
10
11
GCLK@
25MHZ 20PF X3G025000DK1H-X
YCL1
1
3
GND
GND
CCL4
18P_0402_50V8J
GCLK@
+RTCBATT
9
12
PCH_RTCX1_R
5
6
PCH_X1_R_R
LAN_X1_R_R
14
1 GCLK@ 2 LAN_X1_R
LAN_X1_R_R
RCL2
33_0402_5%
1
GCLK@
22U_0805_6.3V6M
CCL7
PCH_RTCX1_R 16
LAN_X1_R 27
CCL10
5P_0402_50V8C
GCLK@
EMI request 11/06
+RTCVCC
1
CLK_X1
PCH_X1_R 17
CCL1
GCLK@
+3V_LAN
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
+3VALW
CCL6
2.2U_0603_6.3V6K
GCLK@
1 @
LAN_X1_R_R
RCL5
2
0_0402_5%
CLK_X2
Reserved for Swing Level adjustment

( Close GCLK side )
CCL5
18P_0402_50V8J
GCLK@
Issued Date
Compal Secret Data
2010/09/03
Deciphered Date
2012/12/31
Title
Size
Date:
PCIe-WLAN/JET/3G/TV/GCLK
Document Number
Rev
0.2
QFKAA
Sheet
26
of
48
UL1
CL1
2 0.1U_0402_10V7K
PCIE_PRX_LANTX_P1
22
17 PCIE_PRX_C_LANTX_N1
CL2
2 0.1U_0402_10V7K
PCIE_PRX_LANTX_N1
23
PCIE_PTX_C_LANRX_P1
PCIE_PTX_C_LANRX_N1
17
18
5,20,26,28,31,32
PLT_RST#
17
17
CLK_LAN
CLK_LAN#
LAN_X1
43
LAN_X2
44
EC_SWI#
28
REFCLK_P
REFCLK_N
EC_SWI#
ISOLATE#
26
14
15
38
RL21 2
1 10K_0402_5%
2 1K_0402_5%
ISOLATEB
18111FVB@ 2
RL26
0_0402_5%
NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT
AVDD33
AVDD33
AVDD33
AVDD33
ENSWREG
EVDD10
34
35
+LAN_VDDREG
VDDREG
VDDREG
AVDD10
AVDD10
AVDD10
AVDD10
1K_0402_5%
RL6
@
46
RSET
24
49
REGOUT
RTL8111F-CGT_QFN48_6x6
8111FVB@
RTL8105E
RTL8111E/F
CL43
1
NC
NC
10K ohm PD
NC
Pin38
NC
1K ohm PH
HIGH
8111FVB@
8111FVB@
2
0_0603_5%
CL28
4.7U_0603_6.3V6K
8111FVB@
+LAN_REGOUT
8111FVB@
CL29
0.1U_0402_10V7K
2 8111FVB@
60 mils
UL1
RL4
LAN_X2
GND
4
CL27
27P_0402_50V8J
NOGCLK@
NC
8105E-VD 10/100M
8105ELDO@
0 ohm
(Pull Down)
RL23
RL23
0_0402_5%
8105ELDO@
2
CL26
27P_0402_50V8J
NOGCLK@
8105E-VL/VD 8105E-VL/VD
8111F/F-VB
PWM Mode
LDO Mode
0 ohm
NC
(Pull High)
PJ32
PAD-OPEN 2x2m
@
+3V_LAN
LAN Conn.
JRJ45
RJ45_MIDI0+
RJ45_MIDI0-
RJ45_MIDI1+
RJ45_MIDI2+
RJ45_MIDI2-
RJ45_MIDI1-
RJ45_MIDI3+
RJ45_MIDI3-
UL3
CL682
1U_0402_6.3V6K
LAN_MDI0+
LAN_MDI0-
LAN_MDI1+
@
LAN_MDI1CL35
0.1U_0402_25V6
2 Place CL35 colse
to UL3
1
+3V_LAN rising time (10%~90%) need > 1ms and <100ms.
D99
LAN_MDI1+
LAN_EN
ISOLATEB
S0
Sx
S0
Sx
---------------------------------------------0
0
0
0
1
1
0
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
0*
I/O4
I/O2
VDD
GND
I/O3
I/O1
LAN_MDI0+
LAN_MDI2+
LAN_MDI2-
WOL
*
S3: after SUSP# assert low over 100ms
S4/S5: after SYSON assert low over 100ms
+3V_LAN
LAN_MDI1-
LAN_MDI0-
LAN_MDI3+
LAN_MDI3-
1
2
3
4
5
6
7
8
TD+
TDCT
NC
NC
CT
RD+
RD-
TX+
TXCT
NC
NC
CT
RX+
RX-
16
15
14
13
12
11
10
9
RJ45_MIDI0+
RJ45_MIDI0-
CL39
2
CL40
2
RJ45_MIDI1+
RJ45_MIDI1-
1000P_0402_50V7K
1
1
RL11
1000P_0402_50V7K
1
1
RL12
2
75_0402_1%
2
75_0402_1%
10/100M transformer_NS681695
UL4
8111FVB@
1
2
3
4
5
6
7
8
TD+
TDCT
NC
NC
CT
RD+
RD-
TX+
TXCT
NC
NC
CT
RX+
RX-
16
15
14
13
12
11
10
9
RJ45_MIDI2+
RJ45_MIDI2-
RJ45_MIDI3+
RJ45_MIDI3-
8111FVB@
CL41 1000P_0402_50V7K
2
1
1
RL13
CL42 1000P_0402_50V7K
2
1
1
RL15
8111FVB@
PR1+
PR1PR2+
For ESD
+3V_LAN
AO3413_SOT23
@
CL482
0.01U_0402_25V7K
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
2
0.1U_0402_10V7K
LAN_X2
10PF_0402_50V9
2 1
2
RL29
22_0402_5%
GCLK@
GCLK@
GND
PJ29
PAD-OPEN 2x2m
2
1
RL8 GCLK@
1
2
0_0402_5%
1
CL19
1
CL20
1
CL21
1
CL22
1
CL23
1
CL24
1
CL25
For P/N and footprint

Please place them to ISPD page
ENSWREG
@ QL51
2
CL681
4.7U_0805_10V4Z
@
PR3+
PR3PR2PR4+
GND
GND
D92
AZC199-02SPR7G_SOT23-3
@
9
10
PR4SANTA_130452-S
@
8111FVB@
2
75_0402_1%
2
75_0402_1%
8111FVB@
D93
@
For ESD
10/100M transformer_NS681695
D100
LAN_MDI2+
I/O4
@
I/O2
LAN_MDI3+
+3V_LAN
VDD
GND
I/O3
I/O1
RJ45_GND
LAN_MDI2-
2
1000P_1808_3KV7K 1
LANGND
1
CL37
220P_0402_50V6K
CL38
@
4.7U_0603_6.3V6K
LAN_MDI3-
Compal Secret Data
Issued Date
1
CL36
CL34
0.1U_0402_25V6
Place CL34 colse
to UL4
8111FVB@
+LAN_VDDREG
1
8111FVB@ LL3
NOGCLK@ YL1 25MHZ_20PF_7V25000016
CL17
0.1U_0402_10V7K
Placement near to YL1
LAN_X1 1
CL483
@
0.1U_0402_10V7K
LAN
+3V_LAN
RL4
0_0402_5%
8111FVB@
+3VALW_PCH
@ RL432
47K_0402_5%
CL18
1U_0402_6.3V6K
Close to Pin 21
LAN_X1_R
36
0.1U_0402_10V7K
HIGH
Pin14
Pin15
+3VALW
WOL_EN#
+LAN_VDD10
0.1U_0402_10V7K
2
S0
+3VALW
31
3
6
9
45
0.1U_0402_10V7K
2
LOW
Sx Disable
Wake up
26
+3VALW TO +3V_LAN
+LAN_EVDD10
0.1U_0402_10V7K
2
Sx Enable
Wake up
RL147
100K_0402_5%
@
21
0.1U_0402_10V7K
2
CL19, CL20,CL21 close to pin 13,29,45, respectively

CL22 close to pin 3, respectively
CL23,CL24,CL25 close to pin 6,9,41, respectively
2
0_0603_5%
WOL_EN#
RL7
15K_0402_5%
WOL_EN#
GND
PGND
+3V_LAN
0.1U_0402_10V7K
2
2
0_0402_5%
+3V_LAN
12
42
47
48
1
RL433
+LAN_VDD10
1
LL2
ISOLATE#
2
2
2.49K_0402_1%
27
39
1
CL3
1
CL4
1
CL5
1
CL6
1
CL7
1
CL8
+LAN_EVDD10
+LAN_VDD10
1
RL5
8111FVB@
DVDD33
DVDD33
CL9
0.1U_0402_10V7K
2 8111FVB@
8111FVB@
LANWAKEB
LAN_EN
13
29
41
DVDD10
DVDD10
DVDD10
+3VS
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-
1
Layout Note: LL1 must be
within 200mil to Pin36,
CL13
CL13,CL9 must be within 4.7U_0603_6.3V6K
200mil to LL1
8111FVB@ 2
+LAN_VDD10
CKXTAL2
33
ENSWREG
1
2
4
5
7
8
10
11
1 10K_0402_5%
1 10K_0402_5%
@
@
RL22 1
2
2
CKXTAL1
1 10K_0402_5% EC_SWI#
+3V_LAN
RL2
RL1
19
20
PERSTB
LANCLK_REQ#
18,26
+3V_LAN
RL25 2
CLK_LAN
CLK_LAN#
MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3
30
32
18111FVB@ 2
RL28
0_0402_5%
8105ELDO@
RL24 2
1 10K_0402_5%
CLKREQB
25
PLT_RST#
+LAN_VDD10
LL1
8111FVB@
1
2
+LAN_REGOUT
2.2UH +-5% NLC252018T-2R2J-N
TL1
+3VS
16
EECS
EEDI
CL3 to CL6 close to Pin 27,39,47,48

CL7 to CL8 close to Pin 12,42
2N7002_SOT23-3
3
LANCLK_REQ#
QL53
HSIP
HSIN
Add test point

for pin37 on DVT
31
37
40
LED3/EEDO
LED1/EESK
LED0
HSON
+3V_LAN
8105ELDO@
1
CLKREQ_LAN#
17 CLKREQ_LAN#
17 PCIE_PTX_C_LANRX_P1
17 PCIE_PTX_C_LANRX_N1
2
G
LAN_EN
LAN_EN
HSOP
17
17 PCIE_PRX_C_LANTX_P1
2011/11/21
2011/12/11
Deciphered Date
C
Title

PCIe-LAN-RTL8105E/8111F
Size
Document Number
Custom
Rev
0.2
QMLE4 LA-8864P
Date:
Sheet

E
27
of
48
CardReader Conn.
Add R2957 0 ohm to protect +3VS
JCRIO
R2957
1
2
0_0603_5%
+3VS
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+3VS_CR
USB20_N8_R
USB20_P8_R
30
30
HP_R
HP_L
HP_R
HP_L
30
30
30
30
MIC1_L
MIC1_R
MIC_SENSE
NBA_PLUG
MIC1_L
MIC1_R
MIC_SENSE
NBA_PLUG
GND
GND
12
11
10
9
8
7
6
5
4
3
2
1
20
USB20_N8
USB20_N8
LR9
3
2
ACES_88058-120N
@
20
USB20_N8_R
4
1
WCM-2012-900T_0805
1
2 RR66
0_0402_5%
USB20_P8
USB20_P8
2 RR67
0_0402_5%
@
USB20_P8_R
CT2
0.1U_0402_10V7K
TPM9655@
CT3
0.1U_0402_10V7K
TPM9655@
CT4
0.1U_0402_10V7K
TPM9655@
0.1U_0402_10V7K
0.1U_0402_10V7K
+3VS
+VSB_TPM
1
TPM1.2 on board
TPM_XTALI
2
CT2
TPM9635@
CT3
CT4
TPM9635@ TPM9635@
1
+3VALW
2
1 0_0603_5%
TPM9635@
CT5
0.1U_0402_10V7K
TPM9655@
15
7
RT7
@ 4.7K_0402_5%
14
TPM_XTALI
13
24
19
10
VSB
GPIO
GPIO2
SLB 9635 TT 1.2

CLKRUN#
TEST1
TESTB1/BADD
6
2
PAD
PAD
TPM_GPIO
TPM_GPIO2
@ T61
@ T62
Base I/O Address

0 = 02Eh
1 =*04Eh
8
9
+3VS
TPM9635@
0_0402_5%
RT5 1
2
TPM9635@
RT3
4.7K_0402_5%
PP
NC
NC
NC
XTALO
3
12
1
XTALI/32K IN
TPM9655@
0_0402_5%
RT12 1
2
RT6
4.7K_0402_5%
@
PLT_RST#
25
18
11
4
RT8
TPM9655@
0_0402_5%
GND
GND
GND
GND
RT8
TPM9635@
0_0402_5%
SLB 9635 TT 1.2_TSSOP28

TPM9635@
RT2
TPM9635@
4.7K_0402_5%
TPM_XTALO
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
LPCPD#
SERIRQ
LCLK
2
1
@
2
CT7
RT4
10_0402_5%
RT11 1
2 0_0402_5%
TPM9635@
26
23
20
17
22
16
28
27
21
@ 1
10P_0402_50V8J
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PLT_RST#
LPC_PD#
SERIRQ
16,31
SERIRQ
20 CLK_PCI_TPM_PCH
+3VS
+3VS
RT9
TPM_XTALO
16,31,32 LPC_AD0
16,31,32 LPC_AD1
16,31,32 LPC_AD2
16,31,32 LPC_AD3
16,31,32 LPC_FRAME#
5,20,26,27,31,32 PLT_RST#
+VSB_TPM
CT5
TPM9635@
1 0.1U_0402_10V7K
RT10 2
1 0_0603_5%
TPM9655@
0.1U_0402_10V7K
2
22P_0402_50V8J
VDD
VDD
VDD
CT6
TPM9635@
+VDD_TPM
@ RT1
10M_0402_5%
UT1
1
RT13
0_0603_5%
TPM9655@
+VSB_TPM
1
YT1
32.768KHZ_12.5P_1TJF125DP1A000D
TPM9635@
1
2
CT1
22P_0402_50V8J
TPM9635@
LPC_PD#
Compal Secret Data
Issued Date
2011/01/31
2012/12/31
Deciphered Date
5
Title

PCIe-CardReader RTS5129/TPM
Size
Document Number
Custom
Date:
Rev
0.2
QFKAA
Sheet

1
28
of
48
2 RR44
0_0402_5%
2 RR45
0_0402_5%
USB20_N0
2
1
CEN
USB20_DN0
USB20_DP0
SELCDP
RB74
4.7K_0402_5%
@
1
2
3
4
9
8
SLP_CHG#
CEN
CB 7
USB20_N0
DM
TDM 6
USB20_P0
DP
TDP 5
SELCDP
VDD
Thermal Pad
SLG55584AVTR_TDFN8_2X2
+USB_VCCB
+5VALW
CB25
0.1U_0402_16V7K
@
31 USB_CHG_EN#
USB_CHG_EN#
2
3
4
1
IN
OUT
IN
OUT
EN/ENB OUT
GND
OCB
1
1000P_0402_50V7K
CR38
USB_OC#0
SA00004KB00
SA00003TV00
CB49
10U_0603_6.3V6M
@
+USB_VCCC
20
+5VALW
CR39
4.7U_0805_10V4Z
2@
R568
+USB_VCCB
AO3413_SOT23
@
100K_0402_5%
D
USB_EN#
25,31 USB_EN#
To EC
+USB_VCCB
Pull-up for SLGC55584AV
6
7
8
5
SY6288DCAC_MSOP8
PAD-OPEN 2x2m
Q8
For EMI
UR3
SLP_CHG# 20
USB20_N0 20
USB20_P0 20
W=80mils
RB75
4.7K_0402_5%
@
4.7U_0805_10V4Z
+USB_VCCC
0.1U_0402_10V7K
W=80mils
SLP_CHG# SELCDP
SELCDP
Function
CR46
DCP autodetect with

mouse/keyboard wakeup
RB76
4.7K_0402_5%
@
S0 charging with SDP only
Pull-down for SLGC55584V
S0 charging with CDP or SDP only
CR40
1
2
W=60mils
2.5A
+5VALW
PJ31
USB20_P0
+5VALW
U15
USB20_DP0
2
G
USB20_DN0
RB73
4.7K_0402_5%
@
Sleep & Charge Function
+5VALW
CR44
220U_6.3V_M
0.1U_0402_10V7K
CR45
1
+ CR47
@
1000P_0402_50V7K
220U_6.3V_M
CR42
4.7U_0805_10V4Z
CR43
CR41
2
1000P_0402_50V7K
20
1 @
U3RXDP1_R
LR1
3
2
20
20
U3TXDP1
CR25 1
2 0.1U_0402_10V7K U3TXDP1_C
LR2
3
2
U3TXDN1
1 @
IUSB30@
20
U3TXDN1_C
3
2
1 @
LR3
3
2
USB20_DN0
2 2
9 8
U3RXDP1_R_L
4 4
7 7
U3RXDP1_R_L
U3RXDN1_R_L
5 5
6 6
U3RXDN1_R_L
@
10 9
U3TXDP1_R_L
U3TXDN1_R_L
U3TXDP1_R_L
+USB_VCCB
U3TXDP1_R_L
U3TXDN1_R_L
USB20_N0_L
3 3
USB20_P0_L
U3RXDP1_R_L
U3RXDN1_R_L
9
1
8
2
7
3
6
4
5
YSCLAMP0524P_SLP2510P8-10-9
2 RR26
0_0402_5%
IUSB30@
DR7
1 1
U3TXDN1_R_L
JUSBA
U3RXDN1_R_L
KINGCORE WCM-2012HS-670T
1
2 RR22
0_0402_5%
@
USB20_DP0
U3TXDP1_R_L
2 RR32
0_0402_5%
IUSB30@
4
4
1
U3RXDP1_R_L
1
2 RR20
@
0_0402_5%
U3RXDN1_R
IUSB30@
2 0.1U_0402_10V7K
CR24 1
2 RR19
0_0402_5%
IUSB30@
U3TXDN1_R_L
USB20_P0_L
DR1
USB20_P0_L
USB20_N0_L
WCM-2012-900T_0805
1
2 RR25
0_0402_5%
@
SSTX+
VBUS
SSTXDGND
10
D+
GND 11
SSRX+
GND 12
GND
GND 13
SSRXGND
OCTEK_USB-09EAEB
@
2
1
3
USB20_N0_L
Change ESD Diode for EMI request
20
1 @
2 RR42
0_0402_5%
1
2
1
2
U3RXDP2_R
LR5
20
U3TXDP2
20
U3RXDN2_R
IUSB30@
2 0.1U_0402_10V7K
CR34 1
@
U3TXDP2_C
U3RXDN2_R_L
JUSBB
U3TXDP2_R_L
DR8
1 1
10 9
U3TXDP2_R_L
U3TXDN2_R_L
2 2
9 8
U3TXDN2_R_L
U3RXDP2_R_L
4 4
7 7
U3RXDP2_R_L
U3RXDN2_R_L
5 5
6 6
U3RXDN2_R_L
IUSB30@
2 RR40
0_0402_5%
1 @
2 RR43
0_0402_5%
1
U3RXDP2_R_L
U3TXDP2_R_L
@
+USB_VCCC
U3TXDN2_R_L
USB20_N1_L
USB20_P1_L
U3RXDP2_R_L
U3TXDP2_R_L
U3RXDN2_R_L
3 3
LR6
U3TXDN2
CR35 1
2 0.1U_0402_10V7K U3TXDN2_C
1
@
SSTX+
VBUS
SSTXDGND
D+
SSRX+
GND
SSRX-
GND
GND
GND
GND
10
11
12
13
OCTEK_USB-09EAEB
@
20
9
1
8
2
7
3
6
4
5
IUSB30@
2 RR41
0_0402_5%
YSCLAMP0524P_SLP2510P8-10-9
U3TXDN2_R_L
IUSB30@
20
1 @
USB20_P1
LR4
3
2
20
USB20_N1
2 RR39
0_0402_5%
IUSB30@
USB20_P1_L
DR4
USB20_P1_L
USB20_N1_L
WCM-2012-900T_0805
1
2 RR38
@
0_0402_5%
2
1
3
USB20_N1_L
Change ESD Diode for EMI request
Issued Date
Compal Secret Data
200910/9
Deciphered Date
2010/01/23
Title
USB3.0
Size
Document Number
Custom
Date:
Rev
0.2
QFKAA

1
Sheet
29
of
48
35mA for 3.3V level
15
14
MIC2_R
MIC2_L
AVDD1
AVDD2
MIC1_VREFO_L
MIC1_VREFO_R
MIC2_VREFO
PVDD1
PVDD2
LINE2_R
LINE2_L
SPK_OUT_R+
SPK_OUT_R-
MONO_OUT
SPK_OUT_L+
SPK_OUT_L-
1
9
+DVDD_IO
+3VS_DVDD
25
38
+AVDD
+AVDD
39
46
+PVDD
+PVDD
45
44
SPKR+
SPKR-
close to pin 25 close to pin 38
2
RA28 0_0603_5%
0.1U_0402_16V4Z +DVDD_IO
+3VS
+AVDD
2
DVDD
DVDD_IO
2
RA17 0_0603_5%
CA4
CA3
10U_0805_6.3V6M
CA42
0.1U_0402_10V7K
0.01U_0402_25V7K
2
@ CA65 1
2
MONO_IN
100P_0402_50V8J
12
PCBEEP
10
16 AZ_SYNC_HD
SYNC
11
16 AZ_RST_HD#
HPOUT_R
HPOUT_L
RESET#
close to pin19
close to pin 28
10U_0603_6.3V6M 1
2
CA54
2
CA53
AC_VREF
1
CA55
2
2
0.1U_0402_10V7K
CA56
2.2U_0603_6.3V6K
@
2
RA34
13 INT_MIC_DATA
19
28
27
1CPVEE
34
2.2U_0603_10V6K 35
1
36
2.2U_0603_10V6K
INT_MIC_CLK_R
SENSE_A
SENSE_B
1
20K_0402_1%
JDREF
LDO_CAP
VREF
CPVEE
CBN
CBP
2
3
BCLK
NC
NC
NC
GPIO0/DMIC_DATA
GPIO1/DMIC_CLK
13
18
AVSS1
AVSS2
PVSS1
PVSS2
DVSS
SENSE_A
SENSE_B
47
4
31 EC_MUTE#
SDATA_OUT
SDATA_IN
2 RA30
1AC_JDREF
20K_0402_1%
2CA60
EAPD
PD#
Thermal Pad
40
41
close to pin39
HP_R
28
HP_L
28
CA32
+5VS
CA36
10U_0805_6.3V6M
0.1U_0402_10V7K
2
AZ_SDOUT_HD 16
AZ_SDIN0_HD 16
2
1
RA23 33_0402_5%
AZ_BITCLK_HD
23
24
48
+5VS
CA39
10U_0603_6.3V6M
place close to chip
AZ_SDIN0_HD_R
CA34
1
10U_0603_6.3V6M
SPKL+
SPKL-
75_0402_1%
33 RA19
32 RA20
75_0402_1%
5
8
CA50
CA35
2
20
1
CA59
CA37
LA6
1
2 0.1U_0402_10V7K
2 PBY160808T-601Y-N_2P
1
+PVDD
CA33
CA47
RA18
1
2
0_0603_5%
0.1U_0402_10V7K
1
1
1
2
1
2
10U_0603_6.3V6M 10U_0603_6.3V6M
0.1U_0402_16V4Z
+3VS_DVDD
1
CA46
CA45
10U_0805_6.3V6M
0.1U_0402_10V7K
1
2
17
16
31
30
29
+MIC1_VREFO_L
+MIC1_VREFO_R
+MIC2_VREFO
+3VS
MIC1_R
MIC1_L
MIC2_R
MIC2_L
22
21
MIC1_R_C_R
MIC1_R_C_L
CA58
CA57
UA1
MIC1_R_R 4.7U_0603_6.3V6K
MIC1_R_L 4.7U_0603_6.3V6K
@
AZ_BITCLK_HD 2
10_0402_5%
AZ_BITCLK_HD
CA51
1
1
2 @
RA29
10P_0402_50V8J
16
For EMI
please place near codec
26
37
42
43
7
EC Beep
AGND
49
1 RA51
31 EC_BEEP#
Beep sound
47K_0402_5%
ALC259-VC2-CG_MQFN48_6X6
PCI Beep
For EMI
RA42
INT_MIC_CLK_R
FBMA-10-100505-301T
CAM@
1
1 RA52
16 PCH_SPKR
DGND
RA49
4.7K_0402_5%
EC_MUTE#
SPKL+
+MIC2_VREFO
RA24
4.7K_0402_5%
AMIC@
SPKL-
2
MIC2_L
MIC2_R
AMIC@
CA26
1 1U_0402_6.3V4Z
1 1U_0402_6.3V4Z
CA28
AMIC@
AMIC@
RA25
1 1K_0402_5%
1 1K_0402_5%
RA26
AMIC@
SPKR+
JMIC
INT_MIC
CA27
1
2
220P_0402_50V7K
AMIC@
1
2
3
4
1
2
GND
GND
ACES_50271-0020N-001
@
SPKR-
close to Codec
placement near Audio Codec

LA7
2
1
0_0603_5%
RA50
4.7K_0402_5%
SPK_L1
2
CA71
@
10U_0603_6.3V6M
1
To solve noise issue

2
2
CA72
@
LA8
10U_0603_6.3V6M
1
2
1
0_0603_5%
LA9
2
1
0_0603_5%
2
CA76
@
10U_0603_6.3V6M
1
CA74
1U_0402_6.3V4Z
@
SPK_L2
2
CA75
@
10U_0603_6.3V6M
LA10
1
2
1
0_0603_5%
Impedance
39.2K
SENSE A
A
Codec Signals
PORT-I (PIN 32, 33)
CA73
1U_0402_6.3V4Z
@
2
RA47
1K_0402_5% RA48
2
1
MIC1_R_R
2
1
1K_0402_5%
RA45
MIC1_R_L
SPK_R2
20K
PORT-B (PIN 21, 22)
10K
PORT-C (PIN 23, 24)
Headphone out
28
MIC_SENSE
2
RA32
1
20K_0402_1%
CA63 1
SENSE_A
Ext. MIC
28
NBA_PLUG
SENSE B
PORT-E (PIN 14, 15)
20K
PORT-F (PIN 16, 17)
10K
PORT-H (PIN 20)
2 0.1U_0603_50V7K
CA66 1
2 0.1U_0603_50V7K
CA62 1
2 0.1U_0603_50V7K
SPK_R1
SPK_R2
SPK_L1
SPK_L2
28
+MIC1_VREFO_L
JSPK
1
2
3
4
1
2
3
4
ACES_85204-0400N
@
39.2K_0402_1%
2
DA11 AZ5125-02S.R7G_SOT23-3
@
Compal Secret Data
2011/11/11
Issued Date
2012/12/31
Deciphered Date
Title
Custom
Date:
28
MIC1_L
DA10 AZ5125-02S.R7G_SOT23-3
@
(PIN 48)
39.2K
1
2.2K_0402_5%
MIC1_R
RA31 0_0603_5%
5.1K
+MIC1_VREFO_R
2 0.1U_0603_50V7K
CA61 1
1
RA33
2
RA46
1
2.2K_0402_5%
place close to chip
Function
Ext.MIC/LINE IN JACK
SPK_R1
SPK Conn.
Sense Pin
CA69
100P_0402_50V8J
2W 4ohm =40mil
1W 8ohm =20mil
Analog MIC
MONO_IN
0.1U_0402_10V7K
EC_MUTE# Internal AMP

Hight
Enable
LOW
Disable
CA52 CAM@
220P_0402_50V7K
CA70
1
2
47K_0402_5%
13 INT_MIC_CLK
USB3.0 control
Rev
Sheet
1
30
of
48
+3VL
CB1
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CB2
0.1U_0402_10V7K
1
1
CB5
CB6
2
2
1000P_0402_50V7K
UB1
20 CLK_PCI_EC
5,20,26,27,28,32 PLT_RST#
+3VL
RB2
47K_0402_5%
1
2
1
CB12
21
EC_SCI#
26 AOAC_WLAN_PWR_EN#
EC_RST#
2
0.1U_0402_10V7K
KSI[0..7]
32
KSO[0..15]
+3VL
RB12
1
1
RB13
2.2K_0402_5%
2 EC_SMB_CK1
2 EC_SMB_DA1
2.2K_0402_5%
+3VS
RB15
1
1
RB16
2.2K_0402_5%
2 EC_SMB_CK2
2 EC_SMB_DA2
2.2K_0402_5%
KSI[0..7]
KSO[0..15]
35,36 EC_SMB_CK1
35,36 EC_SMB_DA1
17 EC_SMB_CK2
17 EC_SMB_DA2
18 PM_SLP_S3#
18 PM_SLP_S5#
21
EC_SMI#
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
RB20
0_0402_5%
1
2
122
123
RB22
100K_0402_5%
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00
21
23
26
27
WL_BT_LED#
EC_BEEP#
63
64
65
66
75
76
BATT_TEMPA
WL_BT_LED# 33
EC_BEEP# 30
ADP_I
UMA_ENBKL
68
70
71
72
SPI Flash ROM
GPIO
Bus
GPIO
XCLKI/GPIO5D
XCLKO/GPIO5E
BATT_TEMPA
1
CB9
2
100P_0402_50V8J
ACIN_D
1
CB10
2
100P_0402_50V8J
+3VS
TV tuner
temperature
19
H_PROCHOT#_EC
EN_DFAN1
PCH_SUSPWRDN#
SUSACK#
EN_DFAN1 5
PCH_SUSPWRDN#
SUSACK# 18
83
84
85
86
87
88
EC_MUTE#
USB_EN#
97
98
99
109
VGATE
WOL_EN#
PWRME_CTRL
VCIN0_PH
119
120
126
128
VCIN0_PH connect to
power portion (9012 only)
EC_MUTE# 30
USB_EN# 25,29
TP_CLK
TP_DATA
35,36
UMA_ENBKL
CB8
47P_0402_50V8J
1
RB6
2
10K_0402_5%
18

2011/10/18a
TP_CLK 33
TP_DATA 33
VGATE
18,42
WOL_EN# 27
PWRME_CTRL 16
VCIN0_PH 35
+3VL
LID_SW#
1
RB35
2
47K_0402_5%
TP_CLK
1
RB8
2
4.7K_0402_5%
TP_DATA
1
RB9
2
4.7K_0402_5%
SYSON
1
RB10
2
4.7K_0402_5%
+5VS
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
GPI
2
G
BATT_TEMPA 35
ADP_I
1
QB1
SPI Device Interface
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
CB16
20P_0402_50V8
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
PS2 Interface
H_PROCHOT#
D
67
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
DA Output
11
24
35
94
113
@
1
2
SUSP#
CB14
180P_0402_50V8J
BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
AD Input
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
PWM Output
CLK_EC
77
78
79
80
FAN_SPEED1
WL_OFF#
E51_TXD
E51_RXD
PM_PWROK
PWR_SUSP_LED#
5 FAN_SPEED1
26
WL_OFF#
26
E51_TXD
26
E51_RXD
5,18 PM_PWROK
33 PWR_SUSP_LED#
18
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
USB_CHG_EN#
BT_ON
29 USB_CHG_EN#
26
BT_ON
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
32
12
13
37
20
38
CLK_PCI_EC
PLT_RST#
EC_RST#
EC_SCI#
AOAC_WLAN_PWR_EN#
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0LPC & MISC
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
AGND/AGND
0_0402_5% RB1
1
2
VR_HOT#
SSM3K7002F_SC59-3
EC_VDD/AVCC
1
1
1
2
3
4
5
7
8
10
GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
21
GATEA20
21 KB_RST#
16,28 SERIRQ
16,28,32 LPC_FRAME#
16,28,32 LPC_AD3
16,28,32 LPC_AD2
16,28,32 LPC_AD1
16,28,32 LPC_AD0
2
CB11
22P_0402_50V8J
@
69
9
22
33
96
111
125
CB4
2
0.1U_0402_10V7K
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
GND/GND
GND/GND
GND/GND
GND/GND
GND0
CLK_PCI_EC
42
CB3
0.1U_0402_10V7K
1
2
H_PROCHOT#_EC
For EMI
RB3
10_0402_5%
@
+3VL
1000P_0402_50V7K
1
1
CB7
V18R
73
74
89
90
91
92
93
95
121
127
DRAMRST_CNTRL_EC
BATT_FULL_LED# 33
WLAN_RST# 26
BATT_FULL_LED#
WLAN_RST#
BATT_CHG_LOW_LED#
SYSON
VR_ON
100
101
102
103
104
105
106
107
108
PCH_RSMRST#
EC_LID_OUT#
PROCHOT_IN
H_PROCHOT#_EC
VCOUT0_PH_L
BKOFF#
PBTN_OUT#
PCH_PWR_EN
SA_PGOOD
110
112
114
115
116
117
118
ACIN_D
EC_ON_R
ON/OFFBTN#
LID_SW#
SUSP#
124
+EC_V18R
BATT_CHG_LOW_LED#
SYSON
38
VR_ON
42
PM_SLP_S4# 18
PCH_RSMRST# 18
EC_LID_OUT# 21
PROCHOT_IN 35
BKOFF#
13
PBTN_OUT# 18
PCH_PWR_EN 34
SA_PGOOD 41
33
2
0_0402_5%
VS_ON
37
RB18
330K_0402_5%
2
1
NV-GPU GPS function control pin

connect to a OR-gate
in the power portion
2
RB751V40_SC76-2
+3VL
1
DB1
ACIN
18,36
B
ON/OFFBTN# 25,33
LID_SW# 33
SUSP#
34,38,39,40
1
RB19
2
H_PECI
43_0402_1%
H_PECI
1
RB34
VCOUT0_PH connect to power portion (9012 only)
VCOUT0_PH connect
to power portion (9012 only)
ACIN_D
EC_PECI
KB9012QF-A3_LQFP128_14X14
VCOUT0_PH_L
PROCHOT_IN connect
to power portion (9012 only)
SUSP#
1
RB21
2
10K_0402_5%
VR_ON
1
RB23
2
10K_0402_5%
CB15
4.7U_0805_10V4Z
Close to EC
1
EC_ON_R
RB36
Voltage Comparator Pins FOR 9012 A3
2
EC_ON
2.2K_0402_5%
1
CB50
1U_0402_6.3V6K
37
VCIN0 pin109
VCIN1 pin102
A
RB27
100K_0402_5%
1
2
>1.2V
<1.2V
VCOUT0 pin104
HIGH
LOW
VCOUT1 pin103
LOW
HIGH
For KB9012 EC_ON low pulse work around
Issued Date
Compal Secret Data
E51_TXD
2010/12/22
2011/12/22
Deciphered Date
5
Title
LPC-EC-KB9012&930
Size
Date:
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev
0.2
Sheet
31
of
48
SPI Flash (128KB)
Lid SW
LPC Debug Port

JDB
Place the JDB under DDR DIMM.
1
2
3
4
5
6
7
8
9
10
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
+3VS
PLT_RST# 5,20,26,27,28,31
CLK_PCI_DDR 20
LPC_FRAME# 16,28,31
LPC_AD3 16,28,31
LPC_AD2 16,28,31
LPC_AD1 16,28,31
LPC_AD0 16,28,31
CLK_PCI_DDR
E-T_3801K-F10N-01L
C457
2 1
22P_0402_50V8J
@
R393
CLK_PCI_DDR
22_0402_5%
@
For EMI
G-Sensor
KEYBOARD CONN.
JKB
26
27
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
GND 24
GND 25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
KSO0
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSO9
KSO8
KSO7
KSI7
KSI6
KSO6
KSI5
KSO5
KSI4
KSI3
KSI2
KSI1
KSO4
KSI0
KSO3
KSO2
KSO1
KSO0
KSO1
KSO2
KSO3
KSI0
KSO4
KSI1
KSI2
KSI3
KSI4
KSO5
KSI5
KSO6
KSI6
ACES_50524-02501-001
@
KSI7
KSO7
KSI[0..7]
KSO[0..15]
KSI[0..7]
31
KSO[0..15] 31
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
1
C406
1
C405
1
C404
1
C408
1
C425
1
C407
1
C431
1
C422
1
C423
1
C424
1
C409
1
C427
1
C411
1
C429
1
C421
1
C412
1
C415
1
C416
1
C417
1
C418
1
C419
1
C413
1
C410
1
C420
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
For EMI
Close to JKB
Issued Date
Compal Secret Data
2010/09/03
Deciphered Date
2012/12/31
Title
Size
Date:
Debug/KB
Document Number
Rev
0.2
QFKAA
Sheet
32
of
48
Power Button
+3VL
SW4
JTP
TP_CLK
TP_DATA
G
G
31
31
6
5
1
2
3
4
5
6
7
8
9
10
11
12
+3VL
NTC017-DA1J-D160T_4P
R395
ON/OFFBTN#
For debug
2
TP_CLK
TP_DATA
R801
LID_SW#
BATT_FULL_LED#
BATT_CHG_LOW_LED#
PWR_SUSP_LED#
HDD_LED#
2 WL_BT_LED_R#
0_0402_5%
1
R802 @
2
0_0402_5%
31
LID_SW#
31 BATT_FULL_LED#
31 BATT_CHG_LOW_LED#
31 PWR_SUSP_LED#
100K_0402_5%
For debug
+5VS +5VALW
Touchpad Connector
ON/OFFBTN#
25,31
31
WL_BT_LED#
C458
0.1U_0402_25V6
@
WIMAX_LED#
1
2
3
4
5
6
7
8
9
10
11 G1
12 G2
13
14
ACES_50504-0120N-001
@
SW3
Mount R802 and un-mount R801

When Wlan LED need Blinking
WiMAX LED
CPU
LED_WIMAX# 26
Screw Hole
R819
H1
VGA
H2
H_4P2
@
1
1
10K_0402_5%
WIMAX@
+3VS
H3
H_4P6
@
H4
PCH
H5
H_4P2x4P6
@
H_3P5
@
H8
H_3P0
@
H_3P0
@
6
5
G
G
NTC017-DA1J-D160T_4P
For EMI request
Q156A
2N7002DW-T/R7_SOT363-6
WIMAX@
Q156B 2N7002DW-T/R7_SOT363-6
WIMAX@
C
WIMAX_LED#
SATA LED
SATA_LED# 16
R820
PTH
NPTH
H14
H_3P0
@
H15
H_3P0
@
H17
H_3P0
@
H9
H_3P0
@
H16
H_3P0x4P0N
@
H_3P0N
@
H13
H_3P0
@
H12
H_3P0
@
H11
H_3P0
@
H10
H_3P0
@
H7
Q5534B
2N7002KDWH_SOT363-6
Q5534A
4 2N7002KDWH_SOT363-6
10K_0402_5%
HDD_LED#
+3VS
@
0_0402_5%
R4534
H18
H19
H_3P0
@
H_3P0
@
PCB Fedical Mark PAD

1
FD3
@
FD4
@
FD2
@
FD1
@
ISPD
ZZZ
PCB LA-8862P
PJP1
45@
PJP1
UH1
HM70R1@
Panther Point BD82HM70

A
UH1
HM76R3@
Panther Point BD82HM76
Issued Date
Compal Secret Data
2010/09/03
Deciphered Date
2012/12/31
Title
TP/PWR/LED/Screw/ISPD
Size
Document Number
Date:
Rev
0.2
QFKAA
Sheet
33
of
48
R413
820K_0402_5%
@
Q11A
Q11B
2
5
SUSP
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
C822
@
2
2
1
2
PCH_PWR_EN#
22,23 PCH_PWR_EN#
C821
1 R410
2
+VSB
200K_0402_5%
R470
470_0805_5%
R5545
10K_0402_5%
For EMI
Q190
2
SUSP
G
2N7002_SOT23-3
2
G
31 PCH_PWR_EN
Q5527
C468
R407
C467
SI4800BDY_SO8
1
470_0805_5%
C461
1U_0402_6.3V6K
3 1
S SB570020110
2N7002E-T1-E3_SOT23-3
R5529
100K_0402_5%
2
2
5
SUSP
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
1
2
3
4
0.1U_0402_10V7K
Q10B
S
S
S
G
0.1U_0402_10V7K
Q10A
D
D
D
D
+5VS
1
R409 2
+VSB
120K_0402_5%
Q30
8
7
6
5
R412
820K_0402_5%
R406
C466
C465
0.022U_0402_25V7K
4.7U_0805_10V4Z
SI4800BDY_SO8
1
C460
C459
1U_0402_6.3V6K
4.7U_0805_10V4Z
1
C462
+1.8VS
+5VALW
+5VS
0.01U_0402_25V7K
1
2
3
4
4.7U_0805_10V4Z
S
S
S
G
D
D
D
D
1
4.7U_0805_10V4Z
470_0805_5%
Q29
8
7
6
5
Vgs=10V,Id=9A,Rds=18.5mohm
+5VALW
Vgs=10V,Id=9A,Rds=18.5mohm
3 1
+3VS
+3VALW
+5VALW TO +5VS
+3VALW TO +3VS
Un-used Dual MOS
+0.75VS
+1.05VS_VCCP
2
+5VALW
For S3 CPU Power Saving
1
D
Q6A
Q189
2
SUSP
G
2N7002_SOT23-3
31,38,39,40 SUSP#
Q60
2N7002_SOT23-3
2
G
2N7002DW-T/R7_SOT363-6
0.75VR_EN 38
Q6B
5
SUSP
R468
470_0805_5%
0.75VR_EN
2
220K_0402_5%
1
R158
39,41 VCCP_PWRGOOD
SUSP
SUSP
5,9
R421
22_0805_5%
R422
100K_0402_5%
2N7002DW-T/R7_SOT363-6
+5VS_ODD
+5VS TO +5VS_ODD
6 1
R457
470_0805_5%
Q53A
+5VS
3
+5VS
2
Q45
2
R440
1
47K_0402_5%
AO3413_SOT23
C217
0.01U_0402_25V7K
PJ28
JUMP_43X79
@
+5VS_ODD
2N7002DW-T/R7_SOT363-6
Q53B
R441
10K_0402_5%
5
4
ODD_EN#
21
C471
0.1U_0402_10V7K
+3VS
ODD_EN#
2N7002DW-T/R7_SOT363-6
1
1
C679
4.7U_0805_10V4Z
@
C680
1U_0402_6.3V6K
Issued Date
Compal Secret Data
2010/09/03
2012/12/31
Deciphered Date
Title
Size
Date:
DC-DC INTERFACE
Document Number
Rev
0.2
QFKAA
Sheet

E
34
of
48
PL1
HCB2012KF-121T50_0805
1
2
PH1 under CPU botten side :

CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
VIN
PL2
HCB2012KF-121T50_0805
1
2
Please locate these parts

Near EC chip
ADP_I
PR4
12.1K_0402_1%
PR5
0_0402_5%
1
2
VCIN0_PH
31
PR2
0_0402_5%
1
2
31 PROCHOT_IN
PH1
100K_0402_1%_TSM0B104F4251RZ
PR1
1K_0402_1%
1
2
1
2
31,36
PR3
20K_0402_1%
SINGA_2DW-0005-B03
PC4
100P_0402_50V8J
+3VL
PC3
1000P_0402_50V7K
PC1
1000P_0402_50V7K
+
1
PC2
100P_0402_50V8J
@ PJP1
PL3
HCB2012KF-121T50_0805
1
2
VMB
BATT+
EC_SMB_DA1 31,36
1
@ PR13
2
1K_0402_1%
PR9
0_0402_5%
1
2VSB_N_002 2
G
POK
+3VL
2
6.49K_0402_1%
18,37
BATT_TEMPA 31
1VSB_N_003
EC_SMB_CK1 31,36
2
100_0402_1%
+VSBP
1
2
VSB_N_001
PQ2
SSM3K7002FU_SC70-3
PC10
.1U_0402_16V7K
2
100_0402_1%
1
PR11
1
PR10
1
@ PR12
PR7
22K_0402_1%
1
2
PR8
100K_0402_1%
PC8
0.22U_0603_25V7K
VL
@ PD2
PJSOT24CW_SOT323-3
2
1
3
1
PR6
100K_0402_1%
PC7
0.01U_0402_25V7K
B+
PC6
10U_0805_25V6K
2
1
1
2
PC5
1000P_0402_50V7K
PD1
PJSOT24CW_SOT323-3
CCM_C250137GR007M262ZR
PQ1
TP0610K-T1-GE3_SOT23-3
PL4
HCB2012KF-121T50_0805
1
2
EC_SMCA
EC_SMDA
TS_A
1
2
3
4
5
6
7
1
2
3
4
5
6
7
@
PJP2
PC9
0.1U_0603_25V7K
ADPIN
PJP3
+VSBP
+VSB
PAD-OPEN 2x2m
RTC Battery
PBJ1
+
1
PR14
560_0603_5%
1
2
PR15
560_0603_5%
1
2
+RTCBATT
@ MAXEL_ML1220T10
SP093MX0000
Compal Secret Data
Issued Date
2009/01/23
Deciphered Date
2010/01/23
Title
Size
Date:

PWR-DCIN / BATT CONN / OTP
Document Number
Rev
0.2
SAMSUNG
D
Sheet
35
of
48
PR225
2
1
PR232
0_0402_5%
PC225
0.01U_0402_50V7K
1
2
PC224
2200P_0402_50V7K
1
2
PC223
10U_0805_25V6K
1
2
PC222
10U_0805_25V6K
PC221
10U_0805_25V6K
PC241
0.1U_0402_25V6
2
1
CSON1
1
2
CSOP1
1
2
PR206
4.7_1206_5%
2
1
PC242
0.1U_0603_16V7K
Remember to change PC124 from SE000006S80

to SE025104K80 (2011-02-22)
ILIM
SCL
BATDRV
BQ24725_BATDRV
+3VALW
10
ACOK
CHG
11
3
2
1
12
PR236
10_0603_1%
2 CSOP1
SRP1
PR237
6.8_0603_5%
2 CSON1
SRN1
13
PC206
680P_0402_50V7K
SRN
DL_CHG
14
PQ202
FDMC7692S_MLP8-5
15
PR222
0.02_1206_1%
1
4
BTST
REGN
HIDRV
ACDRV
SDA
2
10K_0402_1%
SRP
CMSRC
2
10K_0402_1%
PR239
3
2
1
16
17
18
20
GND
IOUT
PL202
4.7UH_ETQP3W4R7WFN_5.5A_20%
BQ24725_LX
LODRV
ACDET
2 BQ24725_ACOK
10K_0402_1%
BATT+
PC205
1
2
ACP
+3VL
BQ24725_ACDRV
1
@ PR238
PQ201
AON7408L
DH_CHG
ACN
+3VALW
1
2
1
BQ24725_REGN2
PR229
2.2_0603_5%
1
BQ24725_BST 2
DH_CHG
PD231
RB751V-40_SOD323-2
BQ24725RGRR_VQFN20_3P5X3P5
BQ24725_CMSRC
PAD
PHASE
VCC
21
2BQ24725_BATDRV_1
PR233
4.12K_0603_1%
PC237
1U_0603_25V6K
PU200
PC240
0.1U_0402_25V6
PR228
10_1206_1%
1 1
2
BQ24725_VCC
1
2
PC235
0.1U_0402_25V6
1
2
PC238
0.1U_0603_25V7K
1
2
PR235
4.12K_0603_1%
BQ24725_ACN
PC239
1
2
1U_0603_25V6K
BQ24725_ACP
PR234
4.12K_0603_1%
0.047U_0402_25V7K
BQ24725_LX
19
PC236
0.1U_0402_25V6
BQ24725_BATDRV
PC234
0.01U_0402_50V7K
PD230
BAS40CW_SOT323-3
BQ24725_ACDRV_1
1
2
3
1
2
PC215
0.1U_0402_25V6
1
2
PC214
10U_0805_25V6K
1
2
8
7
6
5
PC216
0.1U_0402_25V6
VIN
PC213
10U_0805_25V6K
PL201
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
2
PR211
0.01_1206_1%
4
PC212
10U_0805_25V6K
8
7
6
5
PQ207
DMG4406LSS_SO8
PC211
10U_0805_25V6K
1
2
3
B+
1
2
@ PR231
0_0402_5%
1
2
3
P2
PQ205
DMG4406LSS_SO8
P1
PC230
2200P_0402_50V7K
SI1304BDL-T1-GE3_SC70-3
3M_0402_5%
PQ203
TPCA8057-H_PPAK56-8-5
PR226
1M_0402_5%
VIN
PC231
0.1U_0402_25V6
1
1
PQ209
2
G
for reverse input protection
PR241
PR246
100_0402_5%
PC245
100P_0402_50V8J
2
1
1
2
PC246
100P_0402_50V8J
1
2
PR245
66.5K_0402_1%
3A
1
ILIM and external DPM
Max.
Typ
17.296V
17.7V
PC244
0.1U_0402_25V6
H-->L
L-->H
EC_SMB_CK1 31,35
2.4 < Vdetect < 3.15V

Min.
150K_0402_1%
PC243
0.01U_0402_25V7K
1
2
Vin Dectector & ILIM
PR243
270K_0402_1%
BQ24725_ILIM
PR242
100K_0402_1%
VIN
BQ24725_ACDET
PR240
PR244
154K_0402_1%
18,31 ACIN
EC_SMB_DA1 31,35
ADP_I
31,35
Please locate the RC

Near EC chip
2011-02-22
Compal Secret Data
Issued Date
2009/01/23
Deciphered Date
2010/01/23
Title
Size
Date:

PWR-CHARGER
Document Number
Rev
0.2
SAMSUNG
D
Sheet
36
of
48
2VREF_8205
PC333
1U_0603_16V6K
1
19
LG_5V
PL352
1
2
NC
SNUB_5V 2
VREG5
VIN
18,35
RT8205LZQW(2)_WQFN24_4X4
PQ352
FDMC7692S_MLP8-5
VL
PC342
1U_0603_10V6K
PR338
100K_0402_1%
+5VALWP
PC359
4.7U_0805_10V6K
1
+
PC351
220U_6.3V_M
LX_5V
UG_5V
20
PR356
4.7_1206_5%
21
22
PQ351
AON7408L
3
2
1
PR355
PC355
2.2_0402_5%
0.1U_0402_10V7K
2 BST1_5V 1
2
BST_5V 1
PC356
680P_0402_50V7K
23
3
2
1
14
24
POK
13
PC358
10U_0805_25V6K
PC354
2200P_0402_50V7K
2
1
FB1
REF
ENTRIP1
TONSEL
ENTRIP2
LGATE1
PR334
499K_0402_1%
1
2
1
2
3
3/5V_B+
PQ332
FDMC7692S_MLP8-5
FB2
PHASE1
LGATE2
EN
PHASE2
@
2
UGATE1
12
LG_3V
BOOT1
UGATE2
18
5
PC336
PR336
680P_0402_50V7K
4.7_1206_5%
2
1 SNUB_3V 2
1
PC331
220U_6.3V_M
BOOT2
11
LX_3V
PGOOD
17
PL332
2
1
3/5V_B+
PR357
120K_0402_1%
1
2
VO1
VREG3
GND
+3VALWP
VO2
8
PC335
0.1U_0402_10V7K
PR333
1
2
2 BST_3V 9
BST1_3V 1
2.2_0402_5%
UG_3V 10
16
1
2
3
ENTRIP2
P PAD
PQ331
AON7408L
25
PU330
PC341
10U_0805_6.3V6M
PR337
120K_0402_1%
1
2
PC340
4.7U_0805_25V6-K
2
1
PC339
2200P_0402_50V7K
2
1
+3VLP
15
PC338
0.1U_0402_25V6
2
1
PR351
20K_0402_1%
2
FB_5V 1
FB_3V
SKIPSEL
PL331
HCB2012KF-121T50_0805
ENTRIP1
PR331
20K_0402_1%
1
2
3/5V_B+
B+
PR350
30K_0402_1%
1
2
PC353
0.1U_0402_25V6
2
1
PR330
13K_0402_1%
1
2
ENTRIP2
3
2N_3_5V_001
PQ333A
SSM6N7002FU_US6
PR339
100K_0402_5%
1
2
PJP333
PJP352
+5VALWP
+5VALW
+3VLP
(5A,200mils ,Via NO.= 10)
PR341
0_0402_5%
1
2
+3VALWP
+3VL
PJP353
+3VALW
VL
+5VL
PAD-OPEN 2x2m
PAD-OPEN 4x4m
PAD-OPEN 4x4m
PJP332
1
2
1
PAD-OPEN 2x2m
VL
PQ334
DRC5115E0L_SOD323-3
PC343
4.7U_0805_25V6-K
31 VS_ON
PQ333B
SSM6N7002FU_US6
PR340
2.2K_0402_1%
1
2
PC360
0.1U_0603_25V7K
G
S
31 EC_ON
ENTRIP1
6
3/5V_B+
2VREF_8205
Compal Secret Data
2007/08/02
Issued Date
2008/08/02
Deciphered Date
Title

PWR-3.3VALWP/5VALWP
Custom
Date:
Rev
0.2
QCLA4 LA-8861P M/B
Sheet
E
37
of
48
0.75Volt +/- 5%
TDC 0.7A
Peak Current 1A
D
PL151
HCB1608KF-121T30_0603
1
2
B+
1.5V_B+
BST_1.5V
PR155 2
+1.5V
BOOT_1.5V
+0.75VSP
PC262
10U_0805_6.3V6K
1
2
PC261
10U_0805_6.3V6K
20
VTT
18
19
VLDOIN
VTTREF_1.5V
+1.5VP
SYSON
1.5V_B+
PR159
0_0402_5%
1
2
PR154
10.2K_0402_1%
2
1
FB_1.5V
+1.5VP
PR160
10K_0402_1%
PR158
887K_0402_1%
1
2
PC162
.1U_0402_16V7K
VTTREF_1.5V
off
on
on
PC161
0.033U_0402_16V7K
10
+5VALW
1
2
3
PC160
1U_0603_10V6K
PC156
680P_0402_50V7K
31
+0.75VSP
off
off
on
EN_1.5V
Level
L
L
H
VDDQ
VDD
TON_1.5V
Mode
S5
S3
S0
BOOT
VTTREF
+5VALW
PQ152
FDMC7692S_MLP8-5
17
PR156
4.7_1206_5%
GND
RT8207MZQW_WQFN20_3X3
VDDP
21
FB
11
PAD
VTTSNS
S3
VDD_1.5V
CS
PU150
VTTGND
PGND
S5
PR157
5.1_0603_5%
1
2
12
PHASE
16
PC159
1U_0603_10V6K
1
2
LGATE
SNUB_+1.5VP 2
PC152
390U_2.5V_M
14
13
+1.5VP
PR152
20K_0402_1%
1
2CS_1.5V
1
2
3
PQ151
AON7408L
PL152
1UH_FDSD0630-H-1R0M-P3_11A_20%
2
1
15
TON
UGATE
DL_1.5V
PC260
10U_0805_6.3V6K
SW_1.5V
PGOOD
DH_1.5V
PC155
0.22U_0402_10V6K
PC158
4.7U_0805_25V6-K
1
2
PC157
10U_0805_25V6K
1
2
PC154
2200P_0402_50V7K
1
2
PC153
0.1U_0402_25V6
2.2_0402_5%
@PC163
@
PC163
0.1U_0402_10V7K
34 0.75VR_EN
PJP152
31,34,39,40 SUSP#
@PR161
@
PR161
0_0402_5%
2
1
EN_0.75VSP
Note: S3 - sleep ; S5 - power off
PR162
0_0402_5%
2
1
PAD-OPEN 4x4m
PJP153
+1.5VP
+1.5V
(12A,480mils ,Via NO.= 24)

2
PAD-OPEN 4x4m
@ PC164
0.1U_0402_10V7K
PJP76
+0.75VSP
+0.75VS (1A,40mils ,Via NO.= 3)
PAD-OPEN 3x3m
A
Compal Secret Data
Issued Date
2010/07/20
Deciphered Date
2012/12/31
Title

PWR-1.5VP / +0.75VSP
Custom
Date:
Rev
0.2
SAMSUNG
Sheet
1
38
of
48
PL401
HCB1608KF-121T30_0603
2
1
B+
PR401
100K_0402_1%
PC407
10U_0805_25V6K
2
1
PC403
2200P_0402_50V7K
2
1
+3VS
PC401
0.1U_0402_25V6
2
1
+1.05VSP_B+
PC408
10U_0805_25V6K
SW
VFB
V5IN
TST
DRVL
UG_+1.05VSP
SW_+1.05VSP
3
2
1
UG_+1.05VSP1
7
6
11
PQ402
TPCA8059
3
2
1
+1.05VSP1
@ PR408
1.2K_0402_1%
1
2
@ PC413
1000P_0402_50V7K
1
2
+1.05VSP
1
PR406
4.7_1206_5%
PC410
1U_0603_10V6K
PR407
470K_0402_1%
@ PC411
0.1U_0402_16V7K
PL402
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2
+5VALW
LG_+1.05VSP
TP
BST_+1.05VSP
+1.05VSP
PR409
4.99K_0402_1%
2
1
PC402
RF_+1.05VSP
EN
10
2
PC412
.1U_0402_16V7K
330U_D2_2.5VY_R15M
DRVH
FB_+1.05VSP
VBST
TRIP
EN_+1.05VSP
PGOOD
PQ401
AON7518
PR404
0_0402_5%
1
2
TRIP_+1.05VSP
PR402
60.4K_0402_1%
1
2
31,34,38,40 SUSP#
PR405
PC405
2.2_0402_5%
0.22U_0402_10V6K
1
2 BST1_+1.05VSP 1
2
PU400
TPS51212DSCR_SON10_3X3
1 SNUB_+1.05VSP2
34,41 VCCP_PWRGOOD
PC406
680P_0402_50V7K
PR410
100_0402_1%
2
1
VCCIO_SENSE
VCCIO_SENSE1
PR414
10K_0402_1%
PJP402
PAD-OPEN 4x4m
PJP403
+1.05VSP
+1.05VS_VCCP(12A,480mils ,Via NO.= 24)
PAD-OPEN 4x4m
Compal Secret Data
Issued Date
2010/07/20
Deciphered Date
2012/12/31
Title

PWR-V1.05SP
Custom
Date:
Rev
0.2
SAMSUNG
Sheet
1
39
of
48
PU180
SY8033BDBC_DFN10_3X3
2
2
1
2
PR182
10K_0402_1%
PC183
22U_0805_6.3V6M
FB_1.8VSP
PR181
20K_0402_1%
PC182
22U_0805_6.3V6M
+1.8VSP
PC188
68P_0402_50V8J
2
1
1
SNUB_1.8VSP
PR186
4.7_1206_5%
NC
1
@ PR184
47K_0402_5%
FB
EN
PC186
680P_0603_50V7K
EN_1.8VSP
LX
SVIN
11
PR183
0_0402_5%
LX_1.8VSP
PC187
0.1U_0402_10V7K
PG
PVIN
TP
LX
NC
PC184
22U_0805_6.3V6M
PVIN
10
VIN_1.8VSP
31,34,38,39 SUSP#
PL182
1UH_NRS4018T1R0NDGJ_3.2A_30%
1
2
PL181
HCB1608KF-121T30_0603
1
2
+5VALW
PJP182
+1.8VSP
+1.8VS

2
PAD-OPEN 4x4m
Compal Secret Data
Issued Date
2009/01/23
Deciphered Date
2012/12/31
Title
Size
Date:

PWR-1.8VSP
Document Number
Rev
0.2
SAMSUNG
D
Sheet
40
of
48
The 1k PD on the VCCSA VIDs are empty.

These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
VID [0]
0
0
1
1
VID[1]
0
1
0
1
VCCSA Vout
0.9V
0.8V
0.725V
0.675V
output voltage adjustable network
SNUB_+VCCSA
+VCC_SAP
TDC 4.2A
Peak Current 6A
OCP current 7.2A
PR801
4.7_1206_5%
PC805
680P_0402_50V7K
PU801
SY8037BDCC_DFN12_3X3
12
1
PVIN
LX
FB
PG
VOUT
VID1
EN
VID0
3
4
5
SA_PGOOD 31
PR804
100K_0402_5%
2
1
+VCCSAP
+3VS
1
+VCCSA_EN
PR802
1K_0402_5%
1
2
PR806
0_0402_5%
34,39
PC804
22U_0805_6.3V6M
1
2
LX
PC803
22U_0805_6.3V6M
1
2
LX
SVIN
PC802
22U_0805_6.3V6M
1
2
PVIN
PC801
22U_0805_6.3V6M
1
2
2
+VCCSAP_FB
10
13
1
2
PC820
22U_0805_6.3V6M
PC819
22U_0805_6.3V6M
PC817
0.1U_0603_25V7K
PC818
2200P_0402_50V7K
PC815
68P_0402_50V8J
PL801
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2
+VCCSA_PHASE
11
PC809
0.1U_0402_10V7K
+VCCSA_PWR_SRC
PR805
1K_0402_5%
1
2
PL803
HCB1608KF-121T30_0603
1
2
GND
+5VALW
PR812
100_0402_5%
2
1
VCCP_PWRGOOD
PR811
0_0402_5%
2
1
H_VCCSA_VID0
H_VCCSA_VID1
PJP801
+VCCSAP
+VCCSA_SENSE
+VCCSA
PAD-OPEN 4x4m
Compal Secret Data
Issued Date
2010/07/20
Deciphered Date
2012/12/31
Title
Size
C
Date:

PWR-VCC_SAP
Document Number
Rev
0.2
SAMSUNG
1
Sheet
41
of
48
2 PR508
NTC_PH203
2P: install
1P: @
@ PR514
0_0402_5%
PAD
VSNA
VSPA
DIFFA
TRBSTA#
FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
NCP6132BMNR2G_QFN60_7X7
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
PWMA
BSTA
HGA
SWA
LGA
BST2
HG2
SW2
LG2
PVCC
PGND
LG1
SW1
HG1
BST1
1
1
2
PR523
1
BST3
BST2
6132P_VCCP
43
LG3
HG2
43
1
PR525 2 BST2_1 1
4.7_0603_5%
43
LG2
43
2
0_0402_5%
PR530
BST1
LG1
43
HG1
43
1
806_0402_1%
DROOP
CSREF
1000P_0402_50V7K
CSP2A
43
+5VS
CSP1
@ PR553
0_0402_5%
CSREF
2
1500P_0402_50V7K
@ 1
PC537
2
330P_0402_50V7K
1
2
PR557
75K_0402_1%
PC525
0.047U_0402_16V7K
CSREF
@PR537
@
PR537
0_0402_5%
SWN3
43
3P: install
2P: @
PR544 2
5.76K_0402_1%
1
2
PR558
165K_0402_1%
3Phase: @
2Phase: install
CSP3
TSENSE
SWN2
43
SWN1
43
PC530
0.047U_0402_16V7K
PR549 2
5.76K_0402_1%
PR550
PC532
1000P_0402_50V7K
PC535
PR539 2
5.76K_0402_1%
43
2
1
SW1
2Phase: @
1Phase: install
@PR531
@
PR531
0_0402_5%
CSREF
PC533
0.047U_0402_16V7K
CSP3
@ PR542
0_0402_5%
CSREF
+5VS
Option for
1 phase GFX
43
PR554 2
160K_0603_1%
SWN1
PR556 2
160K_0603_1%
SWN2
PR559 2
160K_0603_1%
SWN3
2
PC536
1
PC538
1
2
43
Option for
2 phase CPU
@ PR546
0_0402_5%
.1U_0402_16V7K
SW2
PC522
0.22U_0402_10V6K
DRVEN
CSSUM
PR555
1
PR560
43
6132_PWM 43
PR541
806_0402_1%
2
2.2U_0603_10V7K
2
0_0402_5%
PC520
1
BST1_1 1
100K_0402_1%_TSM0B104F4251RZ
+5VS
SW3
3P: 73.2K
2P: 41.2K
PR536 2
73.2K_0402_1%
PC526
1
2
CSCOMP
PR547
PC529
2
1COMP_CPU1
2
1
6.04K_0402_1%
2200P_0402_50V7K
PH504
PUT CLOSE
TO V_GT
HOT SPOT
PC519
2
0.22U_0402_10V6K
PR532
2
PR533
4.7_0603_5%
.1U_0402_16V7K
CSP1
CSP2
CSP3
122P_0402_50V8J
23.7K_0402_1%
1
2
0.033U_0402_16V7K
PR545
PC528
1
2FB_CPU1 1
2
PR548
PC531
49.9_0402_1%
1
2FB_CPU3 1
2
680P_0402_50V7K
10_0402_1%
0.033U_0402_16V7K
PR551
PR552
1
2
1
2
FB_CPU2
43
HG3
CSP2
CSCOMP
SWN2A
PC518
2
0.22U_0402_10V6K
PC527
2 BST3_1 1
4.7_0603_5%
1
2
1K_0402_1%
PC534
43
2P: 36K
1P: 26.1K
PR543
8.06K_0402_1%
2
PR519
5.49K_0402_1%
VSN
PC524
1000P_0402_50V7K
VSP
TRBST#
SWN1A
2P: install
1P: @
6132_PWMA 43
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TRBST#
FB_CPU
COMP_CPU
IMON
1
2 ILIM_CPU
DROOP
21K_0402_1%
1
2
0_0402_5%
VCCSENSE
VCC
VDDBP
VRDYA
EN
SDIO
ALERT#
SCLK
VBOOT
ROSC
VRMP
VRHOT#
VRDY
VSN
VSP
DIFF
PR538
1
2
0_0402_5%
VSSSENSE
2
CSP2A
CSP1A
TSENSEA
PR520
1
2
36K_0402_1%
PR540
8
.1U_0402_16V7K
VGATE
18,31
VR_HOT#
CSP2A
PC514
0.047U_0402_16V7K
PR535
10K_0402_5%
2
31
TSENSEA
5.49K_0402_1%
2
PH502
100K_0402_1%_TSM0B104F4251RZ
PR529
1K_0402_1%
1
PR534
75_0402_1%
@ PR518
0_0402_5%
PC515
2
TSENSE
PR528
95.3K_0402_1%
1
1
2
CPU_B+
1
2
3
4
VR_ON_CPU
5
VR_SVID_DAT1
PR526
VR_SVID_ALRT# 6
7
10K_0402_1%
VR_SVID_CLK
1
2
8
VBOOT
2
9
ROSC_CPU
10
VRMP
11
VR_HOT#
12
VGATE
13
14
15
DIFF_CPU
PC523
47P_0402_50V8J
VR_ON
+3VS
+1.05VS_VCCP
2VR_SVID_DAT1
0_0402_5%
1PR516
2
21.5K_0402_1%
CSCOMPA
DIFFA
TRBSTA#
FBA
COMPA
IMONA
ILIMA
DROOPA
PR527
TRBST#
FB
COMP
IOUT
ILIM
DROOP
CSCOMP
CSSUM
CSREF
CSP3
CSP2
CSP1
TSNS
DRVEN
PWM
6132_VCC
PR521
0_0402_5%
1
2
PC521
0.01U_0402_25V7K
2
1
2
PR522
1
54.9_0402_1%
8 VR_SVID_DAT
8 VR_SVID_ALRT#
8 VR_SVID_CLK
130_0402_1%
PR524
PC501
2.2U_0603_10V7K
1
2
31
PR515
1
PU500
PC516
.1U_0402_16V7K
CSREFA
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
PR501
2_0603_5%
1
2
+5VS
+1.05VS_VCCP
PC511
0.047U_0402_16V7K
PC512
1000P_0402_50V7K
CSREFA 43
CSSUMA
2
1
9 VSS_AXG_SENSE
CSP1A
CSREFA
SWN1A
SWN2A
80.6K_0603_1%
PC513
1000P_0402_50V7K
CSREFA
1000P_0402_50V7K
80.6K_0603_1%
1 PR513
9 VCC_AXG_SENSE
DROOPA
1 PR512
PC510
1
2
2200P_0402_25V7K
COMPA1
5.11K_0402_1%
HF: 1.65K
2P: 1.65K
1P: 1K
1
PR511
2
PR510
1K_0402_1%
1.65K_0402_1%
165K_0402_1%
1
PC517
.1U_0402_16V7K
CSCOMPA
2 10P_0402_50V8J
PR517
2
PC509
PC506
1
2
13.7K_0402_1%
PC508
680P_0402_50V7K
1
2
FBA2
PR507
13.7K_0402_1%
PR509
10_0402_1%
1
2
PC507
0.033U_0402_16V7K
PH503
220K_0402_5%_ERTJ0EV224J
<BOM Structure>
PR505
24K_0402_1%
PR506
1
2
75K_0402_1%
PR504
806_0402_1%
1
2
FBA1
PC504
1
PR503
8.06K_0402_1%
1
2
TRBSTA#
PUT CLOSE
TO GT
Inductor
PC503
.1U_0402_16V7K
1
2
560P_0402_50V7K
PC502
3300P_0402_50V7K
1
2
FBA3
1500P_0402_50V7K
PR502
10_0402_1%
1
2
PC505
1
PUT CLOSE
TO VCORE
HOT SPOT
PH501
220K_0402_5%_ERTJ0EV224J
PUT CLOSE
TO VCORE
Phase 1
Inductor
Compal Secret Data
Issued Date
2009/12/01
2010/12/31
Deciphered Date
5
Title

PWR-CPU_CORE
Size
Document Number
Custom
Date:
Rev
0.2
QCL70
Sheet
1
42
of
48
PC545
0.1U_0402_25V6
2
1
PC546
2200P_0402_25V7K
2
1
2
1
CSREF 42
42
LG2
PQ504
TPCA8057
10_0402_1%
PC547
SWN1
42
B+
PL516
HCB2012KF-121T50_0805
2
1
PR566
V2N_CPU 2
SNUB_CPU2
V1N_CPU 2
3
2
1
3
2
1
PQ502
TPCA8057
2
PR564
4.7_1206_5%
PR565
1SNUB_CPU1
2
LG1
PC544
10U_0805_25V6K
2
1
PQ507
AON7518
SW2
+CPU_CORE
PL512
0.36UH_FDUE1030D-H-R36M=P3_32A_20%
1
4
42
3
2
1
PR563
4.7_1206_5%
42
PC543
10U_0805_25V6K
2
1
5
PQ505
AON7518
5
1
SW1
HG2
3
2
1
3
2
1
3
2
1
42
+CPU_CORE
PL511
0.36UH_FDUE1030D-H-R36M=P3_32A_20%
1
4
42
PC541
2200P_0402_25V7K
2
1
PC542
0.1U_0402_25V6
2
1
PC540
10U_0805_25V6K
2
1
PC539
10U_0805_25V6K
2
1
@
D
CPU_B+
HG1
PQ503
AON7518
42
PQ501
AON7518
CPU_B+
CSREF
10_0402_1%
SWN2
42
680P_0402_50V7K
CPU_B+
680P_0402_50V7K
HG3
PL513
0.36UH_FDUE1030D-H-R36M=P3_32A_20%
1
4
SW3
CPU_B+
@ PC555
100U_25V_M
QC 45W CPU
VID1=0.9V
IccMax=94A
Icc_Dyn=66A
Icc_TDC=56A
R_LL=1.9m ohm
OCP~110A
+CPU_CORE
3
2
1
3
2
1
42
1
1
PC552
2200P_0402_25V7K
2
1
PC551
0.1U_0402_25V6
2
1
PC550
10U_0805_25V6K
2
1
PC549
10U_0805_25V6K
2
1
PC554
100U_25V_M
PQ511
AON7518
42
PQ509
AON7518
PL517
HCB2012KF-121T50_0805
2
1
@ PC553
0.1U_0603_25V7K
QC 45W CPU (HF)

solution: 3+2
MOS: cpu_core -->
Gfx_core -->
DC 35W CPU
VID1=1.05V
IccMax=53A
Icc_Dyn=43A
Icc_TDC=33A
R_LL=1.9m ohm
OCP~65A
QC 45W CPU
solution: 3+2
MOS: cpu_core -->
Gfx_core -->
1(FDMS0308AS)
2(AON7518)
2(AON7518)1(FDMS0308AS)
1(FDMS0308AS)
1(AON7518)
1(AON7518)1(FDMS0308AS)
PR568
4.7_1206_5%
PC548
PQ506
TPCA8057
SNUB_CPU3
LG3
V3N_CPU 2
PR5691
DC 35W CPU
solution: 2+1
MOS: cpu_core -->
Gfx_core -->
CSREF
10_0402_1%
3
2
1
42
PC556
SWN3
42
680P_0402_50V7K
1(FDMS0308AS)
1(AON7518)
1(AON7518)1(FDMS0308AS)
CPU_B+
+5VS
PR580
4.7_1206_5%
3
2
1
PQ508
TPCA8057
2 PR581
2 PR577 1EN_GFX2 3
2K_0402_1%
1VCC_GFX2
2
1
4
PR578
PR579
0_0402_5%
0_0402_5%
CSREFA 42
10_0402_1%
2
PC568
PWM
EN
VCC
DRVH
SW
GND
DRVL
PC561
2200P_0402_25V7K
2
1
PC560
0.1U_0402_25V6
2
1
PQ519
AON7518
+GFX_CORE
HG2A
SW2A
3
2
1
3
2
1
FLAG
PL515
FDUM0640J-H-R36M=P3
1
2
PR582
4.7_1206_5%
NCP5911MNTBG_DFN8_2X2
PC570
2.2U_0603_10V7K
LG2A
4
PQ510
TPCA8057
SWN1A 42
PR584
0_0402_5%
680P_0402_50V7K
BST
PQ517
AON7518
1
2
PC565
2200P_0402_25V7K
2
1
PC564
0.1U_0402_25V6
2
1
PC563
10U_0805_25V6K
2
1
PQ515
AON7518
PC562
10U_0805_25V6K
2
1
6132_PWM
DRVEN
LG1A
NCP5911MNTBG_DFN8_2X2
PC567
2.2U_0603_10V7K
42
PU502
PL514
FDUM0640J-H-R36M=P3
1
2
GND
DRVL
SW1A
CSREFA
PR583
10_0402_1%
SNUB_GFX2
VCC
SW
HG1A
PC566
0.22U_0402_10V6K
EN
BSTA2_1
3
2
1
DRVH
3
2
1
FLAG
PWM
+GFX_CORE
BST
1 PR571
4.7_0603_5%
1SNUB_GFX1
2
1EN_GFX1
DRVEN
2K_0402_1%
2
1VCC_GFX1
2
1
PR575
PR576
0_0402_5%
0_0402_5%
+5VS
BSTA2
PR573
42 6132_PWMA
PQ513
AON7518
2
PU501
3
2
1
BSTA1_1
PC557
PC558
10U_0805_25V6K
2
1
1
2
4.7_0603_5%
0.22U_0402_10V6K
BSTA1
42
2Phase: install
1Phase:: @
PR570
PC559
10U_0805_25V6K
2
1
CPU_B+
B
SWN2A 42
PR585
0_0402_5%
PC569
680P_0402_50V7K
A
QC 45W GT2
VID1=1.23V
IccMax=46A
Icc_Dyn=37A
Icc_TDC=38A
R_LL=3.9m ohm
OCP~55A
DC 35W GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A
Icc_TDC=21.5A
R_LL=3.9m ohm
OCP~40A
Compal Secret Data
Issued Date
2009/12/01
Deciphered Date
2010/12/31
Title
Size
C
Date:

PWR-CPU_CORE
Document Number
Rev
0.2
QCL70
1
Sheet
43
of
48
+CPU_CORE
Below is 458544_CRV_PDDG_0.5 Table 5-8.
+GFX_CORE
PC1105
10U_0805_6.3V6M
PC1104
10U_0805_6.3V6M
PC1103
10U_0805_6.3V6M
PC1102
10U_0805_6.3V6M
PC1101
10U_0805_6.3V6M
+GFX_CORE
1
+CPU_CORE
Socket Bottom
5 x 22 F (0805)
5 x (0805) no-stuff
sites
Socket Top
7 x 22 F (0805)
2 x (0805) no-stuff
sites
1
2
1
1
PC1121
22U_0805_6.3V6M
1
PC1122
22U_0805_6.3V6M
1
PC1123
22U_0805_6.3V6M
1
PC1124
22U_0805_6.3V6M
1
PC1125
22U_0805_6.3V6M
+
PC1126
22U_0805_6.3V6M
1
PC1127
330U_D2_2V_Y
1
PC1128
330U_D2_2V_Y
1
PC1129
330U_D2_2V_Y
1
+
1
+
PC765
PC763
330U_D2_2V_Y
+CPU_CORE
PC762
PC1120
22U_0805_6.3V6M
330U_D2_2V_Y
22U_0805_6.3V6M
1
PC1119
22U_0805_6.3V6M
PC761
22U_0805_6.3V6M
PC760
22U_0805_6.3V6M
PC759
22U_0805_6.3V6M
PC758
22U_0805_6.3V6M
PC757
22U_0805_6.3V6M
PC756
22U_0805_6.3V6M
PC755
22U_0805_6.3V6M
1
PC1118
22U_0805_6.3V6M
PC754
22U_0805_6.3V6M
PC753
22U_0805_6.3V6M
1
PC1117
22U_0805_6.3V6M
+1.05VS_VCCP
1
PC752
22U_0805_6.3V6M
PC1115
22U_0805_6.3V6M
PC1166
1
PC1116
22U_0805_6.3V6M
PC1165
330U_D2_2V_Y
PC1114
22U_0805_6.3V6M
1
PC1164
330U_D2_2V_Y
PC1113
22U_0805_6.3V6M
330U_D2_2V_Y
PC1162
22U_0805_6.3V6M
PC1112
22U_0805_6.3V6M
1
PC1161
22U_0805_6.3V6M
PC1160
22U_0805_6.3V6M
PC1111
22U_0805_6.3V6M
PC1159
22U_0805_6.3V6M
PC751
22U_0805_6.3V6M
PC1158
22U_0805_6.3V6M
+CPU_CORE
PC1157
22U_0805_6.3V6M
PC1156
22U_0805_6.3V6M
PC1110
10U_0805_6.3V6M
PC1155
22U_0805_6.3V6M
PC1109
10U_0805_6.3V6M
PC1154
22U_0805_6.3V6M
PC1108
10U_0805_6.3V6M
PC1153
22U_0805_6.3V6M
PC1107
10U_0805_6.3V6M
PC1152
22U_0805_6.3V6M
PC1106
10U_0805_6.3V6M
PC1151
22U_0805_6.3V6M
1
PC1130
330U_D2_2V_Y
PC1131
330U_D2_2V_Y
Chief River
330uF*9m
8layer for DC CPU
470uF*4.5m
22uF
10uF
16
10
8layer for QC CPU
16
10
6layer for DC CPU
16
10
6layer for QC CPU
16
10
GFX_CORE DC
12
GFX_CORE QC
12
1.05V_VCCP
12
Compal Secret Data
2008/09/15
Issued Date
Deciphered Date
2012/12/31
Title
Size
Date:

PWR - PROCESSOR DECOUPLING
Document Number
Rev
0.2
QCLA4 LA-8861P M/B

Sheet
1
44
of
48
NO DATE
PAGE
MODIFICATION LIST
PURPOSE
-------------------------------------------------------------------------------------------------------------------------------1.
2.
3.
4.
5.
6.
7.
8.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
2011/09/29
P51-PWR_+3VALWP/+5VALWP
P53-PWR_ +1.05VS_VCCP/+16VSP
P54-PWR_+VCCSAP/1.8VSP
P57-PWR +CPU_CORE DECOUPLING
P53-PWR_ +1.05VS_VCCP/+16VSP
P49-PWR_BATTERY CONN / OTP
Change PU330 to RT8205L

Change PU400 to RT8237C
Change PU450 to SY8037B
Change HMOS to MDV1525
Change HMOS to MDV1525
Change PD5,PD6 to SCA00001G00
Change PR589 from 348 to 8.06k
Change PR590 from 3.65k to 806
Change PC574 from 680P to 0.033u
Change PR548 from 1.21k to 8.06k
Change PR550 from 10.7k to 806
Add snubber and boost resistor
Add PR22 30k,PR27 100k, PR32 0 Ohm
Change PC360 to SE000006R80
Add PR17 14k, PR33 0 Ohm
Add PR373 0 Ohm
Change source
Change source
Change source
Change source
Change source
ESD team request
FAE suggestion
FAE suggestion
FAE suggestion
FAE suggestion
FAE suggestion
FAE suggestion
FAE suggestion
FAE suggestion
For 3x3 H-MOS solution
For 120W adapter protect(9012)
Change source
For CPU temperature protect(9012)
For 3/5V always power on(9012)
Issued Date
Compal Secret Data
2010/11/11
Deciphered Date
2011/11/11
Title
Custom
Date:
Power PIR
Rev
0.2
QFKAA
Sheet
45
of
48
HW PIR (Product Improve Record)
QCLA4,5 LA-7201P SCHEMATIC CHANGE LIST

REVISION CHANGE: 0.0 TO 0.1
GERBER-OUT DATE: 2011/12/30
NO
DATE
PAGE MODIFICATION LIST
PURPOSE
--------------------------------------------------------------------------------------------------------------------1
11/24
33
Change P33 ALC280 schematic to ALC259 schematic.
For audio function
2
11/24
34
Change JEXMIC.4 JACK_SENSE to MIC_SENSE.
For audio function
3
11/24
35
Delete UB3,RB26,CB18,RH296
For delete CIR function
4
11/24 6,13,21 Delete QC1,RC4,C261,U17,R147,R103,R360,R392,R390,R1441~1442,R361,R106,RH304
For LVDS only
5
11/24 6,13,17 Delete Q23,C293,R62,R389,R120,R79,R97,L60,R262~265,R299~300,RH275,R1440
For LVDS only
6
11/24
6,13
Delete CPU_EDP_HPD,+LCD_VDD_R,+PANEL_VDD,LVDS_ENVDD,+3VS_LVDSDDC
For LVDS only
7
11/24
13
Delete D15 BOM structure and JLVDS.10 connect to +3VS
For LVDS function
8
11/24
13
Add J17 connector and change JLVDS from 40 to 30 pin connector.
For LVDS function
9
11/24
20
Delete USB20_N13,USB20_P13
For no Glasses free 3D Panel
10
11/24
13
Change RC82 BOM structure from IEDP@ to @.
For LVDS function
11
11/24
5,17
Change RC157,RC158,RH119,RH203 BOM structure from LVDS@ to mount.
For LVDS function
12
11/24
17
Delete CLK_CPU_EDP#,CLK_CPU_EDP
For LVDS only
13
11/24
15
Delete CEC schematic and JHDMI.13 HDMI_CEC net
For no CEC support
14
11/24
15
Delete R570,D55 and change U9.4 HDMI_HPD_R to HDMI_HPD
For HDMI HPD
15
11/25
15
Change L8~11 to SM070001U00
For HDMI signal
16
11/25
15
Delete U9.5 from +5VL to +5VS
For HDMI HPD
17
11/25
33
Change Audio codec schematic
For ALC259-VC2
18
11/25
17,29 Delete CH16,CH18,card reader schematic
For RTS5129
19
11/25
26
Delete FP & B-CAS schematic
For no support FP & B-CAS function
20
11/25
35,37 Delete JFUN,R8,R1466~1467,D90
For no support JFUN
21
11/25
20,27 Delete USB20_N10,USB20_P10,USB20_N12,USB20_P12
For no support TV tuner & 3G
22
11/25
27
Delete RH181 & 3G,B-CAS,JET schematic
For no support TV tuner & 3G
23
11/25
16,27 Delete mSATA schematic
For no support mSATA function
24
11/25
27
Delete RCL3,271@ component and net OSC_IN_R_R,OSC_IN_R
For no support S&M function
25
11/25
6
Change RC3 from 1Kohm to 10Kohm (SD028100280)
For no support eDP function
26
11/25
35
Delete UB1.89 HDPACT,UB1.86 HDPLOCK,UB1.68 HDPINT
For no support G-SENSOR function
27
11/28
35
Change PCH_PWR_EN from UB1.70 to UB1.68 and add UB1.70 EN_DFAN1
For support RPM FAN
28
11/28
5,35
Delete C1~4,R1~2,D1 and UB1.26 FANPWM
For no support PWM FAN
29
11/29
25
Delete S&C schematic
For no support S&C
30
11/29
31,32 Delete USB3.0 Host schematic
For no support external USB3.0 host IC
31
11/30
38
change R409 from 120K_1% to 120K_5%
For change tolerance
32
11/30
33
change RA17 from 0_1% to 0_5%
For change tolerance
33
11/30
13
Delete R260 and short directly
For reduce circuit
34
12/01
16
change DH1 from @ to NOGCLK@
For BOM control
35
12/01
37
Add SW4
For Debug
36
12/01
36
Delete U21,C453,C452
For LID on small board
37
12/02
35
Delete CPSETIN
For delete EC930 schematic
38
12/02
16
Add JRTC,CH9,DH8,DH9,R227
For non-rechargeable RTC schematic
39
12/02
36
Delete JBLG schematic
For non-keyboard led schematic
40
12/05
36
Modify JKB pin define
For meet SS KB Matrix
41
12/05
13
Change location from J17 to JLVDS1
For location naming
42
12/06
35
Delete UB1.85 SM_SENSE#
For no support S&M
43
12/06
25
Modify JUSIO pin define
For small board connect
44
12/06
38
Delete R425 and 0.75VR_EN#
For Power circuit connect
45
12/07
25
Add JODDB
For 15" ODD connector
46
12/07
15
Change U9.5 connect from +5VS to +HDMI_5V_OUT
For prevent leakage issue
47
12/08
29
Change JCRIO pin define
For small board connect
48
12/12
21
Change UH1.K1 and RH180.2 from BT_ON# to PCH_GPIO34
For common GPIO pins on EC side
49
12/12
35
UB1.18 and RB11 connect to BT_ON#
50
12/12 25,35,37 Delete PWR_ON_LED# net
51
12/12
25
Change JUSIO pin define
For LED behavior
52
12/12
16
Delete CH9,DH8,DH9,R277,JRTC
For RTC change to rechargeable
53
12/13
21
Delete Q51 and change PCH_WL_BT_LED to PCH_GPIO69
For change WL_BT_LED# to EC GPIO
54
12/13
35
UB1.21 connect WL_BT_LED#
For change WL_BT_LED# to EC GPIO
55
12/13
37
Change Q156B.3 from WL_BT_LED# to WIMAX_LED# and connect to R802
For WLAN LED behavior
56
12/13
35
Delete UB1.127 (USB_OC#0) and UB1.17 (USB_OC#1)
For no support USB S&C
57
12/13 20,29
Add TPM schematic
For TPM function
58
12/13
27
Delete Q36
For change BT_ON# to EC GPIO
59
12/13 14,30,37 Change JCRT,JUSBA,JUSBB,JTP symbol
For connector list update
60
12/13
25,29
Change JUSIO,JCRIO symbol
For connector list update
61
12/14
27
Change UCL1 to SLG3NB244VTR
For green clock
62
12/14
29
Change UT1.5 and RT7.1 net from +3VALW to +3VALW_PCH
For ErP Lot6 function
63
12/14
21
Add RH181 and connect ISDBT_DET, delete RH297
For no support TV tuner
64
12/14
21
Change RH194 from 100K 5% to 10K 5%
For update resistor value
65
12/14
21
Change RH315.2 connect +3VS and BOM structure to mount
For update resistor value
66
12/14
37
Change ZZZ P/N to DA60000T600
For update PCB P/N
67
12/14
37
Move D89 to TP small board
For Move to TP small board
68
12/15
16~24
Change UH1 P/N to SA00005FH30
For update UH1 P/N
69
12/15
30
Change CR40 P/N to SF000002Y00
For layout limitation
70
12/15
33
Delete RA53
For common design
71
12/15
25
Delete C381~4
For placement update
72
12/15
30
Delete RR23~24,CR26,RR36~37,CR29
For connect GND directly
73
12/15
9
Delete CC67
For not reserve
74
12/19
16
Delete T67~T69
For not reserve
75
12/19
29
Change YT1 form SJ132P7KW10 to SJ100004Z00 (small package)
For change to small size
76
12/19
29
Change CT2, CT3, CT4, CT5 from SE095104K80 to SE102104K00
For BOM reduce
77
12/19
29
Change JCRIO to SP010015H00
For follow connector list
78
12/20
13
Delete JLVDS.28 (+LCD_INV)
For prevent issue
79
12/20
37
Modify H1~H17
For Update screw hole
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
Title
Custom
HW-PIR
Rev
0.2
QCLA4,5 LA-8862P M/B
Date:
Sheet
1
46
of
48
HW PIR (Product Improve Record)

NO
DATE
PURPOSE
--------------------------------------------------------------------------------------------------------------------80
12/20
35
Change UB1.68 (PCH_PWR_EN) to UB1.107
For EC common
81
12/20
35
Change UB1.73 (UMA_ENBKL) to UB1.76
For Update screw hole
82
12/20
21
Change RH198 from 100k to 10k
For follow Intel checklist
83
12/20
05
Change UC1.5 from +3VALW to +3VALW_PCH
For design change
84
12/20
16
Modify SATA_LED# to10k (RH29) +5VS pull high & 20k (RH35) pull low
For design change
85
12/20
17
Change CLKREQ_CR#,CLKREQ_USBA30#,CLKREQ_USB30# to PCH_GPIO25, 26, 44
For design change
86
12/20
20,23
Change CH104 to 100p and CH71 to 0402
For design change
87
12/20
27,35
Change BT_ON# netname to BT_ON and UA4 to UM4
For design change
88
12/20
27
Modify LED_WIMAX# to 100k +5VS pull high & 200k pull low
For design change
89
12/20
35
Delete CB13
For design change
90
12/20
33
Change CA3,CA46,CA36 to 0805_6.3V6M
For cost down
91
12/20
38
Delete R5534 and short directly
For design change
92
12/20
37
Changr R819 from +5VS to +3VS
For design change
93
12/20
5,25
Changr C13,C17,C356,C355,C354 to 0805_6.3V6M and unmount C354
For cost down
94
12/20
35
Delete UB2,CB17,RB25 and connect UB1.127 to PM_SLP_S4#, UB1.14 to PM_SLP_S5#
For cost down
95
12/20
35
Delete RB24,RB28,RB4,RB5,RB7,R37 and change UB1.119,117,75,64,27,16 to NC
For cost down
96
12/21
28
Change symbol from SP021105131
For apply symbol
97
12/21
35
Change TP_CLK,TP_DATA pull high to +5VS
For TP spec
98
12/21
13
Unmount D84
For reserve
99
12/22 15,25,30 Swap L9,L11,LR1,LR2,L53,L54 signal
For swap signal
100 12/22
30
Swap U3TXDP1_R_L and U3TXDN1_R_L, swap U3RXDP1_R_L and U3RXDN1_R_L
For swap signal
101 12/23
14,15
Change F1,F2 to SP040003A00
For component common
102 12/24
29
Change RR66~67 to mount, LR9 to unmount
For choke reserved
103 12/24
37
Cancel H6, H17 (FAN stand-off) and change H4 to H_3P3 (VGA)
For ME drawing update
104 12/24
28
Change PJ29 from JUMP_43X118 to JUMP_43X39
For layout concern
105 12/24
38
Delete R105, add PJ30 to contact +3VS & +3V_WLAN
For no support AOAC function
106 12/26
36
Update JDB symbol and modify pin define
For connector list update and pin define for customer's request
107 12/26
13,17
Delete RH282, change RH116 to mount, JLVDS1.2 contact LVDS_SEL
For update pin define and BOM reduce
108 12/26
13
JLVDS1.1&11&12 contact GND
For LVDS cable smooth route and BOM reduce
109 12/26
33
Move RA32 & RA33 to Audio/B
For AMIC function
110 12/26
29
JCRIO.11 contact SENSE_A, JCRIO.12 contact INT_MIC
For AMIC function
111 12/26
36
Swap JKB connector pin define
For latest keyboard spec
112 12/26
29
Swap LR9 pin define
For layout concern
113 12/27
29
Swap JCRIO pin define
For layout concern
114 12/27
37
Update JTP pin define
For PIN define rule
115 12/27
29
Update TPM schematic
For co-lay SLB9635 and SLB9655
116 12/27
28
Add CL35 and un-mount
For EMI request
117 12/27
21
Change CIR_EN# to PCH_GPIO39 and ISDBT_DET to PCH_GPIO48
For schematic update
118 12/27
21
Change HDD2_DET# to PCH_GPIO57 and LNB_EN to PCH_GPIO70
119 12/27
21
Change 3D_DET# to PCH_GPIO71
120 12/27 20,30,35 Add S&C schematic
For reserve S&C schematic
121 12/27
33
Add Analog MIC schematic
For Analog MIC
122 12/27
28
Change RL8.2 from LAN_X1 to LAN_X2
For vendor recommendation
123 12/27 11,21
Add D54,RH210,RH100,QC9 and delete RC117,RC118
For Ivy/Sandy bridge M1/M3 co-lay solution
124 12/27
11
Change QC7,QC8 to always mount
For Ivy/Sandy bridge M1/M3 co-lay solution
125 12/27
38
Change R158 from 100Kohm to 220Kohm
For intel S3 power reduce sequence between +1.5VS_CPU and +0.75VS
126 12/27
33
Add CA64 0402 cap @ on SENSE_A
For audio sense A pin
127 12/28
30
Change R569 to PJ31
For S&C function
128 12/28
30
Add RH4,CH80
For prevent abnormal turn on
129 12/28
30
Add CH99,CH102 and delete CH97
For prevent abnormal turn on and do soft start
130 12/29
38
Change R5545 from 100k to 10k
For prevent abnormal turn on and do soft start
131 01/03
28
Change UL3,UL4 from SP050006N00 to SP050005Z00
For update transformer P/N
132 01/03
29
change UT1 P/N from SA00000GG40 to SA00000GG60.
For TPM firmware update
133 01/03
27
change R1456,R1457,C907,C908,Q210 to @
For TPM firmware update
NO
DATE
PURPOSE
--------------------------------------------------------------------------------------------------------------------1
02/01
28
Add PJ32 and connect +3VALW_PCH & +3V_LAN
For power saving
2
02/02
29
Change JCRIO.2 to connect MIC_SENSE and JCRIO.1 to connect NBA_PLUG
For change pin define
3
02/02
33
Delete sense_A off page,CA64 and add RA32,RA33
For sense A circuit
4
02/02
37
Change JTP from SP010015H00 to SP01001BF10
For connector list
5
02/02
33
Add JMIC connector SP02000RO00
For connector list
6
02/02
27
Change JWLAN from SP07000JP00 to SP07000TB00
For connector list
7
02/02
38
Change Q44A to Q6B and delete Q44
For component reduce
8
02/02
16
Delete T67~69
For common design
9
02/03
35
UB1.38 connect AOAC_WLAN_PWR_EN# and UB1.91 connect WLAN_RST#
For WLAN Power on/off and WLAN
10
02/03
27
Change R1456,R1457,C907,C908,Q210 to mount
11
02/03
27
change R1457.1 to connect AOAC_WLAN_PWR_EN#
12
02/03
27
Change JWLAN.22 to connect WLAN_RST#_R
13
02/03
27
Change C260,CM7,CM8,CM9,C254 to connect +1.5VS_WLAN
14
02/03
27
ADD PJ33 (PJ33 don't short),UM5,RM19,RM21 and +1.5VS_WLAN (power)
15
02/03
27
Change UM4.1 to connect AOAC_WLAN_PWR_EN#
16
02/06
28
Change CL63 from SE120102K80 to SE120102K90
For sourcer suggestion
17
02/06
37
Change H18,H19 to H_3P0N
For ME drawing update
18
02/08
21
Change UH1.T7 from HDMI_HPD to CHP3_SERDBG
For Eureka Serial POST GPIO
19
02/08
21
Change RH292 from 10Kohm to 1Kohm and delete T66
20
02/08
21
Change UH1.T7 from HDMI_HPD to CHP3_SERDBG and connect to JCRT.4
2010/09/03
Issued Date
Deciphered Date
reset
reset
reset
reset
reset
reset
reset
Compal Secret Data
2012/12/31
Title
Custom
HW-PIR
Rev
0.2
Date:
Sheet
1
47
of
48

NO
DATE
PURPOSE
--------------------------------------------------------------------------------------------------------------------21
02/08
27
Add TL1 test point
For LAN FAE suggestion
22
02/09
15
Add D94~D96 on HDMI signal
For ESD request
23
02/09
27
Add D99,D100 on LAN signal
For ESD request
24
02/09
14
DEL D3~D5 and add D97,D98 on CRT signal
For ESD request
25
02/09
7,31
Add RC74 and net DRAMRST_CNTRL_EC connect RC74.1 & UB1.89
For DS3 function reserve
26
02/09
25
Add R79~82
For reduce SATA signals reflection
27
02/14
11
Change CD7 from SF000002O00 (H=5.9) to SF000002Z00 (H=4.4)
For thermal issue
Compal Secret Data
2010/09/03
Issued Date
Deciphered Date
2012/12/31
Title
Custom
HW-PIR
Rev
0.2
Date:
Sheet
1
48
of
48

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A

LA-8862P REV 0.2 Schematic

Compal Electronics, Inc.

Compal Secret Data

Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2

USB20 port 2,3

USB20 port 0,1

1.5V DDRIII 1066/1333/1600 MT/s

SATA Gen3 port 1

SATA Gen3 port 0

DC/DC Interface CKT.

Power Circuit DC/DC

Power On/Off CKT.

Compal Electronics, Inc.

Compal Secret Data

Thursday, February 16, 2012

DESIGN CURRENT 0.1A

DESIGN CURRENT 11A

DESIGN CURRENT 1.8A

DESIGN CURRENT 6.5A

DESIGN CURRENT 0.1A

DESIGN CURRENT 0.4A

DESIGN CURRENT 0.3A

DESIGN CURRENT 1.6A

Ipeak=6A, Imax=4.2A, Iocp min=8A DESIGN CURRENT 13.5A

DESIGN CURRENT 1.5A

DESIGN CURRENT 0.3A

DESIGN CURRENT 7.5A

DESIGN CURRENT 0.1A

Ipeak=6A, Imax=4.A, Iocp min=8

Imax=0.3A, Iocp min=0.8A

Ipeak=5A, Imax=3.5A, Iocp min=6.2A

DESIGN CURRENT 94A

DESIGN CURRENT 50A

DESIGN CURRENT 15A

Ipeak=14A, Imax=9.8A, Iocp min=16.92A

Compal Electronics, Inc.

Compal Secret Data

Thursday, February 16, 2012

BTO Option Table

Camera & Mic

Camera & Mic

S5 S4/ Battery only

S5 S4/AC & Battery

Sleep & Charge

description SPI ROM

Sleep & Charge

MINI PCI-E SLOT

PCH SM Bus Address

SLP_S3# SLP_S4# SLP_S5#

Compal Electronics, Inc.

Compal Secret Data

Thursday, February 16, 2012

Stuff RC157 and RC158 if do not support eDP

Please place near JCPU

DDR3 Compensation Signals

by ESD requestion and place near CPU

Layout request for test point

JTAG & BPM

FAN Control Circuit

Compal Electronics, Inc.

Compal Secret Data