8051

MEMORY & I/O ADDRESSING

Memory Addressing
PROGRAM MEMORY -
ROM
• ROM ( READ ONLYMEMORY )
• 8051 can address 4K bytes
on chip memory – map
range 0000 TO 0FFFh
• IT can address 64 KB
external memory
 map range – 0000 TO
FFFFh
• Memory map of internal and
external program overlaps
• The internal and external
ROM distinguished by
PSEN’ signal
ROM - program
DATA MEMORY - RAM
• EXTERNAL RAM
• 8051 supports 64KB external
data memory- range – 0000
to FFFFh
• Accessed by DPTR
• 8051 generates RD’, WR’
during external access .
• CS’ can be derived from
address lines
ONCHIP (INTERNAL) RAM
RAM
INTERNAL RAM
 Registers
1F

Bank 3
Four Register Bank
18 Each bank has R0-R
17
Selectable by psw.2
Bank 2

10
0F

Bank 1

08
07 R7
06 R6
05 R5
04
03
R4
R3
Bank 0
02 R2
01 R1
00 R0
 Bit Addressable Memory
2F 7F 78
2E
20h – 2Fh (16 locations X 8-bits
= 128 bits)
2D
2C
Bit addressing:
2B
mov C, 1Ah
2A
or
29 mov C, 23h.2
28

27
26
25
24
23 1A
22 10
21 0F 08
20 07 06 05 04 03 02 01 00
 Special Function Registers

qDATA registers
q
qCONTROL registers
vTimers
vSerial ports
vInterrupt system
Addresses 80h – FFh
vAnalog to Digital converter
vDigital to Analog converter
Direct Addressing
vEtc.
used to access SPRs
I/O ADDRESSING
 I/O INTERFACING

• External i/o devices are interfaced as

memory mapped i/o devices
• Devices treated as external
memory locations and consume
external memory address
• The address of external program and
data memory may overlap