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Basic Gates

module gates(or1,and1,xor1,not1,not2,nand1,nor1,xnor1,x,y);
input x,y;
output or1,and1,xor1,not1,not2,nand1,nor1,xnor1;
or lor (or1,x,y);
and land (and1,x,y);
xor lxor (xor1,x,y);
not lnot (not1,x,y);
not lnnot (not2,x,y);
nand lnand (nand1,x,y);
nor lnor (nor1,x,y);
xnor lxnor (xnor1,x,y);
endmodule

Not Gate
`timescale 1ns / 1ps
module NOTgate1(A, F);
input A;
output F;
reg F;
always @ (A)
begin
F <= ~A;
end
endmodule

NOR Gate
`timescale 1ns / 1ps
module NOR2gate(A, B, F);
input A;
input B;
output F;
reg F;
always @ (A or B)
begin
F <= ~(A | B);
end
endmodule

NAND Gate
`timescale 1ns / 1ps
module NAND2gate(A, B, F);
input A;
input B;
output F;
reg F;
always @ (A or B)
begin
F <= ~(A & B);
end
endmodule

OR GATE
`timescale 1ns / 1ps
module OR2gate(A, B, F);
input A;
input B;
output F;
reg F;
always @ (A or B)
begin
F <= A | B;
end
endmodule

AND Gate
`timescale 1ns / 1ps
module AND2gate(A, B, F);
input A;
input B;
output F;
reg F;
always @ (A or B)
begin
F <= A & B;
end
endmodule

XOR Gate
`timescale 1ns / 1ps
module XOR2gate(A, B, F);
input A;
input B;
output F;
reg F;
always @ (A or B)
begin
F <= A ^ B;
end
endmodule

XNOR Gate
`timescale 1ns / 1ps
module XNOR2gate(A, B, F);
input A;
input B;
output F;
reg F;
always @ (A or B)
begin
F <= A ~^ B;
end
endmodule

Multiplier
`timescale 1ns / 1ps
module Multiplier(A, B, Result);
input [3:0] A;
input [3:0] B;
output [7:0] Result;
reg [7:0] Result;
always @ (A or B)
begin
Result <= A * B;
end
endmodule

D Flip Flop
module dff_sync_reset (data,clk,reset,q,qb);
//-----------Input Ports---------------

input data, clk, reset ;


//-----------Output Ports--------------output q,qb;
//------------Internal Variables-------reg q,qb;
//-------------Code Starts Here--------always @ ( posedge clk )
if (~reset) begin
q <= 1'b0;
qb <= 1'b0;
end
else
begin
q <= data;
qb<= !data;
end
endmodule //End Of Module dff_sync_reset

4 Bit Counter
module up_counter (
out , // Output of the counter
enable , // enable for counter
clk , // clock Input
reset
// reset Input
);
//----------Output Ports-------------output [3:0] out;
//------------Input Ports-------------input enable, clk, reset;
//------------Internal Variables-------reg [3:0] out;
//-------------Code Starts Here------always @(posedge clk)
if (reset) begin
out <= 3'b0 ;
end else if (enable) begin
out <= out + 1;
end
endmodule

4 Bit Up Down counter


module up_down_counter (data,
out
, // Output of the counter

up_down , // up_down control for counter


clk
, // clock input
reset
// reset input
);
//----------Output Ports-------------output [3:0] out;
//------------Input Ports-------------input [3:0] data;
input up_down, clk, reset;
//------------Internal Variables-------reg [3:0] out;
//-------------Code Starts Here------always @(posedge clk)
if (reset) begin // active high reset
out <= 7'b0 ;
end else if (up_down) begin
out <= out + 1;
end else begin
out <= out - 1;
end
endmodule

1 Bit Full Adder


module full_adder_gates(x,y,z,sum,carry);
input x,y,z;
output sum,carry;
wire and1,and2,and3;
and U_and1 (and1,x,y),
U_and2 (and2,x,z),
U_and3 (and3,y,z);
or U_or (carry,and1,and2,and3);
xor U_sum (sum,x,y,z);
endmodule

16 Bit Binary Adder


module binary_adder_tree(A, B, C, D, E, CLK, OUT);
parameter WIDTH = 16;
input [WIDTH-1:0] A, B, C, D, E;
input
output [WIDTH-1:0] OUT;
wire [WIDTH-1:0]

CLK;

sum1, sum2, sum3, sum4;

reg [WIDTH-1:0] sumreg1, sumreg2, sumreg3, sumreg4;


// Registers
always @ (posedge CLK)
begin
sumreg1 <= sum1;
sumreg2 <= sum2;
sumreg3 <= sum3;
sumreg4 <= sum4;
end
// 2-bit additions
assign
assign
assign
assign
assign
endmodule

sum1 = A + B;
sum2 = C + D;
sum3 = sumreg1 + sumreg2;
sum4 = sumreg3 + E;
OUT = sumreg4;

2x4 Decoder
//`timescale 1ns / 1ps
module Decoder(A, B, D);
input A, B;
output [3:0] D;
reg [3:0] D;
always @ (A or B)
begin
if( A == 0 && B == 0 )
D <= 4'b0001;
else if ( A == 0 && B == 1 )
D <= 4'b0010;
else if ( A == 1 && B == 0 )
D <= 4'b0100;
else
D <= 4'b1000;
end
endmodule

Multiplexer 8*1
module mux(out2,in1, in2);
input [7:0] in1;

input [2:0] in2;


output out2;
reg out2;
always@(in1 or in2)
case (in2)
3'b000: out2 <=in1[0];
3'b001: out2 <=in1[1];
3'b010: out2 <=in1[2];
3'b011: out2 <=in1[3];
3'b100: out2 <=in1[4];
3'b101: out2 <=in1[5];
3'b110: out2 <=in1[6];
3'b111: out2 <=in1[7];
endcase
endmodule

Decoder 3*8
module decoder_always(a, y);
input [2:0] a;
output [7:0] y;
reg [7:0] y;
// a 3:8 decoder
always @(a)
case (a)
3'b000: y <= 8'b00000001;
3'b001: y <= 8'b00000010;
3'b010: y <= 8'b00000100;
3'b011: y <= 8'b00001000;
3'b100: y <= 8'b00010000;
3'b101: y <= 8'b00100000;
3'b110: y <= 8'b01000000;
3'b111: y <= 8'b10000000;
default :$display ("no");
endcase
endmodule

Encoder 4x2
module encoder_4to2_gates (i0,i1,i2,i3,y);
input i0,i1,i2,i3;
output [1:0] y;
or o1 (y[0],i1,i3);
or o2 (y[1],i2,i3);
endmodule

Encoder Using Case 16 to 4


module encoder_using_case(
binary_out , // 4 bit binary Output
encoder_in , // 16-bit Input
enable
// Enable for the encoder
);
output [3:0] binary_out ;
input enable ;
input [15:0] encoder_in ;
reg [3:0] binary_out ;
always @ (enable or encoder_in)
begin
binary_out = 0;
if (enable) begin
case (encoder_in)
16'h0002 : binary_out = 1;
16'h0004 : binary_out = 2;
16'h0008 : binary_out = 3;
16'h0010 : binary_out = 4;
16'h0020 : binary_out = 5;
16'h0040 : binary_out = 6;
16'h0080 : binary_out = 7;
16'h0100 : binary_out = 8;
16'h0200 : binary_out = 9;
16'h0400 : binary_out = 10;
16'h0800 : binary_out = 11;
16'h1000 : binary_out = 12;
16'h2000 : binary_out = 13;
16'h4000 : binary_out = 14;
16'h8000 : binary_out = 15;
endcase
end
end
endmodule

Gray Counter
module gray_counter (
out , // counter out
enable , // enable for counter
clk , // clock
rst
// active hight reset
);
//------------Input Ports-------------input clk, rst, enable;

//----------Output Ports---------------output [ 7:0] out;


//------------Internal Variables-------wire [7:0] out;
reg [7:0] count;
//-------------Code Starts Here--------always @ (posedge clk)
if (rst)
count <= 0;
else if (enable)
count <= count + 1;
assign out = { count[7], (count[7] ^ count[6]),(count[6] ^
count[5]),(count[5] ^ count[4]), (count[4] ^
count[3]),(count[3] ^ count[2]), (count[2] ^
count[1]),(count[1] ^ count[0]) };
endmodule

ROM using FILE


module rom_using_file (
address , // Address input
data , // Data output
read_en , // Read Enable
ce
// Chip Enable
);
input [7:0] address;
output [7:0] data;
input read_en;
input ce;
reg [7:0] mem [0:255] ;
assign data = (ce && read_en) ? mem[address] : 8'b0;
initial begin
$readmemb("memory.list", mem); // memory_list is memory file
end
endmodule

ROM using CASE


module rom_using_case (
address , // Address input
data , // Data output
read_en , // Read Enable
ce
// Chip Enable
);
input [3:0] address;
output [7:0] data;

input read_en;
input ce;
reg [7:0] data ;
always @ (ce or read_en or address)
begin
case (address)
0 : data = 10;
1 : data = 55;
2 : data = 244;
3 : data = 0;
4 : data = 1;
5 : data = 8'hff;
6 : data = 8'h11;
7 : data = 8'h1;
8 : data = 8'h10;
9 : data = 8'h0;
10 : data = 8'h10;
11 : data = 8'h15;
12 : data = 8'h60;
13 : data = 8'h90;
14 : data = 8'h70;
15 : data = 8'h90;
endcase
end
endmodule

Traffic Light Controller


module traffic_verilog(seg_1,seg_2,R1,R2,R3,G1,G2,G3,Y1,Y2,Y3,PR,PG,clk,rst);
output reg R1,R2,R3,G1,G2,G3,Y1,Y2,Y3,PR,PG;
output reg [6:0]seg_1,seg_2;
input clk,rst;
integer timer_count1 = 0,timer_count2 = 0;
reg clk_msec,clk_sec;
reg [7:0]count;
reg [1:0]state = 2'b0;
always@(posedge clk)
begin
if(timer_count1==3999)
begin
timer_count1=0;
clk_msec=1'b1;
end
else

begin
timer_count1=timer_count1+1;
clk_msec=1'b0;
end
end
always@(posedge clk_msec)
begin
if(timer_count2==999)
begin
timer_count2=0;
clk_sec=1'b1;
end
else
begin
timer_count2=timer_count2+1;
clk_sec=1'b0;
end
end
always@(posedge clk_sec)
begin
if(~rst)
begin
R1 = 1'b1; G1 = 1'b0; Y1 = 1'b0;
R2 = 1'b1; G2 = 1'b0; Y2 = 1'b0;
R3 = 1'b1; G3 = 1'b0; Y3 = 1'b0;
state=2'b00;
end
else
begin
case(state)
2'b00://SIGNAL AT SIGNAL LIGHTS ONE
begin
if(count==8'b00100101)
begin
R1 = 1'b0;
G1 = 1'b1;
Y1 = 1'b0;
end
if(count==8'b00101001)
begin
G1 = 1'b1;

Y1 = 1'b0;
state=2'b01;
end
else
state=2'b00;
end
2'b01://SIGNAL AT SIGNAL LIGHTS TWO
begin
if(count==8'b00100101)
begin
Y1 = 1'b1;
G1 = 1'b0;
R2 = 1'b0;
Y2 = 1'b1;
G2 = 1'b0;
end
if(count==8'b00101001)
begin
R1 = 1'b1;
Y1 = 1'b0;
Y2 = 1'b0;
G2 = 1'b1;
state = 2'b10;
end
else
state=2'b01;
end

2'b10://SIGNAL AT SIGNAL LIGHTS THREE


begin
if(count==8'b00100101)
begin
Y2 = 1'b1;
G2 = 1'b0;
R3 = 1'b0;
Y3 = 1'b1;
G3 = 1'b0;
end
if(count==8'b00101001)
begin
R2 = 1'b1;
Y2 = 1'b0;
Y3 = 1'b0;
G3 = 1'b1;

state = 2'b11;
end
else
state=2'b10;
end
2'b11://ALL SIGNAL HIGH TO ALLOW PEDESTRIALS TO CROSS
begin
if(count==8'b00100101)
begin
Y3 = 1'b1;
G3 = 1'b0;
end
if(count==8'b00101001)
begin
R3 = 1'b1;
Y3 = 1'b0;
state = 2'b00;
end
else
state=2'b11;
end
endcase
end
end
always@(count,state)
begin
if((state==2'b00)&&(count==8'b00101001))
begin
PR = 1'b1;
PG = 1'b0;
end
else
begin
PR = 1'b0;
PG = 1'b1;
end
end

always@(posedge clk_sec)
begin
if(rst==1'b0)
count=8'b00000000;
else if(clk_sec)
begin

if(count[3:0]==4'b1001)
begin
count[3:0]=4'b0000;
if(count[7:4]==4'b0010)
count[7:4]=4'b0000;
else
count[7:4]=count[7:4]+1;
end
else
count[3:0]=count[3:0]+1;
end
end
always@(count)
begin
case(count[3:0])
4'b0000:seg_1 = 8'b1111110; //0
4'b0001:seg_1 = 8'b0110000; //1
4'b0010:seg_1 = 8'b1101101; //2
4'b0011:seg_1 = 8'b1111001; //3
4'b0100:seg_1 = 8'b0110011; //4
4'b0101:seg_1 = 8'b1011011; //5
4'b0110:seg_1 = 8'b1011111; //6
4'b0111:seg_1 = 8'b1110000; //7
4'b1000:seg_1 = 8'b1111111; //8
4'b1001:seg_1 = 8'b1111011; //9
default:seg_1 = 8'b0000000; //off
endcase
case(count[7:4])
4'b0000:seg_2 = 8'b1111110; //0
4'b0001:seg_2 = 8'b0110000; //1
4'b0010:seg_2 = 8'b1101101; //2
4'b0011:seg_2 = 8'b1111001; //3
4'b0100:seg_2 = 8'b0110011; //4
4'b0101:seg_2 = 8'b1011011; //5
4'b0110:seg_2 = 8'b1011111; //6
4'b0111:seg_2 = 8'b1110000; //7
4'b1000:seg_2 = 8'b1111111; //8
4'b1001:seg_2 = 8'b1111011; //9
default:seg_2 = 8'b0000000; //off
endcase
end
endmodule

Using FSM
module tlc_fsm(clock,reset,cars,short,long,
highway_light,farm_light,start_timer);
input clock, reset, cars, short, long;
output [1:0] highway_light, farm_light;
output start_timer;
reg [1:0] highway_light, farm_light;
reg start_timer;
reg [1:0] current_state, next_state;
// light encoding: 11 = green, 00 = red, 10 = yellow
'define GREEN '2b11
'define RED '2b00
'define YELLOW '2b10
// state encoding: 00 = hwy-green, 01 = hwy-yellow,
// 10 = farm-green, 11 = farm-yellow
'define HG '2b00
'define HY '2b01
'define FG '2b10
'define FY '2b11
// combinational portion
always @(ctrl_state or short or long or cars) begin
case (ctrl_state)
when HG: begin // state hwy-green
// set lights
highway_light = GREEN;
farm_light = RED;
// decide what to do next
if (cars & long) then
begin ctrl_next = HY; start_timer = 1; end
else begin
ctrl_next = HG; start_timer = 0; end
end
when HY: begin // state highway-yellow
// set lights
highway_light = YELLOW;
farm_light = RED;
// decide what to do next
if (short) then begin ctrl_next = FG; start_timer = 1; end
else begin ctrl_next = HY; start_timer = 0; end
end
when FG: // state farm-green
// set lights

highway_light = RED;
farm_light = green;
// decide what to do next
if (~cars | long) then
begin ctrl_next = FY; start_timer = 1; end
else begin ctrl_next = FG; start_timer = 0; end
end
when FY: // state farm-yellow
// set lights
highway_light = RED;
farm_light = YELLOW;
// decide what to do next
if (short) then begin ctrl_next = HG; start_timer = 1; end
else begin
ctrl_next = FY; start_timer = 0; end
end
endcase
end
// sequential portion
always @(posedge clock or negedge reset) begin
if (~reset)
ctrl_state <= 0;
else
ctrl_state <= ctrl_next;
end
endmodule

Real Time Clock


module
real_time_clk_verilog(clk,clear,hour1,hour2,minute1,minute2,second1,second2,hour_A2,
min_A1,sec_A0,load,data_in);
input clk,clear;
output reg [6:0]hour1,hour2,minute1,minute2,second1,second2;
input load;
input hour_A2,min_A1,sec_A0;
input [7:0]data_in;
reg clk_sec,clk_msec;
reg [7:0]sec,min,hr;
integer timer_count1=0,timer_count2=0;
always@(posedge clk)
begin
if(timer_count1==3999)
begin
timer_count1=0;

clk_msec=1'b1;
end
else
begin
timer_count1=timer_count1+1;
clk_msec=1'b0;
end
end
always@(posedge clk_msec)
begin
if(timer_count2==999)
begin
timer_count2=0;
clk_sec=1'b1;
end
else
begin
timer_count2=timer_count2+1;
clk_sec=1'b0;
end
end
always@(negedge clk_sec)
begin
if(~clear)
begin
sec=0;
min=0;
hr=0;
end
else
if(~load)
begin
if(hour_A2)
begin
if(hr[7:4] == 4'b0010)
begin
if(hr[3:0] < 4'b0100)
hr = data_in;
end
else if(hr[7:4] < 4'b0010)
hr = data_in;
else
hr = 8'b0;
end

if(min_A1)
begin
if(min[7:4] < 4'b0110)
min = data_in;
else
min = 8'b0;
end
if(sec_A0)
begin
if (sec[7:4] < 4'b0110)
sec = data_in;
else
sec = 8'b0;
end
end
else
begin
if(sec[3:0]==4'b1001)
begin
sec[3:0]=4'b0;
if(sec[7:4]==4'b0101)
begin
sec[7:4]=4'b0;
if(min[3:0]==4'b1001)
begin
min[3:0]=4'b0;
if(min[7:4]==4'b0101)
begin
min[7:4]=4'b0;
if(hr==8'b00100100)
hr=0;
else if(hr[3:0]==4'b1001)
begin
hr[3:0]=4'b0;
hr[7:4]=hr[7:4]+1;
end
else
hr[3:0]=hr[3:0]+1; //hours count completed
end
else

min[7:4]=min[7:4]+1;
end
else
min[3:0]=min[3:0]+1; // minutes count
completed
end
else
sec[7:4]=sec[7:4]+1;
end
else
sec[3:0]=sec[3:0]+1; //seconds count completed
end
end
always@(sec)
begin
case (sec[3:0])
4'b0000: second1=7'b1111110;
4'b0001: second1=7'b0110000;
4'b0010: second1=7'b1101101;
4'b0011: second1=7'b1111001;
4'b0100: second1=7'b0110011;
4'b0101: second1=7'b1011011;
4'b0110: second1=7'b1011111;
4'b0111: second1=7'b1110000;
4'b1000: second1=7'b1111111;
4'b1001: second1=7'b1111011;
default: second1=7'b0;
endcase
end
always@(sec)
begin
case(sec[7:4])
4'b0000: second2=7'b1111110;
4'b0001: second2=7'b0110000;
4'b0010: second2=7'b1101101;
4'b0011: second2=7'b1111001;
4'b0100: second2=7'b0110011;
4'b0101: second2=7'b1011011;
4'b0110: second2=7'b1011111;
4'b0111: second2=7'b1110000;
4'b1000: second2=7'b1111111;
4'b1001: second2=7'b1111011;
default: second2=7'b0;

endcase
end
always@(min)
begin
case(min[3:0])
4'b0000: minute1=7'b1111110;
4'b0001: minute1=7'b0110000;
4'b0010: minute1=7'b1101101;
4'b0011: minute1=7'b1111001;
4'b0100: minute1=7'b0110011;
4'b0101: minute1=7'b1011011;
4'b0110: minute1=7'b1011111;
4'b0111: minute1=7'b1110000;
4'b1000: minute1=7'b1111111;
4'b1001: minute1=7'b1111011;
default: minute1=7'b0;
endcase
end
always@(min)
begin
case(min[7:4])
4'b0000: minute2=7'b1111110;
4'b0001: minute2=7'b0110000;
4'b0010: minute2=7'b1101101;
4'b0011: minute2=7'b1111001;
4'b0100: minute2=7'b0110011;
4'b0101: minute2=7'b1011011;
4'b0110: minute2=7'b1011111;
4'b0111: minute2=7'b1110000;
4'b1000: minute2=7'b1111111;
4'b1001: minute2=7'b1111011;
default: minute2=7'b0;
endcase
end
always@(hr)
begin
case(hr[3:0])
4'b0000: hour1=7'b1111110;
4'b0001: hour1=7'b0110000;
4'b0010: hour1=7'b1101101;
4'b0011: hour1=7'b1111001;
4'b0100: hour1=7'b0110011;
4'b0101: hour1=7'b1011011;

4'b0110: hour1=7'b1011111;
4'b0111: hour1=7'b1110000;
4'b1000: hour1=7'b1111111;
4'b1001: hour1=7'b1111011;
default: hour1=7'b0;
endcase
end
always@(hr)
begin
case(hr[7:4])
4'b0000: hour2=7'b1111110;
4'b0001: hour2=7'b0110000;
4'b0010: hour2=7'b1101101;
4'b0011: hour2=7'b1111001;
4'b0100: hour2=7'b0110011;
4'b0101: hour2=7'b1011011;
4'b0110: hour2=7'b1011111;
4'b0111: hour2=7'b1110000;
4'b1000: hour2=7'b1111111;
4'b1001: hour2=7'b1111011;
default: hour2=7'b0;
endcase
end
endmodule

Signed 8 bit Pipelined Multiplier


module pipemulti(inp,clk,rst,outp,sign);
input [7:0] inp;
input clk,rst;
output [15:0]outp;
output sign;
reg [15:0]outp;
reg [1:0] cnt;
reg sign1,sign2;
reg [6:0] mem [1:0];
always @(posedge clk or posedge rst)
begin
if(clk)

begin
if(rst)
begin
outp <= 16'b0;
cnt <= 2'b0;
mem[0] <= 8'b0;
mem[1] <= 8'b0;
end
else
begin
if(cnt < 2'b10)
begin
mem[cnt] <= inp;
cnt <= cnt + 1;
sign2 <= inp[7];
sign1 <= sign2;
end
if(cnt == 2'b10)
begin
outp <= mem[0] * mem[1];
end
end
end
end
assign sign = sign1 ^ sign2;
endmodule

Clockwise pipelined serial and parallel adder to add/ subtract 8 number


of size 12 bits
module alu(inp, sel,clk,rst,cntrl,outps,outpp);
input [11:0] inp;
input sel;
input clk;
input rst;
input cntrl;
output [15:0] outps;
output [15:0] outpp;
reg [15:0] outps;
reg [15:0] outpp;

reg [11:0] mem [7:0];


reg [3:0]cnt;
reg en;

always @(inp or clk or rst or sel or cntrl)


begin
if(clk)
begin
if(rst)
begin
outps = 15'b0;
outpp = 15'b0;
mem[0]=12'b0;
mem[1]=12'b0;
mem[2]=12'b0;
mem[3]=12'b0;
mem[4]=12'b0;
mem[5]=12'b0;
mem[6]=12'b0;
mem[7]=12'b0;
cnt = 4'b0;
en = 1'b1;
end
else
begin
if(sel)
begin
if(cntrl)
begin
if(en)
begin
mem[cnt] = inp;
en = 1'b0;
cnt = cnt + 1;
if((cnt > 4'b0001) && (cnt < 4'b1010))
begin
outps = outps + mem[cnt-2];

end
if(cnt == 4'b1001)

begin
outpp = mem[0] + mem[1] + mem[2] +
mem[3] + mem[4] + mem[5] + mem[6] + mem[7];
end
end
end
else
begin
en = 1'b1;
end
end
else
begin
if(cntrl)
begin
if(en)
begin
mem[cnt] = inp;
if(cnt == 4'b0000)
begin
outps = mem[cnt];
cnt = cnt + 1;
end
else if((cnt > 4'b0001) && (cnt < 4'b1010))
begin
outps = outps - mem[cnt-1];
cnt = cnt + 1;
en = 1'b0;
end
if(cnt == 4'b1001)
begin
outpp = mem[0] - mem[1] - mem[2] mem[3] - mem[4] - mem[5] - mem[6] - mem[7];
end
end
end
else
begin
en = 1'b1;
end

end
end
end
end
endmodule

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