2c390 Compal LA-5841P PDF

A
Compal Confidential
2
Tampa Bay NPVAA

LA-5841P Schematics Document
Intel PineView Processor/ Tiger point
2009-10-21
REV: 1.0
Compal Electronics,Inc
Compal Secret Data
Security Classification
2009/10/21
Issued Date
Deciphered Date
2012/10/21
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SCHEMATICS,MB A5841
Rev
D
401799
Date:
Tuesday, December 15, 2009
Sheet
E
of
39
Compal Confidential
Model Name : NPVAA
File Name : LA-5841P
Thermal Sensor
Fan Control
page 24
Clock Generator
EMC1402
Intel Pineview-M
SLG8SP556VTR
page 5
page 8
CRT Conn.
page 10
(22x22mm)
LVDS
ONE CHANNEL
LED Conn.
page 9
DMI x 2
USB port 6
page 15
PCIeMini Card
WLAN
PCIe port 2
page 15
page 20
USB port 0,1,4

USB
USB
5V 480MHz
PCIeMini Card
GPS
5V 480MHz
PCIe 1x [2,4]
1.5V 2.5GHz(250MB/s)
RTL8103EL 10/100M
BT conn
page 17
PCIe port 3
(17x17mm)
1.5V 2.5GHz(250MB/s)
SATA port 0
page 20
5V 1.5GHz(150MB/s)
SATA HDD
page 17
page 11,12,13,14
USB
5V 480MHz
LPC BUS
HD Audio
page 26
3.3V 24.576MHz/48Mhz
HDA Codec
ALC272-GR
page 18
Debug Port
Power Circuit DC/DC
ENE KB926 D3
page 24
page 22
page 28~34
Touch Pad
IO/B
page 17
USB port 2
Tiger Pointer
DC/DC Interface CKT.
USB port 7
PCIe port 4
page 15
RTS5159 2IN1
USB port 3 page 21
page 13
Int. Camera
page 16
USB port 5
page 15
Card Reader
RTC CKT.
USB Conn X3
PCIeMini Card
WLAN
PCIe 1x
RJ45
page 7
3.3V 33 MHz
PCIeMini Card
WWAN
200pin DDRII-SO-DIMM
1.8V DDRII 667
page 4,5,6
Memory BUS(DDRII)
page 25
Int.KBD
SPI ROM
page 24
page 24
Int.
MIC CONN
page 19
GSENSOR
AMP.
MIC CONN
page 19
TPA6017
HP CONN
page 19
page 19
page 23
SPK CONN
page 19
page 16
Compal Secret Data
2009/10/21
Issued Date
Deciphered Date
2012/10/21
Title
Size
Date:
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
Sheet
E
of
39
Voltage Rails
SIGNAL
Power Plane
Description
S1
S3
S5
G3
VIN
Adapter power supply (19V)
ON
ON
ON
OFF
B+
AC or battery power rail for power circuit.
ON
ON
ON
ON
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
OFF
+0.89VS
0.89VS GFX support voltage
ON
OFF
OFF
OFF
STATE
SLP_S3# SLP_S4# SLP_S5#
+VALW
+V
+VS
Clock
ON
ON
ON
Full ON
HIGH
HIGH
HIGH
ON
S1(Power On Suspend)
HIGH
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
ON
OFF
OFF
OFF
+0.9VS
0.9V switched power rail for DDR terminator
ON
OFF
OFF
OFF
+1.05VS
VCCP switched power rail
ON
OFF
OFF
OFF
+1.5VS
1.5V switched power rail
ON
OFF
OFF
OFF
+1.8V
1.8V power rail for DDR
ON
ON
OFF
OFF
+1.8VS
1.8VS switched power rail
ON
OFF
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON
OFF
+3V_SB
3.3V power rail for LAN
ON
ON
OFF
OFF
+3V_LAN
ON
ON
OFF
OFF
+3V_WLAN
ON
ON
OFF
OFF
+3VS
3.3V switched power rail
ON
OFF
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON
OFF
+5V_SB
5V power rail for SB
ON
ON
OFF
OFF
description
+5VS
5V switched power rail
ON
OFF
OFF
OFF
explain
Wi-Fi
WiMax
3GGPS
3G
+VSB
VSB always on power rail
ON
ON
ON
OFF
+RTCVCC
RTC power
ON
ON
ON
ON
BTO
WLAN@
WIMAX@
3GGPS@
3G@
BTO Option Table

2
Function
STAR
Mini PCI-E SLOT
POWER SAVING
STAR@
Function
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
description
explain
BTO
EC SM Bus1 address
EC SM Bus2 address
Device
Address
Device
Address
Smart Battery
0001 011X b
EMC1402
1001 010X b
Tiger point SM Bus address

Device
Address
Clock Generator
(SLG8SP556VTR)
1101 001Xb
DDR DIMMA
1010 000Xb
Compal Secret Data
2009/10/21
Issued Date
Deciphered Date
2012/10/21
Title
Custom
Date:
SCHEMATICS,MB A5841
Rev
D
401799
Sheet
E
of
39
<7> DDR_A_DQS#[0..7]
PINEVIEW_M
<7> DDR_A_D[0..63]
U1B
REV = 1.1
<7> DDR_A_DM[0..7]
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
<7> DDR_A_DQS[0..7]
<7> DDR_A_MA[0..14]
PINEVIEW_M
U1A
D
REV = 1.1
DMI_RXP0_C
DMI_RXN0_C
DMI_RXP1_C
DMI_RXN1_C
F3
F2
H4
G3
DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1
DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1
G2
G1
H3
J2
DMI_TXP0
DMI_TXN0
DMI_TXP1
DMI_TXN1
<12>
<12>
<12>
<12>
DMI
N7
N6
<8> CLK_CPU_EXP#
<8> CLK_CPU_EXP
EXP_CLKINN
EXP_CLKINP
R10
R9
N10
N9
EXP_RCOMPO
EXP_ICOMPI
EXP_RBIAS
L10
L9
L8
RSVD_TP
RSVD_TP
N11
P11
EXP_TCLKINN
EXP_TCLKINP
RSVD
RSVD
K2
J1
M4
L3
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
DMI_IRCOMP
T1
T2
<7> DDR_A_WE#
<7> DDR_A_CAS#
<7> DDR_A_RAS#
R1
R2
49.9_0402_1%
750_0402_1%
<7> DDR_A_BS0
<7> DDR_A_BS1
<7> DDR_A_BS2
Pull-down must be placed

within 500 mils from Pineview-M
<7> DDR_CS0#
<7> DDR_CS1#
K3
L2
M2
N2
<7> DDR_CKE0
<7> DDR_CKE1
AH19
AJ18
AK18
AK16
AJ14
AH14
AK14
AJ12
AH13
AK12
AK20
AH12
AJ11
AJ24
AJ10
DDR_A_MA_0
DDR_A_MA_1
DDR_A_MA_2
DDR_A_MA_3
DDR_A_MA_4
DDR_A_MA_5
DDR_A_MA_6
DDR_A_MA_7
DDR_A_MA_8
DDR_A_MA_9
DDR_A_MA_10
DDR_A_MA_11
DDR_A_MA_12
DDR_A_MA_13
DDR_A_MA_14
DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#
AK22
AJ22
AK21
DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
AJ20
AH20
AK11
DDR_A_BS_0
DDR_A_BS_1
DDR_A_BS_2
DDR_CS0#
DDR_CS1#
AH22
AK25
AJ21
AJ25
DDR_A_CS#_0
DDR_A_CS#_1
DDR_A_CS#_2
DDR_A_CS#_3
DDR_CKE0
DDR_CKE1
AH10
AH9
AK10
AJ8
DDR_A_CKE_0
DDR_A_CKE_1
DDR_A_CKE_2
DDR_A_CKE_3
M_ODT0
M_ODT1
AK24
AH26
AH24
AK27
DDR_A_ODT_0
DDR_A_ODT_1
DDR_A_ODT_2
DDR_A_ODT_3
1 OF 6
PINEVIEW-M_FCBGA8559
<7> M_ODT0
<7> M_ODT1
C
<12> DMI_RXP0
C1 1
DMI_RXP0_C
2
0.1U_0402_10V6K
<12> DMI_RXN0
C2 1
DMI_RXN0_C
2
0.1U_0402_10V6K
<12> DMI_RXP1
C3 1
DMI_RXP1_C
2
0.1U_0402_10V6K
<12> DMI_RXN1
C4 1
DMI_RXN1_C
2
0.1U_0402_10V6K
<7>
<7>
<7>
<7>
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
Close to CPU
DDR_A_CK_0
DDR_A_CK_0#
DDR_A_CK_1
DDR_A_CK_1#
AC15
AD15
AF13
AG13
DDR_A_CK_3
DDR_A_CK_3#
DDR_A_CK_4
DDR_A_CK_4#
AD17
AC17
AB15
AB17
RSVD
RSVD
RSVD
RSVD
AB4
AK8
RSVD
RSVD
AD3
AD2
AD4
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DM0
DDR_A_DQ_0
DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7
AC4
AC1
AF4
AG2
AB2
AB3
AE2
AE3
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_DQS_1
DDR_A_DQS#_1
DDR_A_DM_1
AB8
AD7
AA9
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DM1
DDR_A_DQ_8
DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15
AB6
AB7
AE5
AG5
AA5
AB5
AB9
AD6
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_DQS_2
DDR_A_DQS#_2
DDR_A_DM_2
AD8
AD10
AE8
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DM2
DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23
AG8
AG7
AF10
AG11
AF7
AF8
AD11
AE10
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_DQS_3
DDR_A_DQS#_3
DDR_A_DM_3
AK5
AK3
AJ3
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DM3
DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31
AH1
AJ2
AK6
AJ7
AF3
AH2
AL5
AJ6
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_DQS_4
DDR_A_DQS#_4
DDR_A_DM_4
AG22
AG21
AD19
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DM4
DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39
AE19
AG19
AF22
AD22
AG17
AF19
AE21
AD21
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_DQS_5
DDR_A_DQS#_5
DDR_A_DM_5
AE26
AG27
AJ27
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DM5
DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47
AE24
AG25
AD25
AD24
AC22
AG24
AD27
AE27
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_DQS_6
DDR_A_DQS#_6
DDR_A_DM_6
AE30
AF29
AF30
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DM6
DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55
AG31
AG30
AD30
AD29
AJ30
AJ29
AE29
AD28
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_DQS_7
DDR_A_DQS#_7
DDR_A_DM_7
AB27
AA27
AB26
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DM7
DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63
AA24
AB25
W24
W22
AB24
AB23
AA23
W27
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
+1.8V
1
7/20 Add R238 and R239 for Ref board design

+1.8V
XDP Reserve
AG15
AF15
AD13
AC13
DDR_A_DQS_0
DDR_A_DQS#_0
DDR_A_DM_0
R238
10K_0402_5%
R4
XDP_TDO
R5
XDP_PREQ#
R7
1
2
51_0402_5%
1
2
51_0402_5%
1
2
51_0402_5%
1
2
51_0402_5%
+1.8V
R6
1
C302
0.01U_0402_16V7K
DDR_RPU
80.6_0402_1%
R8
7/21 Add C302 to GND for Intel request
1
2
51_0402_5%
1
2
51_0402_5%
DDR_VREF
DDR_RPD
DDR_RPU
R12
T3
T4
R9
7/27 Change C302 to GND for +1.8V pull up
DDR_RPD
R11
80.6_0402_1%
1K_0402_1%
C5
0.1U_0402_16V4Z
AB11
AB13
RSVD_TP
RSVD_TP
AL28
AK28
AJ26
DDR_VREF
DDR_RPD
DDR_RPU
AK29
RSVD
R10
XDP_TCK
1K_0402_1%
XDP_TRST#
R239
10K_0402_5%
2
R3
XDP_TMS
XDP_TDI
+1.05VS
DDR_A
8/14 Add +DDR_VREF net name

8/24 Change net to DDR_VREF
JXDP
<5> XDP_PREQ#
<5> XDP_PRDY#
XDP_PREQ#
XDP_PRDY#
<5>
<5>
XDP_BPM#3
XDP_BPM#2
XDP_BPM#3
XDP_BPM#2
<5>
<5>
XDP_BPM#1
XDP_BPM#0
XDP_BPM#1
XDP_BPM#0
<5,13> H_PWRGD
<13> SLPIOVR
+1.05VS
<5,13,15,20,24> PLTRST#
A
R13
R14
PLTRST#
2 1K_0402_5%
2 1K_0402_5%
T5
T6
1
1
2 R15
1 1K_0402_5%
T7
<5> XDP_TDO
<5> XDP_TRST#
<5>
XDP_TDI
<5>
XDP_TMS
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
<5>
XDP_TCK
XDP_TCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
G1
G2
D33
XDP_TDI
XDP_TMS
D34
I/O1
I/O4
REF1 REF2
I/O2
I/O3
XDP_TDO
+3VS
XDP_PREQ#
XDP_TRST#
CM1293A-04SO_SOT23-6
@
I/O1
REF1 REF2
I/O2
I/O4
I/O3
6
+3VS
XDP_TCK
@
2 OF 6
Place diff CPU side

10/19 Change footprint T5, T6 and T7 from TPC24 to TPC12
2009/10/21
Issued Date
Compal Secret Data
ACES_87151-24051
@
2012/10/21
Deciphered Date
Title
Custom
Date:
SCHEMATICS,MB A5841
Rev
D
401799
Sheet

1
of
39
REV = 1.1
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_IRTN
N31
P30
P29
N30
CRT_DDC_DATA
CRT_DDC_CLK
L31
L30
DAC_IREF
P28
DAC_IREF
Y30
Y29
AA30
AA31
CPU_DREFCLK
CPU_DREFCLK#
CPU_SSCDREFCLK
CPU_SSCDREFCLK#
GMCH_CRT_HSYNC
GMCH_CRT_VSYNC
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
<10>
<10>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
GMCH_CRT_R <10>
GMCH_CRT_G <10>
GMCH_CRT_B <10>
LVDS_ACLK#
LVDS_ACLK
LVDS_A0#
LVDS_A0
LVDS_A1#
LVDS_A1
LVDS_A2#
LVDS_A2
R17 be placed <500 mils to U1.P28
REFCLKINP
REFCLKINN
REFSSCLKINP
REFSSCLKINN
GMCH_CRT_DATA <10>
GMCH_CRT_CLK <10>
R17
665_0402_1%
R16
L_IBG
2.37K_0402_1%
R16 be placed U1.R22
CPU_DREFCLK <8>
CPU_DREFCLK# <8>
CPU_SSCDREFCLK <8>
CPU_SSCDREFCLK# <8>
<9> LVDS_SCL
<9> LVDS_SDA
<9> GMCH_ENVDD
+3VS
8/14 Add DAC_IREF net name
RSVD
PM_EXTTS#_1/DPRSLPVR
PM_EXTTS#_0
PWROK
RSTIN#
K29
J30
L5
AA3
PM_EXTTS#1
PM_EXTTS#0
PCH_POK
PLTRST#
0_0402_5%
R19
PM_DPRSLPVR <13>
PM_EXTTS#0 <7>
PCH_POK <13>
PLTRST# <4,13,15,20,24>
T26
T27
T28
T29
AA7
AA6
R5
R6
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
T31
T33
T35
T37
AA21
W21
T21
V21
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
CLK_CPU_HPLCLK#
CLK_CPU_HPLCLK
CLK_CPU_HPLCLK# <8>
CLK_CPU_HPLCLK <8> Close
R22
J28
N22
N23
L27
L26
L23
K25
K23
K24
H26
LIBG
LVBG
LVREFH
LVREFL
LBKLT_EN
LBKLT_CTL
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
SMI#
A20M#
FERR#
LINT0
LINT1
IGNNE#
STPCLK#
E7
H7
H6
F10
F11
E5
F8
H_SMI#
H_A20M#
H_FERR#
H_INTR
H_NMI
H_IGNNE#
H_STPCLK#
DPRSTP#
DPSLP#
INIT#
PRDY#
PREQ#
G6
G10
G8
E11
F15
H_DPRSTP#
H_DPSLP#
H_INIT#
XDP_PRDY#
XDP_PREQ#
THERMTRIP#
E13
H_THERMTRIP#
PROCHOT#
CPUPWRGOOD
C18
W1
H_PROCHOT#
H_PWRGD
GTLREF
VSS
A13
H27
H_GTLREF
RSVD
RSVD
L6
E17
8/24 Change net name to H_GTLREF
BCLKN
BCLKP
H10
J10
CLK_CPU_BCLK#
CLK_CPU_BCLK
BSEL_0
BSEL_1
BSEL_2
K5
H5
K6
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
H30
H29
H28
G30
G29
F29
E29
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
RSVD
RSVD
RSVD
RSVD
L7
D20
H13
D18
RSVD_TP
RSVD_TP
EXTBGREF
K9
D19
K7
<4>
<4>
<4>
<4>
To be placed <250 mils to U1 ball

GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
ENBKL
2
150_0402_1%
1 R22
2
150_0402_1%
1 R23
2
150_0402_1%
R24
100K_0402_5%
<4>
<4>
<4>
<4>
<4>
G11
E15
G13
F13
BPM_1_0#
BPM_1_1#
BPM_1_2#
BPM_1_3#
T30
T32
T34
T36
B18
B20
C20
B21
BPM_2_0#/RSVD
BPM_2_1#/RSVD
BPM_2_2#/RSVD
BPM_2_3#/RSVD
T38
G5
D14
D13
B14
C14
C16
RSVD
TDI
TDO
TCK
TMS
TRST#
D30
E30
THRMDA_1
THRMDC_1
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
R21
To be placed <500 mils to U1 ball
XDP_TDI
XDP_TDO
XDP_TCK
XDP_TMS
XDP_TRST#
H_THERMDA
H_THERMDC
XDP_RSVD_9
0.1U_0402_16V4Z
1
C6
H_DPRSTP#
C151 1
@2 220P_0402_50V7K
H_DPSLP#
C152 1
@2 220P_0402_50V7K
H_PWRGD
C154 1
@2 220P_0402_50V7K
H_A20M#
C134 1
@2 220P_0402_50V7K
H_IGNNE#
C135 1
@2 220P_0402_50V7K
H_INIT#
C136 1
@2 220P_0402_50V7K
H_INTR
C137 1
@2 220P_0402_50V7K
H_FERR#
C138 1
@2 220P_0402_50V7K
H_NMI
C139 1
@2 220P_0402_50V7K
H_SMI#
C140 1
@2 220P_0402_50V7K
H_STPCLK#
C141 1
@2 220P_0402_50V7K
U2
H_THERMDA
H_THERMDC
2200P_0402_50V7K
CPU_THERM#
SMCLK
EC_SMB_CK2
DP
SMDATA
EC_SMB_DA2
DN
ALERT#
THERM#
GND
VDD
2
@ R29
EC_SMB_CK2 <22,23>
EC_SMB_DA2 <22,23>
CLK_CPU_BCLK# <8>
CLK_CPU_BCLK <8>
CPU_BSEL0 <8>
CPU_BSEL1 <8>
CPU_BSEL2 <8>
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
<34>
<34>
<34>
<34>
<34>
<34>
<34>
T39
T40
H_EXTBGREF
THRMDA_2/RSVD
THRMDC_2/RSVD
2009/10/21
Issued Date
Address:0100_1100 EMC1402-1
Address:0100_1101 EMC1402-2
+1.05VS
R25
1K_0402_1%
R26
976_0402_1%
H_GTLREF
C336
H_EXTBGREF
2
@
220P_0402_50V7K
R27
2K_0402_1%
C335
1U_0402_6.3V6K
7/20 Reserve C336 for Ref board design
Deciphered Date
R28
3.3K_0402_1%
7/20 Add C335 for Ref board design
2012/10/21
Title
Size
B
Date:
placed within 0.5" of processor

pin and 5 mils spacing
+1.05VS
Compal Secret Data
EMC1402-1-ACZL-TR_MSOP8
placed within 0.5"

of processor pin.
ESD request
1
+3VS
10K_0402_5%
2
10K_0402_5%
Close to CPU
4 OF 6
CPU THERMAL SENSOR
C7
R30
H_PWRGD <4,13>
R18
68_0402_5%
+3VS
+3VS
H_THERMTRIP# <11>
8/24 Change net name to H_EXTBGREF
7/21 Pull down 1K to GND for Intel request
+1.05VS
2
3 OF 6
H_DPRSTP# <13>
H_DPSLP# <13>
H_INIT# <11>
XDP_PRDY# <4>
XDP_PREQ# <4>
C30
D31
8/14 Change net name to +H_EXTBGREF

R137
1K_0402_5%
H_SMI# <11>
H_A20M# <11>
H_FERR# <11>
H_INTR <11>
H_NMI
<11>
H_IGNNE# <11>
H_STPCLK# <11>
8/14 Change net name to +H_GTLREF
to Processor pin
MISC
W8
W9
LA_CLKN
LA_CLKP
LA_DATAN_0
LA_DATAP_0
LA_DATAN_1
LA_DATAP_1
LA_DATAN_2
LA_DATAP_2
R20
10K_0402_5%
PM_EXTTS#0
HPL_CLKINN
HPL_CLKINP
ENBKL
<22>
ENBKL
<9> GMCH_INVT_PWM
U25
U26
R23
R24
N26
N27
R26
R27
CPU
M30
M29
LVDS
CRT_HSYNC
CRT_VSYNC
ICH
REV = 1.1
XDP_RSVD_00
XDP_RSVD_01
XDP_RSVD_02
XDP_RSVD_03
XDP_RSVD_04
XDP_RSVD_05
XDP_RSVD_06
XDP_RSVD_07
XDP_RSVD_08
XDP_RSVD_09
XDP_RSVD_10
XDP_RSVD_11
XDP_RSVD_12
XDP_RSVD_13
XDP_RSVD_14
XDP_RSVD_15
XDP_RSVD_16
XDP_RSVD_17
L11
PINEVIEW_M
U1D
T25
8/24 Det CRT_IRTN net name
VGA
8/14 Add CRT_IRTN net name
PINEVIEW_M
U1C
D12
T8
A7
T9
D6
T10
C5
T11
C7
T12
C6
T13
D8
T14
B7
T15
A9
T16
XDP_RSVD_9 D9
C8
T17
B8
T18
C10
T19
D10
T20
B11
T21
B10
T22
B12
T23
C11
T24
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
Sheet
1
of
39
+1.05VS
+1.8V
R36
1
2270mA
0_0603_5%
1
1 @
C32
C31
+VCCCK_DDR AK7
AL7
0.1U_0402_10V6K
2
+VCCA_VCCD
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
+VCCCK_DDR
22U_0805_6.3V6M
AK13
AK19
AK9
AL11
AL16
AL21
AL25
1320mA
Please closed U1 ball
U10
U5
U6
U7
U8
U9
V2
V3
V4
W10
W11
AA10
AA11
VCCCK_DDR
VCCCK_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
C20
2 x 330uF(9mohm/2)
+
2
1
+
C23
330U_D2_2.5VY_R9M
C24
+RING_WEST
1 R34
2
0_0603_5%
330U_D2_2.5VY_R9M
2
+CPU_CORE
1 R35
+LGI_VID
2
@
0_0603_5%
C26
1U_0402_6.3V6K
+CPU_CORE
1 R37
+VCC_DMI
0_0603_5%
R38
100_0402_5%
VCCSENSE
VSSSENSE
VCCA
VCCACK_DDR
VCCACK_DDR
C29
B29
Y2
VCCSENSE
VSSSENSE
VCCSENSE <34>
VSSSENSE <34>
+1.05VS
D4
B4
B3
VCCD_AB_DPL
2
C38
@
2
R39
C35
0.01U_0402_16V7K
0.1U_0402_10V6K
1 R40
2
0_0603_5%
+VCCSFR_AB_DPL
100_0402_5%
2
VCCP
VCCP
+1.8VS
+1.5VS
80mA
1
C36
1U_0402_6.3V6K
Please closed U1.Y2
C37
1U_0402_6.3V6K
2
2
Please closed U1.D4

V11
+VCCSFR_AB_DPL
+VCC_CRT_DAC
1
AC31
VCCSFR_AB_DPL
EXP\CRT\PLL
T30
VCCACRTDAC
+3VS
5mA
305mA
+LGI_VID
VCC_GIO
VCCRING_EAST
VCCRING_WEST
VCCRING_WEST
VCCRING_WEST
VCC_LGI
V30
W31
VCCA_DMI
VCCA_DMI
VCCA_DMI
T1
T2
T3
+VCC_ALVD
+VCC_DLVD
C39
1U_0402_6.3V6K
60mA
+DMI_HMPLL
1 R42
2
0_0603_5%
DMI
T31
J31
C3
B2
C2
A21
VCCALVDS
VCCDLVDS
LVDS
154mA
+VCC_CRT_DAC
+RING_EAST
+RING_WEST
1 R41
2
0_0603_5%
VCCD_HMPLL
RSVD
VCCSFR_DMIHMPLL
VCCP
P2
AA1
E2
+VCC_DMI
480mA
+DMI_HMPLL
C40
1U_0402_6.3V6K
T41
104mA
1 R43
2
0_0603_5%
+1.05VS
+VCC_ALVD
5 OF 6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F24
F28
F4
G15
G17
G22
G27
G31
H11
H15
H2
H21
H25
H8
J11
J13
J15
J4
K11
K13
K19
K26
K27
K28
K30
K4
K8
L1
L13
L18
L22
L24
L25
L29
M28
M3
N1
N13
N18
N24
N25
N28
N4
N5
N8
P13
P14
P16
P18
P19
P21
P3
P4
R25
R7
R8
T11
U22
U23
U24
U27
V14
V16
V18
V28
V29
W13
W2
W23
W25
W26
W28
W30
W4
W5
W6
W7
Y28
Y3
Y4
VSS
T29
R44
1
2
0_0603_5%
+0.89VS
REV = 1.1
VSS
VSS
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
RSVD_NCTF
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
RSVD_NCTF
RSVD_NCTF
VSS
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
RSVD_NCTF
VSS
RSVD_NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
6 OF 6
1
C41
22U_0805_6.3V6M
PINEVIEW_M
GND
C17
1U_0402_6.3V6K
C9
4.7U_0603_6.3V6K
C8
22U_0805_6.3V6M
C16
0.1U_0402_10V6K
+RING_EAST
2
0_0603_5%
+CPU_CORE
VCCP
AA19
R32
1U_0402_6.3V6K
+VCC_SM
C27
2.2U_0603_6.3V6K
1U_0402_6.3V6K
2.2U_0603_6.3V6K
1U_0402_6.3V6K
+1.05VS
1U_0402_6.3V6K
2.2U_0603_6.3V6K
C22
1U_0402_6.3V6K
C34
C21
1U_0402_6.3V6K
C25
C14
@1
C33
@2
C13
1U_0402_6.3V6K
2
1
C11
U1F
A11
A16
A19
A29
A3
A30
A4
AA13
AA14
AA16
AA18
AA2
AA22
AA25
AA26
AA29
AA8
AB19
AB21
AB28
AB29
AB30
AC10
AC11
AC19
AC2
AC21
AC28
AC30
AD26
AD5
AE1
AE11
AE13
AE15
AE17
AE22
AE31
AF11
AF17
AF21
AF24
AF28
AG10
AG3
AH18
AH23
AH28
AH4
AH6
AH8
AJ1
AJ16
AJ31
AK1
AK2
AK23
AK30
AK31
AL13
AL19
AL2
AL23
AL29
AL3
AL30
AL9
B13
B16
B19
B22
B30
B31
B5
B9
C1
C12
C21
C22
C25
C31
D22
E1
E10
E19
E21
E25
E8
F17
F19
1
C10
POWER
0_0603_5%
@
C12
+VCC_SM
1
C19
22U_0805_6.3V6M
2 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
CPU
R33
1
C18
1U_0402_6.3V6K
22U_0805_6.3V6M
C30
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
VCCGFX
GFX/MCH
T13
T14
T16
T18
T19
V13
V19
W14
W16
W18
W19
3500mA 1U_0402_6.3V6K
DDR
+1.8V
REV = 1.1
1380mA
A23
A25
A27
B23
B24
B25
B26
B27
C24
C26
D23
D24
D26
D28
E22
E24
E27
F21
F22
F25
G19
G21
G24
H17
H19
H22
H24
J17
J19
J21
J22
K15
K17
K21
L14
L16
L19
L21
N14
N16
N19
N21
22U_0805_6.3V6M
C29
+0.89VS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
C28
PINEVIEW_M
+VCCA_VCCD
2
0_0603_5%
+CPU_CORE
U1E
R31
C15
0.1U_0402_10V6K
+VCC_DLVD
1
C51
C50
C49
C48
C47
C46
C45
1
+
2
C42
1U_0402_6.3V6K
330U_D2_2.5VY_R9M
10U_0805_10V4Z
C53
0.1U_0402_10V6K
C52
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C43
2.2U_0603_10V6K
C44
Close Chipset pin
Compal Secret Data
2009/10/21
Issued Date
2012/10/21
Deciphered Date
Title
SCHEMATICS,MB A5841
Custom
Date:
Rev
D
401799
Sheet

1
of
39
+1.8V
+1.8V
JDDR
1
<4> DDR_A_DQS#[0..7]
DDR_A_D0
DDR_A_D1
1K_0402_1%
2
<4> DDR_A_DM[0..7]
<4> DDR_A_MA[0..14]
DDR_A_DQS#0
DDR_A_DQS0
+DIMM_VREF
1
Layout Note:
Place near JDDR1
<4> DDR_A_DQS[0..7]
Share +DIMM_VREF for

1.DDRII VREF
2.PineView DDR_VREF
R46
1K_0402_1%
D
DDR_A_D2
DDR_A_D3
DDR_A_D9
DDR_A_D8
DDR_A_DQS#1
DDR_A_DQS1
+DIMM_VREF
+1.8V
DDR_A_D10
DDR_A_D11
C58
2.2U_0603_6.3V6K
C57
2.2U_0603_6.3V6K
C56
2.2U_0603_6.3V6K
C55
2.2U_0603_6.3V6K
C54
2.2U_0603_6.3V6K
20mils
C59
2
0.1U_0402_16V4Z
Please closed SO-DIMM
+1.8V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
+DIMM_VREF
R45
<4> DDR_A_D[0..63]
C60
@
2.2U_0603_6.3V6K
7/21 Reserve C60
C291
0.1U_0402_16V4Z
C238
0.1U_0402_16V4Z
C216
0.1U_0402_16V4Z
C217
0.1U_0402_16V4Z
C65
0.1U_0402_16V4Z
C64
0.1U_0402_16V4Z
C63
0.1U_0402_16V4Z
+
2
C62
0.1U_0402_16V4Z
C61
220U_B2_2.5VM_R35
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D16
DDR_A_D17
DDR_A_DM2
DDR_A_D18
DDR_A_D19
7/8 Add 4PCS CAP on 1.8V for EMI request
<4>
DDR_CKE0
DDR_CKE0
DDR_A_BS2
<4> DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
+0.9VS
<4> DDR_A_BS0
<4> DDR_A_WE#
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
<4> DDR_A_CAS#
<4> DDR_CS1#
DDR_A_CAS#
DDR_CS1#
<4>
M_ODT1
M_ODT1
C86
0.1U_0402_16V4Z
C85
0.1U_0402_16V4Z
C84
0.1U_0402_16V4Z
C83
0.1U_0402_16V4Z
C82
0.1U_0402_16V4Z
C81
0.1U_0402_16V4Z
C80
0.1U_0402_16V4Z
1
@
C79
0.1U_0402_16V4Z
1
@
C78
0.1U_0402_16V4Z
C77
0.1U_0402_16V4Z
1
@
C76
0.1U_0402_16V4Z
C75
0.1U_0402_16V4Z
C74
0.1U_0402_16V4Z
1
@
C73
0.1U_0402_16V4Z
C72
0.1U_0402_16V4Z
C71
0.1U_0402_16V4Z
1
@
C70
0.1U_0402_16V4Z
1
@
C69
0.1U_0402_16V4Z
1
@
C68
0.1U_0402_16V4Z
1
@
C67
0.1U_0402_16V4Z
C66
0.1U_0402_16V4Z
DDR_A_D33
DDR_A_D32
DDR_A_DQS#4
DDR_A_DQS4
1
DDR_A_D39
DDR_A_D34
DDR_A_D41
DDR_A_D40
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
9/4 Reserve C66, C67, C68, C69, C72, C75, C77, C78, C79, C81, C83, C84, C85
+0.9VS
RP1
DDR_A_WE#
DDR_A_CAS#
DDR_CS1#
M_ODT1
1
2
3
4
DDR_A_DQS#6
DDR_A_DQS6
RP2
8
7
6
5
8
7
6
5
1
2
3
4
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS0
47_0804_8P4R_5%
RP3
DDR_A_MA12 1
8
DDR_A_MA9 2
7
DDR_A_MA8 3
6
DDR_A_MA5 4
5
47_0804_8P4R_5%
RP4
8
1 M_ODT0
7
2 DDR_A_MA13
6
3 DDR_CS0#
5
4 DDR_A_RAS#
47_0804_8P4R_5%
RP5
1
8
2
7
3
6
4
5
47_0804_8P4R_5%
RP6
8
1 DDR_A_MA4
7
2 DDR_A_MA11
6
3 DDR_A_MA7
5
4 DDR_A_MA14
DDR_A_BS1
DDR_A_MA0
DDR_A_MA2
DDR_A_MA6
47_0804_8P4R_5%
DDR_A_D50
DDR_A_D51
Layout Note:
Place these resistor
closely DIMMA,all
trace length<1000 mil
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D62
DDR_A_D59
0.1U_0402_16V4Z
DDR_A_BS2
DDR_CKE0
1 R50
2
47_0402_5%
1 R51
2
47_0402_5%
1 R52
2
47_0402_5%
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
201
C87
C88
Layout Note:
Place these resistor
closely DIMMA,all
trace length
Max=1000 mil
0.1U_0402_16V4Z
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
G2
202
DDR_A_D5
DDR_A_D4
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
2009/10/21
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR0 <4>
M_CLK_DDR#0 <4>
DDR_A_D14
DDR_A_D15
DDR_A_D24
DDR_A_D25
R47
DDR_A_DM3
PM_EXTTS#0 <5>
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D22
DDR_A_D23
DDR_CKE1
DDR_CKE1 <4>
C
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS0#
DDR_A_BS1 <4>
DDR_A_RAS# <4>
DDR_CS0# <4>
M_ODT0
DDR_A_MA13
M_ODT0 <4>
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D35
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
B
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 <4>
M_CLK_DDR#1 <4>
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D58
DDR_A_D63
R48
R49
1
1
2 10K_0402_5%
2 10K_0402_5%
FOX_AS0A426-N4SN-7F_200P
@
DIMMA
2012/10/21
Deciphered Date
Title
Date:
2
0_0402_5%
DDR_A_D20
DDR_A_D21
Custom
5
DDR_A_D26
DDR_A_D27
Compal Secret Data
Issued Date
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
G1
47_0804_8P4R_5%
DDR_CKE1
CLK_SMBDATA
CLK_SMBCLK
<8,15> CLK_SMBDATA
<8,15> CLK_SMBCLK
+3VS
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
+1.8V
SCHEMATICS,MB A5841
Rev
D
401799
Sheet
1
of
39
FSC
FSB
FSA
CLKSEL2
CLKSEL1
CLKSEL0
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
DOT_96 USB
MHz
MHz
266
100
33.3
14.318
96.0
48.0
133
100
33.3
14.318
96.0
48.0
200
100
33.3
14.318
96.0
48.0
R53
CPU_SSCDREFCLK
250 mA
1
2
FBMH1608HM601-T_0603
+3VS
+3VM_CK505
C89
C90
C91
C328
0.1U_0402_16V4Z
47P_0402_50V8J
C300
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
7/13 For RF request
166
100
33.3
14.318
96.0
80 mA
1
2
FBMH1608HM601-T_0603
48.0
333
100
33.3
14.318
96.0
48.0
100
100
33.3
14.318
96.0
48.0
1
@
C301
33P_0402_50V8K
@
33P_0402_50V8K
7/13 Add 33pFfor RF request
+1.05VM_CK505
R54
+1.05VS
CPU_SSCDREFCLK#
C92
7/21 Reserve 33pFfor RF request

1
C96
C97
C98
C99
C100
+3VS
C101
C329
0.1U_0402_16V4Z
47P_0402_50V8J
7/13 For RF request
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R55
R56
2.2K_0402_5%
+1.5VM_CK505
400
100
33.3
14.318
96.0
48.0
1
2
FBMH1608HM601-T_0603
+1.5VS
Reserved
7/13 For RF request
+3VS
7/21 Delete C296, C297 for RF request

7/13 Add 22pF to gnd and close to U3 for RF request
+3VM_CK505
U3
+3VM_1.5VM_R
2
2
C106
C105
0.1U_0402_16V4Z
+1.05VM_CK505
0.1U_0402_16V4Z
0_0603_5%
R59
1
C104
0_0603_5%
@ R60
1
2
55
0.1U_0402_16V4Z
0_0603_5%
CPU_BSEL0
1
2
R252
0_0402_5%
8/24 Change net name to FSB for U3.2

1
<5>
7/13 For RF request
47P_0402_50V8J
C107
1
R248
470_0402_5%
R251
2.2K_0402_5%
FSA 2
1
+1.05VM_CK505
+1.05VM_1.5VM_R
0_0603_5%
C330
@ R61
1
+1.5VM_CK505
0.1U_0402_16V4Z
+1.05VS
C
@ R253
1K_0402_5%
7/13 Add 33pF to GND for RF request
<21> CLK_48M_CR
7/21 Reserve 33pF to GND for RF request
<12> CLK_PCH_48M
8/27 C303, C324, C325, C326, C327 to GND for RF request
2 R62
22_0402_5% 1
2 R63
2
+1.05VS
<13,22,34> VGATE
CLK_SMBCLK
CLK_CPU_BCLK
VDD_PCI
CPU_0
VDD_CPU
CPU_0#
70
CLK_CPU_BCLK#
19
VDD_48
CPU_1
68
CLK_CPU_HPLCLK
27
VDD_PLL3
CPU_1#
67
CLK_CPU_HPLCLK#
66
VDD_CPU_IO
SRC_0/DOT_96
24
CPU_DREFCLK
31
VDD_PLL3_IO
SRC_0#/DOT_96#
25
CPU_DREFCLK#
62
VDD_SRC_IO
52
VDD_SRC_IO
23
VDD_IO
38
VDD_SRC_IO
FS_B/TEST_MODE
REF_0/FS_C/TEST_
REF_1
CPU_SSCDREFCLK
CPU_SSCDREFCLK#
SRC_2
32
CLK_CPU_EXP
SRC_2#
33
CLK_CPU_EXP#
SRC_3
35
SRC_3#
36
SRC_4
39
CLK_PCIE_SATA
SRC_4#
40
CLK_PCIE_SATA#
NC
SRC_6
57
CLK_PCIE_WLAN
SRC_6#
56
CLK_PCIE_WLAN#
<5>
CPU_BSEL1
1
2
R242
0_0402_5%
R71
R70
<24> CLK_PCI_DDR
33_0402_5% 1
2
+1.05VS
8/14 Add R250 pull up for Intel request
<22> CLK_PCI_LPC
<11> CLK_PCI_PCH
R250
470_0402_5%
CPU_BSEL2
1
2
R247
0_0402_5%
CPU_STOP#
54
PCI_STOP#
2 R72
44
CLK_PCIE_LAN
45
CLK_PCIE_LAN#
15
PCI_3
PCI4_SEL
16
PCI_4/SEL_LCDCL
33_0402_5% 1
2 R74
2
2
17
PCIF_5/ITP_EN
18
VSS_PCI
VSS_REF
1
2
C327 22P_0402_50V8J
50
CLK_PCIE_PCH
51
CLK_PCIE_PCH#
SRC_11
48
CLK_PCIE_WWAN
SRC_11#
47
CLK_PCIE_WWAN#
22
VSS_48
CLKREQ_3#
37
26
VSS_IO
CLKREQ_4#
41
69
VSS_CPU
CLKREQ_6#
58
30
VSS_PLL3
CLKREQ_7#
65
34
VSS_SRC
CLKREQ_9#
43
59
VSS_SRC
SLKREQ_10#
49
42
VSS_SRC
73
VSS
R75
CLKREQ_11#
46
USB_1/CLKREQ_A#
21
CPU_DREFCLK
CPU_DREFCLK#
<5>
<5>
<5>
CPU_SSCDREFCLK
<5>
CPU_SSCDREFCLK#
<5>
CLK_CPU_EXP <4>
CLK_CPU_EXP# <4>
@
R78
10K_0402_5%
10K_0402_5%
10K_0402_5%
SRC0
SRC2
SRC3
SRC4
SRC6
SRC7
SRC8
SRC9
SRC10
SRC11
CPU_DREFCLK
CPU_EXP
PCIE_SATA
PCIE_WLAN
PCIE_LAN
PCIE_PCH
PCIE_WWAN
+3VS
CLK_PCIE_SATA# <11>
WLAN_CLKREQ#
WWAN_CLKREQ#
LAN_CLKREQ#
CLK_PCIE_WLAN <15>
CLK_PCIE_WLAN# <15>
R67
R68
R69
1 10K_0402_5%
1 10K_0402_5%
1 10K_0402_5%
2
2
2
REQ PORT LIST
CLK_PCIE_LAN <20>
CLK_PCIE_LAN# <20>
PORT
CLK_PCIE_PCH <12>
CLK_PCIE_WWAN
CLK_PCIE_WWAN#
WLAN_CLKREQ#
<15>
<15>
WLAN_CLKREQ# <15>
LAN_CLKREQ#
DEVICE
REQ_3#
REQ_4#
REQ_6# PEIC_WLAN
REQ_7#
REQ_9# PCIE_LAN
REQ_10#
REQ_11# PEIC_WWAN
REQ_A#
CLK_PCIE_PCH# <12>
LAN_CLKREQ# <20>
WWAN_CLKREQ#
WWAN_CLKREQ# <15>
A
Issued Date
Compal Secret Data
R77
DEVICE
CLK_PCIE_SATA <11>
2009/10/21
Deciphered Date
2012/10/21
Title
Size
Date:
PORT
PCI2_TME
R76
Routing the trace at least 10mil
CLK_XTAL_OUT
22P_0402_50V8J
PCI4_SEL
ITP_EN
CLK_SMBCLK
7/21 Change WWAN_CLKREQ# from REQ4 to REQ11
SLG8SP556VTR_QFN72_10X10
10K_0402_5%
Y1
14.31818MHZ_16PF_DSX840GA
SRC_10
SRC_10#
+3VS
CLK_XTAL_IN
C109
ITP_EN
2N7002DW-T/R7_SOT363-6
SRC_9
22P_0402_50V8J
64
63
SRC_9#
2 R73
CLK_PCI_DDR_R 13
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
PCI_2
7/22 Add R242 to R253 for Intel request
C108
XTAL_OUT
PCI_1
For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96#

Pin28/29 : LCDCLK / LCDCLK#
1 = Pin24/25 : SRC_0 / SRC_0#
Pin28/29 : 27M/27M_SS
For PCI2_TME:0=Overclocking of CPU and SRC allowed
(ICS only)
1=Overclocking of CPU and SRC NOT allowed
0_0402_5%
XTAL_IN
61
60
14
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
@ R245
SRC_7
SRC_7#
PCI2_TME
1
2
C326 22P_0402_50V8J
33_0402_5% 1
7/13 Add 33pF to GND for RF request
<5>
53
H_STP_PCI#_R
CLK_XTAL_OUT
1
2
C325 22P_0402_50V8J
2 H_STP_PCI#_R
10K_0402_5%
0_0402_5%
FSC
H_STP_CPU#
CLK_XTAL_IN
+3VS
@ R243
R246
10K_0402_5%
2
1
2 @ 0_0402_5%
<13> H_STP_PCI#
CLK_CPU_HPLCLK#
29
CLK_SMBDATA
CKPWRGD/PD#
11
<13> H_STP_CPU#
FSB
R244
1K_0402_5%
2
1
CLK_CPU_HPLCLK <5>
28
1
R249
470_0402_5%
CLK_CPU_BCLK# <5>
LCDCLK/27M
USB_0/FS_A
CLK_CPU_BCLK <5>
LCDCLK#/27M_SS
SRC PORT LIST
CLK_SMBCLK <7,15>
72
20
Q1B
CLK_SMBDATA <7,15>
71
7/22 Add R241 pull up to +3VS for RF Intel request
CLK_SMBDATA
10
12
FSC
VGATE
SCL
VDD_REF
FSB
1
2
C324 22P_0402_50V8J
H_STP_CPU#
2
10K_0402_5%
R241 1
FSA
1
2
C303 22P_0402_50V8J
33_0402_5% 1
2 R65
<13> CLK_PCH_14M
+3VS
22_0402_5% 1
SDA
VDD_SRC
<13> PCH_SMBCLK
7/21 Reserve 22pF to gnd and close to U3 for RF request
R58
+1.5VM_CK505
<13> PCH_SMBDATA
SA000020K00 (Silego : SLG8SP556VTR )
+3VM_CK505
2.2K_0402_5%
Q1A
2N7002DW-T/R7_SOT363-6
C103
10U_0805_10V4Z
8/27 Delete C93, C94, C95, C102 for low power CLK GEN
R57
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
1
Sheet
of
39
LCD POWER CIRCUIT
+LCDVDD
W=40mils
+3VS
+3VS
R79
150_0603_5%
2A
1
47K_0402_5%
R81
0.1U_0402_10V6K
2
2
C110
@
4.7U_0805_10V4Z
Q2B
2N7002DW-T/R7_SOT363-6
C111
S
R80
100K_0402_5%
Q10
AO3413_SOT23
C112
+LCDVDD
0.01U_0402_25V7K
W=40mils
Q2A
+3VS
C114
0.1U_0402_16V4Z
2
1
LVDS_SCL
R84
2.2K_0402_5%
C113
@
4.7U_0805_10V4Z
100K_0402_5%
2N7002DW-T/R7_SOT363-6
R82
R83
2.2K_0402_5%
1
2
<5> GMCH_ENVDD
LVDS_SCL <5>
LVDS_SDA
LED/PANEL BD. Conn.
680P_0402_50V7K
1 C115
68P_0402_50V8J
1 C116
LVDS_SDA <5>
JLVDS
250mA
450mA
B+
+LCDVDD
R85
2 0_0805_5%
R86
2 0_0805_5%
+LEDVDD
(20 MIL)
+3VS
C117
@
680P_0402_50V7K
C118
@
680P_0402_50V7K
For EMI request
<22>
+LCDVDD_L
LCD_PWM
BKOFF#
LVDS_SDA
LVDS_SCL
BKOFF#
<5>
<5>
LVDS_A0
LVDS_A0#
LVDS_A0
LVDS_A0#
<5>
<5>
LVDS_A1
LVDS_A1#
LVDS_A1
LVDS_A1#
<5>
<5>
LVDS_A2
LVDS_A2#
LVDS_A2
LVDS_A2#
LVDS_ACLK
LVDS_ACLK#
<5> LVDS_ACLK
<5> LVDS_ACLK#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND
21
<22> INVT_PWM
<5> GMCH_INVT_PWM
R87
R88
1
1
2
2
@
0_0402_5%
0_0402_5%
LCD_PWM
B
7/2 EVT:Add support DPST function from CPU

8/14 DVT:Add R87 and Det R88 for no support DPST
LVDS_ACLK C331@
LVDS_ACLK#
10P_0402_50V8J
GND
7/21 Reserve Shunt Capacitor for EMI request
22
ACES_87213-2000G
@
Compal Secret Data
2009/10/21
Issued Date
Deciphered Date
2012/10/21
Title
Size
Date:
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
Sheet
1
of
39
CRT CONNECTOR
8/24 Det D1, D2, D3 for ESD request
Place closed to conn.

L1
1
2
NBQ100505T-800Y_0402
L2
1
2
NBQ100505T-800Y_0402
L3
1
2
NBQ100505T-800Y_0402
C120
C121
2.2P_0402_50V8C
C119
2.2P_0402_50V8C
R91
2.2P_0402_50V8C
R90
2
1
150_0402_1%
2
1
150_0402_1%
R89
2
1
150_0402_1%
GMCH_CRT_B
<5> GMCH_CRT_B
C122
CRT_G_L
CRT_B_L
C123
C124
2.2P_0402_50V8C
GMCH_CRT_G
<5> GMCH_CRT_G
CRT_R_L
2.2P_0402_50V8C
<5> GMCH_CRT_R
2.2P_0402_50V8C
GMCH_CRT_R
+CRT_VCC
2
0.1U_0402_16V4Z
SN74AHCT1G125DCKR_SC70-5
P
2
2
10K_0402_5%
U4
CRT_HSYNC_1
R93
2 10_0402_5%
HSYNC
CRT_VSYNC_1
R94
2 10_0402_5%
VSYNC
5
P
2
C127
U5
1
C128
7/10 Add J2 for cost down PolySwitch

9/28 Reserve F1 for cost down PolySwitch
<5> GMCH_CRT_VSYNC
OE#
2
0.1U_0402_16V4Z
1
1
C126
33P_0402_50V8K
+CRT_VCC
33P_0402_50V8K
<5> GMCH_CRT_HSYNC
OE#
R92
1
C125
J2
SN74AHCT1G125DCKR_SC70-5
+5VS
If=1A
+CRT_VCC_R
2
3
+3VS
@
1
+CRT_VCC
JUMP_43X39
F1
30mil
1
2
1.1A_6V_MINISMDC110F-2
1
@
C129
0.1U_0402_16V4Z
2
D4
1
RB491D_SOT23-3
+CRT_VCC
R96
R97
JCRT
R98
4.7K_0402_5%
CRT_R_L
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
+CRT_VCC
+3VS
R95
CRT_DDC_DAT
CRT_G_L
Q4B
4
2
<5> GMCH_CRT_DATA
CRT_DDC_DAT
HSYNC
CRT_B_L
2N7002DW-T/R7_SOT363-6
VSYNC
<5> GMCH_CRT_CLK
Q4A
CRT_DDC_CLK
6
2N7002DW-T/R7_SOT363-6
C130
470P_0402_50V8J
@
CRT_DDC_CLK
C131
470P_0402_50V8J
2 @
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
RGND
ID0
Red
GGND
SDA
Green
BGND
Hsync
Blue
+5V
Vsync
res
SGND
SCL
GND
16
17
GND
GND
SUYIN_070546FR015S263ZR
@
Compal Secret Data
2009/10/21
Issued Date
Deciphered Date
2012/10/21
Title
Size
Date:
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
Sheet
E
10
of
39
+3VS
U6A
PCI_DEVSEL#
CLK_PCI_PCH
PCI_RST#
<8> CLK_PCI_PCH
<22> PCI_RST#
PCI_IRDY#
100K_0402_5%
2
1
+3VS
RP7
1
2
3
4
PCI_PIRQB#
PCI_PIRQF#
PCI_PIRQC#
PCI_PIRQA#
8
7
6
5
8.2K_0804_8P4R_5%
PCI_SERR#
PCI_STOP#
PCI_PLOCK#
PCI_TRDY#
PCI_PERR#
PCI_FRAME#
R101
For EC request.
+3VS
RP8
1
2
3
4
PCI_PIRQE#
PCI_PLOCK#
PCI_PIRQG#
PCI_IRDY#
8
7
6
5
A18
E16
GNT1#
GNT2#
REQ1#
REQ2#
G16
A20
REQ1#
REQ2#
GPIO22
GPIO1
G14
A2
C15
C9
GPIO48/STRAP1#
GPIO17/STRAP2#
GPIO22
GPIO1
B2
D7
B3
H10
E8
D6
H8
F8
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
D11
K9
M13
STRAP0#
RSVD01
RSVD02
PCI
8.2K_0804_8P4R_5%
+3VS
RP9
R103
10K_0402_5%
@
8.2K_0804_8P4R_5%
RP10
1
2
3
4
GPIO22
PCI_DEVSEL#
PCI_PIRQD#
PCI_PIRQH#
8
7
6
5
R104
10K_0402_5%
PCI_PIRQA#
@
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
8.2K_0804_8P4R_5%
RSVD01
RSVD02
+3VS
RP11
REQ2#
REQ1#
PCI_STOP#
PCI_FRAME#
8
7
6
5
C/BE0#
C/BE1#
C/BE2#
C/BE3#
H16
M15
C13
L16
PCI_RST#
D
CLK_PCI_PCH
R102
@ 10_0402_5%
@
C133
8.2P_0402_50V8D
For EMI, close to TigerPoint
R105
1K_0402_5%
+1.05VS
TIGERPOINT_ES1_BGA360
U6C
1
2
3
4
B22
D18
C17
C18
B17
C19
B18
B19
D16
D15
A13
E14
H14
L14
J14
E10
C11
E12
B9
B13
L12
B8
A3
B5
A6
G12
H12
C8
D9
C7
C1
B1
8.2K_0804_8P4R_5%
+3VS
R236
R12
AE20
AD17
AC15
AD18
Y12
AA10
AA12
Y10
AD15
W10
V12
AE21
AE18
AD19
U12
RSVD03
RSVD04
RSVD05
RSVD06
RSVD07
RSVD08
RSVD09
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
AC17
AB13
AC13
AB15
Y14
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
AB16
AE24
AE23
RSVD24
RSVD25
RSVD26
AA14
V14
RSVD27
RSVD28
AD16
AB11
AB10
RSVD29
RSVD30
RSVD31
AD23
GPIO36
TGP
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
AE6
AD6
AC7
AD7
AE8
AD8
AD9
AC9
SATA_CLKN
SATA_CLKP
AD4
AC4
R111
56_0402_5%
SATA_IRX_C_DTX_N0 <17>
SATA_IRX_C_DTX_P0 <17>
SATA_ITX_DRX_N0 <17>
SATA_ITX_DRX_P0 <17>
H_FERR#
R111 closed TigerPoint within 1"
SATA
+3VS
PCI_SERR#
PCI_PERR#
PCI_TRDY#
GPIO1
8
7
6
5
SATARBIAS#
SATARBIAS
SATALED#
CLK_PCIE_SATA# <8>
CLK_PCIE_SATA <8>
AD11 SATARBIAS
AC11
AD25
Please closed Tiger point

PIN within 500 mils
+3VS
R106 24.9_0402_1%
R107
SATALED# <25>
SATALED#
10K_0402_5%
R108
GATEA20
HOST
1
2
3
4
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
RSVD02
PAR
DEVSEL#
PCICLK
PCIRST#
IRDY#
PME#
SERR#
STOP#
PLOCK#
TRDY#
PERR#
FRAME#
C132
0.1U_0402_16V4Z
2 8.2K_0402_5%
A5
B15
J12
A23
B7
C22
B11
F14
A8
A10
D10
A16
R100 1
TGP
RSVD01
8.2K_0402_5%
A20GATE
A20M#
CPUSLP#
IGNNE#
INIT3_3V#
INIT#
INTR
FERR#
NMI
RCIN#
SERIRQ
SMI#
STPCLK#
THRMTRIP#
U16
Y20
Y21
Y18
AD21
AC25
AB24
Y22
T17
AC21
AA16
AA21
V18
AA20
GATEA20
H_A20M#
H_IGNNE#
H_INIT#
H_INTR
H_FERR#
H_NMI
EC_KBRST#
SERIRQ
H_SMI#
H_STPCLK#
GATEA20 <22>
H_A20M# <5>
SERIRQ
10K_0402_5%
R109
2
8.2K_0402_5%
H_IGNNE# <5>
+1.05VS
H_INIT# <5>
H_INTR <5>
H_FERR# <5>
H_NMI
<5>
EC_KBRST# <22>
SERIRQ <22>
H_SMI# <5>
H_STPCLK# <5>
2 8.2K_0402_5%
R110
56_0402_5%
R110 to be within 1" from the Tiger

Point chipset.
R99
H_THERMTRIP# <5>
3
A
A
Compal Secret Data
2009/10/21
Issued Date
Deciphered Date
2012/10/21
Title
Size
Date:
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
Sheet
1
11
of
39
USB PORT LIST
WLAN
WWLAN
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P2
PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
PCIE_ITX_C_PRX_N3
PCIE_ITX_C_PRX_P3
PCIE_PTX_C_IRX_N4
PCIE_PTX_C_IRX_P4
PCIE_ITX_C_PRX_N4
PCIE_ITX_C_PRX_P4
C142 2
C143 2
1 0.1U_0402_10V6K
1 0.1U_0402_10V6K
C144 2
C145 2
1 0.1U_0402_10V6K
1 0.1U_0402_10V6K
C146 2
C147 2
1@ 0.1U_0402_10V6K
1@ 0.1U_0402_10V6K
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P2
PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
PCIE_ITX_PRX_N3
PCIE_ITX_PRX_P3
PCIE_PTX_C_IRX_N4
PCIE_PTX_C_IRX_P4
PCIE_ITX_PRX_N4
PCIE_ITX_PRX_P4
K21
K22
J23
J24
M18
M19
K24
K25
L23
L24
L22
M21
P17
P18
N25
N24
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
H7
H6
H3
H2
J2
J3
K6
K5
K1
K2
L2
L3
M6
M5
N1
N2
OC0#
OC1#
OC2#
OC3#
OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
D4
C5
D3
D2
E5
E6
C2
C3
USBRBIAS
USBRBIAS#
G2
G3
USB
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
PCI-E
LAN
<15>
<15>
<15>
<15>
<20>
<20>
<20>
<20>
<15>
<15>
<15>
<15>
R23
R24
P21
P20
T21
T20
T24
T25
T19
T18
U23
U24
V21
V20
V24
V23
CLK48
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB2(Right)
USB1(Right)
BT
Card Reader
USB3(Left)
WWLAN
WLAN
CMOS
Modify
USB3(Left)
BT
Card Reader
USB2(Right)
USB1(Right)
WWLAN
WLAN
CMOS
USB2(Right)
USB1(Right)
BT
Card Reader
USB3(Left)
WWLAN
WLAN
CMOS
SLP_CHG_M3 <16>
SLP_CHG_M4 <16>
+3V_SB
RP12
USB_OC#3
SLP_CHG_M4
USB_OC#0_1_D
4
3
2
1
10K_0804_8P4R_5%
R112
22.6_0402_1%
CLK_PCH_48M
F4

PIN within 200 mils
5
6
7
8
RP13
USB_OC#7
4
USB_OC#2
3
USB_OC#4_D
2
SLP_CHG_M3
1
10K_0804_8P4R_5%
CLK_PCH_48M <8>
R113
33_0402_5%
@
5
6
7
8
+1.5VS
<8> CLK_PCIE_PCH#
<8> CLK_PCIE_PCH
<16>
<16>
<16>
<16>
<17>
<17>
<21>
<21>
<16>
<16>
<15>
<15>
<15>
<15>
<17>
<17>
DEVICE
7/17 Reassign Tiger point USB port for TOSHIBA concern
USB_OC#0_1_D
USB_OC#0_1_D
USB_OC#2
USB_OC#3
USB_OC#4_D
SLP_CHG_M3
SLP_CHG_M4
USB_OC#7

PIN within 500 mils
R114 24.9_0402_1%
1
2
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
DMI_TXN0
DMI_TXP0
DMI_RXN0
DMI_RXP0
DMI_TXN1
DMI_TXP1
DMI_RXN1
DMI_RXP1
DMI
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
PORT
USB0
USB1
USB2
USB3
USB4
USB5
USB6
USB7
TGP
U6B
H24
J22
DMI_ZCOMP
DMI_IRCOMP
W23
W24
DMI_CLKN
DMI_CLKP
C148
@ 22P_0402_50V8J
2
For EMI, Close to TigerPoint
+3VALW
+3VALW
R115
330K_0402_5%
@
USB_OC#0_1 <16,22>
USB_OC#4_D
CH751H-40PT_SOD323-2
1
R117
@
D6
@
D5
USB_OC#0_1_D 2
R116
330K_0402_5%
@
USB_OC#4 <16,22>
2
0_0402_5%
1
R118
2
0_0402_5%
2009/10/21
Issued Date
Compal Secret Data
2012/10/21
Deciphered Date
Title
SCHEMATICS,MB A5841
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Date:
Rev
D
401799
Sheet

1
12
of
39
+3V_SB
2.2K_0402_5% 1
R119
PCH_SMBCLK
2.2K_0402_5% 1
R120
PCH_SMBDATA
7/2 For EMI, Close to TigerPoint

9/1 C207 change to SE071100J80 for EMI request
HDA_BITCLK
+3V_SB
D
2
C207
10P_0402_50V8J
1
8.2K_0402_5%
10K_0402_5% 2
R122
ICH_RI#
R123 1
EC_SWI#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
<22,24> LPC_FRAME#
R125 2
R126 2
33_0402_5%
1
33_0402_5%
1
R124 2
R127 2
RP15
4 LINKALERT#
3 GPIO11
2 SMLINK0
1 SMLINK1
5
6
7
8
R129
For EMI, Close to TigerPoint
C149
18P_0402_50V8J
2
1
8 GPIO15
7PCH_LOW_BAT#
6 GPIO12
5 EC_LID_OUT#
INTVRMEN
@ 4.7P_0402_50V8C
RTCX2
RTCRST#
<8> PCH_SMBCLK
<8> PCH_SMBDATA
GPIO11
PCH_SMBCLK
PCH_SMBDATA
LINKALERT#
SMLINK0
SMLINK1
2
3MM
T4
P7
B23
AA2
AD1
AC2
W3
T7
U4
LAN_CLK
LANR_RSTSYNC
LAN_RST#
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
W4
V5
T5
RTCX1
RTCX2
RTCRST#
E20
H18
E23
H21
F25
F24
SMBALERT#/GPIO11
SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1
R2
T1
M8
P9
R4
C155
1U_0402_6.3V4Z
1
2
EPROM
CPUPWRGD/GPIO49
SPI_MISO
SPI_MOSI
SPI_CS#
SPI_CLK
SPI_ARB
THRM#
VRMPWRGD
MCH_SYNC#
PWRBTN#
RI#
SUS_STAT#/LPCPD#
SUSCLK
SYS_RESET#
PLTRST#
WAKE#
INTRUDER#
PWROK
RSMRST#
INTVRMEN
SPKR
SLP_S3#
SLP_S4#
SLP_S5#
SPI
INTRUDER#
@ J1
1
C150
EE_CS
EE_DIN
EE_DOUT
EE_SHCLK
SMB
OUT
U3
AE2
T6
V3
RTC
R131 1
20K_0402_5%
+RTCVCC
+RTCVCC
R132
NC
C153
18P_0402_50V8J
2
1
8.2K_0804_8P4R_5%
1M_0402_5% 1
R130
10M_0402_5%
2
1
Y2
32.768K_1TJS125BJ4A421P
2 NC
IN 1
RP16
332K_0402_1%
1 R133
RTCX1
HDA_BIT_CLK
HDA_RST#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDOUT
HDA_SYNC
CLK14
LAN
+3V_SB
@ 10_0402_5%
2
10K_0804_8P4R_5%
1
2
3
4
<18> HDA_SDOUT
<18> HDA_SYNC
<8> CLK_PCH_14M
BITCLK_PCH P6
RST#_PCH U2
W2
V2
P8
SDOUT_PCHAA1
SYNC_PCH Y1
AA3
BMBUSY#/GPIO0
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
DPRSLPVR
STP_PCI#
STP_CPU#
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
CLKRUN#
GPIO33
GPIO34
GPIO38
GPIO39
AUDIO
KC FBMA-11-100505-301T_0402 1
<18> HDA_BITCLK
33_0402_5%
1
<18> HDA_RST#
<18> HDA_SDIN0
LDRQ1#/GPIO23
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LDRQ0#
LFRAME#/FWH4
LPC
<22,24>
<22,24>
<22,24>
<22,24>
9/1 R125 change to SM010027780 for EMI request
+3V_SB
TGP
U6D
AA5
V6
AA6
Y5
W8
Y8
Y4
BATLOW#
DPRSTP#
DPSLP#
RSVD31
8.2K_0402_5%
R256
SLPIOVR
8.2K_0402_5%
R257
PM_CLKRUN#
8.2K_0402_5%
R258
GPIO0
BT_DET# <17>
SLPIOVR <4>
EC_SMI# <22>
EC_SCI# <22>
EC_LID_OUT# <22>
SLP_CHG# <16>
PM_DPRSLPVR <5>
H_STP_PCI# <8>
H_STP_CPU# <8>
1 R128
2
1K_0402_5%
PM_CLKRUN#
C
BT_RST# <17>
BT_OFF
<17>
AB22
H_PWRGD
AB17
V16
AC18
E21
H23
G22
D22
G18
G23
C25
T8
U10
AC3
AD3
J16
EC_THERM#
VGATE
MCH_SYNC#
PBTN_OUT#
ICH_RI#
T43
T44
SYS_RST#
PLTRST#
EC_SWI#
INTRUDER#
PCH_POK
PCH_RSMRST#
INTVRMEN
SB_SPKR
PLTRST#
H_PWRGD <4,5>
EC_THERM# <22>
R254
100K_0402_5%
PBTN_OUT# <22>
7/20 Add test point

PLTRST# <4,5,15,20,24>
EC_SWI# <22>
8/24 Add R254 pull down for EC request

SB_SPKR <18>
H20
E25
F21
PM_SLP_S3# <22>
PM_SLP_S4# <22>
PM_SLP_S5# <22>
B25
AB23
AA18
F20
PCH_LOW_BAT#
H_DPRSTP#
H_DPSLP#
H_DPRSTP# <5>
H_DPSLP# <5>
+3V_SB
7/20 Add SLPIOVR pull up 8.2k to +3vs
D7
PCH_ACIN
1 R240
+3VS
+RTCBATT
R134
330K_0402_5%
9/23 Change RP17 to R256, R257, R258 for layout request
GPIO0
BT_DET#
SLPIOVR
EC_SMI#
EC_SCI#
PCH_ACIN
GPIO12
EC_LID_OUT#
SLP_CHG#
GPIO15
+3VS
T15
W16
W14
K18
H19
M17
A24
C23
P5
E24
AB20
Y16
AB19
R3
C24
D19
D20
F22
AC19
U14
AC1
AC23
AC24
SYS_RST#
R121 1
MISC
10K_0402_5% 2
PCH_POK
1
R136
2
10K_0402_5%
EC_PWROK
1
R139
2
10K_0402_5%
ACIN
<22,25,28>
@
1
2
R141
0_0402_5%
+3VS
R138 2
PCH_RSMRST#
1
2
R140
10K_0402_5%
1U_0402_6.3V6K
2
Y
3
U7
4
Issued Date
2
1
R143
2.2K_0402_5%
1
2
+3V_SB
R142
4.7K_0402_5%
D9A
BAV99DW-7_SOT363
RSMRST# circuit
2012/10/21
Deciphered Date
Title
SCHEMATICS,MB A5841
Date:
Compal Secret Data

2009/10/21
EC_RSMRST# <22>
PCH_POK <5>
TC7SH08FUF_SSOP5
3
MMBT3906_SOT23-3
D9B
BAV99DW-7_SOT363
<22> EC_PWROK
<8,22,34> VGATE
7/21 Change C156 to 1u for Intel request
C293
0.1U_0402_16V4Z
1 @ 0_0402_5%
1 Q11
C
+CHGRTC
C156
+RTCVCC
2
B
D8
BAS40-04_SOT23-3
7/21 Pull up 4.7K to +RTCBATT for Intel request
2 MCH_SYNC#
R135
1K_0402_5% 1
4.7K_0402_5%
Rev
D
401799
Sheet

1
13
of
39
U6F
TGP
+3VS
TGP
+5VS
U6E
F12
+V5REF_RUN
VCC5REF_SUS
F5
+V5REF_SUS
VCCSATAPLL
Y6
+SATAPLL
VCC5REF
D10
AA8
M9
M20
N22
+VSB
VCCSUS3_3_1
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4
H25
AD13
F10
G10
R10
T9
C160
+5VALW
STAR@
10U_0805_10V4Z
1U_0402_6.3V6K
C168
C158
C159
+1.05VS
0_0603_5%
216mA
R149
+VCC33
1
F18
N4
K7
F1
+3VS
0_0603_5%
R152
+VCCSUS33
92mA
1
2
5
1U_0402_6.3V6K
2
100K_0402_5%
1U_0402_6.3V6K
C175
VCC3_3_1
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
+5VALW
1U_0402_6.3V6K
C174
2N7002DW-T/R7_SOT363-6
1
6
Q3A
SBPWR_EN#
STAR@
<22,26> SBPWR_EN#
Q3B
STAR@
2N7002DW-T/R7_SOT363-6
4
3
1 R150
2
47K_0402_5%
1 R151
2
STAR@
@ 330K_0402_5%
1
2
C176
STAR@
0.1U_0402_25V6
1U_0402_6.3V6K
C173
2
0_0603_5%
+5V_SB
SBPWR_EN# 1
R153
J10
K17
P15
V10
955mA
1
10U_0805_6.3V4Z
1
R148
+VCC1_05 1
1U_0402_6.3V6K
C167
VCC1_05_1
VCC1_05_2
VCC1_05_3
VCC1_05_4
0.1U_0402_10V6K
+1.5VS
R147
C177
1U_0402_6.3V6K
C172
1U_0402_6.3V6K
C180
10mA
C166
2
C165
+V5REF_SUS
C170
POWER
RB751V-40TE17_SOD323-2
10_0402_5%
C
0.1U_0402_10V6K
C171
D11
R146
14mA
0_0603_5%
+RTCVCC
1
0.1U_0402_10V6K
VCC1_5_1
VCC1_5_2
VCC1_5_3
VCC1_5_4
+5V_SB +3V_SB
R144
+VCC1_5 1
0.01U_0402_16V7K
V_CPU_IO
W18
1432mA
10U_0805_10V4Z
F6
1U_0402_6.3V6K
C164
VCCUSBPLL
+DMIPLL
1U_0402_6.3V6K
C163
Y25
C161
VCCDMIPLL
2mA
0.1U_0402_10V6K
C162
AE3
1U_0402_6.3V6K
C179
1U_0402_6.3V6K
VCCRTC
C169
6mA
0.1U_0402_10V6K
+V5REF_RUN
C157
0.1U_0402_10V6K
RB751V-40TE17_SOD323-2
100_0402_5%
0.1U_0402_10V6K
C178
R145
VSS01
VSS02
VSS03
VSS04
VSS05
VSS06
VSS07
VSS08
VSS09
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
+3V_SB
0_0603_5%
A1
A25
B6
B10
B16
B20
B24
E18
F16
G4
G8
H1
H4
H5
K4
K8
K11
K19
K20
L4
M7
M11
N3
N12
N13
N14
N23
P11
P13
P19
R14
R22
T2
T22
V1
V7
V8
V19
V22
V25
W12
W22
Y2
Y24
AB4
AB6
AB7
AB8
AC8
AD2
AD10
AD20
AD24
AE1
AE10
AE25
Place closely pin Y25 within 100mlis.
VSS57
VSS58
VSS59
G24
AE13
F2
RSVD32
AE16
+1.5VS
R154
C181
0_0603_5%
C182
4.7U_0603_6.3V6K
+DMIPLL
0.01U_0402_16V7K
24mA
1
@
Place closely pin Y6 within 100mlis.

+1.5VS
R155
C183
C184
0.1U_0402_10V6K
+SATAPLL
0_0603_5%
10U_0805_10V4Z
45mA
2
A
Compal Secret Data
2009/10/21
Issued Date
Deciphered Date
2012/10/21
Title
SCHEMATICS,MB A5841
Date:
Rev
D
401799
Sheet

1
14
of
39
Mini-Express Card for WLAN/WiMax

+3VALW
1
C185
WLAN@
C186
WLAN@
2
0.01U_0402_25V7K
+1.5VS
120 mil
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
1
C187
WLAN@
2
4.7U_0805_10V4Z
C188
WLAN@
C189
WLAN@
2
0.01U_0402_25V7K
WLAN_BT_DATA
WLAN_BT_CLK
WLAN_CLKREQ#
<8> CLK_PCIE_WLAN#
<8> CLK_PCIE_WLAN
<12> PCIE_PTX_C_IRX_N2
<12> PCIE_PTX_C_IRX_P2
<12> PCIE_ITX_C_PRX_N2
<12> PCIE_ITX_C_PRX_P2
WLAN/ WiFi
+3VALW
R156 1
R157 1
1
<22> EC_TX_P80_DATA
<22> EC_RX_P80_CLK
2
2
0_0402_5%
0_0402_5%
Debug card using
AGND
R159
100K_0402_5%
1
3
5
7
9
11
13
15
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
54
GND
GND
+3VALW
+1.5VS
JWLAN
<17> WLAN_BT_DATA
<17> WLAN_BT_CLK
<8> WLAN_CLKREQ#
C190
WLAN@
2 4.7U_0805_10V4Z
2
2
4
6
8
10
12
14
16
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
WL_OFF#
PLTRST#
WL_OFF# <22>
PLTRST# <4,5,13,20,24>
CLK_SMBCLK <7,8>
CLK_SMBDATA <7,8>
USB20_N6 <12>
USB20_P6 <12>
LED_WIMAX#
LED_WIMAX# <25>
WiMax
R158
100K_0402_5%
1
2
+3VS
P-TWO_A54402-A0G16-N
@
9/29 Change JWLAN PIN 54 to AGND

10/6 From JGPS change to JWLAN
Mini-Express Card for 3G/GPS

3G current need to 2750mA
+3VS
1
C191
3GGPS@
+1.5VS
120 mil
0.1U_0402_16V4Z
1
C192
3GGPS@
0.1U_0402_16V4Z
1
C194
3GGPS@
C195
3GGPS@
2
2
0.01U_0402_25V7K
C196
3GGPS@
2
4.7U_0805_10V4Z
+UIM_PWR
2
0.01U_0402_25V7K
C193
3GGPS@
2 4.7U_0805_10V4Z
2
+3VS
+3VS
4
1
C199
10P_0402_50V8J
2 3G@
D13
DAN217_SC59
@
NC
4
5
6
NC
MOLEX_47273-0001
@
D14
D15
DAN217_SC59
DAN217_SC59
@
@
UIM_VPP
UIM_DATA
1
C200
22P_0402_50V8J
2 @
+UIM_PWR
P-TWO_A54402-A0G16-N
@
UWB_OFF#
PLTRST#
UWB_OFF# <22>
CLK_SMBCLK
CLK_SMBDATA
CLK_PCIE_WWAN# C334@ 1
CLK_PCIE_WWAN
10P_0402_50V8J
USB20_N5 <12>
USB20_P5 <12>
7/16 Reserve C333 and C334 for EMI request
LED_WIMAX#
7/21 Reserve Shunt Capacitor C334 for EMI request
Compal Secret Data
2009/10/21
Issued Date
Deciphered Date
2012/10/21
Title
Size
Date:
GND
VPP
I/O
VCC
RST
CLK
C198
10P_0402_50V8J
3G@ 2
1
2
3
1
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
+UIM_PWR
GND
GND
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP
C197
0.1U_0402_16V4Z
2
3G@
53
54
2
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
D12
GLZ20A LL-34
3G@
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
UIM_RST
UIM_CLK
WWAN_CLKREQ#
1
3
5
7
9
11
13
15
+UIM_PWR
+UIM_PWR
<8> WWAN_CLKREQ#
<8> CLK_PCIE_WWAN#
<8> CLK_PCIE_WWAN
1
3
5
7
9
11
13
15
J3GSIM
+1.5VS
JGPS
120 mil
R160
4.7K_0402_5%
@
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
Sheet

E
15
of
39
USB CONN--Right
+USB_VCCA
JPIO
D
1.4A
+5VALW
W=60mils
U12
<22>
1
2
3
4
USB_EN#
USB_EN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
+USB_VCCA
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
RT9715BGS_SO8
C201
@
4.7U_0805_10V4Z
<12>
<12>
USB20_N1
USB20_P1
<12>
<12>
USB20_N0
USB20_P0
<18>
<18>
HP_R
HP_L
AGND
MIC1_L
MIC1_R
<19> MIC1_L
<19> MIC1_R
<18> NBA_PLUG
<18> MIC_SENSE
USB_OC#0_1 <12,22>
8/24 Change U12 to SA00002XX00 for discharge +USB_VCCA
AGND
7/8 Pin swap for AGND
D23
USB20_N1
USB20_P0
I/O4
REF1 REF2
I/O2
I/O1
I/O3
USB20_P1
ACES_85201-20051
9/3 Add PIN 21, PIN 22 for GND pad

+5VALW
9/3 Change JPIO PIN 22 to AGND
USB20_N0
@
7/8 ESD diode change location from Sub board to M/B

9/28 D36 for ESD request
+USB_VCCB
USB Board--Left
W=30mils
+USB_VCCB
+3VALW
0.1U_0402_16V4Z
please close to SB under 30mm

+USB_VCCB
R162
43K_0402_1%
<12> USB20_P4
R161
75K_0402_1%
USB20_P4_S_O
USB20_N4_S_O
R163
51K_0402_1%
C203
0.1U_0402_16V4Z
USB20_P4_S
1D+
VCC
USB20_N4_S
1D-
USB20_P4
2D+
D+
USB20_P4_R
USB20_N4
2D-
D-
USB20_N4_R
OE#
USB_CHG_EN#
<12> USB20_N4
U9
+USB_VCCB
R164
51K_0402_1%
GND
10
C202
150U_B_6.3VM_R40M
C204
C205
SLP_CHG# <13>
2
1000P_0402_50V7K
JUSBC
USB20_N4_R_S
USB20_P4_R_S
7/27 Swap USB20_P4_R_S and USB20_N4_R_S
TS3USB221RSER_QFN10_2X1P5
8/21 USB_CHG_EN# has to be connected to OE# pin for SPEC REV 0.5
D16
SLP_CHG
FUNCTION
U10
<12> SLP_CHG_M3
<12> SLP_CHG_M4
USB20_P4_S
USB20_N4_S
1
4
10
13
1OE#
2OE#
3OE#
4OE#
2
5
9
12
1A
2A
3A
4A
14
+USB_VCCB
1B
2B
3B
4B
GND
USB20_P4_S_O
3
USB20_N4_S_O
6
2 100_0402_5%
8 R165 1
11
LOW
D=1D
HIGH
D=2D
7
1
2
3
4
C206
0.1U_0402_16V4Z
<22> USB_CHG_EN#
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
I/O1
I/O4
REF1 REF2
I/O2
I/O3
Mode 3
HIGH
LOW
W=30mils
8
7
6
5
1
R166
Mode 4
LOW
HIGH
USB20_P4_R_S
USB20_N4_R
USB20_N4_R_S
USB_OC#4 <12,22>
1
R167
2009/10/21
10/20 Delete L4 for EMI request
Deciphered Date
2012/10/21
Title
Size
4
2
0_0402_5%
7/2 For EMI request and change to SM070001310
Date:
2
0_0402_5%
USB20_P4_R
Compal Secret Data
Issued Date
8/19 Change JUSBC to DC233004W00 for ME request
+USB_VCCB
7/17 Change U11 to SA00002XX00 for discharge +USB_VCCB
SLP_CHG_M4
GND1
GND2
GND3
GND4
+5VALW
USB20_N4_R_S
7/16 USB_OC#0 dis-connect to +USB_VCCB
SLP_CHG_M3
5
6
7
8
SUYIN_020173MR004S50DZL
RT9715BGS_SO8
VCC
DD+
GND
@
1.4A
U11
+5VALW
SN74CBT3125PWRG4_TSSOP14
VCC
USB20_P4_R_S
1
2
3
4
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
Sheet
1
16
of
39
SATA Conn.
For 1.8" SSD
1.2A
1
1
+3VS
Place closely JHDD SATA CONN.

1
C208
10U_0805_10V4Z
C209
0.1U_0402_16V4Z
C210
0.1U_0402_16V4Z
C211
0.1U_0402_16V4Z
+3VALW
SSD HDD need 400mA for 3V(PHISON)
C212
@
10U_0805_10V4Z
C213
@
0.1U_0402_16V4Z
C214
@
0.1U_0402_16V4Z
U22
APX9132ATI-TRL_SOT23-3
C215
@
0.1U_0402_16V4Z
JSATA
26
25
boss
boss
24
23
GND
GND
GND
RX+
RXGND
TXTX+
GND
1
2
3
4
5
6
7
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Rsv
GND
12V
12V
12V
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2
SATA_ITX_C_DRX_P0 C218 1
SATA_ITX_C_DRX_N0 C219 1
2
2
0.01U_0402_25V7K
0.01U_0402_25V7K
SATA_IRX_DTX_N0
SATA_IRX_DTX_P0
2
2
0.01U_0402_25V7K
0.01U_0402_25V7K
C220 1
C221 1
VDD
VOUT
C333
0.1U_0402_16V4Z
<22>
1
C332
10P_0402_50V8J
SATA_IRX_C_DTX_N0 <11>
SATA_IRX_C_DTX_P0 <11>
8/19 Add Lid switch function on M/B for ME request

+3VS
+5VS
Camera Conn.
2
Int. Camera
7/21 Swap USB20_P7, USB20_N7 for layout request
W=20mils
8/24 Change JSATA for ME request
8/14 Swap USB20_P7, USB20_N7 for layout request

10/20 Delete L5 for EMI request
1
2
C222
0.1U_0402_16V4Z
+5VS
1
R168
2
0_0402_5%
JCAM
BlueTooth Interface
1
2
3
4
5
GND1
GND2
+3VS
+3VS
1
2
3
4
5
6
7
USB20_N7_R
USB20_P7_R
USB20_N7 <12>
USB20_P7 <12>
1
R169
2
0_0402_5%
ACES_88266-05001
@
C224
For EMI request
0.1U_0402_10V6K
2
G
BT_OFF
47K_0402_5%
2
1
R171
C223
2
1
S
R170
100K_0402_5%
<13>
LID_SW#
SATA_ITX_DRX_P0 <11>
SATA_ITX_DRX_N0 <11>
ALLTO_C16674-12204-L
GND
+5VS
Q12
AO3413_SOT23
0.01U_0402_25V7K
+BT_VCC
Bluetooth Connector
JBT
BT_RST#
1
R173
2 BT_RESET#
100K_0402_5%
1
R172
2
0_0402_5%
<15> WLAN_BT_DATA
1
2
R174 @
4.7K_0402_5%
+3VS
+BT_VCC
C225
0.1U_0402_16V4Z
1 (MAX=200mA)
R175
C227
0.1U_0402_16V4Z
4.7K_0402_5%
C226
4.7U_0805_10V4Z
4
WLAN_BT_CLK
C228@
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
11
12
GND1
GND2
<13>
USB20_P2
USB20_N2
<12> USB20_P2
<12> USB20_N2
<15> WLAN_BT_CLK
<13>
BT_DET#
ACES_87213-1000G
@
Issued Date
Compal Secret Data
2 10P_0402_50V8J
2009/10/21
Deciphered Date
2012/10/21
Title
SCHEMATICS,MB A5841
Custom
Rev
D
401799
Date:

G
Sheet
17
of
H
39
HD Audio Codec
+3VS_DVDD
1
RA2
2
1
0_0603_5%
CA3
0.1U_0402_16V4Z
1
1
CA6
1
2
1
DVDD
+5VS
14
LINE2-L
LOUT1_L
35
AMP_SPK_L <19>
15
LINE2-R
LOUT1_R
36
AMP_SPK_R <19>
16
MIC2_L
LOUT2_L
39
17
MIC2_R
LOUT2_R
41
23
LINE1_L
SPDIFO1
48
24
LINE1_R
SPDIFO2
45
21
MIC1_L
HPOUT_L
33
HP_L_R
22
MIC1_R
HPOUT_R
32
HP_R_R
12
BEEP_IN
MONO_OUT
37
8/14 Add net name to HP_L_R and HP_R_R for layout request
MONO_IN
2
0.1U_0402_16V4Z
<13> HDA_SDOUT
1 HDA_SDIN0_R
33_0402_5%
BITCLK
DMIC_CLK1/2
46
SDATA_OUT
DMIC_CLK3/4
44
LINE2_VREFO
20
RESET#
LINE1_VREFO
18
<13> HDA_SYNC
10
SYNC
MIC1_VREFO
28
MIC2_VREFO
19
CPVEE
31
CPVEE 1
VREF
27
AC_VREF
JDREF
40
AC_JDREF
CBN
30
CBP
29
AVSS1
AVSS2
26
42
8/14 Add R235
SENSE_A
8/24 Change R235 to RA21
SENSE_B
1
RA21
EAPD
2
0_0402_5%
GPIO0/DMIC_DATA1/2
GPIO1/DMIC_DATA3/4
13
34
SENSE B
47
EAPD
43
CA33
2
22P_0402_50V8J
@
1
4
7
RA31
2
HDA_BITCLK
SENSE A
10mil
10mil
1
CA15
RA7
2
CA13
1 RA10
2
20K_0402_1%
2
2.2U_0603_6.3V6K
1
RA11
RA9
2.2U_0603_6.3V6K
CA16
GND
VOUT
SHDN#
BP
2
CA11 @
2
1
4.75V
CA10
@
1U_0402_6.3V4Z
Beep sound
EC Beep
0_0603_5%
<22>
0_0603_5%
PCI Beep
CA17
BEEP#
<13>
SB_SPKR
0_0603_5%
DGND
RA6
1
2
47K_0402_5%
CA14
1
2
RA8
1
2
47K_0402_5%
AGND
AGND
@ RA32
HDA_RST#
0.01U_0402_16V7K
MONO_IN
0.1U_0402_16V4Z
RA12
10K_0402_5%
@ CA34
1
2
DGND
VIN
HP out
+MIC2_VREFO
ALC272-GR_LQFP48_7X7
22_0402_5%
<16>
+MIC1_VREFO
NC
DVSS
DVSS
<16>
HP_R
1
2
30mil
Layout need to open channel
SDATA_IN
7/8 For EMI request and closed UA1
HP_L
10/5 Add RA7 and RA11 for ESD request
11
2
RA5
2
63.4_0402_1%
2
63.4_0402_1%
8/14 Add net name to CPVEE for layout request
<13> HDA_RST#
<13> HDA_SDIN0
1
RA3
1
RA4
+5VS
CA18
0.1U_0402_16V4Z
MIC1_C_R
0.22U_0402_10V4Z
@
APL5151-475BC-TRL_SOT23-5
MIC2_R
<13> HDA_BITCLK
@
1
SPK out
MIC2_L
1
CA12
<22>
CA9
@
1U_0402_6.3V4Z
+VDDA
UA2
<19>
Ext. Mic <19>
@ PJ19
JUMP_43X79
(output= 300mA)
CA8
<19>
<19> MIC1_C_L
0.1U_0402_16V4Z
Int. Mic
10U_0805_10V4Z
1
2
0.1U_0402_16V4Z
DVDD_IO
38
25
AVDD1
UA1
CA7
AVDD2
2
2
2
10U_0805_10V4Z
0.1U_0402_16V4Z
+3VS
CA2
2
0.1U_0402_16V4Z
Audio regulator
RA1
2
1
0_0603_5%
10U_0805_10V4Z
+VDDA
10U_0805_10V4Z
1
1
CA4
CA5
CA1
+AVDD
40mil
30mil
10U_0805_10V4Z
1
+3VS
4.7K_0402_5%
7/2 For EMI request and closed UA1

7/2 For ESD request and closed UA1
Sense Pin
SENSE A
SENSE B
Impedance
Codec Signals
39.2K
PORT-A (PIN 39, 41)
20K
PORT-B (PIN 21, 22)
10K
PORT-C (PIN 23, 24)
5.1K
PORT-D (PIN 35, 36)
39.2K
PORT-E (PIN 14, 15)
20K
PORT-F (PIN 16, 17)
10K
PORT-H (PIN 37)
5.1K
PORT-I (PIN 32, 33)
place close to chip
Function
<16> MIC_SENSE
1
RA13
<16>
1
RA14
SENSE_A
2
20K_0402_1%
Ext. MIC
NBA_PLUG
SPK out
1
RA15
2
5.1K_0402_1%
SENSE_B
2
20K_0402_1%
4
Int. MIC
Headphone out
Compal Secret Data
2009/10/21
Issued Date
Deciphered Date
2012/10/21
Title
SCHEMATICS,MB A5841
Custom
Date:
Rev
D
401799
Sheet
E
18
of
39
TPA6017 Medium Range Amplifier

+5VS
0.1U_0402_16V4Z
Rin =70Kohm
1
CA21
10U_0805_10V4Z
RA34
1
CA22
CA23
10 dB
+5VS
0.1U_0402_16V4Z
CA28
1
2
<18> AMP_SPK_R
RA35
LINE_R_OUTR-
0.033U_0402_16V7K
CA31
1
2
LINE_OUTR-
2K_0402_5%
LINE_C_OUTR-
17
LINE_OUTL+
2K_0402_5%
CA38
1
2
LINE_C_OUTL+
5
2
GAIN0
GAIN1
ROUT+
18
SPKR+
ROUT-
14
SPKR-
LOUT+
SPKL+
LOUT-
SPKL-
RIN-
RA29
100K_0402_5%
RA30
100K_0402_5%
@
LIN+
1U_0402_6.3V6K
RA39
RIN+
1U_0402_6.3V6K
RA38
LINE_R_OUTL+
0.033U_0402_16V7K
CA36
1
2
8.2K_0402_5%
RA22
100K_0402_5%
RA36
RA26
100K_0402_5%
@
UA3
1U_0402_6.3V6K
2K_0402_5%
CA35
1
2 LINE_C_OUTR+
LINE_OUTR+
0.033U_0402_16V7K
16
15
6
RA33
LINE_R_OUTR+
VDD
PVDD1
PVDD2
CA24
1
2
8.2K_0402_5%
LIN-
GAIN0 GAIN1 Av(db) Rin(ohm)
8.2K_0402_5%
CA29
1
2
<18> AMP_SPK_L
RA37
LINE_R_OUTL-
0.033U_0402_16V7K
LINE_OUTL-
2K_0402_5%
CA37
1
2
1U_0402_6.3V6K
19
12
BYPASS
10
Keep 10 mil width

AMP_BYPASS
SHUTDOWN
GND5
GND1
GND2
GND3
GND4
RA40
NC
LINE_C_OUTL-
21
20
13
11
1
8.2K_0402_5%
<22> EC_MUTE#
CA32
7/13 Reserve CA25 for RF request

CA25
1
@
90K
10
70K
0 15.6
45K
1 21.6
25K
0.47U_0603_10V7K 0.1U_0402_16V4Z
1
2
TPA6017A2_TSSOP20
Use mono SPK

setting 68Hz
Ext. Mic
F=1/2RC --> -3db

C=0.033U,R=70K,F=68Hz
<18> MIC1_C_L
7/21 Add RA33~RA40, CA35~CA38 for AMP gain
<18> MIC1_C_R
4.7U_0805_10V4Z
CA19
2
1
4.7U_0805_10V4Z
CA20
2
1
1K_0402_5%
RA18
CA26
2
1
RA23
1K_0402_5%
2
1
MIC2_L
<18>
MIC2_R
1U_0402_6.3V4Z
1U_0402_6.3V4Z
JSPKR
SPK_R1
SPK_R2
1
2
1 NC1
2 NC2
1
CA30
2
1
1K_0402_5%
RA28
1
2
1
2
3
4
GND
GND
ACES_88231-02001
@
DA3
@
PESD5V0U2BT_SOT23-3
2
7/3 Change to SCA00000T00 for ESD request

JSPKL
SPK_L1
SPK_L2
1
2
1 NC1
2 NC2
3
4
ACES_85204-0200N
@
Compal Secret Data
2009/10/21
Issued Date
Deciphered Date
2012/10/21
Title
SCHEMATICS,MB A5841
Custom
10/27 Delete DA4 and DA5 for ESD request
Date:
+MIC2_VREFO
3
2 0_0603_5%
2 0_0603_5%
JMIC
INT_MIC
2
CA27
220P_0402_50V7K
3
4
1
LA4 1
LA3 1
MIC1_R <16>
+MIC1_VREFO
PESD5V0U2BT_SOT23-3
Left Speaker Connector
SPKL+
SPKL-
1
RA20
ACES_85204-0200N
@
DA5
<18>
2 0_0603_5%
2 0_0603_5%
MIC1_L <16>
RA19 1
2
1
2
4.7K_0402_5% DA2
3
LA1 1
LA2 1
+MIC1_VREFO
MIC1_R
2
4.7K_0402_5%
@
PESD5V0U2BT_SOT23-3
2
1
SPKR+
SPKR-
2 RA16
1
1
2
4.7K_0402_5% DA1
MIC1_L
Int. Mic
Right Speaker Connector

DA4
RA17
1K_0402_5%
2
1
Rev
D
401799
Sheet
E
19
of
39
+LAN_VDD12
Close to Pin10,13,30,36
2
Place Close to Chip
UL1
CL5
2 0.1U_0402_10V6K
PCIE_PTX_IRX_P3
20
HSOP
CL6
2 0.1U_0402_10V6K
PCIE_PTX_IRX_N3
21
HSON
15
HSIP
16
HSIN
<8> CLK_PCIE_LAN
<8> CLK_PCIE_LAN#
17
18
REFCLK_P
REFCLK_M
25
CLKREQB
27
PERSTB
<8> LAN_CLKREQ#
<4,5,13,15,24> PLTRST#
RL3
2 2.49K_0402_1%
<22> LOM_WAKE#
+3V_LAN
RL4
ISOLATEB
<22> ISOLATEB
1
100K_0402_5%
LAN_X1
LAN_X2
LED3/EEDO
LED2/EEDI/AUX
LED1/EESK
EECS
RTL8103EL-GR
46
RSET
26
28
LANWAKEB
ISOLATEB
41
42
LED0
38
MDIP0
MDIN0
MDIP1
MDIN1
NC
NC
NC
NC
2
3
5
6
8
9
11
12
NC
CKXTAL1
CKXTAL2
8/24 Connect ISOLATEB to EC
1
2
RL5
1K_0402_5%
ISOLATEB
NC
NC
7
14
31
47
GND
GND
GND
GND
22
GNDTX
RL6
15K_0402_5%
LAN_DO
LAN_DI
1
RL1
1
RL2
LAN_CS
PAD
T42
2
3.6K_0402_5%
2
1K_0402_5%
48
VDDTX
DVDD12
DVDD12
DVDD12
DVDD12
19
30
36
13
10
NC
39
NC
VCTRL12D
44
45
VDD33
VDD33
29
37
AVDD33
NC
NC
1
40
43
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Close to Pin1,37,29
CL7
0.1U_0402_16V4Z
CL8
0.1U_0402_16V4Z
CL9
0.1U_0402_16V4Z
CL10
0.1U_0402_16V4Z
VCTRL12
+EVDD12
+LAN_VDD12
3
Close to Pin 45
Close to Pin19
+LAN_VDD12
+EVDD12
+LAN_VDD12
+3V_LAN
CL11
10U_0805_10V4Z
CL12
0.1U_0402_16V4Z
CL13
1U_0402_6.3V4Z
CL14
1U_0402_6.3V4Z
LAN Conn.
7/17 Change JLAN for don't support LAN LED fuction

7/23 Change JLAN for ME request
8/24 Change JLAN for Deep connecter
CL15
JLAN
27P_0402_50V8J
Place CL20,CL21 closed to UL3
UL2
LAN_MDI0+
LAN_MDI0-
LAN_MDI1+
LAN_MDI1-
1
2
3
4
5
6
7
8
TD+
TDCT
NC
NC
CT
RD+
RD-
TX+
TXCT
NC
NC
CT
RX+
RX-
RJ45_MIDI0+
RJ45_MIDI0-
16
15
14
13
12
11
10
9
PR4-
PR4+
PR2-
PR3-
PR3+
RJ45_MIDI1+
PR2+
RJ45_MIDI0-
PR1-
RJ45_MIDI0+
PR1+
RJ45_MIDI1-
0.01U_0402_16V7K
CL4
+3V_LAN
LAN_X2
27P_0402_50V8J
2
CL17
CL22
0.1U_0402_16V4Z
VCTRL12
YL1
0.01U_0402_16V7K
2
CL3
RTL8103EL-VB-GR_LQFP48_7X7
LAN_X1 2
CL18
1
0.1U_0402_16V4Z
Close to Pin48
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-
25MHz_20pF_6X25000017
CL2
+3V_LAN
VCTRL12A
+3VS
23
24
33
34
35
32
CL1
RL10
CL19 1
1
CL20
RJ45_MIDI1+
RJ45_MIDI1-
2 75_0402_1%
2
75_0402_1%
2 1000P_0402_50V7K 1
2
1
1000P_0402_50V7K
RJ45_GND
SHLD1
SHLD2
10
RL12
SANTA_130452-C
8456E
RJ45_GND
1
CL23
LANGND
2 1000P_1808_3KV7K
1
CL24
0.1U_0402_16V4Z
2009/10/21
Issued Date
Deciphered Date
4.7U_0603_6.3V6K
Compal Secret Data
CL25
2012/10/21
Title
SCHEMATICS,MB A5841
Custom
Date:
Rev
D
401799
Sheet
E
20
of
39
+3VS_CR
RC1
+3VS
+3VALW
0_0603_5%
2
1
@
RC2
2
0_0603_5%
confirm that whether can be removed
CC1
0.1U_0402_16V4Z
RC3
2
CC2
1
0_0402_5%
1
D
0.1U_0402_16V4Z
2
UC1
+3VS_CR
2
CC3
2
RC4
100K_0402_5%
0.1U_0402_16V4Z
1
1
3
7
9
11
33
AV_PLL
NC
NC
CARD_3V3
D3V3
D3V3
CLK_48M_CR
8
44
45
47
48
3V3_IN
RST#
MODE_SEL
XTLO
XTLI
CR_LED#
4
5
14
DM
DP
GPIO0
+VCC_3IN1
VREG
MS_D4
NC
10
22
30
XD_CLE_SP19
XD_CE#_SP18
XD_ALE_SP17
SD_DAT2/XD_RE#_SP16
SD_DAT3/XD_WE#_SP15
XD_RDY_SP14
SD_DAT4/XD_WP#/MS_D7_SP13
SD_DAT5/XD_D0/MS_D6_SP12
SD_CLK/XD_D1/MS_CLK_SP11
MS_INS#_SP9
XD_D5_SP5
XD_D4/SD_DAT1_SP4
SD_CD#_SP3
SD_WP_SP2
XD_CD#_SP1
EEDI
43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18
XTAL_CTR
MS_D5
13
24
EEDO
EECS
EESK
SD_CMD
15
16
17
36
+3VS_CR
RST#
1
RC5
2
0_0402_5%
RST#_R
1
+3VS_CR
CC5
RST#_R
MODE SEL
4.7U_0603_6.3V6K
CC6
1U_0402_6.3V4Z
<12>
<12>
USB20_N3
USB20_P3
48Mhz
MODE SEL
CLK_48M_CR
RC8
0_0402_5%
@
10_0402_5%
1
2
10P_0402_50V8J
RC7
CC7
CC8
0.1U_0402_16V4Z
@
CLK_48M_CR
<8> CLK_48M_CR
RC11
6.19K_0402_1%
+3VS
RREF
12
32
DGND
DGND
6
46
AGND
AGND
CC4
1U_0402_6.3V4Z
SD_DATA2
SD_DATA3
SD_MS_CLK
RC6
SDCLK
2 33_0402_5%
SD_MS_DATA0
C
SD_DATA1
SDCD#
SDWP#
8/24 Det RC9

+3VS_CR
XTAL_CTR
SDCMD
Description
Use 12MHz Crystal
Use 48MHz CLK Gen
0
1
RTS5159-GR_LQFP48_7X7
RC12
0_0402_5%
2 in 1 Card Reader
RC10
220_0402_5%
JCARD
SD_DATA3
SDCMD
DC1
HT-191UYG-DT YEL/GRN_0603
+VCC_3IN1
1U_0402_6.3V4Z
1
CR_LED#
7/23 Change to TOP view LED
USB AUTO DE-LINK MS FORMATTER
NC
YES
NC
47P
YES
NC
NC
NC
680P
1
2
3
4
5
6
SDCLK
1
CC9
0.1U_0402_16V4Z
SD_MS_DATA0
SD_DATA1
SD_DATA2
SDWP#
SDCD#
CC10
Description
D3
CMD
VSS1
VDD
CLK
VSS2
7
8
9
10
11
D0
D1
D2
WP
CD
12
13
14
15
GND1
GND2
GND3
GND4
Recommended
TAITW_PSDAT3-09GLAS1N14N
YES
Compatible with RTS5158E
YES
8/19 Change push pull Conn for ME request
LED ON
10_0402_5%
1
2
SDCLK
10K 180P
LED ON
10P_0402_50V8J
@ RC14
@ CC11
10K 680P
YES
2009/10/21
Issued Date
Compal Secret Data
2012/10/21
Deciphered Date
Title
SCHEMATICS,MB A5841
Date:
Rev
D
401799
Sheet

1
21
of
39
+3VALW
+3VALW
2
C237
1
0.1U_0402_16V4Z
KSO[0..15]
KSI[0..7]
<24>
KSI[0..7]
confirm battery team change +5VALW to +3VALW

RP18
+3VALW
+5VS
1
2
3
4
8
7
6
5
EC_SMB_CK1
EC_SMB_DA1
TP_CLK
TP_DATA
4.7K_0804_8P4R_5%
0.1U_0402_16V4Z
2.2K_0402_5%
2.2K_0402_5%
For EC recommend 10/17
<29>
<29>
<5,23>
<5,23>
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
BATT_TEMPA
1
C239
2
100P_0402_50V8J
ACIN_D
2
100P_0402_50V8J
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
12
13
37
20
38
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
77
78
79
80
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
HDPINT
INVT_PWM
FAN_SPEED1
USB_CHG_EN#
EC_TX_P80_DATA
EC_RX_P80_CLK
ON/OFFBTN#
PWR_SUSP_LED#
NUM_LED#
68
70
71
72
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
83
84
85
86
87
88
EC_MUTE#
USB_EN#
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
97
98
99
109
VGATE
WOL_EN#
SBPWR_EN#
LID_SW#
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
119
120
126
128
EC_SI_SPI_SO
EC_SO_SPI_SI
EC_SPICLK_R
SPI_CS#
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
73
74
89
90
91
92
93
95
121
127
USB_OC#0_1
USB_OC#4
FSTCHG
BATT_FULL_LED#
CAPS_LED#
BATT_CHG_LOW_LED#
PWR_ON_LED#
SYSON
VR_ON
ACIN_D
100
101
102
103
104
105
106
107
108
EC_RSMRST#
EC_LID_OUT#
EC_ON
EC_SWI#
EC_PWROK
BKOFF#
WL_OFF#
UWB_OFF#
ARROW_LED#
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
110
112
114
115
116
117
118
PM_SLP_S4#
ENBKL
EAPD
EC_THERM#
SUSP#
PBTN_OUT#
LOM_WAKE#
V18R
124
+EC_V18R
SPI Flash ROM
GPIO
SM Bus
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
GPI
2CRY2
KB926QFC0_LQFP128
@ 20M_0402_5%
AGND
XCLK1
XCLK0
R184
CRY1
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
BEEP#
<18>
ACOFF
<30>
C236
@ 22P_0402_50V8J
BATT_TEMPA <29>
ADP_I
ADP_V
ADP_I
ADP_V
HDPACT
<30>
<30>
HDPACT <23>
Place closely pin 109
R178
EN_DFAN1
IREF
CHGVADJ
+3VALW
EN_DFAN1 <24>
IREF
<30>
CHGVADJ <30>
LID_SW#
47K_0402_5%
EC_MUTE# <19>
USB_EN# <16>
TP_CLK
TP_DATA
TP_CLK <25>
TP_DATA <25>
VGATE
<8,13,34>
WOL_EN# <26>
SBPWR_EN# <14,26>
LID_SW# <17>
+3VALW
1
330K_0402_5%
2
R179
D17
EC_SI_SPI_SO <24>
EC_SO_SPI_SI <24>
ACIN_D
ACIN
<13,25,28>
SPI_CS# <24>
Add D21 for AC-IN leakage issue

USB_OC#0_1 <12,16>
USB_OC#4 <12,16>
FSTCHG <30>
BATT_FULL_LED# <25>
CAPS_LED# <24>
BATT_CHG_LOW_LED# <25>
PWR_ON_LED# <25>
SYSON
<26,32>
VR_ON
<34>
EC_RSMRST# <13>
EC_LID_OUT# <13>
EC_ON
<25>
EC_SWI# <13>
EC_PWROK <13>
BKOFF# <9>
WL_OFF# <15>
UWB_OFF# <15>
ARROW_LED# <25>
L6
EC_SPICLK_R
1
2
KC FBMA-11-100505-900T 0402
EC_SPICLK <24>
C323
6P_0402_50V8D
Add R235 and C323 for EMI and closed U13.126

7/6 Change R235 to L6 for EMI request
PM_SLP_S4# <13>
ENBKL
<5>
EAPD
<18>
EC_THERM# <13>
SUSP#
<26,30,32,33>
PBTN_OUT# <13>
LOM_WAKE# <20>
20mil
C241
4.7U_0603_6.3V6K
69
2
47K_0402_5%
2
47K_0402_5%
BATT_TEMPA
SPI Device Interface
GND
GND
GND
GND
GND
KSO2
1
R182
1
R183
ACOFF
63
64
65
66
75
76
PS2 Interface
11
24
35
94
113
KSO1
122
123
BEEP#
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
7/15 USB_CHG_EN# from PIN 68 change to PIN 29

CRY1
CRY2
21
23
26
27
PWM Output
AD
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
<20> ISOLATEB
+3VALW
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
DA Output
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
<23> HDPINT
<9> INVT_PWM
<24> FAN_SPEED1
<16> USB_CHG_EN#
<15> EC_TX_P80_DATA
<15> EC_RX_P80_CLK
<25> ON/OFFBTN#
<25> PWR_SUSP_LED#
<25> NUM_LED#
R176
@ 10_0402_5%
AVCC
VCC
VCC
VCC
VCC
VCC
VCC
1
2
3
4
5
7
8
10
7/15 INVT_PWM from PIN 21 change to PIN 25

<13> PM_SLP_S3#
<13> PM_SLP_S5#
<13> EC_SMI#
CLK_PCI_LPC
67
9
22
33
96
111
125
+3VS
EC_SMB_CK2
R180
EC_SMB_DA2
R181
1
C240
C235
1
2
ECRST#
KSO[0..15]
<24>
C234
1000P_0402_50V7K
<13>
EC_SCI#
<25> WL_BT_LED#
U13
CLK_PCI_LPC
PCI_RST#
ECRST#
EC_SCI#
WL_BT_LED#
<8> CLK_PCI_LPC
<11> PCI_RST#
R177
47K_0402_5%
2
1
GATEA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
<11>
GATEA20
<11> EC_KBRST#
<11>
SERIRQ
<13,24> LPC_FRAME#
<13,24> LPC_AD3
<13,24> LPC_AD2
<13,24> LPC_AD1
<13,24> LPC_AD0
+3VALW
C233
1000P_0402_50V7K
C232
0.1U_0402_16V4Z
C231
0.1U_0402_16V4Z
C230
0.1U_0402_16V4Z
C229
0.1U_0402_16V4Z
to avoid EC entry ENE test mode
NC
C243
15P_0402_50V8J
IN
OUT
NC
X1
1
1
15P_0402_50V8J
C242
Issued Date
32.768KHZ_12.5PF_1TJS125BJ4A421P
Compal Secret Data
2009/10/21
Deciphered Date
2012/10/21
Title
Custom
SCHEMATICS,MB A5841
Rev
D
401799
Date:
Sheet
22
of
39
G-Sensor
U14
2
12
+3VS_HDP
D
SELF_TEST
Vdd1
Vdd2
4
6
8
ST
PD
FS
+3VS_HDP
Rev
Voutx
Vouty
Voutz
3
5
7
NC1
NC2
NC3
NC4
NC5
10
11
14
15
16
GND1
GND2
1
13
VOUTX C244 1
VOUTY C245 1
VOUTZ C246 1
2 0.033U_0402_16V7K
2 0.033U_0402_16V7K
2 0.033U_0402_16V7K
TSH35TR LGA
+5VS
C249
1U_0402_6.3V4Z
+3VS_HDP
IN
GND
SHDN#
OUT
2
@ C252
2
1
BYP
G9191-330T1U_SOT23-5
+3VS_HDP
U16
U15
D18
1
2
@
C251
1U_0402_6.3V4Z
@ C247
0.1U_0402_16V4Z 2
1VOUTX 2
XOUT
@ C248
0.1U_0402_16V4Z 2
1VOUTY 3
YOUT
@ C250
0.1U_0402_16V4Z 2
1VOUTZ 4
ZOUT
9
7
10
13
+3VS_HDP
0.22U_0402_10V4Z
SELF_TEST
VDD
0G-DET
SLEEP#
G-SELECT
ST
NC
NC
NC
NC
NC
1
8
11
12
14
VSS
MMA7360LR2_LGA14
@
U17
P3_5/SSCK/SCL/CMP1_2
P1_6/CLK0/SSI01
11
SELF_TEST
P3_7/CNTR0#/SSO/TXD1
P1_5/RXD0/CNTR01/INT11#
12
RESET#
P1_4/TXD0
13
XOUT/P4_7
P1_3/KI3#/AN11/TZOUT
14
VSS/AVSS
P1_2/KI2#/AN10/CMP0_2
15
R185 2
1 4.7K_0402_5%
R187 2
1 4.7K_0402_5%
HDPACT
<22>
R186
47K_0402_5%
+3VS_HDP
EC_SMB_CK2
<5,22> EC_SMB_CK2
XOUT
R188 2
1 4.7K_0402_5%
R189 2
<22>
HDPINT
HDPINT
XIN
1 4.7K_0402_5%
R190 2
1 1K_0402_5%
XIN/P4_6
VCC/AVCC
MODE
P4_5/INT0#/RXD1
10
P1_7/CNTR00/INT10#
P4_2/VREF
P1_1/KI1#/AN9/CMP0_1
17
VOUTX
VOUTY
P1_0/KI0#/AN8/CMP0_0
18
P3_3/TCIN/INT3#/SSI00/CMP1_0
19
P3_4/SCS#/SDA/CMP1_1
20
VOUTZ
16
+3VS_HDP
EC_SMB_DA2
C253
0.1U_0402_16V4Z
EC_SMB_DA2 <5,22>
R5F211B4D34SP LSSOP 20
C254
0.1U_0402_16V4Z
C255
0.1U_0402_16V4Z
7/17 From R5F211B4D31SP change to R5F211B4D34SP
Compal Secret Data
Issued Date
2009/10/21
Deciphered Date
2012/10/21
Title
Custom
SCHEMATICS,MB A5841
Rev
D
401799
Date:

1
Sheet
23
of
39
SPI Flash (8Mb*1)
FAN Control Circuit
+3VALW
U28
+5VS
<22> SPI_CS#
C256
+FAN1
<22> EN_DFAN1
EN
VIN
VOUT
VSET
GND
GND
GND
GND
8
7
6
5
APL5607KI-TRG_SO8
D19
1SS355_SOD323-2
+3VALW
JFAN
12
1
2
3
4
U19
+FAN1
D20
1A
C261
@
1000P_0402_25V8J
BAS16_SOT23-3
C262
10U_0805_10V4Z
<22> EC_SI_SPI_SO
CE#
VDD
SO
HOLD#
WP#
SCK
EC_SPICLK
VSS
SI
EC_SO_SPI_SI
2
2
470P_0402_50V8J
10U_0805_10V4Z
8/19 Change JFAN to SP02000JR00 for ME request
C260
1
2
3
1
2
3
4
5
GND
GND
330P_0402_50V7K
R191
C259
0.1U_0402_16V4Z
EC_SPICLK <22>
EC_SO_SPI_SI <22>
MX25L8005M2C-15G_SO8
ACES_85204-0300N
330P_0402_50V7K
1
1
C257
C258
@
@
C263 @
1
2
10K_0402_5%
1
+3VS
R192 @
1
2
33_0402_5%
EC_SPICLK
33P_0402_50V8K
FAN_SPEED1 <22>
8/14 Change U28 from SA00000XT00 to SA00002TO00 for BIOS ROM size
11/12 Change U28 from SA000002T00 to SA0000XTO00 for BIOS ROM size
C264
@
1 0.01U_0402_16V7K
LPC Debug Port
KEYBOARD
CONN.
Please place the connector neer to DDR door
KSI0
C265 1
100P_0402_50V8J
KSI1
C266 1
100P_0402_50V8J
KSI2
C267 1
100P_0402_50V8J
KSI3
C268 1
100P_0402_50V8J
KSI4
C269 1
100P_0402_50V8J
KSI5
C270 1
100P_0402_50V8J
KSI6
C271 1
100P_0402_50V8J
KSI7
C272 1
100P_0402_50V8J
KSO0
C273 1
100P_0402_50V8J
KSO1
C274 1
100P_0402_50V8J
KSO2
C275 1
100P_0402_50V8J
KSO3
C276 1
100P_0402_50V8J
KSO4
C277 1
100P_0402_50V8J
KSO5
C278 1
100P_0402_50V8J
KSO6
C279 1
100P_0402_50V8J
KSO7
C280 1
100P_0402_50V8J
KSO8
C281 1
100P_0402_50V8J
KSO9
C282 1
100P_0402_50V8J
KSO10
C283 1
100P_0402_50V8J
KSO11
C285 1
100P_0402_50V8J
KSO12
C286 1
100P_0402_50V8J
KSO13
C287 1
100P_0402_50V8J
KSO14
C288 1
100P_0402_50V8J
KSO15
C289 1
100P_0402_50V8J
CAPS_LED#
C290 1
100P_0402_50V8J
JLPC
<4,5,13,15,20> PLTRST#
CLK_PCI_DDR
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PLTRST#
KSI[0..7]
1
2
3
4
5
6
7
8
9
10
GND
GND
KSO[0..15]
KSI[0..7]
<22>
KSO[0..15] <22>
JKB @
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
ACES_85201-1005N
@
CLK_PCI_DDR
<13,22> LPC_AD0
<13,22> LPC_AD1
<13,22> LPC_AD2
<13,22> LPC_AD3
<13,22> LPC_FRAME#
1
2
3
4
5
6
7
8
9
10
11
12
R194
22_0402_5%
@
+3VS
<8> CLK_PCI_DDR
2
C284
22P_0402_50V8J
1
@
R193 1
KSI1
KSI6
KSI5
KSI0
KSI4
KSI3
KSI2
KSI7
KSO15
KSO12
KSO11
KSO10
KSO9
KSO8
KSO13
KSO7
KSO6
KSO14
KSO5
KSO3
KSO4
KSO0
KSO1
KSO2
2 300_0402_5%
CAPS_LED# <22>
+3VS
ACES_88170-3400
Compal Secret Data
Issued Date
7/8 Add C265 to C290 for EMI request
2009/10/21
Deciphered Date
2012/10/21
Title
Size
Date:
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
Sheet
24
of
39
Power Button
+3VALW
2
Touch/B Connector
R195
7/3 Lid switch from M/B change to T/P board
100K_0402_5%
@
TOP side
ON/OFFBTN# <22>
51_ON#
4
6
5
ON/OFFBTN#_R
8/19 Lid switch from T/P change to M/B board
D21
SW2
1
CHN202UPT SC-70
+5VS
SMT1-05_4P
1
EC_ON
R196
10K_0402_5%
7/2 Reserve ESD Diode
SMT1-05_4P
JTOUCH
@
2
7/14 Change to NON-ZIF Conn for ME request
8/19 TP Conn from 6P to 4P for ME request
ISPD
JPOWER
1
2
3
4
5
6
3
1
C322
D35
ZZZ
1
2
3
4
GND
GND
PJP1
PCB
DC-IN
PCB LA-5841PR01 BOM
10/27 MP PCB P/N Change to DAZ0BH00100
P-TWO_161011-04021
@
PJP1
45@
U1
C321
180P_0402_50V8J
C320
180P_0402_50V8J
D22
0_0402_5%
0_0402_5%
0_0402_5%
2
2
2
180P_0402_50V8J
R232 1
R233 1
R234 1
TP_CLK
TP_DATA
S 2N7002_SOT23
7/14 Change to NON-ZIF Conn for ME request
PWR_ON_LED#
PWR_ON_LED
ON/OFFBTN#_R
<22>
<22>
PESD5V0U2BT_SOT23-3
7/15 Delete ESD Diode
debug phase using
Q13
C292
1U_0402_6.3V4Z
2
G
3
6
5
BTM side
<22>
P-TWO_161011-04021
6 GND
5 GND
4 4
3 3
2 2
1 1
<28>
SW3
PESD24VS2UT_SOT23-3~D
CPU
7/8 Reserve ESD Diode
CPU N470
N470@
LED Conn
POWER LED
PWR_ON_LED
HDD LED
7/21 Change R197 to 300 ohm

Vf=2.0V(typ),2.4V(max)
If=20mA(max)
ACIN
2
2
220_0402_5%
3
S
2
220_0402_5%
D27
3
YG
1
R201
HT-297DQ-GQ_AMB-YG
POWER/SUSPEND LED
2N7002DW-T/R7_SOT363-6
WIMAX_LED_GND 1 R202
2
LED_WIMAX# <15>
0_0402_5%
@
Q5A
2N7002DW-T/R7_SOT363-6
2 R203
1
6
1
+5VS
10K_0402_5%
WIMAX@
WIMAX@
If=20mA(max)
+3VALW
2
510_0402_5%
WiMAX&3G LED
D26
1
R235
Q8A
3
Q8B
Vf=2.1V(typ),2.4V(max) for amber

Vf=2.2V(typ),2.4V(max) for green
If=25mA(max)
+3VALW
Q14 2N7002_SOT23
BATT CHARGE/FULL LED
2
2
220_0402_5%
1
R198
1
+3VS
R200
+3VALW
2 R199
1
10K_0402_5%
+3VS
D25
<13,22,28>
2
G
D24
ACIN
SATALED# <11>
2N7002DW-T/R7_SOT363-6
1
DC-IN LED
SATALED#
2
2
300_0402_5%
1
R197
+5VALW
+5VS
BATT_CHG_LOW_LED# <22>
1
2
2
R204
300_0402_5%
WIMAX@
BATT_FULL_LED# <22>
WIMAX_LED_GND 3
HT-191NBQA_BLUE_0603
WIMAX@
Q5B
4
2N7002DW-T/R7_SOT363-6
WIMAX@

8/28 Change to SC5191UD000 and SC591UYG000 for HW design
WL&BT LED
9/23 Change R235, R255 to SD028220080 and +5VALW to +3VALW for HW design
8/28 Delet D37, D38 and Change D26 and D28 to SC500001900 for ME request
D28
2
510_0402_5%
+3VALW
1
R205
2
220_0402_5%
1
R255
PWR_SUSP_LED# <22>
YG
+3VALW
PWR_ON_LED# <22>
If=30mA(max)
D29
+3VS
HT-297DQ-GQ_AMB-YG
ARROW MODE
4
+3VS
1
R207
LED
D30
+3VS
1
R208
2
2
220_0402_5%
WL_BT_LED# <22>
HT-191UD_AMBER_0603
WLAN@
2
2
220_0402_5%
NUMERIC MODE
1
2
R206
510_0402_5%
WLAN@
ARROW_LED# <22>
LED
D31
Compal Secret Data
NUM_LED# <22>
2009/10/21
Issued Date
Deciphered Date
2012/10/21
Title
SCHEMATICS,MB A5841
Custom
Date:
Rev
D
401799
Sheet
E
25
of
39
R213
Q7A
Q7B
330K_0402_5%
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
C306
C307
1 R212
2
47K_0402_5%
R214
200K_0402_5%
@
+VSB
4.7U_0805_10V4Z
R210
3 1
470_0805_5%
C299
1U_0402_6.3V4Z
Q9A
Q9B
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
+VSB
C298
1
2
3
4
S
S
S
G
SI4800BDY_SO8
C305
D
D
D
D
0.01U_0402_25V7K
4.7U_0805_10V4Z
C304
1 R211
2
47K_0402_5%
8
7
6
5
R209
SI4800BDY_SO8
4.7U_0805_10V4Z
0.01U_0402_25V7K
1U_0402_6.3V4Z
Q16
C295
+5VS
C294
1
2
3
4
3 1
S
S
S
G
D
D
D
D
4.7U_0805_10V4Z
Q15
8
7
6
5
+5VALW
Vgs=-0V,Id=9A,Rds=18.5mohm
+3VS
470_0805_5%
+3VALW
+5VALW TO +5VS
+3VALW TO +3VS
+3VALW TO +3V_LAN
+3VALW TO +3V_SB
Vgs=10V,Id=6A,Rds=35mohm
+3VALW
1U_0402_6.3V4Z
STAR@
Q6B
2N7002DW-T/R7_SOT363-6
STAR@
Q6A
1
2
G
Q19
C313
0.1U_0402_25V6
STAR@
SYSON
SYSON
<14,22> SBPWR_EN#
5
4
C315
SBPWR_EN#
<22,32>
STAR@R220
STAR@R220
120K_0402_5%
C314
4.7U_0805_10V4Z
@ 2
R218
STAR@
470_0805_5%
2N7002_SOT23
SBPWR_EN#
R221
10K_0402_5%
2N7002DW-T/R7_SOT363-6
STAR@
2
0.01U_0402_25V7K
STAR@
2
1
R219 47K_0402_5%
STAR@
SYSON#
1
1
4.7U_0603_6.3V6K
C311
C310
STAR@
@
1U_0402_6.3V4Z
2
2
STAR@
SI3456BDV-T1-E3_TSOP6
3
+VSB
+3V_LAN
C309
STAR@
1
1
R216
100K_0402_5%
2
2
3
1
PJ18
JUMP_43X79
@
6 1
2
Q18
AO3413_SOT23
STAR@
1
C312
2
47K_0402_5%
STAR@
C308
0.1U_0402_10V6K
@ JUMP_43X79
6
5
2
1
1
STAR@
1
R217
<22> WOL_EN#
Q17
4.7U_0603_6.3V6K
PJ17
Vgs=-4.5V,Id=3A,Rds<97mohm
R215
100K_0402_5%
STAR@
+5VALW
+3V_SB
+3VALW
+3VALW
+5VALW
+1.8VS
1
2
G
Q23
2N7002_SOT23
2
G
Q24
2N7002_SOT23
R226
10K_0402_5%
+0.9VS
+1.8V
+1.05VS
10/5 Reserve R223~R225, R229~R231 Q22~Q24, Q26~Q28 for HW cost down
R229
470_0603_5%
R230
470_0603_5%
1
2
3
C316
C317
10U_0805_10V4Z
1U_0402_6.3V4Z
8/31 Change Q20 from SB000002880 to SB00000DW00 for HW design
C318
1 R227
2
47K_0402_5%
1
R237
C319
0.01U_0402_25V7K
R228
10K_0402_5%
D
Q29
2
G
2N7002_SOT23-3
2 SUSP
G
Q26
2N7002_SOT23
@
S
@
S
Q30
2
G
VCCP_POK <32>
4
2 SYSON#
G
Q27
2N7002_SOT23
+VSB
+3VALW
8/14 R237 for HW design
R231
470_0603_5%
2
G
Q22
2N7002_SOT23
4.7U_0805_10V4Z
SUSP
2N7002_SOT23
D
SUSP
8
7
6
5
1
D
SUSP
2
G
Q21
D
@
<22,30,32,33> SUSP#
SUSP
Q20
IRF8113PBF_SO8
SUSP
+1.8VS
R225
470_0603_5%
R224
470_0603_5%
R223
470_0603_5%
200K_0402_5%
2
1
+1.8V
<33>
+1.5VS
+1.8V TO +1.8VS
+0.89VS
R222
100K_0402_5%
2N7002_SOT23-3
2 SUSP
G
Q28
2N7002_SOT23
7/9 Add Q29, Q30, R228 for Intel power sequence
Issued Date
Compal Secret Data
2009/10/21
Deciphered Date
2012/10/21
Title
Custom
SCHEMATICS,MB A5841
Rev
D
401799
Date:
Sheet
E
26
of
39
7/21 Placed closed H9
+CRT_VCC_R
7/23 Placed closed PJ9
+5VALW
10/5 Placed closed Q2
2
C353
0.1U_0402_16V4Z
+5VALW
2
C351
2
C352
0.1U_0402_16V4Z
C349
0.1U_0402_16V4Z
C350
0.1U_0402_16V4Z
2
C339
0.1U_0402_16V4Z
C341
@
7/23 Placed closed PJ14
+3VS
B+
0.1U_0402_16V4Z
C346
0.1U_0402_16V4Z
+3VS
B+
C340
0.1U_0402_16V4Z
B+
+5VALW
7/23 Placed closed R42
0.1U_0402_16V4Z

0.1U_0402_16V4Z
+3VS
C345
0.1U_0402_16V4Z
+3VALW
+5VALW
C347
0.1U_0402_16V4Z
+3VS
C342
C343
+5VALW
0.1U_0402_16V4Z
1U_0402_6.3V6K
+5VALW
C348
C354
1U_0402_6.3V6K
7/21 These cap for ESD request

10/5 Add C339, C340~C342, C345, C350~C354 for ESD request
10/5 Change C343 to SE000000K80 for ESD request
10/6 Change C354 to SE000000K80 for ESD request
Screw Hole
9/23 Change H12, H13 to 3P3 for ME request
M/B
H1
KB
H2
FAN
H4
H7
H9
H12
H13
H14
H17
H21
H25
H18
H_3P0
H20
H_3P5X4P5N
FIDUCIAL_C40M80
H_3P3
9/2 Det H24 with H_2P0X5P5N for ME request
H_3P3
9/29 Det H19 with H_2P0X5P5N for ME request
2009/10/21
Issued Date
Deciphered Date
FM2
@
FM3
FM4
@
4
Compal Secret Data
FM1
H16
H_3P3
H_2P1N
8/19 Add NON PTH hole H22 for Thermal module
H_3P3
H_3P5N
H15
@
H_2P0X5P0N
H22
@
8/28 Add H24 with H_2P0X5P5N for ME request

@
@
H_3P3
H_3P0
MINI Card
H11
H_3P3
8/28 Add H25 with H_5P0X2P0N for ME request
H10
H_3P3
H_3P3
H_3P3
H_3P0
H23
@
H_3P0
H_3P0
H_3P0
H8
@
H_3P0
H6
@
H_3P0
H5
H_3P0
2012/10/21
Title
Custom
SCHEMATICS,MB A5841
Rev
D
401799
Date:
Sheet
E
27
of
39
VS
PF1
VIN
1
PR3
5.6K_0402_5%
2
2
<13,22,25>
PACIN
PC6
.1U_0402_16V7K
ACIN
PU1A
PACIN
<30>
LM393DG_SO8
PD1
GLZ4.3B_LL34-2
PR7
10K_0402_1%
1
PR8
10K_0402_1%
VIN
RTCVREF
3.3V
Vin Detector
PD2
RLS4148_LL34-2
High 18.384 17.901 17.430

Low 17.728 17.257 16.976
PR11
200_0603_5%
1
2
PR10
68_1206_5%
N1
VS
2
PR15
22K_0402_1%
PU1B
O
RTC Battery
51_ON#
2
<25>
PC8
0.1U_0603_25V7K
PC7
0.22U_0603_25V7K
PR13
100K_0402_1%
CHGRTCP
PR9
PQ1
68_1206_5%
TP0610K-T1-E3_SOT23-3
2
PD3
RLS4148_LL34-2
1
BATT+
PR6
20K_0402_1%
PC5
0.068U_0402_10V6K
@ SINGA_2DW-0005-B03
PR4
10K_0402_1%
1
2
2
1
1U_0603_25V6K
PR5
22K_0402_1%
1
2
100P_0402_50V8J
PC4
100P_0402_50V8J
1
PC3
1000P_0402_50V7K
VS
PR2
84.5K_0402_1%
PC12
1U_0603_25V6K
PC2
1000P_0402_50V7K
-
PC11
PC1
PJP1
DC_IN_S1
PR1
1M_0402_1%
1
2
VIN
PL1
SMB3025500YA_2P
1
2
5A_24VDC_429007.WRML
DC301001M80
LM393DG_SO8
RTCVREF
PR17
200_0603_5%
OUT
IN
GND
PC9
10U_0805_10V4Z
N2
PBJ1
2
+
1
+RTCBATT
+RTCBATT
3.3V
G920AT24U_SOT89-3
@ MAXEL_ML1220T10
PU2
PC10
1
2
PR22
560_0603_5%
1
2
+CHGRTC
PR21
560_0603_5%
1
2
SP093MX0000
1U_0805_25V4Z
PJ1
2
+3VALWP
PJ2
+3VALW
+1.8VP
@ JUMP_43X118
+1.8V
@ JUMP_43X118
(5A,200mils ,Via NO.= 10)
(OCP min=6.52A)
(OCP min=7.16A)
PJ3
2
+5VALWP
PJ4
+5VALW
+1.05VSP
@ JUMP_43X118
PJ6
+VSB
+1.5VSP
+1.5VS
(3A,120mils ,Via NO.=6)
(120mA,40mils ,Via NO.= 1)

PJ7
2
@ JUMP_43X79
@ JUMP_43X39
+0.9VSP
+1.05VS
(OCP min=3.95A)
PJ5
2
(3.5A,140mils ,Via NO.=7)
(OCP min=6.39A)
+VSBP
@ JUMP_43X118
PJ8
+0.9VS
+0.89VSP
+0.89VS
@ JUMP_43X79
@ JUMP_43X118
(1.5A,60mils ,Via NO.=3)
(OCP min=2.1A)
Issued Date
Compal Secret Data
2009/10/21
Deciphered Date
2012/10/19
Title
Size
Date:
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
D
Sheet
28
of
39
PH1
100K_0402_1%_TSM0B104F4251RZ
2
1
8
+
PQ4
DTC115EUA_SC70-3
PD6
RLS4148_LL34-2
LM393DG_SO8
3
1
VL
PR38
100K_0402_1%
1
1
2
PR40
100K_0402_1%
2
PR39
1K_0402_1%
PC18
1000P_0402_50V7K
1
2
PR37
15.8K_0402_1%
+3VALWP
PR36
6.49K_0402_1%
2
1
PJSOT24C_SOT23-3
PU3A
PR35
100_0402_1%
MAINPWON <31>
1
PR31
47K_0402_1%
1
2
PR32
12.4K_0402_1%
1
2
PR30
47K_0402_1%
TM_REF1
PD18
1
PC16
0.1U_0603_25V7K
PC15
0.01U_0402_25V7K
PC14
1000P_0402_50V7K
+3VALWP
VL
2
PR29
47K_0402_1%
PR34
100_0402_1%
1
PR33
1K_0402_1%
@ SUYIN_250005MR007G163ZR
2
PR28
1K_0402_1%
BATT_P3
BATT_P4
BATT_P5
EC_SMDA
EC_SMCA
VL
VL
2
3
4
5
6
7
PC17
0.22U_0805_16V7K
2
3
4
5
6
7
BATT+
BATT_S1
PL2
SMB3025500YA_2P
1
2
VMB
PF2
7A_24VDC_429007.WRML
1
2
PD8
PJSOT24C_SOT23-3
PJP2
PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C
BATT_TEMPA <22>
EC_SMB_DA1 <22>
EC_SMB_CK1 <22>
PH2 near main Battery CONN :

BAT. thermal protection at 92 degree C
Recovery at 53 degree C
VL
8
+
PR46
16.9K_0402_1%
PU3B
O
PC21
0.22U_0805_16V7K
1
2
1
LM393DG_SO8
PD7
RLS4148_LL34-2
2
1
PR48
0_0402_5%
2
PQ6
SSM3K7002FU_SC70-3
2
G
PC22
@.1U_0402_16V7K
1
1
POK
TM_REF1
1
2
2
PR44
12.1K_0402_1%
1
2
PR47
100K_0402_1%
<31>
PR41
47K_0402_1%
PR42
47K_0402_1%
1
2
100K_0402_1%_TSM0B104F4251RZ
PC19
@ 0.22U_1206_25V7K
PR45
22K_0402_1%
1
2
2
1
PR43
100K_0402_1%
VL
3
PH2
+VSBP
1
PC20
@ 0.1U_0603_25V7K
B+
VL
2
PQ5
TP0610K-T1-E3_SOT23-3
Issued Date
Compal Secret Data
2009/10/21
Deciphered Date
2012/10/19
Title
Size
Date:
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
D
Sheet
29
of
39
PQ7
AO4407A_SO8
P2
P3
B+
PR49 0.05_1206_1%
PJ9
CSOP
ICOMP
CSIN
20
VCOMP
CSIP
19
3
3
VREF
UGATE
17
16
ACLIM
VDDP
15
PR72
20K_0402_1%
11
VADJ
LGATE
14
GND
PGND
13
12
4
1
1
DL_CHG
PD14
RB751V-40TE17_SOD323-2
6251VDDP
26251VDD
PR73
4.7_0603_5%
PC43
4.7U_0805_6.3V6K
ISL6251AHAZ-T_QSOP24
<BOM Structure>
PR74
15.4K_0402_1%
1
2
CHG
BOOT
CHLIM
9
10
PC39
0.1U_0603_25V7K
BST_CHGA 2
1
6251aclim
DH_CHG
PR69
2.2_0603_5%
BST_CHG 1
2
5
8
BATT+
PR75
31.6K_0402_1%
2
Iada=0~1.579A(30W) CP= 92%*Iada; CP=1.4526A
6251VREF
PR70
24.9K_0402_1%
6251VREF 1
2
<22> CHGVADJ
18
2 PACIN
G
PQ14
SSM3K7002FU_SC70-3
PR66
0.02_1206_1%
PL3
10UH_MPL73-100_3A_20%
1
2
3
2
1
PR71
100K_0402_1%
PHASE
ACOFF
ICM
PR64
2.2_0603_5%
LX_CHG
ACOFF
<22>
PR65 47K_0402_1%
2
7
IREF
6.81K_0402_1%
2
1
@PC37
@
PC37 100P_0402_50V8J
1
2
PC38
.1U_0402_16V7K
ADP_I
PC42
0.01U_0402_25V7K
2
1
<22>
PQ19
DTC115EUA_SC70-3
PR68
<22>
309K_0402_1%
2
1
PR63
1
CSOP
D
PC33
0.1U_0603_25V7K
PC41
10U_1206_25V6M
2
1
CELLS
21
1SS355_SOD323-2
CSON
PC32
0.047U_0603_16V7K
1
2
PR61
20_0603_5%
2
1
PR62
PC36
20_0603_5%
0.1U_0603_25V7K
1
2
22
PD13
2
CSON
ACOFF
PR57
200K_0402_1%
1
2 VIN
PR19
4.7_1206_5%
EN
1SS355_SOD323-2
PC13
680P_0603_50V8J
PR60
20_0603_5%
1
2
PQ16
23
VIN
PD11
PQ15
DTC115EUA_SC70-3
SIS412DN-T1-GE3_POWERPAK8-5
ACSET ACPRN
PC31
0.1U_0603_25V7K
2
1
3
2
1
DCIN
24
0.01U_0402_25V7K
PR67
22K_0402_1%
PACIN 1
2
PACIN
PC35
1
2
SUSP# <22,26,32,33>
PQ17
SSM3K7002FU_SC70-3
2
G
6800P_0402_25V7K
2
1
3
PC34
1
DCIN
VDD
47K_0402_1%
PR55
10K_0402_1%
3
PU5
1
FSTCHG
RB715F_SOT323-3
2
CSON
2
PC28
2.2U_0603_6.3V6K
2
1
PR59
100K_0402_1%
6251_EN
PR53
PD10
2
8
7
6
5
@PC30
@
PC30
680P_0402_50V7K
1
2
1
2
3
1
PR54
100K_0402_1%
2
1
2
1
PC29
.1U_0402_16V7K
PR58
150K_0402_1%
PQ11
DTC115EUA_SC70-3
PC131
0.1U_0402_25V6
2
1
1
3
DCIN
6251VDD
PR56
10K_0402_1%
2
1
<22> FSTCHG
PQ13
SSM3K7002FU_SC70-3
PR123
10_0603_5%
1
2
PR52
100K_0402_1%
PD12
1SS355_SOD323-2
1
2
PQ12
DTC115EUA_SC70-3
PQ8
P2003EVG_SO8
CSIN
1
2
P3
2
G
<28>
1
3
PC26
5600P_0402_25V7K
PC27
0.1U_0603_25V7K
PC40
10U_1206_25V6M
2
1
@ JUMP_43X118
PR51
47K_0402_1%
PQ10 TP0610K-T1-E3_SOT23-3
CSIP
PR50
200K_0402_1%
PQ9
DTA144EUA_SC70-3
PQ18
PC124
2200P_0402_50V7K
2
1
B340A_SMA2
8
7
6
5
PC24
4.7U_0805_25V6-K
2
1
1
2
3
PC23
4.7U_0805_25V6-K
2
1
B+
CHG_B+
PD9
VIN
CP mode
Vaclim=2.39*(20K//152K/(24.9K//152K+20K//152K))=1.0817V
VIN
Iinput=(1/0.05)((0.05*Vaclm)/2.39+0.05)
where Vaclm=1.0817V, Iinput=1.4526A
PR76
309K_0402_1%
CHGVADJ=(Vcell-4)/0.10627
IREF=1.636*Icharge
Vcell
IREF=0.409V~3.272V
4V
VCHLIM need over 95mV
4.2V
1.2V
4.35V
3.3V
PR77
47K_0402_1%
PR12
10K_0402_1%
1
2
CHGVADJ
0V
ADP_V
<22>
PC44
.1U_0402_16V7K
CC=0.25A~2A
CELLS
CELL number
VDD
GND
Float
Issued Date
Compal Secret Data
2009/10/21
Deciphered Date
2012/10/19
Title
Size
Date:
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
D
Sheet
30
of
39
TPS51427_B+
TPS51427_B+
16
LX5
DRVL1
18
DL5
23
DRVL2
VL
30
VOUT2
32
REFIN2
PGND
22
VOUT1
10
FB1
11
VSW
2VREF_TPS51427
1
1
+ PC60
150U_B_6.3VM_R45M
2
C
FB3
@ PR85
10K_0402_1%
PR86
0_0402_5%
2
PC130
0.1U_0402_25V6
2
1
PC50
2200P_0402_50V7K
2
1
PC49
4.7U_0805_25V6-K
2
1
PC48
4.7U_0805_25V6-K
2
1
2
DL3
@ PC59
680P_0603_50V8J
PC120
.1U_0402_16V7K
2
1
LL1
LL2
PR84
@ 61.9K_0402_1%
1
2
25
@ PR82
4.7_1206_5%
3
2
1
LX3
PC57
0.1U_0603_25V7K
PC56
0.1U_0603_25V7K
1
2
3
DH5
PR83
2.2_0603_5%
BST5A 1
2
17
+5VALWP
15
VBST1
Ipeak=5A
Imax=3.5A
F=400K
PL5
4.7UH_PCMC063T-4R7MN_5.5A_20%
2
1
DRVH1
VBST2
PQ22
AON7702L_DFN8-5
DRVH2
PC54
1U_0603_10V6K
1
2
PQ21
3
2
1
PC53
4.7U_0805_6.3V6K
2
1
19
24
LDO
26
V5DRV
AON7702L_DFN8-5
1
2
PQ23
1
@ PC58
680P_0603_50V8J
PC52
1U_0603_10V6K
1
2
DH3
BST3A
PR80
0_0402_5%
PR79
2.2_0603_5%
1
2
V5FILT
TP
150U_B2_6.3VM_R35M
1
PC55
PC99
.1U_0402_16V7K
2
1
@ PR81
4.7_1206_5%
PU6
33
+3VALWP
VIN
PL4
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2
PC51
0.1U_0603_25V7K
Ipeak=5A
Imax=3.5A
F=300K
VL
1
2
3
PC129
0.1U_0402_25V6
2
1
@ JUMP_43X118
PQ20
1
PC47
2200P_0402_50V7K
2
1
PC46
4.7U_0805_25V6-K
2
1
PC45
4.7U_0805_25V6-K
2
1
PR78
0_0805_5%
1
2
PJ10
B+
FB5
VREF2
PC61 0.22U_0603_10V7K
Toatal Capacitor 150u
LDOREFIN
SKIPSEL
ESR=35 mohm
@ PR87 0_0402_5%
2
1
29
VL
PR88 0_0402_5%
1
2
EN_LDO
PGOOD1
13
TRIP1
12
ILM1
PR91
200K_0402_1%
2
1
TRIP2
31
ILIM2
PC63
1U_0603_10V6K
1
2
GND
EN2
SN0806081RHBR_QFN32_5X5
21
27
TONSE
EN1
VREF3
14
POK
<29>
PR92
200K_0402_1%
PR96
0_0402_5%
2VREF_TPS514272
1
2
3
2
PR94
0_0402_5%
1
@ PR98
47K_0402_5%
1
2
PC64
0.047U_0603_16V7K
PR97
0_0402_5%
2
1
2VREF_TPS514271
@ PR93
0_0402_5%
PR95
806K_0603_1%
<29> MAINPWON
28
VL
PD17
1SS355_SOD323-2
ESR=45 mohm
PGOOD2
2
1
PC62
0.22U_0603_10V7K
NC
VS
20
PR89
100K_0402_1%
1
2
PR90
200K_0402_1%
1
2
PD16
GLZ5.1B_LL34-2
1
2
@ PC65
0.047U_0402_16V7K
PQ24
TP0610K-T1-E3_SOT23-3
Compal Secret Data
2009/10/21
Issued Date
Deciphered Date
2012/10/19
Title
Size
Date:
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
Sheet
1
31
of
39
PJ11
TRIP
V5DRV
10
DL_1.05V
15
TP
PC74
4.7U_0805_10V6K
PR105
8.25K_0402_1%
1
2
PC127
0.1U_0402_25V6
2
1
B+
1
2
1
PC25
1U_0603_25V6K
PC125
2200P_0402_50V7K
2
1
1
2
1
2
1
PR104
5.36K_0402_1%
DRVL
+5VALW
TPS51117RGYR_QFN14_3.5x3.5
PR124
10K_0402_1%
PGND
PGOOD
@PC73
@
PC73
47P_0402_50V8J
1
2
GND
PC71
4.7U_0805_10V6K
VCCP_POK
<26>
3
2
1
LX_1.05V
1
12
11
VFB
LL
0.1U_0603_25V7K
V5FILT
DH_1.05V
13
@ JUMP_43X118
PC132
1U_0603_25V6K
Ipeak=3.5A
Imax=2.45A
F=315K
PL6
2.2UH_PCMC063T-2R2MN_8A_20%
1
2
PQ26
AON7702L_DFN8-5
VOUT
DRVH
VBST
TON
PC69
BST_1.05V-1
3
2
1
PR103
100_0402_1%
1
2
14
PU7
+5VALW
@PC68
@PC68
.1U_0402_16V7K
EN_PSV
<22,26,30,33> SUSP#
PR101
2.2_0603_5%
BST_1.05V1
2
+1.05VSP

ESR=35 mohm
PC121
@ .1U_0402_16V7K
2
1
PR99
1
2
255K_0402_1%
PR100
0_0402_5%
1
2
PC67
4.7U_0805_25V6-K
@ RLS4148_LL34-2
PR102
4.7_1206_5%
PC72
680P_0603_50V8J
PQ25
PD4
1
PC66
4.7U_0805_25V6-K
1.05V_B+
+
2
PC70
220U_B2_2.5VM_R35
+3VS
PR106
20.5K_0402_1%
PJ12
DL_1.8V
1
PGND
DRVL
PC83
4.7U_0805_10V6K
PC128
0.1U_0402_25V6
2
1
B+
1
PC134
1U_0603_25V6K
1
PC133
1U_0603_25V6K
PC76
4.7U_0805_25V6-K
PC126
2200P_0402_50V7K
2
1
1
2
PC75
4.7U_0805_25V6-K
+5VALW
@ JUMP_43X118
Ipeak=6A
Imax=4.2A
F=312K
+1.8VP
PC122
@ .1U_0402_16V7K
2
1
10
PR110
4.7_1206_5%
V5DRV
2
PR112
10K_0402_1%
PC81
680P_0603_50V8J
3
2
1
14
15
TP
8
PGOOD
GND
PC82
@ 47P_0402_50V8J
1
2
PC80
4.7U_0805_10V6K
VFB
11
LX_1.8V
12
TRIP
V5FILT
13
LL
DRVH
PQ28
AON7702L_DFN8-5
VOUT
0.1U_0603_25V7K
PL7
1
2
TON
BST_1.8V-1
DH_1.8V
3
2
1
PC78
PR111
100_0402_1%
1
2
PU8
EN_PSV
@PC77
@PC77
.1U_0402_16V7K
2
+5VALW
PR109
2.2_0603_5%
BST_1.8V 1
2
SYSON
PR108
0_0402_5%
1
2
VBST
<22,26>
PR107
255K_0402_1%
1
2
PQ27
51117_B+
1
+ PC79
220U_B2_2.5VM_R25M
2

ESR=14.5 mohm
PR113
28.7K_0402_1%
1
2
PR114
20.5K_0402_1%
4
Issued Date
Compal Secret Data
2009/10/21
Deciphered Date
2012/10/19
Title
Size
Date:
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
D
Sheet
32
of
39
+1.8V
+1.8V
GND
NC
VREF
NC
VOUT
NC
TP
PC85
1U_0603_10V6K
PR115
1K_0402_1%
1
2
+3VALW
PC91
1U_0603_10V6K
VCNTL
VIN
PU9
PC92
PC84
4.7U_0805_6.3V6K
PJ15
@ JUMP_43X39
PJ13
@ JUMP_43X79
D
+5VALW
10U_0805_6.3V6M
PU11
PR120
2.7K_0402_1%
APL5930KAI-TRG_SO8
PC95
@ 0.47U_0402_6.3V6K
PR121
3K_0402_1%
PC94
22U_0805_6.3V6M
FB
+1.5VSP
1
EN
POK
3
4
PC93
0.01U_0402_25V7K
8
7
VOUT
VOUT
VCNTL
VIN
VIN
<22,26,30,32> SUSP#
6
5
9
PC90
10U_0805_6.3V6M
PR119
0_0402_5%
1
2
GND
+0.9VSP
2
PC88
.1U_0402_16V7K
2
1
PR118
1K_0402_1%
PQ29
SSM3K7002FU_SC70-3
PC89
@ 0.1U_0402_16V7K
2
G
3
<26> SUSP
APL5331KAC-TRL_SO8
PR117
0_0402_5%
1
2
PJ14
10
9
DL_0.89V
DRVL
4
1
PGND
2
PGOOD
@PC141
@
PC141
47P_0402_50V8J
1
2
GND
PC139
4.7U_0805_10V6K
+5VALW
PC86
4.7U_0805_10V6K
PC137
0.1U_0402_25V6
2
1
PC87
4.7U_0805_25V6-K
PC143
2200P_0402_50V7K
2
1
PC123
@ .1U_0402_16V7K
2
1
V5DRV
2
PR158
6.49K_0402_1%
11
PR162
4.7_1206_5%
TRIP
0.1U_0603_25V7K
LX_0.89V
15
14
DH_0.89V
12
VFB
13
LL
PC144
680P_0603_50V8J
DRVH
V5FILT
VBST
TP
VOUT
0.89V_FB
TON
B+
PC142
1U_0603_25V6K
PL10
1
2
PC138
BST_0.89V-1
PQ33
AON7702L_DFN8-5
0.89V_V5FILT
@ JUMP_43X118
PC136
1U_0603_25V6K
Ipeak=1.5A
Imax=1.05A
F=316K
PQ32
3
2
1
+5VALW
PR157
100_0402_1%
1
2
PU10
EN_PSV
@PC140
@PC140
.1U_0402_16V7K
3
2
1
0.89V_EN
PR161
2.2_0603_5%
BST_0.89V1
2
<22,26,30,32> SUSP#
1
2
5
PR156
1
2
255K_0402_1%
0.89V_TON
PR159
0_0402_5%
1
2
PC146
4.7U_0805_25V6-K
0.89V_B+
+0.89VSP
1
+ PC145
220U_B2_2.5VM_R35
2

ESR=8.07 mohm
PR116
3.92K_0402_1%
1
2
PR160
21K_0402_1%
2009/10/21
Issued Date
Compal Secret Data
Deciphered Date
2012/10/19
Title
Size
Date:
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
Sheet
1
33
of
39
<5>
<5>
<5>
CPU_VID2
<22>
CPU_VID3
<5>
CPU_VID4
<5>
CPU_VID5
<5>
CPU_VID6
<5>
VR_ON
CPU_VID1
CPU_VID0
0_0402_5%
17
AGND
3
2
1
2
1
2
@
PR122
4.7_1206_5%
PC186
2.2U_0603_10V6K
4
PQ31
AON7702L_DFN8-5
33
PC148
0.1U_0402_25V6
1
2
PC147
2200P_0402_50V7K
1
2
PC102
4.7U_0805_25V6M
1
2
PC104
4.7U_0805_25V6M
PC101
4.7U_0805_25V6M
1
2
AGND
3211_DRVL
+CPU_CORE
JUMP_43X118
LL=5.9m ohm
OCP=6.2A
VID:0.75V~1.1V
Io(max)=3.5A
PC109
680P_0603_50V8J
3
2
1
CSCOMP
CSFB
CSREF
PH4
100K_0402_1%_TSM0B104F4251RZ
1
Place RTH1 close to inductor

on the same layer
1
1
2
LLINE
RAMP
RT
PC189
1000P_0402_50V7K
PC190
220P_0402_50V7K
PR217
75K_0402_1%
1
3
PR218
309K_0402_1%
PC191
1000P_0402_50V7K
PJ16
+CPU_COREP
1
19
18
+5VS
Connect to input caps
PL14
1
2
DRVL
PGND
B+
16
15
14
13
12
3211_RAMP
1
2
1
20
PR213
35.7K_0402_1%
2
1
PR214
499K_0402_1%
RPM
3211_VCC
25
26
VID5
27
VID4
VID3
VID6
PVCC
3211_RAMP-1
PR219
1K_0402_1%
2
1
<6>
<6>
VCCSENSE
VSSSENSE
+CPU_B+
28
29
VID2
VID1
30
11
3211_RT
PR211
200K_0402_1%
1
2 3211_RPM
PR210
80.6K_0402_1%
3211_IREF
1
2
3211_CSCOMP 1
2
1
1
3
3211_SW
3211_CSCOMP
PR152
0_0402_5%
3211_CSFB
PU15
3211_CSCOMP
PR150
0_0402_5%
3211_DRVH
21
PQ30
SIS412DN-T1-GE3_PAK1212-8
ILIM
22
SW
PR206
PC183
0_0603_5%
0.22U_0603_25V7K
2CPU_BOOST-1
1
2
3211_ILIM 8
DRVH
COMP
PR207
28K_0402_1%
Avoid high dV/dt
23 CPU_BOOST 1
GPU
PR209
2.8K_0402_1%
24
BST
31
32
EN
FB
3211_COMP 6
PC188
470P_0402_50V8J
ADP3211AMNR2G_QFN32_5X5
IREF
FBRTN
PR208
1K_0402_1%
23211_COMP-1
1
CLKEN#
PC187
47P_0402_50V8J
IMON
10
3211_FB
PC185
390P_0402_50V7K
CLK_ENABLE#
VCC
PWRGD
PR212
274K_0402_1%
1
2
PC184
1000P_0402_50V7K
VID0
1
2
1
2
PC182
1U_0805_25V6K
PC100
4700P_0402_25V7K
1
VID6
1
VID5
PR200
10_0603_1%
+3VS
PR205
10K_0402_1%
PL9
FBMA-L11-201209-121LMA50T_0805
0_0402_5%
+CPU_B+
PR204
0_0402_5%
+5VS
1
VID4
PR202
1
VID3
PR203
0_0402_5%
2
1
VID2
PR201
0_0402_5%
0_0402_5%
2
1
VID1
PR198
1
VID0
PR199
0_0402_5%
2
2
1
3211_EN
<8,13,22> VGATE
PR196
PR195
0_0402_5%
2
13211_PWRGD
PR197
PR194
10K_0402_1%
0_0402_5%
+3VS
PC192
1000P_0402_50V7K
Shortest the
net trace
2009/10/21
Issued Date
Compal Secret Data
Deciphered Date
2012/10/19
Title
Size
Date:
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
Sheet
34
H
of
39
NO DATE
PAGE
MODIFICATION LIST
PURPOSE
------------------------------------------------------------------------------------------------------------EVT
P37-CPU_CORE
Change PU15
SA00003DA0L --> SA00003DA00
Choice the A51 material
EVT
P35-1.05VSP/1.8VP
Change PR124
DVT
P33-CHARGER
Delete PD15
422 ohm -->10K ohm
Deign change
DVT
P35-1.05VSP/1.8VP
Change PR104 13.7K-->5.36K
DVT
P35-1.05VSP/1.8VP
Change PR124
DVT
P32-Battery conn/otp
Reserve the ESD diode
Deign change
PVT
P37-CPU_CORE
Change PR209 1.8K-->2.8K
Change the OCP 6A-->9A

EMI approvel
Deign change(Cause layout)
the same
part number with
Deign change(OCP point)

PR4
Deign change(Use the same part number)
PVT
P34-+5VALWP/+3VALWP
Reserve the sunnber PR82&PR81&PC58&PC59
PVT
P28-DCIN&DECTOR
Change PC7 1206-->0603
For cost down
PVT
P32-Battery conn/otp
Add the ESD diode
EMI require
PVT
P28-DCIN&DECTOR
pre-mp
P29-Battery conn / OTP
pre-mp
P33-0.9VSP/1.5VSP/0.89VP
Change DC-IN jack DC301009G00
Design change
Change PR32 -->12.4K , PR37-->15.8k,PR44-->12.1k,PR46-->16.9K

Change PR158 2.49K-->6.49K
Thermal commond
Design change
Compal Secret Data
Issued Date
2009/10/21
Deciphered Date
2012/10/21
Title
Size
Date:
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
Sheet
35
of
39
PIR (Product Improve Record)

KAVAA LA-5841P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1
NO DATE
PAGE MODIFICATION LIST
PURPOSE
---------------------------------------------------------------------------------------------------------------------
Item Date
Page
Component
Solution
Request
-----------------------------------------------------------------------------------------------1)
7/2
9
Reserve
R87 with 0 ohm
For support DPST function
2)
7/2
22
Add
R235 90 ohm bead and C323 with 6P
For EMI request
3)
7/2
13
Reserve
C207 with 22P
For EMI request
4)
7/2
18
Reserve
CA33 with 22P and RA31 with 22 ohm
For EMI request
5)
7/2
16
Change
Change L4 to SM070001310
For EMI request
6)
7/2
18
Reserve
CA34 with 0.01U to GND and RA32 with 4.7K ohm up +3VS
For ESD request
7)
7/2
25
Reserve
D32 with SCA00000R00
For ESD request
8)
7/3
25
Change
Lid switch from M/B change to T/P board
For design change
9)
7/3
19
Change
Change DA3,DA4,D22 to SCA00000T00
For ESD request
10)
7/3
4
Reserve
D33,D34 with SC300000O00
For ESD request
11)
7/3
16
Reserve
D23 with SC300000O00 from Sub board to M/B
For ESD request
12)
7/6
22
Change
Change R235 to L6 with SM010009E00
For EMI request
13)
7/8
24
ADD
Add C265~C290 with SE071101J80
For EMI request
14)
7/8
16
Swap
Pin swap for AGND
For layout
15)
7/8
18
Reserve
R235 withSD028000080
For EMI request
16)
7/8
27
Modify
Modify screw hole location
17)
7/8
25
Reserve
D32 with SCA00000R00
For ESD request
18)
7/8
16
Reserve
D36 with SC300000O00 from Sub board to M/B
For ESD request
19)
7/8
07
Add
C216,C217,C238,C291 with SE070104Z80
For EMI request
20)
7/9
26
Add
D29, D30 with SB570020020 and R228 with SD028100280
For power sequence
21)
7/9
13
Add
C293 with SE070104Z80
22)
7/9
25
Change
R232, R233, R234 with SD028000080
Need to EMI confirm on EVT
23)
7/9
18,19 Modify
modify 2 SPK solution
For TOSHIBA request
24)
7/10
20
Change
UL1 with SA00002XC10
For low power solution
25)
7/10
16
Change
JUSBC1 to DC233004Q00
For ME suggest
26)
7/10
16
Swap
USB20_P0_R USB20_N0_R, USB20_P0_R_S, USB20_N0_R_S
For layout request
27)
7/10
10
Add
J2
For cost down PolySwitch
28)
7/13
8
Add
C296, C297 with SE071220J80
For RF request
29)
7/13
8
Add
C300, C301 with SE068330K80
For RF request
30)
7/13
8
Add
C302, C303, C324 with SE068330K80
For RF request
31)
7/13
8
Add
C325, C326, C327 with SE068330K80
For RF request
32)
7/13
8
Change
R53, R54, R57 to SM01000B200
For RF request
33)
7/13
8
Add
C328, C329, C330 with SE071470J80
For RF request
34)
7/13
19
Reserve
CA25 with SE070104Z80
For RF request
35)
7/14
21
Delete
YC1, CC12, CC13
For cost down
36)
7/14
25
Change
JTOUCH1 to NON-ZIF
For ME suggest
37)
7/14
25
Change
JPOWER1 to NON-ZIF
For ME suggest
38)
7/15
22
Change
INVT_PWM from PIN 21 change to PIN 25
For EC suggest
39)
7/15
22
Change
USB_CHG_EN# from PIN 68 change to PIN 29
For EC suggest
40)
7/15
5
Change
SB to CPU signal to CPU side
For placement
41)
7/15
16
Swap
USB20_N3 and USB20_P4 location
For layout request
42)
7/15
25
Delete
D32
For ESD request
43)
7/16
17
Delete
BT and Camera BTO item
For BOM request
44)
7/16
19
Delete
MIC BTO item
For BOM request
45)
7/16
21
Change
For RC8 change to reserve
For realtek request
46)
7/16
23
Delete
G-senser BTO item
For BOM request
47)
7/16
16
modify
USB_OC#0 dis-connect to +USB_VCCB
For schematic error
48)
7/16
26
modify
Change Q22 pull up from 0.89V to 0.89VS
For schematic error
49)
7/16
9
Reserve
C331 and C332 with SE071100J80
For EMI request
50)
7/16
9
Reserve
C333 and C334 with SE071100J80
For EMI request
51)
7/17
23
Change
U17 from R5F211B4D31SP change to R5F211B4D34SP
For TOSHIBA request
52)
7/17
12
Change
Reassign Tiger point USB port
For TOSHIBA concern
53)
7/17
21
Delete
RC13
For cost down
54)
7/17
20
Change
JLAN from SANTA_130452-3_13P-T to Santa_130452-8_8P-T
For not support LAN LED fuction
55)
7/17
20
Delete
RL7, RL8, RL9, RL11, CL16, CL21
For not support LAN LED fuction
56)
7/17
15
Change
R156, R157 for JWLAN1 change to JGPS1
For debug
57)
7/20
4
Add
R238, R239 with SD028100280
For Ref board design
58)
7/20
5
Add
C335 with SE000000K80
59)
7/20
5
Reserve
C336 with SE074221K80
60)
7/20
13
Delete
EC_THERM# pull up
Follow NIM10
61)
7/20
13
Add
T43, T44
Follow NIM10
62)
7/20
13
Add
SLPIOVR pull up 8.2k to +3vs
Follow NIM10
63)
7/21
3
Swap
XDP_TRST#, XDP_TDO, XDP_TDI, XDP_TCK, XDP_TMS
For layout request
64)
7/21
7
Reserve
C60 with SE107225K80
2009/10/21
Issued Date
Compal Secret Data
2012/10/21
Deciphered Date
Title
Size
Date:
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
Sheet

1
36
of
39

KAVAA LA-5841P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1-->0.2
NO DATE
PURPOSE
---------------------------------------------------------------------------------------------------------------------
65)
66)
67)
68)
69)
70)
71)
72)
73)
74)
75)
76)
77)
78)
79)
80)
81)
82)
83)
84)
85)
86)
87)
88)
88)
89)
90)
91)
92)
93)
94)
95)
96)
97)
98)
99)
100)
101)
102)
103)
104)
105)
106)
107)
108)
109)
110)
111)
112)
113)
114)
115)
116)
117)
118)
119)
120)
121)
122)
123)
124)
125)
126)
127)
128)
129)
130)
131)
132)
132)
132)
133)
7/21
7/21
7/21
7/21
7/21
7/21
7/21
7/21
7/21
7/21
7/21
7/22
7/22
7/22
7/22
7/23
7/23
7/23
7/23
7/23
7/27
7/27
8/14
8/14
8/14
8/14
8/14
8/14
8/14
8/14
8/14
8/14
8/14
8/14
8/14
8/14
8/14
8/19
8/19
8/19
8/19
8/19
8/19
8/19
8/21
8/24
8/24
8/24
8/24
8/24
8/24
8/24
8/24
8/24
8/24
8/24
8/24
8/23
8/27
8/27
8/27
8/28
8/28
8/31
8/31
9/1
9/1
9/2
9/3
9/3
9/3
9/4
8
8
9
15
17
19
25
4
13
13
27
8
19
8
8
20
21
21
25
27
4
16
4
5
5
5
5
8
13
17
18
18
18
26
9
9
24
25
17
21
24
16
25
27
16
4
5
5
5
16
8
10
17
18
20
20
21
27
8
8
8
27
25
27
26
13
13
27
16
16
16
7
Reserve
Change
Change
Change
Swap
Add
Change
Add
Add
Change
Add
Add
Add
Delete
Add
Change
Change
Change
Change
Reserve
Change
Swap
Add
Add
Add
Change
Change
Add
Add
Swap
Add
Add
Add
Add
Add
Det
Change
Det
Add
Change
Change
Change
Change
Add
Add
Change
Det
Change
Change
Change
Change
Change
Change
Change
Change
Add
Det
Reserve
Det
Add
Det
Add
Change
Add
Change
Change
Add
Det
Add
Add
Add
Reserve
C303,C324,C325,C326,C327,C296,C297,C300,C301
WWAN_CLKREQ# from REQ4 to REQ11
C331 to Shunt Capacitor
C334 to Shunt Capacitor
USB20_N7, USB20_P7
RA33, RA34 with SD028820180
R197 to 300ohm
R137 to GND
R240 pull up to +RTCBATT
C156 with SE000000K80
C339~C345 with SE070104Z80
R241 pull up to +3VS
RA33~RA40, CA35~CA38
R64, R66
R242~R253
JLAN from Santa_130452-8_8P-T to SANTA_130452-6
JCARD with TAITW_PSDAT3-09GLAS1N14N
DC1 for TOP view LED
D24~D31 for TOP view LED
C346~C348 with SE070104Z80
C302 to GND for +1.8V pull up
USB20_P4_R_S and USB20_N4_R_S
DDR_VREF net name
CRT_IRTN net name
DAC_IREF net name
Net name from H_GTLREF to +H_GTLREF
Net name from H_EXTBGREF to +H_EXTBGREF
R250 pull up with SD028470080
R254 pull down with SD028100380
USB20_N7, USB20_P7
R235 with SD028000080
Net name to HP_L_R and HP_R_R
Net name to CPVEE
R237 with SD028200380
R87 with SD028000080
R88 with SD028000080
U28 from SA00000XT00 to SA00002TO00
Lid switch from T/P change to M/B board
U22, C332, C333 for Lid function
JCARD for push pull Conn
JFAN to SP02000JR00
JUSBC to DC233004W00
JTOUCH to SP01000WX00
H22 NON PTH hole
USB_CHG_EN# has to be connected to OE# pin
+DDR_VREF to DDR_VREF
CRT_IRTN net name
+H_GTLREF to H_GTLREF
+H_EXTBGREF to H_EXTBGREF
U12 to SA00002XX00
Net name to FSB for U3.2
D1, D2, D3
JSATA to ALLTO_C16674-12204-L
R235 to RA21
JLAN for Deep connecter
Connect ISOLATEB to EC
RC9
C343, C342, C345, C341, C339, C340
C93, C94, C95, C102
C303, C324, C325, C326, C327 to GND
296, C297
H24 with H_2P0X5P5N
SC5191UD000 and SC591UYG000
H25 with H_5P0X2P0N
Q20 from SB000002880 to SB00000DW00
R125 to SM010027780
C207 to SE071100J80
H24 with H_2P0X5P5N
PIN 21, PIN 22 on JUSB
PIN 3, PIN 4 on JSPKR, JSPKL
PIN 35, PIN 36 on JKB
C66, C67, C68, C69, C72, C75, C77, C78, C79, C81,
C83, C84, C85
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
silego suggest
EMI request
EMI request
layout request
AMP gain
common design
Intel request
Intel request
Intel request
ESD request
Intel request
AMP gain
Intel suggest CLK schematic
Intel suggest CLK schematic
ME request
TOSHIBA request
ME request
ME request
ESD request
schematic error
schematic error
layout request
layout request
layout request
layout request
layout request
Intel request
EC request
layout request
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
For
layout request
layout request
HW design
not support DPST
not support DPST
BIOS ROM size
ME request
ME request
ME request
ME request
ME request
ME request
Thermal module
SPEC REV 0.5
HW schematic review
HW schematic review
HW schematic review
HW schematic review
HW schematic review
For ESD request

For ME request
For ME request
For
For
For
For
For
For
For
For
For
For
For
For
For
low power CLK GEN

RF request
RF request
ME request
HW design
ME request
HW design
EMI request
EMI request
ME request
layout request
layout request
layout request
2009/10/21
Issued Date
Compal Secret Data
2012/10/21
Deciphered Date
Title
Size
Date:
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
Sheet
1
37
of
39

NPVAA LA-5841P SCHEMATIC CHANGE LIST
NO DATE
PURPOSE
---------------------------------------------------------------------------------------------------------------------
134)
135)
136)
137)
138)
140)
141)
142)
143)
144)
145)
146)
9/23
9/23
9/23
9/28
9/28
10/5
10/5
10/5
10/5
10/6
10/6
10/6
13
27
25
16
10
27
27
18
26
25
15
27
Change
Change
Change
Det
Reserve
Add
Change
Add
Reserve
Change/Det
Change
Change
RP17 to R256, R257, R258

H12, H13 to 3P3
R235, R255 to SD028220080 and +5VALW to +3VALW
D36 with SC300000O00
Reserve F1 for cost down PolySwitch
C339, C340~C342, C345, C350~C354 with SE070104Z80
C343 to SE000000K80
RA7 and RA11 with SD013000080
R223~R225, R229~R231 Q22~Q24, Q26~Q28 for HW cost down
Delet D37, D38 and Change D26 and D28 to SC500001900
R156, R157 for JWLAN change to JGPS
C354 to SE000000K80
For
For
For
For
layout request
ME request
HW design
ESD request
For
For
For
For
For
For
For
ESD request
ESD request
ESD request
HW cost down
ME request
debug
ESD request
2009/10/21
Issued Date
Compal Secret Data
2012/10/21
Deciphered Date
Title
Size
Date:
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
Sheet

1
38
of
39

NPVAA LA-5841P SCHEMATIC CHANGE LIST
NO DATE
PURPOSE
---------------------------------------------------------------------------------------------------------------------
147)
148)
149)
150)
10/19
10/20
10/27
11/12
4
16,17
19
24
Change
Det
Det
Change
footprint T5, T6 and T7 from TPC24 to TPC12

L4, and L5
DA4 and DA5
U28 from SA000002T00 to SA0000XTO00
For
For
For
For
layout request
EMI request
ESD request
BIOS ROM size
2009/10/21
Issued Date
Compal Electroinc,Inc.
Compal Secret Data
2012/10/21
Deciphered Date
Title
Size
Date:
SCHEMATICS,MB A5841
Document Number
Rev
D
401799
Sheet

1
39
of
39

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Tampa Bay NPVAA

Compal Secret Data

Tuesday, December 15, 2009

USB port 0,1,4

Power Circuit DC/DC

DC/DC Interface CKT.

1.8V DDRII 667

Compal Secret Data

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

0.89VS GFX support voltage

SLP_S3# SLP_S4# SLP_S5#

0.9V switched power rail for DDR terminator

VCCP switched power rail

1.5V switched power rail

1.8V power rail for DDR

1.8VS switched power rail

3.3V always on power rail

3.3V power rail for LAN

3.3V power rail for LAN

3.3V power rail for LAN

3.3V switched power rail

5V always on power rail

5V power rail for SB

5V switched power rail

VSB always on power rail

BTO Option Table

Mini PCI-E SLOT

Tiger point SM Bus address

Compal Secret Data

Tuesday, December 15, 2009

Pull-down must be placed

7/20 Add R238 and R239 for Ref board design

7/21 Add C302 to GND for Intel request

7/27 Change C302 to GND for +1.8V pull up

8/14 Add +DDR_VREF net name

Place diff CPU side

Compal Secret Data

Tuesday, December 15, 2009

R17 be placed <500 mils to U1.P28

R16 be placed U1.R22

8/14 Add DAC_IREF net name

8/24 Change net name to H_GTLREF

To be placed <250 mils to U1 ball

To be placed <500 mils to U1 ball

7/20 Reserve C336 for Ref board design

7/20 Add C335 for Ref board design

placed within 0.5" of processor

Compal Secret Data

placed within 0.5"

CPU THERMAL SENSOR

8/24 Change net name to H_EXTBGREF

7/21 Pull down 1K to GND for Intel request

8/14 Change net name to +H_EXTBGREF

8/14 Change net name to +H_GTLREF

8/24 Det CRT_IRTN net name

8/14 Add CRT_IRTN net name

Please closed U1 ball

Please closed U1.Y2

Please closed U1.D4