HDL Interfacing

DCMOTOR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dcmotor is
Port ( psw : in STD_LOGIC_vector(2 downto 0);
pdcm : out STD_LOGIC;
p100k : in STD_LOGIC);
end dcmotor;
architecture behavioral of dcmotor is
signal sclkdiv : std_logic_vector(11 downto 0);
begin
-- count upto 3000
process(p100k)
begin
if( rising_edge(p100k)) then
sclkdiv <= sclkdiv+1;
end if;
if(sclkdiv = "101110111000") then
sclkdiv <= "000000000000";
end if;
end process;
process(psw,sclkdiv)
variable vdcm : bit;
begin
if(sclkdiv = "000000000000") then
vdcm := '1';
end if;
-- 1f4,320,44c,578,6a4,7d0,8fc,9c4
if(psw = "111" and sclkdiv = "000111110100") then vdcm := '0';
elsif(psw = "110" and sclkdiv = "001100100000") then vdcm := '0';

end if;
if(vdcm = '1') then pdcm <= '1';
else pdcm <= '0';
end if;
end process;
end behavioral;
UCF Fle:
NET "psw<0>"
NET "psw<1>"
NET "psw<2>"
NET "p100k"
NET "pdcm"
LOC = "P2";
LOC = "P3";
LOC = "P5";
LOC = "P7";
LOC = "P9";
LED DISPLAY:
library IEEE;
entity Seg7x4 is
port ( clk100k : in std_logic;
LG_Xclk : out std_logic;
Header1 : out std_logic_vector(7 downto 0);
Header2 : out std_logic_vector(7 downto 0) );
end Seg7x4;
architecture Behavioral of Seg7x4 is
signal clkdiv : std_logic_vector(20 downto 0);
signal state16: std_logic_vector(3 downto 0);
signal statedsp: std_logic_vector(1 downto 0);
signal shiftreg: std_logic_vector(7 downto 0);
alias seldisp : std_logic_vector(3 downto 0) is Header1(7 downto 4);
alias segdata : std_logic_vector(7 downto 0) is Header2(7 downto 0);
begin
P1:process (clk100k)
begin
if( rising_edge(clk100k)) then
clkdiv <= clkdiv + 1;
end if;
state16 <= clkdiv(16 downto 13);
statedsp <= clkdiv(18 downto 17);
end process P1;
P2:process (statedsp)
begin
case statedsp is -- support for 7407 buffer
when "00" => seldisp <= "1110";
when "01" => seldisp <= "1101";
when "10" => seldisp <= "1011";
when "11" => seldisp <= "0111";
when others => seldisp <="1111";
end case ;
end process P2;
P3:process (state16)
begin
case state16 is
-------------------------"*gfedcba"
when "0000" => segdata <="00111111"; --3F
when "0001" => segdata <="00000110"; --06
when "0010" => segdata <="01011011"; --5b
when "0011" => segdata <="01001111"; --4f
when "0100" => segdata <="01100110"; --66
when "0101" => segdata <="01101101"; --6d
when "0110" => segdata <="01111101"; --7d
when "0111" => segdata <="00000111"; --07
when "1000" => segdata <="01111111"; --7f
when "1001" => segdata <="01100111"; --67
when "1010" => segdata <="01110111"; --77
when "1011" => segdata <="01111100"; --7c
when "1100" => segdata <="00111001"; --39
when "1101" => segdata <="01011110"; --5e
when "1110" => segdata <="01111001"; --79
when "1111" => segdata <="01110001"; --71
when others => segdata <="01111111";
end case ;
end process P3;
-- Use Pin 49 (CLK1) for syncrounous clocking on LGLite, set ext clock
-- NET "LG_Xclk"
LOC = "P205"; new added for synchronous sampling
Header1(3 downto 0) <= state16;
LG_Xclk
<= clkdiv(12);
end Behavioral;
UCF file:
NET "clk100k" LOC = "P77" ;
NET "LG_Xclk"
LOC = "P205";
NET "Header1<0>" LOC = "P2" ;
ELEVATOR:
library IEEE;
entity TKBELE is
Port ( Header1 : inout std_logic_vector(7 downto 0);
clk100k : in std_logic);
end TKBELE;
architecture behavioral of TKBELE is
signal scurflr,snxtflr,skeyflr : integer range 0 to 15;
signal sdir, skeyhit : std_logic;
signal skeyscn : std_logic_vector(3 downto 0);
signal lkeyscn : std_logic_vector(3 downto 0);
signal lkeyret : std_logic_vector(3 downto 0);
signal sclkdiv : std_logic_vector(15 downto 0);
signal sflrclk,skeyclk : std_logic;
signal sshiftcount : std_logic_vector(2 downto 0);
signal sshiftreg : std_logic_vector(7 downto 0);
alias pkeyret : std_logic_vector(3 downto 0) is Header1(3 downto 0);
alias pkeyscn : std_logic_vector(7 downto 4) is Header1(7 downto 4);
alias pclk100k : std_logic is clk100k;
alias pdspmux : std_logic_vector(3 downto 0) is Header2(7 downto 4);
alias pdspseg : std_logic_vector(6 downto 0) is Header3(6 downto 0);
begin
-- process keypress
process(pkeyret)
begin
case pkeyret is
when "1110" => skeyhit <= '1';
when "1101" => skeyhit <= '1';
when "1011" => skeyhit <= '1';
when "0111" => skeyhit <= '1';
when others => skeyhit <= '0';
end case;
end process;
process(skeyhit)
begin
if( rising_edge(skeyhit)) then

lkeyscn <= skeyscn;
lkeyret <= pkeyret;
end if;
end process;
-- process keyval
process(skeyhit)
begin
if( rising_edge(skeyhit)) then
if(lkeyscn = "1110" and lkeyret = "1110")
then skeyflr <= 0;
elsif(lkeyscn = "1110" and lkeyret = "1101")
then skeyflr <= 1;
then skeyflr <= 2;
then skeyflr <= 3;
then skeyflr <= 4;
then skeyflr <= 5;
then skeyflr <= 6;
then skeyflr <= 7;
then skeyflr <= 8;
then skeyflr <= 9;
then skeyflr <= 10;
then skeyflr <= 11;
then skeyflr <= 12;
then skeyflr <= 13;
then skeyflr <= 14;
then skeyflr <= 15;
end if;
end if;
end process;
-- process clk divider-process(pclk100k)

begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;
skeyclk <= sclkdiv(6);
sflrclk <= sclkdiv(15);
end process;
-- process for key scan clkscan
process(skeyclk)
begin
if(rising_edge(skeyclk)) then
if skeyscn = "1110" then skeyscn <= "1101";
elsif skeyscn = "1101" then skeyscn <= "1011";
else skeyscn <= "1110";
end if;
end if;
pkeyscn <= skeyscn;
end process;
-- process floor motion
process(sflrclk)
begin
if(rising_edge(sflrclk)) then
if(not (skeyflr = scurflr) ) then
if(skeyflr > scurflr) then scurflr <= scurflr+1;
else scurflr <= scurflr-1;
end if;
end if;
end if;
end process;
-- process display 7seg
process(scurflr)
type tseg7 is array(0 to 15) of std_logic_vector (6 downto 0);
constant segval
: tseg7 :=
("0111111","0000110","1011011","1001111","1100110","1101101","1111101","0000111"
,"1111111","1101111","1110111","1111100","1011000","1011110","1111001","1110001")
;
begin
pdspseg <= segval(scurflr);
pdspmux <= "1110";
end process;
-- supress errors for pins not used
Header2(3 downto 0) <= "0000";
Header3(7) <= '0';
end behavioral;
UCF File:
NET "clk100k" LOC = "P77" ;

HDL Interfacing

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DCMOTOR

elsif(psw = "010" and sclkdiv = "011111010000") then vdcm := '0';

if( rising_edge(skeyhit)) then

-- process clk divider-process(pclk100k)

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