CONTENTS

Chapter no.

Title

Pg. No.

List Of abbreviation

II

List Of figures

III

List Of tables

IV

Introduction

01

Background and Previous Work

04

2.1 Basics Of Mcml

04

2.2 Mcml Vs Cmos

04

2.3 Previous Work In Mixed Signal Circuits

08

Cs-Cmos Logic

10

3.1 Static Transfer Characteristics

10

3.1 Dynamic Transfer Characteristics

13

Current Supply Spikes

18

CS-Cmos Gates

20

Decimation Filter and Frequency Divider

22

Experimental Results

24

Conclusion

27

References

28

LIST OF ABBREVIATION

SoC........................................
SILICON ON CHIP
CMOS...................................
COMPLEMENTARY METAL OXIDE SEMICONDUCTOR
CPL.......................................
COMPLEMENTARY PASS-TRANSISTOR LOGIC
DCVSL.................................
DIFFERENTIAL CASCODE VOLTAGE SWITCH LOGIC
CML......................................
CURRENT MODE LOGIC
CSL.......................................
CURRENT STEERING LOGIC
CBL.......................................
CURRENT BALANCED LOGIC
CS-CMOS.............................
CURRENT STEERING COMPLEMENTARY MOSFET
VLSI........................

VERY LARGE SCALE INTEGRATED CIRCUITS

ii

LIST OF FIGURES

Sl.no:

Name of figures

Page no:

1.1

Carrier injection through the substrate

1.2

Package parasitic induces noise in the on-chip supply-ground

2.1

Classical MOS Logic Inverter

2.2

Classical MOS Logic Inverter WITH OUTPUT ZERO

2.3

Classical MOS Logic Inverter WITH OUTPUT ONE

2.4

Transfer characteristics of a Classical MOS Logic Inverter

2.5

Current vs. Input Voltage for the Classical MOS Logic

2.6

MOS Current mode Logic Inverter

2.7

Transfer characteristics of a MCML inverter

2.8

Current steering Logic Inverter

2.9

Inverter voltage transfer curve

3.1

CS-CMOS Inverter

10

3.2

DC voltage transfer characteristics of the CS-CMOS inverter

12

3.3

CSL and CBL inverter

14

3.4

Propagation delay for CSL, CBL, and CS-CMOS inverters

15

3.5

Energy Delay Product for CBL, CSL, and CS-CMOS

16

3.6

figure of merit for CBL, CSL, and CS-CMOS inverters

16

4.1

Parasitic capacitances in a CS-CMOS inverter

18

6.1

Decimation filter used for comparing CS-CMOS and CSL

22

7.1

Die photograph of the 15stage CS-CMOS

24

7.2

Measured propagation delay for various bias

24

7.3

Comparison of energy delay products of CSL and CS-CMOS

25

7.4

Measured propagation delay for variations in supply voltage

25

iii

LIST OF TABLES

Sl.no:

Name of figures

Page no:

Device dimension for CS-SMOS,CSL and CBL

11

II

Figure of merit for logic families

17

III

Propagation delay for ISCAS85 benchmarks circuits

21

IV

Propagation delay for the filter and freq. divider

23

iv