module Bisseccao(xE, xD,clk,xm);

input [31:0] xE, xD;

reg [31:0] xtemp, xtemp1, erro,erro1,eps, xd, xe,r1,r2;
reg [1:0] reset;
input clk;
output [63:0] xm;
initial begin
reset=0;
erro=32'b0000_1000;
eps= 32'b0000_0001;
end
always@(negedge clk)
begin
if(reset==1)
begin
r1= (2*xe - 3*xe)+30;
r2= (2*xm - 3*xm) +30;
end
if(reset==0)
begin
xd = xD;
xe = xE;
end
else
begin
if ((r1[31]==0 & r2[31]==0) || (r1[31]==1 & r2[31]==1))
begin
xe=xtemp1;
end
else
begin
xd=xtemp1;
end
erro1= xd - xe;
if(erro1[7]==1)
begin
erro1=erro1*(-1);
end
end
end
always@(posedge clk)
begin
reset=1;
if(erro1>eps)
begin
xtemp=xe+xd;
if(xtemp[31]==1)
begin

xtemp1 = xtemp>>1;
xtemp1[31]=1;
end
else
begin
xtemp1 = xtemp>>1;
end
end
end
assign xm = xtemp1;
endmodule