Lab 6: Introduction to Logic

Simulation and Verilog

Kevin Bradshaw
ECEN 248: Introduction to Digital Design, Section 302
TA: Daniel Mcbride
Due date: July 15, 2014

Objectives:
The purpose of this lab is to learn the basics of Verilog coding in order to test larger circuits in an
efficient manner. Instead of building the circuits designed on a breadboard, they are simulated
with Verilog, a standard Hardware Description Language. This helps the students reinforce their
knowledge on digital logic concepts learned in lecture.

Design
Using the information given in the Pre-Lab and background section of the manual, the circuits
were written in Verilog in ISE Design Suite. The source code for experiments one and two are
attached to this document.

The first source code implements a gate-level schematic of a 1-bit wide, 2:1 MUX. This
initial design introduces the students how to define a module, declare inputs and outputs,
declare internal nets, and instantiate modules.
The second source code implements the same gate-level schematic as the first source
code four times, all wired together to create a 4-bit wide, 2:1 MUX.
The third source code implements a gate-level schematic of a full-adder. This is similar to
the first source code but in addition uses dataflow to describe the gate-level activity.
The fourth source code implements the same gate-level schematic as the third source
code four times, all wired together to create an Addition/Subtraction Unit with overflow
detection.

Results
Experiment 1
All Verilog codes compiled and ran successfully, implementing the 1-bit wide 2:1 MUX. Figure
1 shows the waveform of the first source code.
Figure 1:
1-bit wide,
2:1 MUX

Experiment 2
The results of experiment 2 show how code can be tied together to implement circuits that utilize
the building blocks of digital logic. If these circuits were to be built on a breadboard, they would
take far too much time and wiring. Figure 2 shows the waveform of the first part of experiment
2.
Figure 2:
4-bit wide,
2:1 MUX

The second part of experiment 2 implements a full-adder. This is a little more complicated than a
2:1 MUX because it contains 3 inputs and 2 outputs. Figure 3shows the waveform for the fulladder
Figure 3:
Full-Adder

The third part of experiment 2 implements four full adders that indicates binary algebra with a 4bit result and overflow detection. It can do both operations, addition and subtraction, by
changing the input port opSel. Figure 4 shows the waveform for the Addition/Subtraction Unit.
Figure 4:
Addition/
Subtraction
Unit

Experiment 3
This experiment was cancelled, therefore no information is available.

Post-Lab Questions
1. Examine the 1-bit, 2:1 MUX test bench code. Attempt to understand what is going on in the
code. The test bench is written using behavior Verilog, which will read much like a
programming language. Explain briey what it is the test bench is doing.
The test bench code for the 2:1 MUX uses the first source code written and tests it to see if it's
valid, if so, it displays a message on the console of ISE Design. It also keeps track of the number
of tests passed.
2. Examine the 4-bit, 2:1 MUX test bench code. Are all of the possible input cases being tested?
Why or why not?
The only input not being tested is S, because this only selects the input of the MUX.

3. In this lab, we approached circuit design in a different way compared to previous labs.
Compare and contrast bread-boarding techniques with circuit simulation. Discuss the advantages
and disadvantages of both. Which do you prefer? Similarly, provide some insight as to why
HDLs might be preferred over schematics for circuit representation. Are there any disadvantages
to describing a circuit using an HDL compared to a schematic? Again, which would you prefer.
There are some major differences between the two techniques for testing a circuit. Breadboarding is direct and the designer doesn't have to worry about translating a circuit into Verilog
code. To build on a breadboard, it's simply following the picture of the schematic, the
disadvantage to this is that wires can't get messy, especially as the circuit gets more complicated.
Circuit simulation with HDL is very convenient, especially for those complicated circuits, and
can offer the user faster debugging of the circuit. The disadvantage is when it comes to coding, it
may compile correctly, but the translation for the schematic to the design may be incorrect. I still
prefer the bread-boarding method because it provides a more absolute answer. HDLs may be
preferred over schematics for circuit representation though since it allows easier simulations of
complicated circuits with unlimited circuit tools.
4. Two different levels of abstraction were introduced in this lab, namely structural and dataow.
Provide a comparison of these approaches. When might you use one over the other?
Structural is used for low level gate schematics and dataflow is used in higher level complicated
schematics that incorporate smaller circuit designs into a sequence.

Conclusion
In this lab, all the source codes worked properly to show how HDL circuit representation is a
convenient way for electrical engineers to test circuits. By writing code in Verilog and then
assessing it with the test bench code, I was able to demonstrate how to translate a simple
schematic into written code. The results shown helped me understand waveforms that are
displayed in timing diagrams. These diagrams show at what moment the outputs of the circuit are
producing voltages which in turn interpret information such as numbers in binary algebra. By
following the procedure in the lab, I learned why HDL's are important to electrical engineering
practices.

Student Feedback
1. What did you like most about the lab assignment and why? What did you like least about it
and why?
I liked this lab because it took a lot less time to do four different circuits than it would have taken
one bread boarded circuit. Debugging the code was my least favorite parts, mainly because I'm a
beginner coder.

2. Were there any sections of the lab manual that were unclear? The Pre-Lab could have been a
little more detailed to better explain the type of circuits that were going to be needed in the
design.
The translation between the schematic and the codes for each design could have been more
detailed.
3. What suggestions do you have to improve the overall lab assignment?
To improve the lab assignment, there should be more instruction on how to debug the Verilog
code.