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Lab 8: Introduction to Sequential

Logic
Kevin Bradshaw
ECEN 248: Introduction to Digital Design, Section 302
TA: Daniel Mcbride
Due date: July 29, 2014

Objectives:
The purpose of this lab is to learn about sequential logic circuits using Verilog. Different
methods of storage techniques will be used by covering circuits that use latches and flip-flops.
This introduction allows the students to use the building blocks of digital logic in higher level
abstraction to write better code than describing every gate-level structure. By building one
building block and using the same defined module in series or parallel, a variety of useful
circuits can be built and tested. This helps students learn the hierarchy of abstraction in coding.

Design
Using the information given in the Pre-Lab and background section of the manual, the circuits
were written in Verilog in ISE Design Suite. The source code for experiments one and two are
attached to this document.
The first source code implements a SR Latch using structural Verilog and built-in gate
level primitives. This design uses the basic abstraction levels learned in the previous labs
to build a basic memory storage circuit with the introduction of unit delays.
The second source code implements a D Latch, again using structural Verilog and built-in
gate level primitives.. This design also uses basic abstraction levels and unit delays.
The third source code is the last design using only structural Verilog and built-in gate
level primitives in order to implement a D Flip-Flop. This is done by instantiating the D
latches created with the second source code.
The fourth source code implements another D Latch, this time using a behavioral model
to show a higher level of abstraction in Verilog. It describes the behavior of a D Latch
using an always statement.
The fifth source code implements another D Flip-Flop, this time using a behavioral model
again to show a higher level of abstraction in Verilog. It describes the behavior of a D
Flip-Flop using an always statement and a non-blocking assignment statement.
The sixth source code is the same full adder designed in lab 6, only this time, unit delays
are added to each gate-level assignment.
The seventh source code implements a 2-bit Ripple Carry Adder using structural Verilog
to instantiate the full adder designed with unit delays.
The eighth source code implements a Synchronous Adder using the 2-bit Ripple Carry
Adder used in the previous source code and behavioral modeling.
The ninth source code is the modified test bench file for the Synchronous Adder.

Results
Experiment 1
All Verilog codes compiled and ran successfully. Figure 1 shows the waveform of the SR Latch
which follows the characteristics table given in the background section of the lab.
Figure 1:
SR Latch, 2 Unit Delays

Table 1: SR Latch Function Table


En
0
1
1
1
1

S
X
0
0
1
1

R
X
0
1
0
1

Q
Q'
HOLD
HOLD
0
1
1
0
UNDEFINED

Figure 2 shows the waveform for the same SR Latch, but this time, the unit delays were
increased to 4 instead of 2. Some of the tests failed because there was too much of a delay when
switching from Enable to Hold
Figure 2:
SR Latch,
4 Unit Delays

Figure 3 is a simulation of the first D Latch using gate-level construction. Figure 4 is a


simulation of the first D Flip-Flop also using gate-level construction. The Flip-Flop was
instantiated using only two D Latch modules and two inverter gates, all four with unit delays.
The latches do not behave as expected because some of the tests failed. This happened because
flip-flops use the positive edge of a clock, not the active level, and by using structural and gate
level primitives, this can't be defined. The D Flip-Flop behavioral model shows the working
circuit because this can be described easily using a trigger edge and a non-blocking assignment
statement.
Figure 3:
Figure 4:
D Latch
D Flip-Flop

Figure 5 is a simulation of the second D Latch using behavioral modeling. Figure 6 is a


simulation of the second D Flip-Flop also using behavioral modeling. Compared to the structural
models, both these waveforms pass the tests because of how their described with triggers.
Figure 5
Figure 6
D Latch using Behavioral Modeling
D Flip-Flop using Behavioral Modeling

Experiment 2
Experiment 2 shows how building gate-level modules for memory storage circuits can be
manipulated together with behavioral modeling to describe a 2-bit Ripple Carry Adder and a
Synchronous Adder. Figure 7 shows the waveform for the first circuit. The worst propagation
delay would be 16 ns for the path of the output Carry. This is calculated because two AND gates
with two inputs are 4 ns each and two OR gates with two inputs are also 4 ns each. Four gates,
each at 4 ns makes a 16 ns delay.
Figure 7:
2-bit Ripple Carry Adder

Figure 8 shows the waveform for Synchronous Adder using the 2-bit Ripple Carry Adder
combined with four flip-flops.
Figure 9: Synchronous Adder with a Lower
Figure 8: Synchronous Adder
Clock Rate

Figure 9 shows the waveform for the same circuit but with a lower clock rate. This shows the
proper propagation delay for the ripple adder.

Post-Lab Questions
1. Compare the behavioral description of the synchronous adder found in the test bench code
with the combination of structural and dataflow Verilog you used in the lab assignment. What
are the advantages and disadvantages of each? Which do you prefer and why?
The advantage of the behavioral description is that there is less code and its more efficient. The
disadvantage is that it's harder to understand why and how its behaving at a certain instance
because structural and dataflow Verilog describes the all the way down to each gate.
2. Based on the clock period you measured for your synchronous adder, what would be the
theoretical maximum clock rate? What would be the effect of increasing the width of the adder
on the clock rate? How might you improve the clock rate of the design.
The theoretical maximum clock rate would be 16 ns, explained with Figure 7. By increasing the
width of the adder on the clock rate, it minimizes the output delay until a certain threshold. To
improve the clock rate of the design, a Carry Look-ahead Generator could be added to the circuit.

Conclusion
In this lab, all the source codes worked properly showing how higher level abstraction to
manipulate modules designed by the student can be instantiated together to build memory
storage units. By testing the code with structural and dataflow methods, then by testing the code
with behavioral methods, I was able to demonstrate how describing modules can be in different
instances of coding. The results I obtained helped me better understand how Verilog can be
much easier than building and testing an entire circuit on a breadboard.

Student Feedback
1. What did you like most about the lab assignment and why? What did you like least about it
and why?
I liked this lab because I learned how to reuse code I previously wrote to efficiently build new
circuits. I didn't like that there were so many different parts to the experiment.
2. Were there any sections of the lab manual that were unclear?
The lab manual could have been more in depth in the comments for students to better understand
what statements were exactly doing in the code.

3. What suggestions do you have to improve the overall lab assignment?


To improve the lab assignment, there should be more descriptions on what tests do and why in
the test bench files.