Processor Implementation

ECE437: Introduction to
Digital Computer Design
Output
Control

Mithuna Thottethodi
Chapter 4

Memory
Datapath

Input

Fall 2014
ECE437, Fall 2014

Outline

(2)

Datapath for Instructions

Datapath - single cycle

single instruction, 2s complement, unsigned

Control

Single cycle datapath

Compose using well-understood pieces
Mux, flip-flops and gates
ALU
Register file

ECE437, Fall 2014

ECE437, Fall 2014

(3)

Comb. Logic Elements

(4)

Storage Elements

CarryIn
A

Adder

Adder

32

32

Sum
Carry

32

32

ALU

ALU

32

(5)

busW
32
Clk

Memory

Selec
t
32

MUX

32

busA
32
32 32-bit
32 bit
Registers busB

Write Enable

1 input bus
1 output bus
Not bidirectional

Data In
32
Clk

32
ECE437, Fall 2014

Data Out
N

Clk
RW RARB
Write Enable 5 5 5

for PC

32 registers
2 read ports/buses
1 write port/bus

Result

32

Mux
ECE437, Fall 2014

Register
Register file

O
P

Write Enable
Data In
N

Address
DataOut
32

(6)

Computer as State Machine

Processor Implementation
This Lecture: Datapath

Storage
Output
Control
Comb. Logic
Memory
Datapath

Storage elements

Input

Memory, Register file, PC

Combinational elements
ALUs, Adders, Muxes

ECE437, Fall 2014

ECE437, Fall 2014

(7)

Rs

Assumption: Get one whole instruction

done in one long cycle

nPC_sel

Rs

Rt
5

busA
Rw Ra
R
R Rb
32
32 32-bit
You will busB
design this
Registers
0
32

Clk
Clk
imm16

16

Extender

Adder

(9)

Outline
Datapath - single cycle

single instruction, 2s complement, unsigned

Control

ECE437, Fall 2014

32
Data In

32
Clk

32
WrEn Adr

Data
Memory

ALUSrc

(10)

Register Transfer Language

op | rs | rt | rd | shamt | funct = MEM[ PC ]
op | rs | rt | Imm16

= MEM[ PC ]

Register Transfers

ADDU

R[rd] < R[rs] + R[rt];

PC < PC + 4

SUBU

R[rd] < R[rs] R[rt];

PC < PC + 4

ORi

R[rt] < R[rs] OR zero_ext(Imm16);

PC < PC + 4

LOAD

R[rt] < MEM[ R[rs] + sign_ext(Imm16)]; PC < PC + 4

STORE

MEM[ R[rs] + sign_ext(Imm16) ] < R[rt]; PC < PC + 4

BEQ

(11)

!!

RTL gives the meaning of the instructions

All start by fetching the instruction

inst

ECE437, Fall 2014

MemtoReg

Mux

00

ExtOp
ECE437, Fall 2014

ALUctr MemWr

Equal

ALU

32

Imm16

Mux

PC

Mux

busW

Rd

RegWr 5

Add
der

PC Ext

imm16

Rt

Rd Rt
1

fetch, decode/read operands, execute,

memory writeback
memory,
useful way to represent steps and identify
required datapath elements: RTL

For single instruction

Put it together

RegDst

Instruction<31:0>

<0:15>

Adr

<11:15>

Inst
Memory

<16:20>

<21:25>

Datapath - 1 CPI

(8)

ECE437, Fall 2014

if ( R[rs] == R[rt] ) then PC < PC +

sign_ext(Imm16)] || 00
else PC < PC + 4
(12)

A Simple Implementation
ADD and SUB

addU rd, rs, rt

subU rd, rs, rt

31

OR Immediate:

ori rt, rs, imm16

lw rt, rs, imm16

sw rt, rs, imm16

21
rs
5 bits

16
rt
5 bits

31

26

21

16

31

op
6 bits
26
op
6 bits

rs
5 bits
21
rs
5 bits

rt
5 bits
16
rt
5 bits

31

26

BRANCH:

21

op
6 bits

beq rs, rt, imm16

ECE437, Fall 2014

rs
5 bits

11
rd
5 bits

6
shamt
5 bits

0
funct
6 bits

Fetch instruction, then update PC

PC updated (at the end of) every cycle
What if no branches or jumps?

0
immediate
16 bits
0

Next Address
Logic

PC

Clk

immediate
16 bits

16

rt
5 bits

Address

immediate
16 bits

Instruction Word

Instruction
Memory

32

ECE437, Fall 2014

(13)

ALU Instructions
R[rd] <- R[rs] op R[rt] Example: addU

(14)

Logical operation with Immediate

R[rt] <- R[rs] op ZeroExt[imm16] ]

rd, rs, rt

31

Ra, Rb, and Rw come from instructions rs, rt, and rd fields
ALUctr and RegWr: control logic after decoding the
instruction
31

26

21

op
6 bits

16

rs
5 bits

11

rt
5 bits

rd
5 bits

RegDst

funct
6 bits

32

32

32

imm16

16

Result
32

Mux

busB
32
ZeroExt

busB

immediate
16 bits

ALUctr

32 32-bit
Registers

32
Clk

Result

busA
ALU

32

Rs
5
5

Rw Ra Rb

busW

ALU

busW
32
Clk

11
16
rt
immediate
5 bits
16 bits
rd?
16 15

Mux

ALUctr
busA

Rw Ra Rb
32 32-bit
Registers

21
rs
5 bits

0000000000000000
16 bits

Rt

Rd

RegWr 5
Rd Rs Rt
RegWr 5 5
5

26
op
6 bits

31

shamt
5 bits

Next Address
Logic

Adder

LOAD and
STORE Word

26
op
6 bits

Fetch Instructions

32
ALUSrc

ECE437, Fall 2014

ECE437, Fall 2014

(15)

(16)

Load Instruction

R[rt] <- Mem[R[rs] + SignExt[imm16]]

31

26

21

op
Rd
RegDst

Mux
RegWr 5

Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: sw rt, imm16(rs)

31

26
op
6 bits

immediate

5 bits

rd

16 bits
Rd

Rs
5
5
b A
busA

Data
Memory

ALUctr

MemWr

W_Src

32
Clk

Rs
5

Rt
5

Rw Ra Rb
32 32-bit
Registers

32
imm16

16

busA
32
busB
32

32
WrEn Adr

Data In 32

32

Mux

Data In
32
Clk

0
immediate
16 bits

Mux

WrEn Adr

16
rt
5 bits

Rt

Extender

ALUSrc

Mux

Mux

Extender

32

busW

32
MemWr

21
rs
5 bits

Mux
RegWr 5

W S
W_Src

32
busB
32

16

RegDst

ALUctr

Rw Ra Rb
32 32-bit
Registers

imm16

ALU

32
Clk

5 bits

Store Instruction

rt, imm16(rs)
11

16
rt

ALU

busW

rs

6 bits

Rt

Example: lw

Clk

Data
Memory

32

ExtOp
ECE437, Fall 2014

(17)

ECE437, Fall 2014

(18)

Conditional Branch Instruction

26

21

op

16

rs

6 bits

5 bits

Datapath generates condition (equal)

rt

Datapath for beq

rs, rt, imm16

31

immediate

5 bits

16 bits

26
op
6 bits

beq rs, rt, imm16

A
Adder

32
Data In

32

00

ExtOp

Clk

32

busA
32
busB
32

00

Clk

(20)

ORI is not in the book

ORI shows that some instructions need
zero extension instead of sign extension

0
Mux

16

ALU

imm16

Rw Ra Rb
32 32-bit
Registers

Logical
L i l vs. arithmetic
ith ti ops

=
32
Mux

imm16

Rt

Extender

PC Ext

Adder

Clk

ECE437, Fall 2014

MemtoReg

busA
Rw Ra
R
R Rb
32 32-bit
Registers
busB
32

Clk

PC

Mux

Rs
5

Adder

<0:15>

<11:15>

Mux

PC

Add
der

32

ALUctr MemWr

busW

Rt

ORI

Imm16
Equal

RegWr 5

Rs

Clk

Instruction<31:0>

RegWr 5
busW

Rd

Rd Rt
1

Rt

Cond
32

ECE437, Fall 2014

<16:20>

<21:25>

Rs
RegDst

PCSrc

PC Ext

imm16

(19)

Adr

immediate
16 bits

PCSrc

What is this?

Inst
Memory

16
rt
5 bits

Inst Address

IR = Mem[PC] // Fetch the instruction from memory

COND <<- R[rs] == R[rt] // Calculate the branch condition
if (COND eq 0) // Calculate the next instructions address
PC <- PC + 4 + ( SignExt(imm16) x 4 )
else
PC <- PC + 4

ECE437, Fall 2014

21
rs
5 bits

Equal?

31

beq

WrEn Adr
Data
Memory

What will change in the datapath if ORI

is absent?

ALUSrc

(21)

ECE437, Fall 2014

Exercise

(22)

Worksheet
The image cannot be display ed. Your computer may not hav e enough memory to open the image, or the image may hav e been corrupted. Restart y our computer, and then open the file again. If the red x still appears, y ou may hav e to delete the image and then insert it again.

See worksheet (Fig 4.15)

Highlight active datapath for

Add
B
Beq
Sw
Lw

ECE437, Fall 2014

(23)

ECE437, Fall 2014

(24)

4
00

imm16

16

Exercise

32
Data In

32

Mux

Clk
Clk

ECE437, Fall 2014

(25)

MemtoReg

=
32

ALU

32

Extender

imm16

Rs Rt
5
5
busA
Rw Ra
R
R Rb
32 32-bit
Registers
busB
32

WrEn Adr

32
Clk

ExtOp
ECE437, Fall 2014

ALUctr MemWr

Equal

Mux

Adder

PC Ext

Selection controls for muxes

ALU controls for ALU ops
Register address controls
Write enables for registers/memory

busW

PC

Mux

Controls : later

Imm16

RegWr 5

Add
der

Rinse and repeat

Reuse components by using muxes

Rd

Rd Rt
1

To add instructions

Rt

Instruction<31:0>

<0:15>

Rs
RegDst

PCSrc

<11:15>

Adr

Describe operation in RTL

Use ALUs, Registers, Memory, adders to achieve
reqd. functionality

<16:20>

Inst
Memory

For a given instruction

<21:25>

Summary

Data
Memory

ALUSrc

(26)

Control for Datapath

Instruction<31:0>

Rt

op

Imm16

target address

PCSrc RegWr RegDst ExtOp ALUSrc ALUctr MemWr MemtoReg

(27)

Textbook version

Equal

jump

See worksheet #1
ECE437, Fall 2014

Rd

Control

PC <- (PC+4)[31:28] // Addr // 00

J-type

Rs

<0:15>

Op Fun

j Addr
RTL

<11:15>

Adr

<16:20>

Add jump instruction to single cycle

datapath

<21:25>

<21:25>

Inst
Memory

DATA PATH

ECE437, Fall 2014

(28)

Controls for Add Operation

R[rd] = R[rs] + R[rt]
Instruction<31:0>

RegWr = 1 5

ALUctr = Add

Rt

Rt

32

Imm16

1
32

MemWr = 0
0

32
32
WrEn Adr

Data In 32
Clk

Mux

ALU

16

Extender

imm16

Zero

Mux

Rw Ra Rb
32 32-bit
Registers
busB
32

32
Clk

Rd

MemtoReg = 0
busA

busW

Rs

<0:15>

Clk
Rs

<11:15>

Rt

1 Mux 0

<16:20>

Rd
RegDst = 1

Instruction
Fetch Unit

<21:25>

PCSrc= +4

Data
Memory

ALUSrc = 0
ExtOp = x
ECE437, Fall 2014

(29)

ECE437, Fall 2014

(30)

Meaning of Control Signals

rs, rt, rd and imm16 hardwired in datapath

PCSrc:
0 => PC < PC + 4; 1 => PC < PC + 4 + SignExt(Im16) || 00

Meaning of Control Signals

ExtOp:
ALUsrc:
ALUctr:

zero, sign
0 => regB; 1 => immed
add, sub, or

Inst
Memory

RegDst

Rs

16

00

=
32
0

ORI Controls: Worksheet

ALUSrc

(32)

ORI Controls: Solution

R[rt] <- R[rs] or ZeroExt[Imm16]

R[rt] <- R[rs] or ZeroExt[Imm16]

Instruction<31:0>

5
busA

RegWr = 1 5

32

busA

Rw Ra Rb
32 32-bit
Registers
busB
32

32
Clk

WrEn Adr
Data In 32

Data
Memory

Clk

imm16

16

LW Controls

Clk

Instruction<31:0>

16

1
32

Rd

32
32
WrEn Adr

Data In 32
Clk

Imm16

MemWr =

Mux

imm16

32

Rs

<0:15>

Rw Ra Rb
32 32-bit
Registers
busB
32

32
Clk

Zero

<11:15>

32

Rt

ALUctr =

ALU

Data
Memory

Rt

Mux

Clk

WrEn Adr
Data In 32

Rs

busA

busW
0

32

Clk

1 Mux 0

RegWr =

<16:20>

MemWr = 0

RegDst =

Instruction
Fetch Unit

<21:25>

Imm16
MemtoReg = 1

Rt

Extender

32

Rd

Mux

Rs

Rd

Data
Memory

ALUSrc =

ALUSrc = 1
ExtOp =

ExtOp = 1
ECE437, Fall 2014

Data
Memory

R[rt] -> Data Memory {R[rs] + SignExt[imm16]}

<0:15>

Zero
ALU

16

Extender

imm16

Data In 32

PCSrc=

<11:15>

Rt

Mux

32
Clk

WrEn Adr

SW Controls: Worksheet
<16:20>

ALUctr
= Add

Rt

busA
Rw Ra Rb
32
32 32-bit
Registers
busB
0
32

busW

<21:25>

Instruction
Fetch Unit

Clk

1 Mux 0

RegWr = 1 5

32

(34)

Instruction<31:0>
PCSrc= +4

Rs

MemWr = 0

ExtOp = 0

R[rt] <- Data Memory {R[rs] + SignExt[imm16]}

Rt

Imm16
MemtoReg = 0

32

32

ECE437, Fall 2014

(33)

Rd

Rd

ALUSrc = 1

ExtOp =

RegDst = 0

Rs

Zero

32

ALUSrc =

ECE437, Fall 2014

Rt

ALUctr = Or

Mux

32

Rt

ALU

Clk
Rs

Mux

1
32

MemWr =

Rt

1 Mux 0

Extender

16

MemtoReg =

Rd
RegDst = 0

busW

ALU

Extender

imm16

Zero

32
Mux

32
Clk

Imm16

Mux

Rw Ra Rb
32 32-bit
Registers
busB
32

busW

Rd

<0:15>

ALUctr =

Rs

<11:15>

Rt

Instruction
Fetch Unit

<16:20>

RegWr =

Rt

PCSrc= +4

<21:25>

Rs

<0:15>

Clk

1 Mux 0

Instruction<31:0>

<11:15>

Rt

<21:25>

Rd
RegDst =

Instruction
Fetch Unit

<16:20>

PCSrc=

Data
Memory

Clk

ECE437, Fall 2014

(31)

WrEn Adr

32

ExtOp
ECE437, Fall 2014

32
Data In

32

Mux

imm16

Rt

ALU

Adder

PC Ext

imm16

Clk

0 => rt; 1 => rd

Mux

Clk

RegDst:

Extender

Mux

PC

Adder

32

busA
Rw Ra Rb
32 32-bit
Registers
busB
32

busW

1 => Mem

RegWr 5
4

write memory

MemtoReg:

RegWr:
write dest register
ALUctr MemWr MemtoReg
Equal

Rd Rt
1

Addr

PCSrc

MemWr:

(35)

ECE437, Fall 2014

(36)

SW Controls: Solution

BEQ Controls
if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0

R[rt] <- Data Memory {R[rs] + SignExt[imm16]}

Instruction<31:0>

Data
Memory

imm16

16

1
32

Imm16
MemtoReg = x

32
32
WrEn Adr

Data In 32
Clk

Data
Memory

ExtOp = x
(37)

ECE437, Fall 2014

Summary of Control Signals

(38)

Control Logic

Register Transfer

ADD
R[rd] < R[rs] + R[rt];
PC < PC + 4
ALUsrc = RegB, ALUctr = add, RegDst = rd, RegWr, PCSrc = +4
SUB
R[rd] < R[rs] R[rt];
PC < PC + 4
ALUsrc = RegB, ALUctr = sub, RegDst = rd, RegWr, PCSrc = +4
ORi
R[rt] < R[rs] + zero_ext(Imm16);
PC < PC + 4
ALUsrc = Im
Im, Extop = Z
Z , ALUctr = or
or , RegDst = rt
rt, RegWr,
RegWr PCSrc =
+4
LOAD
R[rt] < MEM[ R[rs] + sign_ext(Imm16)]; PC < PC + 4
ALUsrc = Im, Extop = Sn, ALUctr = add,
MemtoReg, RegDst = rt, RegWr, PCSrc = +4
STORE MEM[ R[rs] + sign_ext(Imm16)] < R[rs]; PC < PC + 4
ALUsrc = Im, Extop = Sn, ALUctr = add, MemWr, PCSrc = +4

Logic must generate appropriate signals

for all instructions
Summary slide (previous)
A way of
f representing
ti the
th ttruth
th ttable
bl

First:
Equations in terms of opcodes

Next
Equations in terms of instruction bits

BEQ
if ( R[rs] == R[rt] ) then PC < PC + sign_ext(Imm16)] || 00 else PC
< PC + 4;
ALUsrc = RegB, PCSrc = Beq AND ZERO, ALUctr = sub
ECE437, Fall 2014

(39)

ECE437, Fall 2014

Controls: Logic equations

Rd

ALUSrc = 0

ExtOp = 1

inst

32

Rs

M W =0
MemWr

Mux

Rw Ra Rb
32 32-bit
Registers
busB
32

32
Clk

ALUSrc = 1

ECE437, Fall 2014

Rt
Z
Zero

<0:15>

ALUctr =
Subtract

<11:15>

Clk

Mux

WrEn Adr
Data In 32

32

Rt
b A
busA

busW

32

Rs

Extender

RegWr = 0

32

Clk

1 Mux 0

M W =1
MemWr

Mux

RegDst = x

Imm16

Instruction
Fetch Unit

ALU

32

ALU

16

Extender

imm16

Z
Zero

Mux

Rw Ra Rb
32 32-bit
Registers
busB
32

32
Clk

Rd

MemtoReg = x

busA

busW

Rs

Rt

<16:20>

Rt

PCSrc= Br
Rd

<21:25>

ALUctr
= Add

Rt

<0:15>

Rs

Instruction<31:0>

<11:15>

Clk

1 Mux 0

RegWr = 0 5

Instruction
Fetch Unit

<16:20>

RegDst = x

Rt

<21:25>

PCSrc= +4
Rd

PCSrc

(40)

Controls: Logic equations

<= if (OP == BEQ) then ZERO else 0

PCSrc

<= if (OP == BEQ) then EQUAL else 0

ALUsrc

<= if (OP == R-type) then regB

elseif (OP == BEQ) then regB, else imm

ALUctr

<= if (OP == R-type) then funct

elseif (OP == ORi) then OR
elseif (OP == BEQ) then sub
else add
<= if (OP == ORi) then
th zero

else
l sign
i

ALUsrc

<=if (OP == R-type) then regB

elseif (OP == BEQ) then regB, else imm

ALUctr

<= if (OP == R-type) then funct

elseif (OP == ORi) then OR
elseif (OP == BEQ) then sub
else add

ExtOp

<= _____________

E tO
ExtOp

MemWr

<= _____________

MemWr

<= (OP == Store)

MemtoReg

<= _____________

MemtoReg

<= (OP == Load)

RegWr:

<= _____________

RegWr:

<= if ((OP == Store) || (OP == BEQ)) then 0 else 1

RegDst:

<= _____________

RegDst:

<= if ((OP == Load) || (OP == ORi)) then 0 else 1

ECE437, Fall 2014

(41)

ECE437, Fall 2014

(42)

Truth Table summary

See
Appendix A

Local vs Global Control

func 10 0000 10 0010

We Dont Care :-)
op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
add
sub
ori
lw
sw
beq
jump

RegDst
ALUSrc
MemtoReg
RegWrite

1
0
0
1

1
0
0
1

0
1
0
1

0
1
1
1

x
1
x
0

x
0
x
0

x
x
x
0

MemWrite
PCSrc

0
0

0
0

0
0

0
0

1
0

0
1

0
0

Jump
ExtOp

0
x

0
x

0
0

0
1

0
1

0
x

1
x

Add

Subtract

Or

Add

Add

Subtract

xxx

ALUctr<2:0>
31

26

21

16

R-type

op

rs

rt

I-type

op

rs

rt

J-type

op

11
rd

ALUctr

31

<= if (OP == R-type) then funct

elseif (OP == ORi) then OR
elseif (OP == BEQ) then sub
else add

26

R-type

21

op

funct

RegDst
ALUSrc
MemtoReg
RegWrite
MemWrite
Branch
Jump
ExtOp
ALUop<N:0>

ECE437, Fall 2014

0
1
0
1

0
1
1
1

x
1
x
0

x
0
x
0

x
x
x
0

0
0
0
x
R-type

0
0
0
0
Or

0
0
0
1
Add

1
0
0
1
Add

0
1
0
x

0
0
1
x
xxx

6
ALUop

(44)

ECE437, Fall 2014

func

Subtract

op

(1) R-type instructions

I-type instructions that require the ALU to perform:

(1) R-type instructions

I-type instructions that require the ALU to perform:

00 0000

lw

sw

beq

jump

RegDst
ALUSrc
MemtoReg
RegWrite

1
0
0

0
1
0

0
1
1

x
1
x

x
0
x

x
x
x

MemWrite
Branch
Jump
ExtOp
ALUop<2:0>

0
0

0
0

0
0

1
0

0
1

0
0

0
x
R-type
(100)

0
0
Or
(010)

0
1
Add
(000)

0
1
Add
(000)

0
x

1
x
xxx

Main
Control

func
6
ALUop

ECE437, Fall 2014

(47)

lw
Add
0 00

sw
Add
0 00

beq

jump
xxx
xxx

Subtract
0 01

(46)

op

00 0000

00 1101 10 0011 10 1011 00 0100 00 0010

R-type

ori

lw

sw

beq

jump

RegWrite

RegWrite = R-type + ori + lw

= !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0> (R-type)
+ !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0>
(ori)
+ op<5>
p
& !op<4>
p
& !op<3>
p
& !op<2>
p
& op<1>
p
& op<0>
p
((lw))
op<5>

..

op<5>

<0>

..

op<5>

<0>

..

..

op<5>

<0>

..

..

op<5>

<0>

op<5>

<0>

op<0>

ALUctr
3

R-type

ori

lw

sw

beq

jump
RegWrite

ALU

ALU
Control
(Local)

Subtract
(001)

ori
Or
0 10

Truth Table for RegWrite

00 1101 10 0011 10 1011 00 0100 00 0010

ori

R-type
R-type
1 00

ECE437, Fall 2014

R-type

op

(2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi)

ALUop (Symbolic)
ALUop<2:0>

Global Control: Truth Table

op

(2) Or, (3) Add, and (4) Subtract

To implement the full MIPS ISA, ALUop has to be 3 bits to

represent:

(45)

ALUctr
3

In this exercise, ALUop has to be 2 bits wide to represent:

ALUctr

ALU
Control
(Local)

ALU
Control
(Local)

6
ALUop
N

Main
Control

ALU

funct

Encoding

00 1101 10 0011 10 1011 00 0100 00 0010

ori
lw
sw
beq
jump

1
0
0
1

Main
Control

shamt

jump

func
op

rd

ori, lw, sw, beq

Global Control: Truth Table

00 0000
R-type

11

rt

add, sub

immediate

(43)

op

16

rs

shamt

target address

ECE437, Fall 2014

One more layer of abstraction

ECE437, Fall 2014

(48)

op<5>

..

PLA implementation
..

..

op<5>

<0>

op<5>

<0>

R-type

op<5>

..

<0>

ori

lw

op<5>

..

<0>

sw

op<5>

beq

PLA Representation

..

<0>

op<0>

jump

RegWrite
ALUSrc
RegDst
MemtoReg
MemWrite
Branch
Jump
ExtOp
ALUop<2>
ALUop<1>
ALUop<0>

ECE437, Fall 2014

ECE437, Fall 2014

(49)

Putting it all together

ALUop

op
6
Instr<31:26>

RegDst
Main
Control

func
Instr<5:0> 6

ALUSrc

32

MemtoReg

MemWr
0

32
32
WrEn Adr

Data In 32
Clk

Imm16

Mux

Rd

<0:15>

Extender

16

Zero

Rs

<11:15>

busA
Rw Ra Rb
32
32 32-bit
Registers
busB
0
32

imm16
Instr<15:0>

Rt

ALUctr

Mux

32
Clk

Rt
5

ALU

busW

Rs
5

<16:20>

Instruction
Fetch Unit

Clk

1 Mux 0
RegWr
g
5

Textbook version (4.24)

ALUctr

Instruction<31:0>

nPC_sel

Rt

ALU
Control

<21:25>

Rd
RegDst

Data
Memory

ALUSrc
ECE437, Fall 2014

ExtOp

(50)

(51)

Including jump
ECE437, Fall 2014

Cycletime

(52)

Timing: R-type inst

Clk
PC

Storage
Setup time

Comb. Logic

What should the clock period be?

Clk-to-Q
New Value

Old Value

Rs, Rt, Rd,

Op, Func

Old Value

ALUctr

Old Value

RegWr

Old Value

(53)

New Value

Old Value

busW

Old Value

Register File Access Time

New Value
ALU Delay
New Value

Rd Rs Rt
RegWr 5 5
5
busW
32
Clk
ECE437, Fall 2014

Rw Ra Rb
32 32-bit
Registers

ALUctr

Register Write
Occurs Here

busA
32
busB
32

ALU

ECE437, Fall 2014

Delay through Control Logic

New Value

busA, B

Enough to compute the next state values

Propagation clk-to-Q (new state)
Comb. Logic delay
Setup requirements

Instruction Memory Access Time

New Value

Result
32

(54)

lw Instruction
Longer critical path

Instruction
Rd Rs
5
5

Instruction
Address

Rt
5

Imm
16
A

Rw Ra Rb
32 32-bit
Registers

PC

32

32
32

ALU

Next Address

Critical Path (Load Operation) =

PCs Clk-to-Q +
Instruction Memorys Access Time +
Register Files Access Time +
ALU to Perform a 32-bit Add +
Data Memory Access Time +
Setup Time for Register File Write +
Clock Skew

Data
Address
Data In

Ideal
Data
Memory

Rs, Rt, Rd,

Op, Func

Old Value

ALUctr

Old Value

Instruction Memory Access Time

New Value
Delay through Control Logic
New Value

ExtOp

Old Value

New Value

ALUSrc

Old Value

New Value

MemtoReg

Old Value

New Value

RegWr

Old Value

New Value

busA

Register File Access Time

New Value

Old Value
Delay through Extender & Mux
Old Value

busB

Register
Write Occurs

New Value
ALU Delay

Clk
Clk

32

ECE437, Fall 2014

Clk

(55)

Cycle Time

Performance
f
Implications
p
Minimize all three
Insts/prog fixed -- f(interface,compiler)
CPI = 1 : As good as it gets (*)
Clock cycle time : high, lw critical path

ECE437, Fall 2014

(57)

Old Value

New Value
Data Memory Access Time
New
(56)

Whats wrong with our CPI=1 processor?

Arithmetic & Logical
PC
Inst Memory

CPI

Inst. Count

Address

busW
Old Value
ECE437, Fall 2014

Single-cycle Datapath

Clk-to-Q
New Value

Old Value

PC

lower bound on cycletime

Ideal
Instruction
Memoryy

Worst case timing

Clk

Load
PC
Store
PC
Branch
PC

Reg File

mux

ALU

Inst Memory

mux
Reg File
Critical Path

ALU

Data Mem

Inst Memory

Reg File

ALU

Data Mem

Inst Memory

Reg File

mux

cmp

mux

setup

mux setup

mux

Long Cycle Time

All instructions take as much time as the slowest
Real memory is not so nice as our idealized memory
cannot always get the job done in one (short) cycle

ECE437, Fall 2014

(58)

10