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A

PHRAA
Superior 10/10G

LA-7211P REV 1.0 Schematic


Intel Processor(Sandy Bridge) / PCH(Cougar Point)
2011-01-31 Rev 1.0

Toshiba Satellite C7xx P770 P775


4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
E

of

59

Fan Control

Intel CPU
Sandy Bridge

PCI-Express 16X 5GHz

VGA Thermal Sensor

APL5607

ADM1032ARMZ-2

page 6

page 14

Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2

rPGA-989

37.5mm*37.5mm

Dual Channel

page 5,6,7,8,9,10

page 11,12

BANK 0, 1, 2, 3

1.5V DDRIII 1066/1333/1600 MT/s

VGA (DDR3)
NVIDIA N12M-GE, 64bit with 512MB/1GB

USB/B Right

CRT

FDI X8

page 26

DMI X4

2.7GT/s

NVIDIA N12P-GS/GE, 128bit with 1GB/2GB

Left USB

USB port 0,1


page 37

5GT/s

IR Emitter

page 13,14,15,16,17,18,19,20,21,22,23,24

Felica

USB port 5
page 38

USB

FingerPrinter

USB port 2
page 37

USB port 8
page 38

Int. Camera

USB port 9
page 38

USB port 11
page 25

5V 480MHz

LVDS Conn.
page 25
2

USB
5V 480MHz

EC SMBus

HDMI-CEC
page 27

1.5V 5GT/s

Intel PCH
Cougar Point - M

page 27

RTL8105E 10/100M
RTL8111E 1G PCIe port 1

RJ45

page 40

SATA port 0
5V 6GHz(600MB/s)

1.5V 5GT/s

PCIeMini Card
JET
PCIe port 4

3G/TV#1
TV#2

USB port 12
USB port 10
page 39

page 39

SATA HDD

B-CAS

page 38

SATA port 1
page 37

SIM

page 39

FCBGA-989
25mm*25mm

Cardreader
JMB389C

PCIeMini Card
WLAN PCIe port 2

page 39

PCIe 1x

page 40

PCIeMini Card

page 39

PCIe 1x

HDMI Conn.

PCIeMini Card
WiMax USB port 13

SATA port 2
5V 3GHz(300MB/s)

SATA ODD

SATA port 4
page 37

PCIe 1x
1.5V 5GT/s

page 28,29,30,31,32,33,34,35,36

PCIe port5
page 41

PCIe 1x

USB3.0
TUSB7320

1.5V 5GT/s

3.3V 24MHz

HD Audio

LPC BUS

PCIe port6
page 42

3.3V 33 MHz

TP& Light Pipe/B


LS-6061P page 46

RTC CKT.
page 28

DC/DC Interface CKT.

Cap Sensor
& Light Sensor/B
LS-6062P page 46
LED/B
LS-6063P

Debug Port

ENE KB930

page 45

Touch Pad

page 46

Int.KBD

page 45

page 36

EC ROM
(128KB)
page 45

Power Circuit DC/DC


page 48,49,50,51,52
53,54,55,56,57

Power On/Off CKT.


page 46

Audio & USB/B


LS-6064P page

CIR

page 44

page 43

G-Sensor

page 45

Int.
MIC Conn

JPIO
(HP &page
MIC)
37

page 43

37

2011/01/31

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

page 46

Date:

SPK Conn

page 25

EC SMBus

Finger Printer/B
LS-6065P page 38
Power/B_FPC
DA300006JM0

ALC269

page 38

page 44

page 47
4

HDA Codec

MDC 1.5 Conn


SPI ROM
(4MB)
page 28

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
E

of

59

DESIGN CURRENT 0.1A

+3VL
+5VL

DESIGN CURRENT 0.1A

B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9

DESIGN CURRENT 5A

+5VALW

DESIGN CURRENT 2A

+1.8VS

SUSP#

SY8033BDBC
SUSP
DESIGN CURRENT 4A

N-CHANNEL

+5VS

BCPWON

SI4800

DESIGN CURRENT 0.5A

+5VS_L_BCAS

P-CHANNEL
AO-3413
KB_LED

UP6182CQAG

DESIGN CURRENT 400mA

+5VS_LED

DESIGN CURRENT 300mA

+3VS_HDP

DESIGN CURRENT 1.6A

+5VS_ODD

P-CHANNEL
AO-3413
+5VS

LDO
G9191
ODD_EN#

P-CHANNEL
AO-3413
Ipeak=5A, Imax=3.5A, Iocp min=7.7

DESIGN CURRENT 5A

+3VALW

WOL_EN#

P-CHANNEL
AO-3413

DESIGN CURRENT 330mA

+3V_LAN

SYSON
DESIGN CURRENT 0.2A

+3V

P-CHANNEL
AO-3413

SUSP
C

DESIGN CURRENT 4A

N-CHANNEL

+3VS

LCD_ENVDD

SI4800

P-CHANNEL
AO-3413

DESIGN CURRENT 1.5A

+LCD_VDD

DESIGN CURRENT 0.5A

+FLICA_VCC

DESIGN CURRENT 0.1A

+3VS_DGPU

FELICA_PWR

P-CHANNEL
AO-3413
DGPU_PWR_EN
VR_ON

P-CHANNEL
AO-3413

ISL95831HRTZ-T

DESIGN CURRENT 94A

+CPU_CORE

DESIGN CURRENT 33A

+GFX_CORE

DESIGN CURRENT 15A

+1.05VS_VCCP

SUSP#

Ipeak=18A, Imax=12.6A, Iocp min=19.8

RT8209BGQW
DGPU_PWR_EN#
DESIGN CURRENT 3A

N-CHANNEL
AO3416

+1.05VS_DGPU

VCCPPWRGD

Ipeak=6A, Imax=4.2A, Iocp min=7

DESIGN CURRENT 6A

Ipeak=15A, Imax=10.5A, Iocp min=16.5

DESIGN CURRENT 10A

+VCCSA

RT8209BGQW
SYSON

RT8209BGQW

+1.5V

SUSP
DESIGN CURRENT 2A

N-CHANNEL

+1.5V_CPU

FDS6676AS
SUSP

N-CHANNEL

DESIGN CURRENT 2A

+1.5VS

DESIGN CURRENT 1A

+1.05V

FDS6676AS
+3V

APL5930KAI-TRG
SUSP or 0.75VR_EN#
DESIGN CURRENT 1.5A

+0.75VS

DESIGN CURRENT 11A

+VRAM_1.5VS

DESIGN CURRENT 30A

+VGA_CORE

G2992F1U
VGA_PWROK
A

N-CHANNEL

FDS6676AS
SUSP#

Ipeak=24A, Imax=16.8A, Iocp min=32.14

TPS51218DSCR

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
1

of

59

Platform

Voltage Rails

( O MEANS ON

+RTCVCC

+5VL

+5VALW

+3VL

+3VALW

+1.5V

+5VS

Calpella

+3VS
+1.8VS

+VSB

power
plane

SKU
CPU
PCH
HM55@/HM57@
UMA(OPT@) Arrandale
Discrete Clarksfield/
HM55@/HM57@/PM55@
(DIS@)
Arrandale
Optimus
Arrandale
HM55@/HM57@
(OPT@)

X MEANS OFF )

B+

VGA
N/A
N11P@/N11M@
N11P@/N11M@

+1.5VS
1

+1.05VS

BTO Option Table

+0.75VS
+CPU_CORE
+VGA_CORE

HDMI

Function

+GFX_CORE
+VTT

State

+VRAM_1.5VS

explain

UMA

Discrete/
Optimus

BTO

IHDMI@

DHDMI@

+3VS_DGPU
+1.05VS_DGPU

S1

S3

S5 S4/AC

BTO
2

S5 S4/ Battery only


S5 S4/AC & Battery
don't exist

3G
3G@

Device

HEX

Address

+3VS

DDR SO-DIMM 0

A0 H

1010 0000 b

+3VS

DDR SO-DIMM 1

A4 H

1010 0100 b

+3VS

Clock Generator

D2 H

1101 0010 b

+3VS

New Card

+3VS

WLAN/WIMAX

+3VS

Clock Generator

+3VS

3G

TV@

CIR

KB Light

Modem

CIR

KB Light

WIMAX@

8105E@

8111E@

FP@

G-SENSOR

CIR@

MDC@

description Felica

BLUE TOOTH

G-SENSOR

SKU

explain

Felica

BLUE TOOTH

G-SENSOR

Discrete

BTO

FELICA@

BT@

GSENSOR@

KBL@

OPT@

Discrete
3D@

BTO

NOPS@

Function

PS@

Card reader

New Card

JMB385C/389C

New Card

JMB385C

JMB389C

BTO

JMB385@

JMB389@

SIGNAL

Full ON

Camera & Mic

OPTFH@

NO3D@

N11P & N11E

Power Saving

explain

Camera & Mic


Optimus

CAM@

GPU

S3 Power Saving

No Power Saving

Camera & Mic

3D Panel
Optimus

DIS@

S3 Power Saving

explain

EC SM Bus2 Address

LVDS

SKU

N11M

VRAM

N11P

N11E

N11M-GE1

N11M-GE2

N11M-OP1

8PCS@

N11P@

N11E@

N11MGE1@

N11MGE2@

N11MOP@

New Card
NEW@

SLP_S3# SLP_S4# SLP_S5#


HIGH

HIGH

HIGH

Address

Power

Device

HEX

Address

S1(Power On Suspend)

HIGH

HIGH

HIGH

16 H

0001 0110 b

+3VS

PCH

96 H

1001 0110 b

S3 (Suspend to RAM)

LOW

HIGH

HIGH

+3VL

HDMI-CEC

34 H

0011 0100 b

+3VS

NVIDIA GPU

9A H

1001 1010 b

+3VS

G-Sensor

40 H

0100 0000 b

S4 (Suspend to Disk)

LOW

LOW

HIGH

+3VS

Light Sensor

52 H

0101 0010 b

S5 (Soft OFF)

LOW

LOW

LOW

G3

LOW

LOW

LOW

Cap. Sensor

KB Light

Modem

HEX

+3VL

CIR

Fingerprint

Device

Address

Modem

Fingerprint

Smart Battery

HEX

Fingerprint

Giga

Power

Device

PSM3@

LAN

+3VL

Power

M3@

10/100M

BLUE TOOTH

STATE

M1@

WIMAX

Felica

Function

description

EC SM Bus1 Address

Clarksfield with
S3 Power Saving

description

Power

Clarksfield

CEC@

SLOT1

Clarksfield

Arrandale

LAN

TV Tuner

Function

PCH SM Bus Address

CEC

HDMI@

SLOT2

description
explain

COMMON

MINI PCI-E SLOT

Function
S0

CPU
Arrandale

HDMI

description

Virtual I2C

2011/01/31

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, MB A7211
Rev
B

4019BD

Date:

Monday, February 28, 2011

Sheet
E

of

59

JCPUB

H_SNB_IVB#

<32> H_SNB_IVB#

C26

SNB_IVB#

@
1 C488

H_PWRGOOD

T1

PAD

TP_SKTOCC#

AN34

SKTOCC#

T2

<44>

PAD

H_PECI

+1.05VS_VCCP

1 62_0402_5%

CATERR#

H_PECI

AN33

PECI

AL32

PROCHOT#

2 H_PROCHOT#_R
56_0402_5%

H_PROCHOT#
R14
1

2 H_THERMTRIP#_R AN32
0_0402_5%

A28
A27

CLK_CPU_DMI
CLK_CPU_DMI#

Stuff R41 and R42 if do not support eDP

CLK_CPU_DMI <29>
CLK_CPU_DMI# <29>

+1.05VS_VCCP

120 MHz
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

A16
A15

CLK_CPU_DPLL
CLK_CPU_DPLL#

R8

H_DRAMRST#

AK1
A5
A4

SM_RCOMP_0 R1437 2
SM_RCOMP_1 R1438 2
SM_RCOMP_2 R1439 2

CLK_CPU_DPLL#

R42 1

2 1K_0402_5%

CLK_CPU_DPLL

R41 1

2 1K_0402_5%

H_DRAMRST# <7>

1 140_0402_1%
1 25.5_0402_1%
1 200_0402_1%

DDR3 Compensation Signals


Layout Note:Place these
resistors near Processor

THERMTRIP#

H_PWRGOOD

1 10K_0402_5%

<30> H_PM_SYNC

H_PM_SYNC

AM34

PM_SYNC

<33> H_PWRGOOD

H_PWRGOOD

AP33

UNCOREPWRGOOD

PM_SYS_PWRGD_BUF 1
R454

2 PM_DRAM_PWRGD_R
130_0402_5%

BUF_CPU_RST#

V8

AR33

PWR MANAGEMENT

<33> H_THERMTRIP#
R51

AL33

R450
<44,49> H_PROCHOT#

R47

H_CATERR#

THERMAL

SM_DRAMPWROK

RESET#

+3VALW

PAD
PAD

T3
T4

PRDY#
PREQ#

AP29
AP27

TCK
TMS
TRST#

AR26
AR27
AP30

XDP_TCK_R
XDP_TMS_R
XDP_TRST#_R

TDI
TDO

AR28
AP26

XDP_TDI_R
XDP_TDO_R

DBR#

AL35

XDP_DBRESET#_R

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

R36
1
2
1K_0402_5%
R11 1

XDP_DBRESET#

2 0_0402_5%

+3VS
XDP_DBRESET# <30>
C

PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD

T8
T9
T10
T44
T45
T46
T47
T48

+1.5V_CPU

Sandy Bridge_rPGA_Rev0p61

C93
0.1U_0402_16V4Z

JTAG & BPM

1000P_0402_50V7K 2

BCLK
BCLK#

DDR3
MISC

PM_DRAM_PWRGD_R

MISC

PROC_SELECT#
1 C487

CLOCKS

100 MHz
@
1000P_0402_50V7K 2

2
1

PM_SYS_PWRGD_BUF

PU/PD for JTAG signals

+1.05VS_VCCP

<30> DRAMPWROK

R339
200_0402_5%

R312
0_0402_5%
2

U10
74AHC1G09GW_TSSOP5

<30,44> PM_PWROK

2 0_0402_5%

1 2

R3841

R340
39_0402_5%
@

SUSP

<9,39,47,54> SUSP

2
G
3

Q5
2N7002_SOT23
@

XDP_TMS_R

R28

1 51_0402_5%

XDP_TDI_R

R29

1 51_0402_5%

XDP_TDO_R

R30

1 51_0402_5%

XDP_TCK_R

R31

1 51_0402_5%

XDP_TRST#_R

R32

1 51_0402_5%

FAN Control Circuit

+5VS

R154

1A

Buffered Reset to CPU

1
2

+3VS

2
0_0603_5%

+FAN1

R3
10K_0402_5%

<44>
<44> FAN_SPEED1

1 0.1U_0402_16V4Z
C84
+1.05VS_VCCP

PLT_RST# <32,39,40,41,42,44,45>

JFAN
1
2
3
4

C3
10U_0805_10V6K
@ 1

+3VS

FANPWM
+FAN1

C6
0.01U_0402_25V7K
@

1
2
3
4

ACES_85204-0400N
@

IN

OUT

GND

BUFO_CPU_RST#

D58
1

R155
43_0402_1%
1
2 BUF_CPU_RST#

1
1SS355_SOD323-2

D88

BAS16_SOT23-3
R209
0_0402_5%
@

74AHC1G125GW_SOT353-5

1
C1

C4

2
2
10U_0603_6.3V6M 1000P_0402_50V7K

+5VS

R69
75_0402_5%

5
2

VCC

OE#

U3
PLT_RST#

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

2012/12/31

Deciphered Date

Title

SCHEMATIC, MB A7211

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019BD

Date:

Sheet

Monday, February 28, 2011


1

of

59

+1.05VS_VCCP

R34
24.9_0402_1%

DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3

<30>
<30>
<30>
<30>

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

<30>
<30>
<30>
<30>

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

<30>
<30>
<30>
<30>
<30>
<30>
<30>
<30>

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

B27
B25
A25
B24

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3

B28
B26
A24
B23

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

G21
E22
F21
D21

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

G22
D22
F20
C21

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

A21
H19
E19
F18
B21
C20
D18
E17

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

A22
G19
E20
G18
B20
C19
D19
F17

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

<30> FDI_FSYNC0
<30> FDI_FSYNC1

FDI_FSYNC0
FDI_FSYNC1

J18
J17

FDI0_FSYNC
FDI1_FSYNC

<30> FDI_INT

FDI_INT

H20

FDI_INT

<30> FDI_LSYNC0
<30> FDI_LSYNC1

FDI_LSYNC0
FDI_LSYNC1

J19
H17

FDI0_LSYNC
FDI1_LSYNC

A18
A17
B16

eDP_COMPIO
eDP_ICOMPO
eDP_HPD

C15
D15

eDP_AUX
eDP_AUX#

C17
F16
C16
G15

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

C18
E16
D16
F15

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

+1.05VS_VCCP

R9

2 24.9_0402_1%

+1.05VS_VCCP

R33

1 10K_0402_5%

EDP_COMP

Sandy Bridge_rPGA_Rev0p61

PCI EXPRESS* - GRAPHICS

eDP_COMP signals should be


shorted near balls and
routed with typical
impedance <25m ohm

<30>
<30>
<30>
<30>

DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3

Intel(R) FDI

DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3

eDP

<30>
<30>
<30>
<30>

DMI

PEG_COMP

FDI_FSYNC0
FDI_FSYNC1
A

FDI_LSYNC0
FDI_LSYNC1

1 DIS@
R689
1 DIS@
R690
1 DIS@
R695
1 DIS@
R696
1 DIS@
R697

PEG_ICOMPI and RCOMPO signals should be


shorted and routed
with - max length = 500 mils - typical
impedance = 43 m ohm (4 mils)
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 m ohm (12 mils)

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

J22
J21
H22

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

PCIE_GTX_C_CRX_N0
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_N3
PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_N5
PCIE_GTX_C_CRX_N6
PCIE_GTX_C_CRX_N7
PCIE_GTX_C_CRX_N8
PCIE_GTX_C_CRX_N9
PCIE_GTX_C_CRX_N10
PCIE_GTX_C_CRX_N11
PCIE_GTX_C_CRX_N12
PCIE_GTX_C_CRX_N13
PCIE_GTX_C_CRX_N14
PCIE_GTX_C_CRX_N15

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_P5
PCIE_GTX_C_CRX_P6
PCIE_GTX_C_CRX_P7
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_P15

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N15

C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C52
C51
C59
C53

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_N15

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P15

C60
C72
C73
C74
C76
C75
C78
C77
C62
C61
C67
C66
C69
C68
C71
C70

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_P15

PCIE_GTX_C_CRX_N[0..15] <13>

PCIE_GTX_C_CRX_P[0..15] <13>

PCIE_CTX_C_GRX_N[0..15] <13>

PCIE_CTX_C_GRX_P[0..15] <13>
B

Close to CPU
FDI_INT

JCPUA

Typ- suggest 220nF. The change in AC capacitor


value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)

2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%

2011/01/31

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, MB A7211
Rev
B

4019BD

Date:

Sheet

Monday, February 28, 2011


1

of

59

JCPUC

<11> DDR_A_D[0..63]

JCPUD

<11> DDR_A_BS0
<11> DDR_A_BS1
<11> DDR_A_BS2

C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

AE10
AF10
V6

SA_BS[0]
SA_BS[1]
SA_BS[2]

AE8
AD9
AF9

SA_CAS#
SA_RAS#
SA_WE#

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#

<11> DDR_A_CAS#
<11> DDR_A_RAS#
<11> DDR_A_WE#

SA_CLK[0]
SA_CLK#[0]
SA_CKE[0]

AB6
AA6
V9

DDRA_CLK0
DDRA_CLK0#
DDRA_CKE0

SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]

AA5
AB5
V10

DDRA_CLK1
DDRA_CLK1#
DDRA_CKE1

SA_CLK[2]
SA_CLK#[2]
SA_CKE[2]

AB4
AA4
W9

SA_CLK[3]
SA_CLK#[3]
SA_CKE[3]

AB3
AA3
W10

SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]

AK3
AL3
AG1
AH1

DDRA_SCS0#
DDRA_SCS1#

SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]

AH3
AG3
AG2
AH2

DDRA_ODT0
DDRA_ODT1

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

DDRA_CLK0 <11>
DDRA_CLK0# <11>
DDRA_CKE0 <11>

DDRA_CLK1 <11>
DDRA_CLK1# <11>
DDRA_CKE1 <11>

DDRA_SCS0# <11>
DDRA_SCS1# <11>

DDRA_ODT0 <11>
DDRA_ODT1 <11>

DDR_A_DQS#[0..7]

DDR_A_DQS#0
C4
G6 DDR_A_DQS#1
DDR_A_DQS#2
J3
M6 DDR_A_DQS#3
AL6 DDR_A_DQS#4
AM8 DDR_A_DQS#5
AR12 DDR_A_DQS#6
AM15 DDR_A_DQS#7

DDR_A_DQS[0..7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

D4
F6
K3
N6
AL5
AM9
AR11
AM14

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_MA[0..15]

Sandy Bridge_rPGA_Rev0p61

<11>

<11>

<11>

<12> DDR_B_BS0
<12> DDR_B_BS1
<12> DDR_B_BS2

<12> DDR_B_CAS#
<12> DDR_B_RAS#
<12> DDR_B_WE#

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

AA9
AA7
R6

SB_BS[0]
SB_BS[1]
SB_BS[2]

AA10
AB8
AB9

SB_CAS#
SB_RAS#
SB_WE#

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

DDR SYSTEM MEMORY B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR SYSTEM MEMORY A

<12> DDR_B_D[0..63]

SB_CLK[0]
SB_CLK#[0]
SB_CKE[0]

AE2
AD2
R9

DDRB_CLK0
DDRB_CLK0#
DDRB_CKE0

SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]

AE1
AD1
R10

DDRB_CLK1
DDRB_CLK1#
DDRB_CKE1

SB_CLK[2]
SB_CLK#[2]
SB_CKE[2]

AB2
AA2
T9

SB_CLK[3]
SB_CLK#[3]
SB_CKE[3]

AA1
AB1
T10

SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]

AD3
AE3
AD6
AE6

DDRB_SCS0#
DDRB_SCS1#

SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]

AE4
AD4
AD5
AE5

DDRB_ODT0
DDRB_ODT1

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

D7
F3
K6
N3
AN5
AP9
AK12
AP15

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

C7
G3
J6
M3
AN6
AP8
AK11
AP14

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

Sandy Bridge_rPGA_Rev0p61

DDRB_CLK0 <12>
DDRB_CLK0# <12>
DDRB_CKE0 <12>

DDRB_CLK1 <12>
DDRB_CLK1# <12>
DDRB_CKE1 <12>

DDRB_SCS0# <12>
DDRB_SCS1# <12>

DDRB_ODT0 <12>
DDRB_ODT1 <12>

DDR_B_DQS#[0..7]

DDR_B_DQS[0..7]

DDR_B_MA[0..15]

<12>

<12>

<12>

H_DRAMRST#
2

2
1

R467
1K_0402_5%
2

SM_DRAMRST# <11,12>

BSS138_NL_SOT23-3
2

R464
4.99K_0402_1%

R465
1K_0402_5%

Q14
DDR3_DRAMRST#_R
1

<5> H_DRAMRST#

+1.5V
R466
0_0402_5%
1
2
@

<29> DRAMRST_CNTRL_PCH

1
R463

2 DRAMRST_CNTRL
0_0402_5%
1

Compal Electronics, Inc.

Compal Secret Data

Security Classification

C140
0.047U_0402_25V6K

2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, MB A7211
Rev
B

4019BD

Date:

Monday, February 28, 2011

Sheet
1

of

59

+CPU_CORE

POWER

JCPUF

94A (Quad Core 45W)


53A (SV 35W)

+1.05VS_VCCP

PEG AND DDR

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

VCCIO40

J23

22U_0805_6.3V6M
1
C146
C144

22U_0805_6.3V6M
1
C143
C141

22U_0805_6.3V6M
1
C137
C136

22U_0805_6.3V6M
1
C135
C134

22U_0805_6.3V6M
1
C133
C142

C147

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1
1
C145
C163
@

22U_0805_6.3V6M
1
1
C153
C160
@
@

22U_0805_6.3V6M
1
1
C152
C139
@
@

22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
1
C138
C132
@
@

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

+CPU_CORE Decoupling:
4X 470U (4m ohm), 16X 22U, 10X 10U

22U_0805_6.3V6M

Bottom Socket Cavity


+CPU_CORE

22U_0805_6.3V6M

10U_0805_10V6K

C101

C102

10U_0805_10V6K

C103

C104

10U_0805_10V6K

C105

C106

C107

10U_0805_10V6K

C108

10U_0805_10V6K

C109

C110

C111

330U_D2_2V_Y

ESR 9mohm

Bottom Socket Cavity x 5

C10 +
330U_D2_2V_Y

C11 +

C12 +
@

10U_0805_10V6K

10U_0805_10V6K

10U_0805_10V6K

10U_0805_10V6K

10U_0805_10V6K

10U_0805_10V6K

330U_D2_2V_Y
C

Top Socket Edge


+CPU_CORE

22U_0805_6.3V6M

C151

+1.05VS_VCCP

+1.05VS_VCCP

1
R70
130_0402_5%

C130

22U_0805_6.3V6M

C129

C124

22U_0805_6.3V6M

22U_0805_6.3V6M

C123

22U_0805_6.3V6M

C122

22U_0805_6.3V6M

C121

C125
@

22U_0805_6.3V6M

22U_0805_6.3V6M

R68
75_0402_5%

AJ29
AJ30
AJ28

H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

SVID

Top Socket Cavity


VIDALERT#
VIDSCLK
VIDSOUT

1
R67 1
R63 1
R66

2
2 43_0402_1%
2 0_0402_5%
0_0402_5%

VR_SVID_ALRT# <55>
VR_SVID_CLK <55>
VR_SVID_DAT <55>

+CPU_CORE
B

22U_0805_6.3V6M

Pull high resistor on VR side


C158

C150

C128

22U_0805_6.3V6M

C127

22U_0805_6.3V6M

C120

22U_0805_6.3V6M

22U_0805_6.3V6M

C118

2
22U_0805_6.3V6M

22U_0805_6.3V6M

C119

C117

22U_0805_6.3V6M

+CPU_CORE

Co-Lay with C2, C5, C7, C9


R64
100_0402_1%

AJ35 VCCSENSE_R
AJ34 VSSSENSE_R

R65 1
R52 1

+CPU_CORE

+CPU_CORE
330U_D2_2V_Y
330U_D2_2V_Y

2 0_0402_5%
2 0_0402_5%

VCCSENSE <55>
VSSSENSE <55>

+
VCCIO_SENSE

R62
100_0402_1%

<54>

+ C891

1
C894

C2

470U_D2_2VM_R4.5M

330U_D2_2V_Y

2 3

C5

1
C7

C9

330U_D2_2V_Y
2

330U_D2_2V_Y
A

470U_D2_2VM_R4.5M

+1.05VS_VCCP

2011/01/31

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Close to CPU
Sandy Bridge_rPGA_Rev0p61

2 3

R105
100_0402_1%
@

C890

R102
0_0402_5%

VSS_SENSE_VCCIO

B10 VCCIO_SENSE
A10
2

VCCIO_SENSE
VSSIO_SENSE

TOP Socket Edge

Close to CPU

1
VCC_SENSE
VSS_SENSE

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

22U_0805_6.3V6M

SENSE LINES

TOP Socket Cavity x 7

C159

CORE SUPPLY

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

+1.05VS_VCCP Decoupling:
2X 330U (6m ohm), 12X 22U
8.5A

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

2012/12/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, MB A7211
Rev
B

4019BD

Date:

Monday, February 28, 2011

Sheet
1

of

59

+GFX_CORE

ESR 17mohm

+GFX_CORE Decoupling:
2X 470U (4m ohm), 12X 22U

+GFX_CORE

+GFX_CORE

Bottom Socket Edge

+
2

C873
330U_2.5V_M_R17
@

POWER

2
JCPUG

R74
100_0402_1%
OPT@

Close to CPU

C342
OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

Bottom Socket Edge


1

C344
OPT@

Top Socket
Cavity

22U_0805_6.3V6M
1

C345
OPT@

C346
OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M
1

C347
OPT@

C348
OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

Top Socket Edge

22U_0805_6.3V6M
C349
@

22U_0805_6.3V6M

C350
@

C351
@

C391
@

22U_0805_6.3V6M

+1.8VS

22U_0805_6.3V6M

R76
2
1
0_0805_5%

1.2A
+1.8VS_VCCPLL

10U_0805_10V6K

1
C185
@+

C186

2
330U_B2_2.5VM_R15M

C206

1U_0402_6.3V6K

B6
A6
A2

VCCPLL1
VCCPLL2
VCCPLL3

C230
1U_0402_6.3V6K

Sandy Bridge_rPGA_Rev0p61

C148

5A
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

1
2

1
2

+V_SM_VREF

1
R486

1
1

Q2
@
AP2302GN-HF_SOT23-3

AL1 +V_SM_VREF_CNT

VCCPLL Decoupling:
1X 330U (6m ohm), 1X 10U, 2x1U

SM_VREF

R252
1K_0402_0.5%

+1.5V_CPU Decoupling:
1X 330U (6m ohm), 6X 10U

2
RUN_ON_CPU1.5VS3

+1.5V_CPU
+1.5V_CPU
10U_0805_10V6K

10U_0805_10V6K

10U_0805_10V6K
1

C114

C115

C116

C149

C154

C155

ESR 6mohm

ESR 17mohm
1

C180
@
330U_D2_2VM_R6M

C875
330U_2.5V_M_R17

+
2

10U_0805_10V6K

10U_0805_10V6K

10U_0805_10V6K
C

Co-lay for Cost Down Plan

+VCCSA Decoupling:
1X 330U (6m ohm), 3X 10U
+VCCSA

Bottom Socket Cavity

6A
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

M27
M26
L26
J26
J25
J24
H26
H25

10U_0805_10V6K

VCCSA_VID0

Co-lay for Cost Down Plan


+VCCSA

10U_0805_10V6K

VCCSA_VID1

+VCCSA

0.90 V

0.80 V

0.75 V

0.65 V

For Sandy Bridge

ESR 17mohm
C100

C447

C476

C477

+
2

2
2

10U_0805_10V6K

2VCCSA_SENSE
0_0402_5%

1
1 R253

1
+

C485
@
330U_D2_2VM_R6M

@
C877 2
330U_2.5V_M_R17

10U_0805_10V6K

Bottom Socket Edge


VCCSA_SENSE

H23 VCCSA_SENSE

FC_C22
VCCSA_VID1

VCCSA_SENSE <53>
1 R95
0_0402_5% @

VCCSA_VID0
C22 VCCSA_VID0
C24
R114
@

VCCSAP_VID1

<53>

R119
@
10K_0402_5%

10K_0402_5%

+1.5V_CPU
+1.5V_CPU

+1.5VS
PJ30

+1.5V

JUMP_43X118

Reserve it to
follow CRB 1.0.

Vgs=10V,Id=14.5A,Rds=6mohm
C213 1

2 0.1U_0402_16V4Z
2 0.1U_0402_16V4Z

C211 1

2 0.1U_0402_16V4Z

C210 1

2 0.1U_0402_16V4Z

R449
470_0805_5%

C179
10U_0805_10V4K

C472
0.1U_0402_25V6
4

2N7002DW-T/R7_SOT363-6

D
D
D
D

8
7
6
5

Q46B
SUSP

S
S
S
G

+1.5V

FDS6676AS_SO8
RUN_ON_CPU1.5VS3

2
3 1

C212 1

Q33
1
2
3
4

R420
820K_0402_5%

Issued Date

SUSP

SUSP

<5,39,47,54>

2N7002DW-T/R7_SOT363-6

Compal Electronics, Inc.

Compal Secret Data


2011/01/31

+VSB

Q46A
2

Security Classification

R455
1
2
220K_0402_5%

OPT@

R122
1K_0402_0.5%

C341

R111
0_0402_5%
2
1

OPT@

22U_0805_6.3V6M
1

R75
100_0402_1%
OPT@

OPT@

C338

22U_0805_6.3V6M

22U_0805_6.3V6M
C343

OPT@

C271

VCC_AXG_SENSE <55>
VSS_AXG_SENSE <55>

+V_SM_VREF should
have 20 mil trace width

0.1U_0402_16V4Z

OPT@

Bottom Socket
Cavity

22U_0805_6.3V6M

C267

2 0_0402_5%
2 0_0402_5%
+1.5V_CPU

100K_0402_5%

OPT@

R121 1 OPT@
R251 1 OPT@

C266

33A

VCC_AXG_SENSE_R
VSS_AXG_SENSE_R

AK35
AK34

22U_0805_6.3V6M

VAXG_SENSE
VSSAXG_SENSE

VREF

330U_D2_2VM_R6M

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

DDR3 -1.5V RAILS

AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17

SA RAIL

OPT@

ESR 6mohm

MISC

R71
0_0402_5%
DIS@

C113 +

GRAPHICS

C112

1.8V RAIL

470U_D2_2V_C
1

SENSE
LINES

Co-lay for Cost Down Plan

2012/12/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, MB A7211
Rev
B

4019BD

Date:

Monday, February 28, 2011

Sheet
1

of

59

CFG Straps for Processor

T22
T24
T25
T23

PAD
PAD
PAD
PAD

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

AK28
AK29
AL26
AL27
AK26
AL29
AL30
AM31
AM32
AM30
AM28
AM26
AN28
AN31
AN26
AM27
AK31
AN29

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35

AT26
AM33
AJ27

RSVD37
RSVD38
RSVD39
RSVD40

T8
J16
H16
G16

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

AR35
AT34
AT33
AP35
AR34

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50

B34
A33
A34
B35
C35

RSVD51
RSVD52

AJ32
AK32

RSVD53

AH27

RSVD54
RSVD55

AN35
AM35

CFG2

PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD

R254
1K_0402_1%
@

T20
T5
T6
T7
T11
T12
T15
T18
T16
T19
T21
T49
T50
T51
T52
T53
T26
T27

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

1: Normal Operation; Lane #


socket pin map definition

definition matches

0:Lane Reversed

RSVD5

SA_DIMM_VREFDQ
RSVD6
RSVD7

SB_DIMM_VREFDQ

R116
1K_0402_1%

RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23

J20
B18
A19

RSVD24
RSVD25
RSVD26

*
CFG4

1 : Disabled; No Physical Display Port


attached to Embedded Display Port

0 : Enabled; An external Display Port device is


connected to the Embedded Display Port

T28 PAD
CFG6
CLK_RES_ITP <29>
CLK_RES_ITP# <29>

CFG5
R257
1K_0402_1%
@

VCCIO_SEL
J15

Embedded Display Port Presence Strap

R115
1K_0402_1%

F25
F24
F23
D24
G25
G24
E23
D23
C30
A31
B30
B29
D30
B31
A30
C29

B4
D1

RSVD56
RSVD57
RSVD58

AT2
AT1
AR1

R256
1K_0402_1%
@

CPU_RSVD6
CPU_RSVD7

R255
1K_0402_1%
@

AJ26

RSVD1
RSVD2
RSVD3
RSVD4

AJ31
AH31
AJ33
AH33

CFG4

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

RESERVED

VSS

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

(CFG[17:0] internal pull high to VCCIO)


L7
AG7
AE7
AK2
W8

RSVD27
KEY

B1

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

Sandy Bridge_rPGA_Rev0p61

*10: x8, x8 - Device 1 function 1 enabled ; function 2

CFG[6:5]

Sandy Bridge_rPGA_Rev0p61

disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG7

Sandy Bridge_rPGA_Rev0p61

T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
P9
P8
P6
P5
P3
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
M34
L33
L30
L27
L9
L8
L6
L5
L4
L3
L2
L1
K35
K32
K29
K26
J34
J31
H33
H30
H27
H24
H21
H18
H15
H13
H10
H9
H8
H7
H6
H5
H4
H3
H2
H1
G35
G32
G29
G26
G23
G20
G17
G11
F34
F31
F29

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

JCPUE

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

JCPUI

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

JCPUH

AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AT7
AT4
AT3
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AL7
AL4
AL2
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25

R258
1K_0402_1%
@

PEG DEFER TRAINING

CFG7

1: (Default) PEG Train immediately following xxRESETB


de assertion
0: PEG Wait for BIOS for training

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Deciphered Date

2012/12/31

Title

SCHEMATIC, MB A7211

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019BD

Date:

Monday, February 28, 2011

Sheet
1

10

of

59

+1.5V
JDDRL

Close to JDDRL.1

DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDRA_CKE0

<7> DDRA_CKE0
C

DDR_A_BS2

<7> DDR_A_BS2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDRA_CLK0
DDRA_CLK0#

<7> DDRA_CLK0
<7> DDRA_CLK0#

DDR_A_MA10
DDR_A_BS0

<7> DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

<7> DDR_A_WE#
<7> DDR_A_CAS#

DDR_A_MA13
DDRA_SCS1#

<7> DDRA_SCS1#

DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57

C181

1
1
C182

+0.75VS
R91
10K_0402_5%

+3VS

2.2U_0603_6.3V4Z

0.1U_0402_16V4Z

DDR_A_D58
DDR_A_D59
R90 1
2
10K_0402_5%

205
207

GND1
GND2

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

BOSS1
BOSS2

206
208

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D[0..63]
DDR_A_MA[0..15]

DDR_A_D6
DDR_A_D7

<7>

<7>
<7>

DDR_A_D12
DDR_A_D13
SM_DRAMRST#

SM_DRAMRST# <7,12>

+1.5V

DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21

R79
1K_0402_1%

+VREF_DQA

DDR_A_D22
DDR_A_D23

R81
1K_0402_1%

DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31

DDRA_CKE1

DDRA_CKE1 <7>

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
+1.5V

DDR_A_MA2
DDR_A_MA0

1
C317

2
33P_0402_50V8K

+1.5V

1
C319

2
33P_0402_50V8K

1
C339

2
33P_0402_50V8K

1
C340

2
33P_0402_50V8K

+VREF_CAA

1
C352

2
33P_0402_50V8K

DDR_A_D36
DDR_A_D37

1
C353

2
33P_0402_50V8K

DDRA_CLK1
DDRA_CLK1#
DDR_A_BS1
DDR_A_RAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1

DDRA_CLK1 <7>
DDRA_CLK1# <7>
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDRA_SCS0# <7>
DDRA_ODT0 <7>

R80
1K_0402_1%

DDRA_ODT1 <7>

R82
1K_0402_1%
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47

C161

C162

0.1U_0402_16V4Z

DDR_A_D40
DDR_A_D41

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

<7>

DDR_A_DQS#[0..7]

2.2U_0603_6.3V4Z

DDR_A_D34
DDR_A_D35

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDR_A_DQS[0..7]

DDR_A_DQS#1
DDR_A_DQS1

DDR3 SO-DIMM A
Reverse Type

DDR_A_D8
DDR_A_D9

DDR_A_D4
DDR_A_D5

DDR_A_D2
DDR_A_D3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

Layout Note:
Place near JDDRL

close to JDDRL.126
+1.5V

DDR_A_D52
DDR_A_D53

DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

Layout Note:
Place near JDDRL1.203 and 204

+1.5V

DDR_A_D54
DDR_A_D55

Layout Note: Place these 4 Caps near


Command and Control signals of DIMMA

Change C218 to OSCON at DVT

C218 1

2.2U_0603_6.3V4Z

0.1U_0402_16V4Z

C157

DDR_A_D0
DDR_A_D1

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

C156

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

+VREF_DQA

+1.5V

+0.75VS

2 390U_2.5V_M_R10

C166 1

2 10U_0603_6.3V6M

C168 1

2 10U_0603_6.3V6M

C171 1

2 10U_0603_6.3V6M

C174 1

2 10U_0603_6.3V6M

C176 1

2 10U_0603_6.3V6M

C178 1

2 10U_0603_6.3V6M

C164 1

2 0.1U_0402_16V4Z

C167 1

2 0.1U_0402_16V4Z

C170 1

2 0.1U_0402_16V4Z

C173 1

2 0.1U_0402_16V4Z

C165 1

2 10U_0603_6.3V6M

C169 2

1 1U_0402_6.3V6K

C172 2

1 1U_0402_6.3V6K

C175 2

1 1U_0402_6.3V6K

C177 2

1 1U_0402_6.3V6K

PM_SMBDATA
PM_SMBCLK

PM_SMBDATA <12,29,39>
PM_SMBCLK <12,29,39>

+0.75VS

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Issued Date

FOX_AS0A626-U2SN-7F_204P
@

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, MB A7211
Rev
B

4019BD

Date:

Monday, February 28, 2011

Sheet
1

11

of

59

+1.5V

+1.5V
JDDRH

DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDRB_CKE0

<7> DDRB_CKE0
2

DDR_B_BS2

<7> DDR_B_BS2

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDRB_CLK0
DDRB_CLK0#

<7> DDRB_CLK0
<7> DDRB_CLK0#

DDR_B_MA10
DDR_B_BS0

<7> DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

<7> DDR_B_WE#
<7> DDR_B_CAS#

DDR_B_MA13
DDRB_SCS1#

<7> DDRB_SCS1#

DDR_B_D37
DDR_B_D36
DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59
R98 1
2
10K_0402_5%

+3VS
2.2U_0603_6.3V4Z
1
C207
@ 2

1 R99
2
10K_0402_5%

C208
2 @
0.1U_0402_16V4Z

+0.75VS

205
207

GND1
GND2

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

BOSS1
BOSS2

206
208

SM_DRAMRST#

DDR_B_D[0..63]

<7>
<7>

<7>

DDR_B_MA[0..15]

<7>

SM_DRAMRST# <7,11>

DDR_B_D14
DDR_B_D15
+1.5V

DDR_B_D20
DDR_B_D21

R83
1K_0402_1%

DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29

+VREF_DQB

DDR_B_DQS#3
DDR_B_DQS3

R84
1K_0402_1%

DDR_B_D30
DDR_B_D31

DDRB_CKE1

DDRB_CKE1 <7>

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDRB_CLK1
DDRB_CLK1#
DDR_B_BS1
DDR_B_RAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1

DDRB_CLK1 <7>
DDRB_CLK1# <7>
+1.5V

DDR_B_BS1 <7>
DDR_B_RAS# <7>
DDRB_SCS0# <7>
DDRB_ODT0 <7>

R86
1K_0402_1%

DDRB_ODT1 <7>

+VREF_CAB
DDR_B_D32
DDR_B_D33
C187
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47

C188
0.1U_0402_16V4Z

DDR_B_D40
DDR_B_D41

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

DDR_B_D12
DDR_B_D13

2.2U_0603_6.3V4Z

DDR_B_D34
DDR_B_D35

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDR_B_DQS[0..7]

Close to JDDRH.1

DDR_B_DQS#[0..7]

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D6
DDR_B_D7

DDR_B_D8
DDR_B_D9

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

Reverse Type
DDR3 SO-DIMM B

DDR_B_D4
DDR_B_D5

R94
1K_0402_1%

Layout Note:
Place near JDDRH

Close to JDDRH.126

DDR_B_D52
DDR_B_D53

Layout Note: Place these 4 Caps near


Command and Control signals of DIMMB

Layout Note:
Place near JDDRH.203 and 204

+1.5V
+1.5V

@
C189 1
DDR_B_D50
DDR_B_D51
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

C184
0.1U_0402_16V4Z

2.2U_0603_6.3V4Z

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

C183

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

DDR_B_D0
DDR_B_D1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

+VREF_DQB

+0.75VS

2 330U_B2_2.5VM_R15M

C192 1

2 10U_0603_6.3V6M

C194 1

2 10U_0603_6.3V6M

C197 1

2 10U_0603_6.3V6M

C200 1

2 10U_0603_6.3V6M

C202 1

2 10U_0603_6.3V6M

C204 1

2 10U_0603_6.3V6M

C190 1

2 0.1U_0402_16V4Z

C193 1

2 0.1U_0402_16V4Z

C196 1

2 0.1U_0402_16V4Z

C199 1

2 0.1U_0402_16V4Z

C191 1

2 10U_0603_6.3V6M

C195 2

1 1U_0402_6.3V6K

C198 2

1 1U_0402_6.3V6K

C201 2

1 1U_0402_6.3V6K

C203 2

1 1U_0402_6.3V6K
4

PM_SMBDATA
PM_SMBCLK

PM_SMBDATA <11,29,39>
PM_SMBCLK <11,29,39>

+0.75VS

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Issued Date

FOX_AS0A626-UASN-7F_204P
@

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, MB A7211
Rev
B

4019BD

Date:

Monday, February 28, 2011

Sheet
E

12

of

59

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

45mA

LV13
+1.05VS_DGPU

1
2
BLM18PG330SN1D_0603
@
1
1
CV224
@

CV222
@

2
1U_0402_6.3V6K

2
1U_0402_6.3V6K

LV2
BLM18PG330SN1D_0603
OPT@

CV85
10U_0603_6.3V6M
OPT@

CV8
0.1U_0402_16V4Z
OPT@

CV9
0.1U_0402_16V4Z
OPT@

CV7
22U_0805_6.3V6M
OPT@

CV12
0.1U_0402_16V4Z
OPT@

Lane Reversal
PCIE_GTX_C_CRX_P15
PCIE_GTX_C_CRX_N15
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_N14
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_N13
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_N12
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_N11
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_N10
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_N9
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_N8
PCIE_GTX_C_CRX_P7
PCIE_GTX_C_CRX_N7
PCIE_GTX_C_CRX_P6
PCIE_GTX_C_CRX_N6
PCIE_GTX_C_CRX_P5
PCIE_GTX_C_CRX_N5
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_N3
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_N1
PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_N0

CV11
0.1U_0402_16V4Z
OPT@

CV5
0.1U_0402_16V7K
OPT@
CV13
0.1U_0402_16V7K
OPT@
CV15
0.1U_0402_16V7K
OPT@
CV17
0.1U_0402_16V7K
OPT@
CV19
0.1U_0402_16V7K
OPT@
CV21
0.1U_0402_16V7K
OPT@
CV23
0.1U_0402_16V7K
OPT@
CV25
0.1U_0402_16V7K
OPT@
CV27
0.1U_0402_16V7K
OPT@
CV29
0.1U_0402_16V7K
OPT@
CV31
0.1U_0402_16V7K
OPT@
CV33
0.1U_0402_16V7K
OPT@
CV35
0.1U_0402_16V7K
OPT@
CV37
0.1U_0402_16V7K
OPT@
CV39
0.1U_0402_16V7K
OPT@
CV41
0.1U_0402_16V7K
OPT@

+SP_PLLVDD

4.7U_0603_6.3V6K
CV223
1 @

CV6
0.1U_0402_16V7K
OPT@
CV14
0.1U_0402_16V7K
OPT@
CV16
0.1U_0402_16V7K
OPT@
CV18
0.1U_0402_16V7K
OPT@
CV20
0.1U_0402_16V7K
OPT@
CV22
0.1U_0402_16V7K
OPT@
CV24
0.1U_0402_16V7K
OPT@
CV26
0.1U_0402_16V7K
OPT@
CV28
0.1U_0402_16V7K
OPT@
CV30
0.1U_0402_16V7K
OPT@
CV32
0.1U_0402_16V7K
OPT@
CV34
0.1U_0402_16V7K
OPT@
CV36
0.1U_0402_16V7K
OPT@
CV38
0.1U_0402_16V7K
OPT@
CV40
0.1U_0402_16V7K
OPT@
CV42
0.1U_0402_16V7K
OPT@

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

CV5
CV6
CV13
CV14
CV15
CV16
CV17
CV18
CV19
CV20
CV21
CV22
CV24
CV23
CV26
CV25
CV27
CV28
CV37
CV38
CV40
CV39
CV42
CV41
CV29
CV30
CV31
CV32
CV34
CV33
CV36
CV35

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

PCIE_GTX_CRX_P15
PCIE_GTX_CRX_N15
PCIE_GTX_CRX_P14
PCIE_GTX_CRX_N14
PCIE_GTX_CRX_P13
PCIE_GTX_CRX_N13
PCIE_GTX_CRX_P12
PCIE_GTX_CRX_N12
PCIE_GTX_CRX_P11
PCIE_GTX_CRX_N11
PCIE_GTX_CRX_P10
PCIE_GTX_CRX_N10
PCIE_GTX_CRX_P9
PCIE_GTX_CRX_N9
PCIE_GTX_CRX_P8
PCIE_GTX_CRX_N8
PCIE_GTX_CRX_P7
PCIE_GTX_CRX_N7
PCIE_GTX_CRX_P6
PCIE_GTX_CRX_N6
PCIE_GTX_CRX_P5
PCIE_GTX_CRX_N5
PCIE_GTX_CRX_P4
PCIE_GTX_CRX_N4
PCIE_GTX_CRX_P3
PCIE_GTX_CRX_N3
PCIE_GTX_CRX_P2
PCIE_GTX_CRX_N2
PCIE_GTX_CRX_P1
PCIE_GTX_CRX_N1
PCIE_GTX_CRX_P0
PCIE_GTX_CRX_N0

AL17
AM17
AM18
AM19
AL19
AK19
AL20
AM20
AM21
AM22
AL22
AK22
AL23
AM23
AM24
AM25
AL25
AK25
AL26
AM26
AM27
AM28
AL28
AK28
AK29
AL29
AM29
AM30
AM31
AM32
AN32
AP32

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_REQ_GPU#

AR16
AR17
AR13

PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#

AJ17
AJ18

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

<29> CLK_PCIE_VGA
<29> CLK_PCIE_VGA#
@
1
2
RV16
200_0402_1%

Differential signal
RV30
0_0402_5%
OPT@

PLTRST_VGA_R#
1 DIS@ 2
RV18
0_0402_5%
1 DIS@ 2
RV19
2.49K_0402_1%

<32> PLTRST_VGA#

RV18
0_0402_5%
OPT@

RV19
2.49K_0402_1%
OPT@

RV26
10K_0402_5%
OPT@

RV25
10K_0402_5%
OPT@

45mA
+SP_PLLVDD

1 DIS@ 2
RV30
0_0402_5%

YV1
27MHZ_16PF_X5H027000FG1H
OPT@
CV45
18P_0402_50V8J
OPT@

60mA

+PLLVDD

RV26 2 DIS@

CV46
18P_0402_50V8J
OPT@

XTAL_OUTBUFF
XTAL_SSIN

VGA_EDID_CLK
VGA_EDID_DATA

<26> VGA_CRT_CLK
<26> VGA_CRT_DATA

SMB_CLK_GPU
E2
SMB_DATA_GPU E1

I2CS_SCL
I2CS_SDA

VGA_EDID_CLK E3
VGA_EDID_DATA E4

I2CC_SCL
I2CC_SDA

G3
G2

I2CB_SCL
I2CB_SDA

VGA_CRT_CLK
G1
VGA_CRT_DATA G4

I2CA_SCL
I2CA_SDA

HDCP_SCL
HDCP_SDA

RV118
10K_0402_5%

F6
G6

K1
K2
K3
H3
H2
H1
H4
H5
H6
J7
K4
K5
H7
J4
J6
L1
L2
L4
M4
L7
L5
K6
L6
M6
M7

MIOA_D0_NC
MIOA_D1_NC
MIOA_D2_NC
MIOA_D3_NC
MIOA_D4_NC
MIOA_D5_NC
MIOA_D6_NC
MIOA_D7_NC
MIOA_D8_NC
MIOA_D9_NC
MIOA_D10_NC
MIOA_D11_NC
MIOA_D12_NC
MIOA_D13_NC
MIOA_D14_NC

N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6

MIOB_D0_NC
MIOB_D1_NC
MIOB_D2_NC
MIOB_D3_NC
MIOB_D4_NC
MIOB_D5_NC
MIOB_D6_NC
MIOB_D7_NC
MIOB_D8_NC
MIOB_D9_NC
MIOBD_10_NC
MIOB_D11_NC
MIOB_D12_NC
MIOB_D13_NC
MIOB_D14_NC

Y1
Y2
Y3
AB3
AB2
AB1
AC4
AC1
AC2
AC3
AE3
AE2
U6
W6
Y6

MIOA_HSYNC_NC
MIOA_VSYNC_NC

N3
L3

MIOB_HSYNC_NC
MIOB_VSYNC_NC

W1
W2

MIOA_DE_NC
MIOA_CTL3_NC
MIOA_VREF_NC

N2
P5
N5

MIOB_DE_NC
MIOB_CTL3_NC
MIOB_VREF_NC

Y5
W3
AF1

ACIN_VGA

VGA_BL_PWM <25>
VGA_ENVDD <25>
VGA_ENBKL <25>
GPU_VID0 <56>
GPU_VID1 <56>
@
2 RV129 1
0_0402_5%
D25 @
2
1

EDP@
2 RV125 1
0_0402_5%

TV6

R1436
100K_0402_5%
OPT@

RV10
100K_0402_5%
OPT@

RV6
2.2K_0402_5%
OPT@

RV7
2.2K_0402_5%
OPT@

RV8
2.2K_0402_5%
@

RV9
2.2K_0402_5%
@

RV11
2.2K_0402_5%
OPT@

RV12
2.2K_0402_5%
OPT@

RV13
2.2K_0402_5%
OPT@

HDCP_SDA

RV14
2.2K_0402_5%
OPT@

RV121
2.2K_0402_5%
OPT@

VGA_CRT_DATA

AA7
AA6

SMB_CLK_GPU
RV8
RV9
ACIN_VGA

HDCP_SCL

RV32
330K_0402_5%
OPT@
I2CB_SCL

RV37
10K_0402_5%
OPT@
RV15
10K_0402_5%
OPT@

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

Close to GPU

120mA
0.1U_0402_16V4Z

+DACA_VDD
CV73
0.1U_0402_16V4Z
DIS@

1
CV72
DIS@

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

DACA_HSYNC
DACA_VSYNC

AM13
AL13

VGA_CRT_HSYNC
VGA_CRT_VSYNC

DACA_VDD
DACA_VREF
DACA_RSET

AJ12
AK12
AK13

+DACA_VDD
+DACA_VREF
DACA_RSET

AK4
AL4
AJ4

DACB_HSYNC
DACB_VSYNC

AM1
AM2

@
CLK_REQ_GPU#

1
RV28

1
CV80
DIS@

DIS@
DIS@
DIS@
DIS@

CV81
DIS@

LV3
1
2
+3VS_DGPU
MMZ1608D301BT_0603
DIS@
1
1
CV50
CV49
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
DIS@
DIS@
2
2

0.1U_0402_16V4Z
LV3
MMZ1608D301BT_0603
OPT@

VGA_CRT_R <26>
VGA_CRT_G <26>
VGA_CRT_B <26>

RV27
124_0402_1%
DIS@

1 DIS@ 2
RV20
150_0402_1%
1 DIS@ 2
RV21
150_0402_1%
1 DIS@ 2
RV23
150_0402_1%

VGA_CRT_HSYNC <26>
VGA_CRT_VSYNC <26>

07/10/2010
HDMI HPD for OPT DGPU output

AG7 +DACB_VDD 2
1
RV31
10K_0402_5%
AK6
AH7
DIS@

C879
@
0.1U_0402_16V4Z
1
2

+3VS

CV47
0.1U_0402_16V4Z
DIS@

<32,33,47,56> VGA_PWROK

R1430
@
0_0402_5%
2
1 1

IN1

IN2

<27,31,33> HDMI_HPD

U55

2
RV123
10K_0402_5%
@

XTALIN

HDMI_HPD_VGA

SN74AHC1G08DCKR_SC70-5
@

N12PGSR3@
RV31
10K_0402_5%
OPT@

Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

0_0402_5%
DHDMI@
R1431

XTAL_OUT

27MHZ_16PF_X5H027000FG1H
DIS@
1
1
CV45
CV46
18P_0402_50V8J
DIS@
DIS@
18P_0402_50V8J
2
2

+3VS_DGPU

N12P-GS1-A1_BGA_973P

2
10M_0402_5%
YV1

RV128
10K_0402_5%
@

1U_0402_6.3V6K

1
CV48
DIS@

DIS@

2
2.2K_0402_5%
2
2.2K_0402_5%
2
330K_0402_5%
2
100K_0402_5%
2
10K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%

1 DIS@ 2
RV121
2.2K_0402_5%
1 DIS@ 2
RV122
2.2K_0402_5%

I2CB_SDA

RV17
10K_0402_5%
OPT@

1 @

1 DIS@ 2
RV13
2.2K_0402_5%
1 DIS@ 2
RV14
2.2K_0402_5%

VGA_CRT_CLK
RV122
2.2K_0402_5%
OPT@

1 @

1
RV32
1
RV10
1
RV37
1
RV11
1
RV12

OVERT#_VGA

0.1U_0402_16V4Z

DACB_RED
DACB_GREEN
DACB_BLUE

2
RV6
2.2K_0402_5%
1 DIS@ 2
RV7
2.2K_0402_5%

THERM#_GPU

AM15
AM14
AL14

1 DIS@

SMB_DATA_GPU

DACA_RED
DACA_GREEN
DACA_BLUE

2
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%
2
100K_0402_5%
2
100K_0402_5%
2
100K_0402_5%
1
100K_0402_5%
1
100K_0402_5%

+3VS_DGPU

VGA_EDID_CLK
VGA_EDID_DATA

MIOB_CLKIN_NC
MIOB_CLKOUT_NC

MIOBCAL_PD_VDDQ_NC
MIOBCAL_PU_GND_NC

1 DIS@
RV1
2 DIS@
RV2
VGA_BL_PWM
2 3D@
RV3
HPD_C
1 DIS@
RV4
EDP_HPD_R
1 DIS@
RV5
HPD_F
1 DIS@
RV29
HDMI_HPD
@
2
R1429
HDMI_HPD_VGA
2 DIS@
R1436

RV4
100K_0402_5%
OPT@
RV5
100K_0402_5%
OPT@
RV29
100K_0402_5%
OPT@

1 DIS@ 2
RV17
10K_0402_5%

U5
T5

VGA_ENVDD

EDP_HPD <25>

1 DIS@ 2
RV15
10K_0402_5%

MIOACAL_PD_VDDQ_NC
MIOACAL_PU_GND_NC

<30,44,46,50>

HPD_F

AE1
V4
T4
W4

ACIN

PCIE_CTX_C_GRX_N[0..15]

<6> PCIE_CTX_C_GRX_N[0..15]

VGA_ENBKL

N4
R4

MIOA_CLKOUT_NC_N
MIOB_CLKOUT_NC_N

PCIE_CTX_C_GRX_P[0..15]

<6> PCIE_CTX_C_GRX_P[0..15]

THERM#_VGA <14>

CH751H-40PT_SOD323-2

EDP_HPD_R

PCIE_GTX_C_CRX_N[0..15]

<6> PCIE_GTX_C_CRX_N[0..15]

HDMI_HPD_VGA

MIOA_CLKIN_NC
MIOA_CLKOUT_NC

DACB_VDD
DACB_VREF
DACB_RSET

I2CH_SCL
I2CH_SDA

OVERT#_VGA
THERM#_GPU

PCIE_GTX_C_CRX_P[0..15]

<6> PCIE_GTX_C_CRX_P[0..15]

HPD_C
VGA_BL_PWM
VGA_ENVDD
VGA_ENBKL
GPU_VID0
GPU_VID1

2 1
G

VID_PLLVDD

D1
D2

CRT

SP_PLLVDD

1 10K_0402_5% XTALOUT
2 DIS@ 1 XTALSSIN
RV25
10K_0402_5%

I2CB_SCL
I2CB_SDA

1
2
G

@
3

2N7002_SOT23-3
1 @
2
RV110
0_0402_5%

D
2N7002_SOT23-3
QV3

AF9
AD9

XTAL_IN
XTAL_OUT

+3VS_DGPU

QV2
1

PLLVDD

B1
B2

<32,47,56> DGPU_PWR_EN

<29> CLK_REQ_VGA#

AE9

XTALIN
XTAL_OUT

<14> SMB_CLK_GPU
<14> SMB_DATA_GPU

PEX_RST_N
PEX_TERMP

Internal Thermal Sensor

LVDS<25>
<25>

RV124
10K_0402_5%
@

45mA

AM16
AG21

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24

Part 1 of 7

DIS@ 1
CV9

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

DIS@ 1
CV12

DIS@ 1
CV11

AP17
AN17
AN19
AP19
AR19
AR20
AP20
AN20
AN22
AP22
AR22
AR23
AP23
AN23
AN25
AP25
AR25
AR26
AP26
AN26
AN28
AP28
AR28
AR29
AP29
AN29
AN31
AP31
AR31
AR32
AR34
AP34

DIS@ 1
CV8

PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_N15
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0

GPIO

22U_0805_6.3V6M

+PLLVDD

0.1U_0402_16V4Z

PCI EXPRESS
DVO

150mA

LV2
1
2
BLM18PG330SN1D_0603
DIS@ 2
DIS@ 1
DIS@
CV85
CV7

I2C
DACs

+1.05VS_DGPU

UV1A

Lane Reversal

CLK

Compal Electronics, Inc.


SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
1

13

of

59

UV1D
Part 4 of 7

EDP@

2 RV126

VGA_EDP_AUX
1
100K_0402_5%

2 RV127

VGA_EDP_AUX1
100K_0402_5%

IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N

External VGA Thermal Sensor


STRAP4 <24>

VGA_EDP_TX0+
VGA_EDP_TX0VGA_EDP_TX1+
VGA_EDP_TX1VGA_EDP_TX2+
VGA_EDP_TX2VGA_EDP_TX3+
VGA_EDP_TX3-

AR8
AR7
AP7
AN7
AN5
AP5
AR5
AR4

IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N

<27> VGA_HDMI_TX2+
<27> VGA_HDMI_TX2<27> VGA_HDMI_TX1+
<27> VGA_HDMI_TX1<27> VGA_HDMI_TX0+
<27> VGA_HDMI_TX0<27> VGA_HDMI_CLK+
<27> VGA_HDMI_CLK-

VGA_HDMI_TX2+
VGA_HDMI_TX2VGA_HDMI_TX1+
VGA_HDMI_TX1VGA_HDMI_TX0+
VGA_HDMI_TX0VGA_HDMI_CLK+
VGA_HDMI_CLK-

AH6
AH5
AH4
AG4
AF4
AF5
AE6
AE5

IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N

AL2
AL3
AJ3
AJ2
AJ1
AH1
AH2
AH3

IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N

AP2
AN3

IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N

VGA_EDP_AUX
VGA_EDP_AUX-

AP4
AN4

IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N

VGA_HDMI_CLK
VGA_HDMI_DATA

AE4
AD4

IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N

TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

AF3
AF2

IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N

SERIAL

SMB_DATA_GPU <13>

@
2
CV53

UV2
1
1
0.1U_0402_16V4Z
2

THERM_D+

THERM_D-

SCLK

VGA_SMB_CK2

D+

SDATA

VGA_SMB_DA2

ALERT#

THERM#_VGA

GND

CV54
1
2 @

D-

2200P_0402_50V7K

THERM#

ADM1032ARMZ-2REEL_MSOP8

RV33
0_0402_5%
OPT@

N12PGV@
GPU_PGOOD 2
1
RV115
10K_0402_5%

Internal Thermal Sensor


Address: 0x9E H, 0x9A H

eDP

VGA_HDMI_CLK
1 DIS@ 2
RV119
4.7K_0402_5%

HDMI

<27> VGA_HDMI_CLK
<27> VGA_HDMI_DATA

VGA_HDMI_DATA
1 DIS@ 2
RV120
4.7K_0402_5%

RV119
4.7K_0402_5%
OPT@

RV120
4.7K_0402_5%
OPT@

RV49
10K_0402_5%
OPT@

CV53
0.1U_0402_16V4Z
@

+3VS_DGPU
<24>
<24>
<24>

STRAP0
STRAP1
STRAP2

1 DIS@ 2
RV49
10K_0402_5%
STRAP0
STRAP1
STRAP2

AB5
W5
W7
V7

2
RV22
2.2K_0402_5%
OPT@
VDD_SENSE_0
VDD_SENSE_1
VDD_SENSE_2

D35
P7
AD20

GND_SENSE_0
GND_SENSE_1
GND_SENSE_2

AD19
E35
R7

VDD_SENSE

VDD_SENSE <56>

RV24
2.2K_0402_5%
OPT@

VGA_SMB_CK2

4
OPT@
QV1A
1

TEST
AP35
AP14
AN14
AN16
AR14
AP16

TESTMODE

ROM_CS_N
ROM_SI
ROM_SO
ROM_SCLK

C3
D3
C4
D4

ROM_CS#
ROM_SI
ROM_SO
ROM_SCLK

NC/SPDIF_NC

A5

MULTI_STRAP_REF0_GND

N9

MULTI_STRAP_REF1_GND

M9

THERMDP
THERMDN

B5
B4

CEC

1
RV41

2
10K_0402_5%

EC_SMB_DA2 <29,44,45,46>

VGA_SMB_DA2

EC_SMB_CK2
1 DIS@ 2
RV35
0_0402_5%
EC_SMB_DA2
1 DIS@ 2
RV36
0_0402_5%

+3VS_DGPU
RV47
10K_0402_5%
DIS@

ROM_CS#

2
RV44

1
10K_0402_5%

ROM_SI
<24>
ROM_SO <24>
ROM_SCLK <24>

1 DIS@ 2
RV48
40.2K_0402_1%
1 DIS@ 2
RV50
40.2K_0402_1%
THERM_D+
THERM_D-

RV48
40.2K_0402_1%
OPT@
RV50
40.2K_0402_1%
OPT@

N12PGSR3@

Issued Date

Compal Secret Data


2011/01/31

2012/12/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

EC_SMB_CK2 <29,44,45,46>

2N7002DW-T/R7_SOT363-6

TV2
TV3
TV4
TV5

Security Classification

OPT@
QV1B
3

2N7002DW-T/R7_SOT363-6

RV47
10K_0402_5%
OPT@

BUFRST_N

N12P-GS1-A1_BGA_973P

+3VS_DGPU

VGA_SMB_DA2

STRAP0
STRAP1
STRAP2

CV54
2200P_0402_50V7K
@

+3VS_DGPU

GENERAL
A4

RV34
0_0402_5%
OPT@

UV2
ADM1032ARMZ-2REEL_MSOP8
@

+3VS_DGPU

<25> VGA_eDP_AUX
<25> VGA_eDP_AUX-

THERM#_VGA <13>

VDD

VGA_SMB_CK2
EDP@

1
2

+3VS_DGPU

STRAP_REF2

RV34
0_0402_5%
DIS@
2

RV33
0_0402_5%
DIS@

GPU_PGOOD

N12PGV@
STRAP_REF2 1
2
RV114
40.2K_0402_1%

<25> VGA_EDP_TX0+
<25> VGA_EDP_TX0<25> VGA_EDP_TX1+
<25> VGA_EDP_TX1<25> VGA_EDP_TX2+
<25> VGA_EDP_TX2<25> VGA_EDP_TX3+
<25> VGA_EDP_TX3-

SMB_CLK_GPU <13>

Address: 0x9A H

STRAP3 <24>

AM7
AM6
AL5
AM5
AM3
AM4
AP1
AR2

LVDS/TMDS

eDP is supported
only on IFPD

IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

A2
A7
B7
C5
C7
D5
D6
D7
E5
E7
F4
G5
H32
J25
J26
P6
U7
V6
Y4
AA4
AB4
AB7
AC5
AD6
AF6
AG6
AG20
AJ5
AK15
AL7

<25> VGA_TZCLK+
<25> VGA_TZCLK<25> VGA_TZOUT0+
<25> VGA_TZOUT0<25> VGA_TZOUT1+
<25> VGA_TZOUT1<25> VGA_TZOUT2+
<25> VGA_TZOUT2-

AP13
AN13
AN8
AP8
AP10
AN10
AR11
AR10
AN11
AP11

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29

VGA_TZCLK+
VGA_TZCLKVGA_TZOUT0+
VGA_TZOUT0VGA_TZOUT1+
VGA_TZOUT1VGA_TZOUT2+
VGA_TZOUT2-

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N

AM11
AM12
AM8
AL8
AM10
AM9
AK10
AL10
AK11
AL11

<25> VGA_TXCLK+
<25> VGA_TXCLK<25> VGA_TXOUT0+
<25> VGA_TXOUT0<25> VGA_TXOUT1+
<25> VGA_TXOUT1<25> VGA_TXOUT2+
<25> VGA_TXOUT2-

NC

VGA_TXCLK+
VGA_TXCLKVGA_TXOUT0+
VGA_TXOUT0VGA_TXOUT1+
VGA_TXOUT1VGA_TXOUT2+
VGA_TXOUT2-

Compal Electronics, Inc.


SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
1

14

of

59

For PHQAA EVT Phase only

N12M-GE Performance Mode

+VGA_CORE

Mode

0.95 V

P0

0.950V

P8

0.825 V

P12

TBD

Mode

VID1

VID0

P0(Cold)

P0

P8/P12

N12P-GS Performance Mode


NVCLK (MHz)

MCLK (MHz)

+VGA_CORE

Mode

606

790

1.00 V

P0

TBD

TBD

TBD

TBD

P8

TBD

TBD

TBD

P12

TBD

NVCLK (MHz)

+VGA_CORE

MCLK (MHz)

N12P-GE Performance Mode


NVCLK (MHz)

+VGA_CORE

Mode

TBD

TBD

P0

TBD

TBD

TBD

TBD

TBD

P8

TBD

TBD

TBD

TBD

TBD

P12

TBD

TBD

TBD

for
for
for
for

N12PGSR3@

+VGA_CORE

1
CV57

+VGA_CORE

330U_2.5V_M_R17
1

CV226
22U_0603_6.3V6M
@

CV227
22U_0603_6.3V6M
@

CV57
330U_2.5V_M_R17
OPT@

CV58
330U_2.5V_M_R17
OPT@

CV10
47U_0805_4V6
OPT@

CV43
22U_0805_6.3V6M
OPT@

CV60
10U_0603_6.3V6M
OPT@

CV61
10U_0603_6.3V6M
OPT@

CV51
4.7U_0603_6.3V6K
OPT@

CV62
1U_0402_6.3V6K
OPT@

CV44
0.22U_0402_6.3V6K
OPT@

CV52
0.22U_0402_6.3V6K
OPT@

CV55
0.22U_0402_6.3V6K
OPT@

CV59
0.1U_0402_16V7K
OPT@

CV63
0.1U_0402_16V7K
OPT@

CV64
0.047U_0402_25V6K
OPT@

CV65
0.047U_0402_25V6K
OPT@

CV66
0.047U_0402_25V6K
OPT@

CV70
0.022U_0402_25V7K
OPT@

CV71
0.022U_0402_25V7K
OPT@

CV123
0.022U_0402_25V7K
OPT@

CV74
0.01U_0402_25V7K
OPT@

CV75
0.01U_0402_25V7K
OPT@

CV76
0.01U_0402_25V7K
OPT@

CV77
0.01U_0402_25V7K
OPT@

CV78
0.01U_0402_25V7K
OPT@

CV79
0.01U_0402_25V7K
OPT@

CV124
0.01U_0402_25V7K
OPT@

CV125
0.01U_0402_25V7K
OPT@

22U_0603_6.3V6M

+ CV58

330U_2.5V_M_R17
DIS@ 2

CV225
@

2 DIS@

22U_0603_6.3V6M

CV226
@

CV227
@

22U_0603_6.3V6M

+VGA_CORE

DIS@

CV60
DIS@

22U_0805_6.3V6M

CV61
DIS@

CV51
DIS@

10U_0603_6.3V6M

CV62
DIS@

CV44

DIS@

1U_0402_6.3V6K

CV52

0.22U_0402_6.3V6K

DIS@

CV55

CV43

0.22U_0402_6.3V6K

DIS@

CV10
47U_0805_4V6
DIS@

4.7U_0603_6.3V6K

10U_0603_6.3V6M

0.22U_0402_6.3V6K

+VGA_CORE
0.1U_0402_16V7K

CV59

CV63

0.1U_0402_16V7K
DIS@ 2

DIS@

0.047U_0402_25V6K

CV64
DIS@

CV65
DIS@

0.047U_0402_25V6K

CV66
DIS@

0.022U_0402_25V7K

CV70
DIS@

CV71
DIS@

0.047U_0402_25V6K

0.022U_0402_25V7K

CV123
DIS@

0.022U_0402_25V7K

+VGA_CORE
0.01U_0402_25V7K

CV74
N12P-GS1-A1_BGA_973P

CV225
22U_0603_6.3V6M
@

N11E-GE1-LP
N11P-GE1
N11M-GE1 & N11M-OP1
N11M-GE2

VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
VDD_77
VDD_78
VDD_79
VDD_80
VDD_81
VDD_82
VDD_83
VDD_84
VDD_85
VDD_86
VDD_87
VDD_88
VDD_89
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
VDD_98
VDD_99
VDD_100
VDD_101
VDD_102
VDD_103
VDD_104
VDD_105
VDD_106
VDD_107
VDD_108
VDD_109
VDD_110

32A
28A
16A
14A

Part 7 of 7

P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55

POWER

AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD12
AD14
AD16
AD18
AD22
AD24
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
M12
M14
M16
M18
M20
M22
M24
P11
P13
P15
P17
P19

+VGA_CORE

+VGA_CORE
UV1G

MCLK (MHz)

0.01U_0402_25V7K
DIS@ 2

CV75
DIS@

CV76
DIS@

0.01U_0402_25V7K

CV77
DIS@

0.01U_0402_25V7K

CV78
DIS@

0.01U_0402_25V7K

CV79
DIS@

0.01U_0402_25V7K

CV124
DIS@

0.01U_0402_25V7K

CV125
DIS@

0.01U_0402_25V7K

Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
1

15

of

59

UV1E

3.5A
1

CV83

4.7U_0603_6.3V6K
DIS@ 2

DIS@

CV67
DIS@

CV68
DIS@

CV86
DIS@

2 0.1U_0402_16V4Z

1U_0402_6.3V6K
D

0.1U_0402_16V4Z

+VRAM_1.5VS
CV99

CV100

0.1U_0402_16V4Z
DIS@ 2

DIS@

0.1U_0402_16V4Z

CV101
DIS@

CV102
DIS@

DIS@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CV103

CV104
DIS@

0.1U_0402_16V4Z

CV126
DIS@

0.1U_0402_16V4Z

CV82
4.7U_0603_6.3V6K
OPT@

CV83
4.7U_0603_6.3V6K
OPT@

CV67
1U_0402_6.3V6K
OPT@

CV68
1U_0402_6.3V6K
OPT@

CV86
0.1U_0402_16V4Z
OPT@

CV99
0.1U_0402_16V4Z
OPT@

CV100
0.1U_0402_16V4Z
OPT@

CV101
0.1U_0402_16V4Z
OPT@

CV102
0.1U_0402_16V4Z
OPT@

CV103
0.1U_0402_16V4Z
OPT@

CV104
0.1U_0402_16V4Z
OPT@

CV126
0.1U_0402_16V4Z
OPT@

+IFPAB_PLLVDD
@
1
2
RV96
1K_0402_1%

Part 5 of 7

J23
J24
J29
AA27
AA29
AA31
AB27
AB29
AC27
AD27
AE27
AJ28
B18
E21
G17
G18
G22
G8
G9
H29
J14
J15
J16
J17
J20
J21
J22
N27
P27
R27
T27
U27
U29
V27
V29
V34
W27
Y27

+IFPAB_IOVDD

AK9
AJ11
AG9
AG10

+IFPD_PLLVDD

AJ9
AK7

+IFPD_IOVDD

AJ8

@
1
2
RV51
1K_0402_1%

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
IFPAB_PLLVDD
IFPAB_RSET

+1.05VS_DGPU

PEX_SVDD_3V3
PEX_SVDD_3V3_NC

AG19
F7

J10
J11
J12
J13
J9

IFPD_IOVDD
IFPEF_PLLVDD
IFPEF_RSET

+IFPE_IOVDD

AE7
AD7

IFPE_IOVDD
IFPF_IOVDD

LV5

CV117
4.7U_0603_6.3V6K
DIS@

+IFPAB_PLLVDD

1U_0402_6.3V6K

2
1
BLM18PG121SN1D_0603
DIS@

1
CV118
DIS@

CV127
4.7U_0603_6.3V6K
DHDMI@

1U_0402_6.3V6K

220mA
+IFPAB_IOVDD

0.1U_0402_16V4Z
1

1
CV134
DIS@

1
CV135
DIS@

CV213
0.1U_0402_16V4Z
DIS@

CV94
2

CV95
DIS@

1
CV96
DIS@

+1.05VS_DGPU

1
CV97
DIS@

1
CV98
DIS@

4.7U_0603_6.3V6K

1
CV105
DIS@

1
CV107
DIS@

LV4
2
1
BLM18PG121SN1D_0603
DIS@

120mA

N12PGSR3@

CV108
4.7U_0603_6.3V6K
2 DIS@

CV109
4.7U_0603_6.3V6K
DIS@

1
CV128
DHDMI@

1
CV129
DHDMI@

1
CV130
DHDMI@

1
CV131
DHDMI@

+1.05VS_DGPU
LV10
2
1 4.7U_0603_6.3V6K
BLM18PG181SN1D_0603
DHDMI@
1
1
CV141
CV142
4.7U_0603_6.3V6K
DHDMI@
DHDMI@
2
2

+3VS_DGPU
CV110
0.1U_0402_16V4Z
1U_0402_6.3V6K
DIS@

0.1U_0402_16V4Z
1

1
CV217
DIS@

0.1U_0402_16V4Z

1
CV216
DIS@

1
CV112
DIS@

1
CV113
DIS@

1 DIS@
CV111
4.7U_0603_6.3V6K

CV114
4.7U_0603_6.3V6K
DIS@

+3VS_DGPU

CV111
4.7U_0603_6.3V6K
OPT@

CV110
0.1U_0402_16V4Z
OPT@

CV3
22U_0805_6.3V6M
OPT@

CV4
22U_0805_6.3V6M
OPT@

CV93
0.1U_0402_16V4Z
OPT@

CV92
10U_0603_6.3V6M
OPT@

CV98
10U_0603_6.3V6M
OPT@

CV94
0.1U_0402_16V4Z
OPT@

CV91
4.7U_0603_6.3V6K
OPT@

CV97
4.7U_0603_6.3V6K
OPT@

CV87
0.1U_0402_16V4Z
OPT@

CV89
1U_0402_6.3V6K
OPT@

CV90
1U_0402_6.3V6K
OPT@

CV88
0.1U_0402_16V4Z
OPT@

CV95
1U_0402_6.3V6K
OPT@

CV96
1U_0402_6.3V6K
OPT@

@
+MIO_VDDQ
2
R196

1
0_0603_5%

+3VS_DGPU

CV115
10K_0402_5%
DIS@

CV116
0.1U_0402_16V4Z
@

CV115
10K_0402_5%
OPT@

CV215
0.1U_0402_16V4Z
DHDMI@

CV131
10K_0402_5%
IHDMI@

LV11
2
1
BLM18PG181SN1D_0603
EDP@
1

CV140
4.7U_0603_6.3V6K
EDP@

1U_0402_6.3V6K

1
CV220
EDP@

4.7U_0603_6.3V6K

CV113
1U_0402_6.3V6K
OPT@

CV216
0.1U_0402_16V4Z
OPT@

CV217
0.1U_0402_16V4Z
OPT@

1
CV214
EDP@

CV112
0.1U_0402_16V4Z
OPT@

1
CV144
DHDMI@

CV145
0.1U_0402_16V4Z
DHDMI@

CV143
10K_0402_5%
IHDMI@

+1.05VS_DGPU
LV12
2
1 4.7U_0603_6.3V6K
BLM18PG181SN1D_0603
EDP@
1
1
CV219
CV147
4.7U_0603_6.3V6K
EDP@
EDP@
2
2

CV213
10K_0402_5%
OPT@

1
CV221
EDP@

CV221
10K_0402_5%
NOEDP@

CV218
0.1U_0402_16V4Z
EDP@

0.1U_0402_16V4Z
CV212
10K_0402_5%
NOEDP@
0.1U_0402_16V4Z
1

1
CV148
EDP@

+IFPD_IOVDD
1

CV197
EDP@

CV212
0.1U_0402_16V4Z
EDP@

1U_0402_6.3V6K

Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

+IFPD_PLLVDD

0.1U_0402_16V4Z

1
CV139
EDP@

CV114
4.7U_0603_6.3V6K
OPT@

+IFPE_IOVDD

CV105
0.1U_0402_16V4Z
OPT@

0.1U_0402_16V4Z

285mA

CV143
DHDMI@

+1.05VS_DGPU

RV481
1
2
0_0402_5% OPT@

+PEX_SVDD_3V3

0.1U_0402_16V4Z

CV107
1U_0402_6.3V6K
OPT@

RV480
0_0402_5% @
1
2

120mA

0.1U_0402_16V4Z

CV109
4.7U_0603_6.3V6K
OPT@

0.1U_0402_16V4Z

+IFPEF_PLLVDD

0.1U_0402_16V4Z

CV108
4.7U_0603_6.3V6K
OPT@

+1.05VS_DGPU

+PEX_PLLVDD

AA9
AB9
W9
Y9

MIOB_VDDQ_NC_0
MIOB_VDDQ_NC_1
MIOB_VDDQ_NC_2
MIOB_VDDQ_NC_3

CV4
22U_0805_6.3V6M
DIS@

LV4
BLM18PG121SN1D_0603
OPT@

1U_0402_6.3V6K

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V4Z

1U_0402_6.3V6K

CV92
DIS@

+3VS_DGPU

4.7U_0603_6.3V6K

LV8
2
1 4.7U_0603_6.3V6K
BLM18PG181SN1D_0603
DIS@
1
1
CV132
CV133
4.7U_0603_6.3V6K
DIS@
DIS@
2
2

CV3
22U_0805_6.3V6M
DIS@

4.7U_0603_6.3V6K

1U_0402_6.3V6K

2 DIS@

0.1U_0402_16V4Z

+1.8VS

CV91
DIS@

220mA

LV7
2
1
BLM18PG181SN1D_0603
DHDMI@
1

CV120
DIS@

R9
T9
U9

+3VS_DGPU

2
4.7U_0603_6.3V6K

CV93
DIS@

1
CV119
DIS@

CV90
DIS@

+1.05VS_DGPU

240mA
P9

MIOA_VDDQ_NC_0
MIOA_VDDQ_NC_1
MIOA_VDDQ_NC_2
MIOA_VDDQ_NC_3

AJ6
AL1

AG14

IFPC_IOVDD

AK8

CV89
DIS@

1U_0402_6.3V6K

+IFPEF_PLLVDD

PEX_PLLVDD

IFPC_PLLVDD
IFPC_RSET

+IFPD_IOVDD

CV88
DIS@

0.1U_0402_16V4Z

120mA

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4

IFPD_PLLVDD
IFPD_RSET

220mA

CV87
DIS@

0.1U_0402_16V4Z

CV120
10K_0402_5%
OPT@

10U_0603_6.3V6M

1U_0402_6.3V6K

AK16
AK17
AK21
AK24
AK27

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4

N12P-GS1-A1_BGA_973P

1U_0402_6.3V6K

600mA

IFPA_IOVDD
IFPB_IOVDD

AC6
AB6

1DHDMI@ 2
RV53
1K_0402_1%

0.1U_0402_16V4Z

AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24
AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16

120mA

+IFPD_PLLVDD
1 EDP@ 2
RV52
1K_0402_1%

2200mA

1600mA
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18
PEX_IOVDDQ_19
PEX_IOVDDQ_20
PEX_IOVDDQ_21
PEX_IOVDDQ_22
PEX_IOVDDQ_23
PEX_IOVDDQ_24

CV82

1U_0402_6.3V6K

POWER

4.7U_0603_6.3V6K

+VRAM_1.5VS

Compal Electronics, Inc.


SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Sheet

Monday, February 28, 2011


1

16

of

59

UV1F

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96

Part 6 of 7
GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192

GND

B3
B6
B9
B12
B15
B21
B24
B27
B30
B33
C2
C34
E6
E9
E12
E15
E18
E24
E27
E30
F2
F31
F34
F5
J2
J5
J31
J34
K9
L9
M2
M5
M11
M13
M15
M17
M19
M21
M23
M25
M31
M34
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
P12
P14
P16
P18
P20
P22
P24
R2
R5
R31
R34
T11
T13
T15
T17
T19
T21
T23
T25
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
V2
V5
V9
V12
V14
V16

V18
V20
V22
V24
V31
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
AA2
AA5
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA34
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC9
AD2
AD5
AD11
AD13
AD15
AD17
AD21
AD23
AD25
AD31
AD34
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG5
AG31
AG34
AK2
AK5
AK14
AK31
AK34
AL6
AL9
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AN2
AN34
AP3
AP6
AP9
AP12
AP15
AP18
AP21
AP24
AP27
AP30
AP33

N12P-GS1-A1_BGA_973P

N12PGSR3@

Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
1

17

of

59

UV1B
Part 2 of 7
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

+VRAM_1.5VS

RV55
1.1K_0402_1%
@
+FB_VREF

12mil
1

RV56
1.1K_0402_1%
@
2

CV146
0.01U_0402_25V7K
@

+1.05VS_DGPU

CV106
10U_0603_6.3V6M
DIS@

LV6
1
2
BLM18PG330SN1D_0603
DIS@
2
2
CV69
DIS@

100mA

1U_0402_6.3V6K

10U_0603_6.3V6M

CV149
DIS@

CV84
DIS@

+FB_AVDD0

L32
N33
L33
N34
N35
P35
P33
P34
K35
K33
K34
H33
G34
G33
E34
E33
G31
F30
G30
G32
K30
K32
H30
K31
L31
L30
M32
N30
M30
P31
R32
R30
AG30
AG32
AH31
AF31
AF30
AE30
AC32
AD30
AN33
AL31
AM33
AL33
AK30
AK32
AJ30
AH30
AH33
AH35
AH34
AH32
AJ33
AL35
AM34
AM35
AF33
AE32
AF34
AE35
AE34
AE33
AB32
AC35

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

AG27
AF27

FB_DLLAVDD_0
FB_PLLAVDD_0

J19
J18

FB_DLLAVDD_1
FB_PLLAVDD_1

+FB_AVDD1
0.1U_0402_16V4Z
+VRAM_1.5VS

RV101

+FB_VREF
J27
2 DIS@ 1 60.4_0402_1%T30
T29
2
1
RV57
10K_0402_5%
DIS@

MEMORY INTERFACE
A

MDA[0..63]

<20,21> MDA[0..63]

U30
V30
U31
V32
T35
U33
W32
W33
W31
W34
U34
U35
U32
T34
T33
W30
AB30
AA30
AB31
AA32
AB33
Y32
Y33
AB34
AB35
Y35
W35
Y34
Y31
Y30
W29
Y29

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

P32
H34
J30
P30
AF32
AL32
AL34
AF35

DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

L35
G35
H31
N32
AD32
AJ31
AJ35
AC34

DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

L34
H35
J32
N31
AE31
AJ32
AJ34
AC33

DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7

FBA_WCK0
FBA_WCK0_N
FBA_WCK1
FBA_WCK1_N
FBA_WCK2
FBA_WCK2_N
FBA_WCK3
FBA_WCK3_N

P29
R29
L29
M29
AG29
AH29
AD29
AE29

FB_VREF_NC
FBA_DEBUG0
FBA_DEBUG1
N12P-GS1-A1_BGA_973P

+1.05VS_DGPU

100mA

LV9
+FB_AVDD1
1U_0402_6.3V6K
1
2
BLM18PG330SN1D_0603
DIS@
2
2
1
1
CV137
CV121
CV150
CV136
10U_0603_6.3V6M
DIS@
DIS@
DIS@
0.1U_0402_16V4Z
DIS@
1
1
2
2
10U_0603_6.3V6M

RV57
10K_0402_5%
OPT@

LV9
BLM18PG330SN1D_0603
OPT@

CV121
10U_0603_6.3V6M
OPT@

CV136
0.1U_0402_16V4Z
OPT@

CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15
CMDA16
CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30

RV101
60.4_0402_1%
OPT@

<20>

CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15
CMDA16

<20>
<20>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<21>

CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30

<21>
<21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>
<20,21>

GB2-128
Mode E - Mirror Mode Mapping

FBA_CLK0
FBA_CLK0_N

T32
T31

CLKA0
CLKA0#

FBA_CLK1
FBA_CLK1_N

AC31
AC30

CLKA1
CLKA1#

CKE_L
A8

CMD21

A7

A6

CMD24

A2

A1

CMD23

A11

A9

CMD26

A5

A4

CMD7

A0

A12

CMD15

CAS#

CAS#

CMD13

BA1

A3

CMD4

A9

CMD29

BA0

BA0

CMD27

BA2

A15

CMD6

A3

BA1
ODT_H

CMD22

A4

A5

CMD12

A13

A14

CMD28

WE#

A10

CMD10

A1

A2

CMD25

A10

WE#

CMD9

A12

A0

CMD1

CS1#_L

CMD11

CS1#_H

CMD19

<20,21>

A11
CS0#_H

CMD17

DQSA[7..0]

A8

CS0#_L

CMD18

<20,21>

32..63

RAS#

CMD0

ODT_L

CMD5

A6

RAS#
B

A7
CKE_H

CMD20

RST

RST

CMD14

A14

A13

CMD30

A15

BA2

CLKA0 <20>
CLKA0# <20>
CLKA1 <21>
CLKA1# <21>

N12PGSR3@

CV106
10U_0603_6.3V6M
OPT@

CV69
10U_0603_6.3V6M
OPT@

CV149
1U_0402_6.3V6K
OPT@

CV84
0.1U_0402_16V4Z
OPT@

Compal Secret Data


2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

CMD3
CMD2

Date:

0..31

CMD8

DQMA[7..0] <20,21>

DQSA#[7..0]

DATA Bus
Address

CMD16

Security Classification

CV150
1U_0402_6.3V6K
OPT@

CMDA0

LV6
BLM18PG330SN1D_0603
OPT@

CV137
10U_0603_6.3V6M
OPT@

CMDA0

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

Compal Electronics, Inc.


SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
1

18

of

59

UV1C
Part 3 of 7
MDB[0..63]

RV58
40.2_0402_1%
OPT@
RV59
40.2_0402_1%
OPT@
RV60
60.4_0402_1%
OPT@

+VRAM_1.5VS

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

B13
D13
A13
A14
C16
B16
A17
D16
C13
B11
C11
A11
C10
C8
B8
A8
E8
F8
F10
F9
F12
D8
D11
E11
D12
E13
F13
F14
F15
E16
F16
F17
D29
F27
F28
E28
D26
F25
D24
E25
E32
F32
D33
E31
C33
F29
D30
E29
B29
C31
C29
B31
C32
B32
B35
B34
A29
B28
A28
C28
C26
D25
B25
A25

F18
E19
D18
C17
F19
C19
B17
E20
B19
D20
A19
D19
C20
F20
B20
G21
F22
F24
F23
C25
C23
F21
E22
D21
A23
D22
B23
C22
B22
A22
A20
G20

FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7

A16
D10
F11
D15
D27
D34
A34
D28

DQMB0
DQMB1
DQMB2
DQMB3
DQMB4
DQMB5
DQMB6
DQMB7

FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7

B14
B10
D9
E14
F26
D31
A31
A26

DQSB#0
DQSB#1
DQSB#2
DQSB#3
DQSB#4
DQSB#5
DQSB#6
DQSB#7

FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7

C14
A10
E10
D14
E26
D32
A32
B26

FBC_WCK0
FBC_WCK0_N
FBC_WCK1
FBC_WCK1_N
FBC_WCK2
FBC_WCK2_N
FBC_WCK3
FBC_WCK3_N

G14
G15
G11
G12
G27
G28
G24
G25

FBCAL_TERM_GND

FBC_CLK0
FBC_CLK0_N

E17
D17

CLKB0
CLKB0#

FBC_DEBUG0
FBB_DEBUG1

FBC_CLK1
FBC_CLK1_N

D23
E23

CLKB1
CLKB1#

1 DIS@

FBCAL_PD_VDDQ

1 DIS@

FBCAL_PU_GND

K27
2
40.2_0402_1%
L27
2
RV59
40.2_0402_1%
M27
1 DIS@ 2
RV60
60.4_0402_1%
+VRAM_1.5VS RV105 2 DIS@ 1 60.4_0402_1%G19
G16
2
1
RV61
10K_0402_5%
DIS@
RV58

CMDB0

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
FBC_CMD31

FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63

MEMORY INTERFACE C

<22,23> MDB[0..63]

N12P-GS1-A1_BGA_973P

CMDB2
CMDB3
CMDB4
CMDB5
CMDB6
CMDB7
CMDB8
CMDB9
CMDB10
CMDB11
CMDB12
CMDB13
CMDB14
CMDB15
CMDB16
CMDB18
CMDB19
CMDB20
CMDB21
CMDB22
CMDB23
CMDB24
CMDB25
CMDB26
CMDB27
CMDB28
CMDB29
CMDB30

CMDB0

<22>

CMDB2
CMDB3
CMDB4
CMDB5
CMDB6
CMDB7
CMDB8
CMDB9
CMDB10
CMDB11
CMDB12
CMDB13
CMDB14
CMDB15
CMDB16

<22>
<22>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<23>

CMDB18
CMDB19
CMDB20
CMDB21
CMDB22
CMDB23
CMDB24
CMDB25
CMDB26
CMDB27
CMDB28
CMDB29
CMDB30

<23>
<23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22,23>

GB2-128
Mode E - Mirror Mode Mapping
DATA Bus
Address

0..31

CMD3

CKE_L

CMD8
CMD2

DQMB[7..0] <22,23>

32..63

A8

A8

CS0#_L

CMD21

A7

A6

CMD24

A2

A1

CMD23

A11

A9

CMD26

A5

A4

CMD7

A0

A12

CMD15

CAS#

CAS#

CMD13

BA1

A3

CMD4

A9

DQSB#[7..0] <22,23>

A11

CMD29

BA0

BA0

CMD27

BA2

A15

CMD6

A3

BA1

CMD17

CS1#_H
ODT_H

CMD19

DQSB[7..0]

<22,23>

CMD22

A4

A5

CMD12

A13

A14

CMD28

WE#

A10

CMD10

A1

A2

CMD25

A10

WE#

CMD9

A12

A0

CMD1

CS1#_L

CMD11

RAS#

CMD0

ODT_L

CMD5

A6

CLKB1 <23>
CLKB1# <23>

N12PGSR3@

RAS#
A7
CKE_H

CMD16

CLKB0 <22>
CLKB0# <22>

CS0#_H

CMD18

DQSB0
DQSB1
DQSB2
DQSB3
DQSB4
DQSB5
DQSB6
DQSB7

CMD20

RST

RST

CMD14

A14

A13

CMD30

A15

BA2

RV61
10K_0402_5%
OPT@
RV105
60.4_0402_1%
OPT@

Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.


SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
1

19

of

59

MDA[0..63] <18,21>

Memory Partition A - Lower 32 bits

CMDA[30..0]

<18,21>

DQMA[7..0] <18,21>
UV5
+VRAM_1.5VS

+FBA_VREF0

RV62
1.1K_0402_1%
DIS@

2
1

+FBA_VREF0

RV63
1.1K_0402_1%
DIS@

CV151
0.01U_0402_25V7K
DIS@

CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14
CMDA30

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

CMDA29
CMDA13
CMDA27

M2
N8
M3

BA0
BA1
BA2

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

MDA3
MDA6
MDA1
MDA4
MDA2
MDA7
MDA0
MDA5

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDA29
MDA26
MDA30
MDA24
MDA27
MDA25
MDA31
MDA28

RV64
160_0402_1%
DIS@

CLKA0
CLKA0#
CMDA3

CLKA0
CLKA0#

CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14
CMDA30

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

CMDA29
CMDA13
CMDA27

M2
N8
M3

BA0
BA1
BA2

E3
F7
F2
F8
H3
H8
G2
H7

MDA19
MDA17
MDA18
MDA16
MDA20
MDA22
MDA21
MDA23

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDA14
MDA9
MDA12
MDA11
MDA13
MDA8
MDA15
MDA10

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

CMDA0
CMDA2
CMDA11
CMDA15
CMDA28

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSA2
DQSA1

F3
C7

DQSL
DQSU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA2
DQMA1

E7
D3

DML
DMU

DQSA#2
DQSA#1

G3
B7

DQSL
DQSU

CMDA20

T2

RESET

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

J7
K7
K9

CK
CK
CKE/CKE0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

GB2-128
Mode E - Mirror Mode Mapping
DATA Bus

Group1

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

F3
C7

DQSL
DQSU

CV151
0.01U_0402_25V7K
OPT@

RV64
160_0402_1%
OPT@

DQMA0
DQMA3

E7
D3

DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQSA#0
DQSA#3

G3
B7

DQSL
DQSU

CMDA20

T2

RESET

CV230
1U_0402_6.3V6K
OPT@
CV152
1U_0402_6.3V6K
OPT@
CV159
1U_0402_6.3V6K
OPT@
CV154
0.1U_0402_16V4Z
OPT@
CV156
0.1U_0402_16V4Z
OPT@
CV158
0.1U_0402_16V4Z
OPT@
CV162
0.1U_0402_16V4Z
OPT@
CV164
0.1U_0402_16V4Z
OPT@
CV228
1U_0402_6.3V6K
OPT@

CV231
1U_0402_6.3V6K
OPT@
CV153
1U_0402_6.3V6K
OPT@
CV160
1U_0402_6.3V6K
OPT@
CV155
0.1U_0402_16V4Z
OPT@
CV157
0.1U_0402_16V4Z
OPT@
CV161
0.1U_0402_16V4Z
OPT@
CV163
0.1U_0402_16V4Z
OPT@
CV165
0.1U_0402_16V4Z
OPT@
CV229
1U_0402_6.3V6K
OPT@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

RV67
243_0402_1%
OPT@

ZQ/ZQ0

J1
L1
J9
L9

RV66
243_0402_1%
DIS@

RV65
10K_0402_5%
DIS@

RV65
10K_0402_5%
OPT@

L8

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

RV67
243_0402_1%
DIS@

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
@

CV152
DIS@

RV98
10K_0402_5%
DIS@

2
2
1U_0402_6.3V6K

CV153
DIS@

0.1U_0402_16V4Z
CV154
DIS@

2
2
0.1U_0402_16V4Z

0.1U_0402_16V4Z

CV155
DIS@

CV156
DIS@

2
2
0.1U_0402_16V4Z

CV157
DIS@

RV102
10K_0402_5%
DIS@

CV158
DIS@
0.1U_0402_16V4Z

CV159
DIS@

2
2
1U_0402_6.3V6K

RV98
10K_0402_5%
OPT@

RV102
10K_0402_5%
OPT@

CV160
DIS@

0.1U_0402_16V4Z
CV161
DIS@

2
2
0.1U_0402_16V4Z

CV162
DIS@

0.1U_0402_16V4Z

CV163
DIS@

32..63

A8

A8

CS0#_L

CMD21

A7

A6

CMD24

A2

A1

CMD23

A11

A9

CMD26

A5

A4

CMD7

A0

A12

CMD15

CAS#

CAS#

CMD13

BA1

A3

CMD4

A9

A11

CMD29

BA0

BA0

CMD27

BA2

A15

CMD6

A3

BA1
CS1#_H
ODT_H

CMD22

A4

A5

CMD12

A13

A14

CMD28

WE#

A10

CMD10

A1

A2

2
2
0.1U_0402_16V4Z

CV164
DIS@

CV165
DIS@
0.1U_0402_16V4Z

CV231
DIS@

CV230
DIS@

CMD25

A10

WE#

CMD9

A12

A0

CMD1

CS1#_L
RAS#

RAS#

CMD0

ODT_L

CMD5

A6

A7
CKE_H

CMD16

1U_0402_6.3V6K

CS0#_H

CMD11

CMD20

RST

RST

CMD14

A14

A13

CMD30

A15

BA2

2
2
1U_0402_6.3V6K

+VRAM_1.5VS

1U_0402_6.3V6K

CV228
DIS@

CV229
DIS@

Compal Secret Data

Security Classification
2011/01/31

Issued Date

2
2
1U_0402_6.3V6K

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

CKE_L

CMD19

+VRAM_1.5VS

1U_0402_6.3V6K

CMD3

CMD17

+VRAM_1.5VS

1U_0402_6.3V6K

0..31

CMD18

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
@

+VRAM_1.5VS

CMDA3

DQSA0
DQSA3

RV63
1.1K_0402_1%
OPT@

CMDA0

ODT/ODT0
CS/CS0
RAS
CAS
WE

Address

CMD2

K1
L2
J3
K3
L3

<18,21>
<18,21>
D

CMDA0
CMDA2
CMDA11
CMDA15
CMDA28

DQSA[7..0]
DQSA#[7..0]

Group2

CMD8

B2
D9
G7
K2
K8
N1
N9
R1
R9

CLKA0
CLKA0#
CMDA3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

+VRAM_1.5VS

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

RV62
1.1K_0402_1%
OPT@

RV66
243_0402_1%
OPT@

Group3

VREFCA
VREFDQ

CLKA0#

J7
K7
K9

Group0

M8
H1

<18>
<18>

+FBA_VREF0

+VRAM_1.5VS

CLKA0

VREFCA
VREFDQ

E3
F7
F2
F8
H3
H8
G2
H7

UV6

M8
H1

Compal Electronics, Inc.


SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
1

20

of

59

Memory Partition A - Upper 32 bits


MDA[0..63] <18,20>
UV8

+VRAM_1.5VS
+FBA_VREF1

M8
H1

VREFCA
VREFDQ

CMDA9
CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5
CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12
CMDA27

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

CMDA29
CMDA6
CMDA30

M2
N8
M3

BA0
BA1
BA2

1
RV68
1.1K_0402_1%
DIS@

2
1

+FBA_VREF1

RV69
1.1K_0402_1%
DIS@

CV166
0.01U_0402_25V7K
DIS@

CLKA1
CLKA1#
CMDA16

CLKA1
CLKA1#

J7
K7
K9

D7
C3
C8
C2
A7
A2
B8
A3

MDA42
MDA45
MDA40
MDA46
MDA41
MDA47
MDA43
MDA44

Group4

Group5

CK
CK
CKE/CKE0

M8
H1

VREFCA
VREFDQ

CMDA9
CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5
CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12
CMDA27

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

CMDA29
CMDA6
CMDA30

M2
N8
M3

BA0
BA1
BA2

CLKA1#

MDA58
MDA59
MDA57
MDA61
MDA60
MDA62
MDA56
MDA63

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDA51
MDA52
MDA48
MDA53
MDA49
MDA54
MDA50
MDA55

B2
D9
G7
K2
K8
N1
N9
R1
R9

Group7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

CMDA19
CMDA18
CMDA11
CMDA15
CMDA25

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSA7
DQSA6

F3
C7

DQSL
DQSU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA7
DQMA6

E7
D3

DML
DMU

DQSA#7
DQSA#6

G3
B7

DQSL
DQSU

CMDA20

T2

RESET

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

CLKA1
CLKA1#
CMDA16

J7
K7
K9

CK
CK
CKE/CKE0

B2
D9
G7
K2
K8
N1
N9
R1
R9

DQSA4
DQSA5

F3
C7

DQSL
DQSU

DQMA4
DQMA5

E7
D3

DML
DMU

DQSA#4
DQSA#5

G3
B7

DQSL
DQSU

CMDA20

T2

RESET

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

CV234
1U_0402_6.3V6K
OPT@
CV167
1U_0402_6.3V6K
OPT@
CV174
1U_0402_6.3V6K
OPT@
CV169
0.1U_0402_16V4Z
OPT@
CV171
0.1U_0402_16V4Z
OPT@
CV173
0.1U_0402_16V4Z
OPT@
CV177
0.1U_0402_16V4Z
OPT@
CV179
0.1U_0402_16V4Z
OPT@
CV232
1U_0402_6.3V6K
OPT@

CV235
1U_0402_6.3V6K
OPT@
CV168
1U_0402_6.3V6K
OPT@
CV175
1U_0402_6.3V6K
OPT@
CV170
0.1U_0402_16V4Z
OPT@
CV172
0.1U_0402_16V4Z
OPT@
CV176
0.1U_0402_16V4Z
OPT@
CV178
0.1U_0402_16V4Z
OPT@
CV180
0.1U_0402_16V4Z
OPT@
CV233
1U_0402_6.3V6K
OPT@

RV71
243_0402_1%
OPT@

L8

ZQ/ZQ0

J1
L1
J9
L9

RV72
243_0402_1%
DIS@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

RV72
243_0402_1%
OPT@

RV71
243_0402_1%
DIS@

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

CV167
DIS@

RV100
10K_0402_5%
DIS@

RV100
10K_0402_5%
OPT@

+VRAM_1.5VS

1U_0402_6.3V6K

CMDA16

2
2
1U_0402_6.3V6K

CV168
DIS@

0.1U_0402_16V4Z
CV169
DIS@

CV170
DIS@

2
2
0.1U_0402_16V4Z

0.1U_0402_16V4Z

CV171
DIS@

RV104
10K_0402_5%
DIS@

RV104
10K_0402_5%
OPT@

2
2
0.1U_0402_16V4Z

CV172
DIS@

CV173
DIS@
0.1U_0402_16V4Z

CV174
DIS@

CV175
DIS@

2
2
1U_0402_6.3V6K

0.1U_0402_16V4Z
CV176
DIS@

2
2
0.1U_0402_16V4Z

CV177
DIS@

0.1U_0402_16V4Z

32..63

A8

A8

CS0#_L

CMD21

A7

A6

CMD24

A2

A1

CMD23

A11

A9

CMD26

A5

A4

CMD7

A0

A12

CMD15

CAS#

CAS#

CMD13

BA1

A3

CMD4

A9

CV178
DIS@

2
2
0.1U_0402_16V4Z

CV179
DIS@

1U_0402_6.3V6K

A11
CS0#_H

CMD29

BA0

BA0

CMD27

BA2

A15

CMD6

A3

BA1
CS1#_H
ODT_H

CMD19
CMD22

A4

A5

CMD12

A13

A14

CMD28

WE#

A10

CMD10

A1

A2

CV180
DIS@
0.1U_0402_16V4Z

CV234
DIS@

CV235
DIS@

CMD25

A10

WE#

CMD9

A12

A0

CMD1

CS1#_L
RAS#

RAS#

CMD0

ODT_L

CMD5

A6

A7
CKE_H

CMD16
CMD20

RST

RST

CMD14

A14

A13

CMD30

A15

BA2

2
2
1U_0402_6.3V6K

+VRAM_1.5VS
A

1U_0402_6.3V6K

CV232
DIS@

CV233
DIS@

Compal Secret Data

Security Classification

2
2
1U_0402_6.3V6K

2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

CKE_L

CMD11

+VRAM_1.5VS

1U_0402_6.3V6K

CMD3

CMD17

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
@

+VRAM_1.5VS

0..31

CMD18
CMDA19

L8

Address

CMD2

RV70
160_0402_1%
OPT@

ODT/ODT0
CS/CS0
RAS
CAS
WE

CV166
0.01U_0402_25V7K
OPT@

K1
L2
J3
K3
L3

<18,20>
<18,20>

DATA Bus

Group6

RV69
1.1K_0402_1%
OPT@

CMDA19
CMDA18
CMDA11
CMDA15
CMDA25

DQSA[7..0]
DQSA#[7..0]

GB2-128
Mode E - Mirror Mode Mapping

+VRAM_1.5VS

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

<18,20>

DQMA[7..0] <18,20>

CMD8

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

RV68
1.1K_0402_1%
OPT@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

<18>
<18>

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

+FBA_VREF1

RV70
160_0402_1%
DIS@

MDA38
MDA33
MDA39
MDA35
MDA36
MDA34
MDA37
MDA32

+VRAM_1.5VS

CLKA1

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

CMDA[30..0]

UV7

Compal Electronics, Inc.


SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
1

21

of

59

MDB[0..63] <19,23>

Memory Partition C - Lower 32 bits

CMDB[30..0]

<19,23>

DQMB[7..0] <19,23>
DQSB[7..0] <19,23>
+VRAM_1.5VS

UV9

+FBB_VREF0

RV73
1.1K_0402_1%
8PCS@

CMDB7
CMDB10
CMDB24
CMDB6
CMDB22
CMDB26
CMDB5
CMDB21
CMDB8
CMDB4
CMDB25
CMDB23
CMDB9
CMDB12
CMDB14
CMDB30

+FBB_VREF0

RV74
1.1K_0402_1%
8PCS@

CV181
0.01U_0402_25V7K
8PCS@

CMDB29
CMDB13
CMDB27

M8
H1

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB3
MDB5
MDB2
MDB4
MDB1
MDB6
MDB0
MDB7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB31
MDB25
MDB29
MDB24
MDB28
MDB26
MDB30
MDB27

RV75
160_0402_1%
8PCS@

<19>
<19>

CLKB0
CLKB0#

J7
K7
K9

CMDB7
CMDB10
CMDB24
CMDB6
CMDB22
CMDB26
CMDB5
CMDB21
CMDB8
CMDB4
CMDB25
CMDB23
CMDB9
CMDB12
CMDB14
CMDB30

Group0

Group3

CMDB29
CMDB13
CMDB27

M8
H1

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

CMDB0
CMDB2
CMDB11
CMDB15
CMDB28
DQSB2
DQSB1

F3
C7

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMB2
DQMB1

E7
D3

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

BA0
BA1
BA2

CK
CK
CKE/CKE0

M2
N8
M3

CLKB0
CLKB0#
CMDB3

DQSB#[7..0] <19,23>

J7
K7
K9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB16
MDB17
MDB19
MDB18
MDB23
MDB21
MDB22
MDB20

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB13
MDB9
MDB14
MDB11
MDB12
MDB8
MDB15
MDB10

GB2-128
Mode E - Mirror Mode Mapping

Group2

DATA Bus

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

CK
CK
CKE/CKE0

CLKB0#

CMDB0
CMDB2
CMDB11
CMDB15
CMDB28

K1
L2
J3
K3
L3

DQSB0
DQSB3

F3
C7

DQMB0
DQMB3

E7
D3

ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU

CMDB0

CMDB20

T2

RESET

L8

ZQ/ZQ0

DQSL
DQSU

G3
B7

CMDB20

T2

RESET

L8

ZQ/ZQ0

DQSL
DQSU

2
RV106
10K_0402_5%
8PCS@

J1
L1
J9
L9

RV78
243_0402_1%
8PCS@

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
@
+VRAM_1.5VS

CV236
8PCS@

2
2
1U_0402_6.3V6K

CV237
8PCS@

CV182
8PCS@

2
2
1U_0402_6.3V6K

CV183
8PCS@

0.1U_0402_16V4Z
CV184
8PCS@

2
2
0.1U_0402_16V4Z

CV185
8PCS@

0.1U_0402_16V4Z

CV186
8PCS@

2
2
0.1U_0402_16V4Z

CV187
8PCS@

+VRAM_1.5VS

1U_0402_6.3V6K

CV188
0.1U_0402_16V4Z
8PCS@

CV189
8PCS@

2
2
1U_0402_6.3V6K

CV190
8PCS@

0.1U_0402_16V4Z
CV191
8PCS@

2
2
0.1U_0402_16V4Z

CV192
8PCS@

0.1U_0402_16V4Z

CV193
8PCS@

CV194
8PCS@

2011/01/31

Issued Date

A7

A6

CMD24

A2

A1

CMD23

A11

A9

CMD26

A5

A4

CMD7

A0

A12

CMD15

CAS#

CAS#

CMD13

BA1

A3

CMD4

A9

2
2
0.1U_0402_16V4Z

Deciphered Date

CV195
0.1U_0402_16V4Z
8PCS@

CV238
8PCS@

BA0

BA0

CMD27

BA2

A15

CMD6

A3

BA1
CS1#_H
ODT_H

CMD22

A4

A5

CMD12

A13

A14

CMD28

WE#

A10

CMD10

A1

A2

CMD25

A10

WE#

CMD9

A12

A0

CMD1

CS1#_L
RAS#

RAS#

CMD0

ODT_L

CMD5

A6

A7
CKE_H

CMD20

RST

RST

CMD14

A14

A13

CMD30

A15

BA2

CV239
8PCS@

2
2
1U_0402_6.3V6K

2012/12/31

Title

Date:

A11
CS0#_H

CMD29

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

1U_0402_6.3V6K

Compal Secret Data

Security Classification

A8

CMD16

+VRAM_1.5VS

1U_0402_6.3V6K

A8
CS0#_L

CMD21

CMD11

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
@

+VRAM_1.5VS

1U_0402_6.3V6K

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

RV77
243_0402_1%
8PCS@

RV76
10K_0402_5%
8PCS@

J1
L1
J9
L9

32..63

CMD19
RV111
10K_0402_5%
8PCS@

G3
B7

DQSB#2
DQSB#1

CKE_L

CMD17

DQSB#0
DQSB#3

DML
DMU

CMD3

CMD18

CMDB3

DML
DMU

0..31

CMD2

+VRAM_1.5VS

BA0
BA1
BA2

Address

CMD8

Group1

CLKB0
CLKB0#
CMDB3

+FBB_VREF0

+VRAM_1.5VS

CLKB0

UV10

SCHEMATIC, MB A7211
Rev
B

4019BD

Monday, February 28, 2011

Sheet
1

22

of

59

Memory Partition C - Upper 32 bits


MDB[0..63] <19,22>
UV11

RV80
1.1K_0402_1%
8PCS@

CV196
0.01U_0402_25V7K
8PCS@

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

CMDB29
CMDB6
CMDB30

M2
N8
M3

BA0
BA1
BA2

CLKB1

<19>
<19>

RV81
160_0402_1%
8PCS@

CLKB1
CLKB1#
CMDB16

CLKB1
CLKB1#

CLKB1#

VREFCA
VREFDQ

CMDB9
CMDB24
CMDB10
CMDB13
CMDB26
CMDB22
CMDB21
CMDB5
CMDB8
CMDB23
CMDB28
CMDB4
CMDB7
CMDB14
CMDB12
CMDB27

J7
K7
K9
K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSB4
DQSB5

F3
C7

DQSL
DQSU

DQMB4
DQMB5

E7
D3

DML
DMU

DQSB#4
DQSB#5

G3
B7

DQSL
DQSU

RESET

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

D7
C3
C8
C2
A7
A2
B8
A3

MDB41
MDB46
MDB42
MDB47
MDB44
MDB45
MDB40
MDB43

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

CMDB19
CMDB18
CMDB11
CMDB15
CMDB25

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSB7
DQSB6

F3
C7

DQSL
DQSU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMB7
DQMB6

E7
D3

DML
DMU

DQSB#7
DQSB#6

G3
B7

DQSL
DQSU

T2

RESET

L8

ZQ/ZQ0

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

Group5

VREFCA
VREFDQ

CMDB9
CMDB24
CMDB10
CMDB13
CMDB26
CMDB22
CMDB21
CMDB5
CMDB8
CMDB23
CMDB28
CMDB4
CMDB7
CMDB14
CMDB12
CMDB27

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

CMDB29
CMDB6
CMDB30

M2
N8
M3

BA0
BA1
BA2

CLKB1
CLKB1#
CMDB16

J7
K7
K9

MDB56
MDB63
MDB57
MDB62
MDB58
MDB60
MDB59
MDB61

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB49
MDB55
MDB48
MDB53
MDB51
MDB52
MDB50
MDB54

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

RV83
243_0402_1%
8PCS@

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
@

CV122
390U_2.5V_M_R10
8PCS@

0.1U_0402_16V4Z

CV198
8PCS@

CV199
8PCS@

CV200
8PCS@

2
2
0.1U_0402_16V4Z

CV201
8PCS@

CV202
8PCS@

2
2
0.1U_0402_16V4Z

CV203
8PCS@

CV204
0.1U_0402_16V4Z
8PCS@

CV205
8PCS@

2
2
1U_0402_6.3V6K

0..31

CMD3

CKE_L

CV206
8PCS@

0.1U_0402_16V4Z
CV207
8PCS@

CMDB19

A8

2
2
0.1U_0402_16V4Z

CV208
8PCS@

CV209
8PCS@

A8

CS0#_L

CMD21

A7

A6

CMD24

A2

A1

CMD23

A11

A9

CMD26

A5

A4

CMD7

A0

A12

CMD15

CAS#

CAS#

CMD13

BA1

A3

CMD4

A9

CMDB16

A11

CMD29

BA0

BA0

CMD27

BA2

A15

CMD6

A3

BA1
CS1#_H

CMD19
RV108
10K_0402_5%
8PCS@

RV112
10K_0402_5%
8PCS@

ODT_H

CMD22

A4

A5

CMD12

A13

A14

CMD28

WE#

A10

CMD10

A1

A2

CMD25

A10

WE#

CMD9

A12

A0

CMD1

CS1#_L

CMD11

2
2
0.1U_0402_16V4Z

CV210
8PCS@

CV211
0.1U_0402_16V4Z
8PCS@

ODT_L

CMD5

A6

CV242
8PCS@

CV243
8PCS@

RAS#

RAS#

CMD0

A7

CMD16

1U_0402_6.3V6K

CS0#_H

CMD17

0.1U_0402_16V4Z

32..63

CMD18

+VRAM_1.5VS

Address

CMD2

0.1U_0402_16V4Z

2
2
1U_0402_6.3V6K
A

DATA Bus

Group6

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
@

1U_0402_6.3V6K
1U_0402_6.3V6K

<19,22>
<19,22>

GB2-128
Mode E - Mirror Mode Mapping

+VRAM_1.5VS

DQSB[7..0]
DQSB#[7..0]

Group7

+VRAM_1.5VS
+VRAM_1.5VS

<19,22>

DQMB[7..0] <19,22>

+VRAM_1.5VS

CK
CK
CKE/CKE0

RV82
243_0402_1%
8PCS@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

CMD8

CMDB20

T2

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

Group4

M8
H1

CMDB20

+FBB_VREF1

+VRAM_1.5VS

CK
CK
CKE/CKE0

CMDB19
CMDB18
CMDB11
CMDB15
CMDB25

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

MDB37
MDB35
MDB36
MDB34
MDB38
MDB32
MDB39
MDB33

CMDB[30..0]

UV12

E3
F7
F2
F8
H3
H8
G2
H7

+FBB_VREF1

RV79
1.1K_0402_1%
8PCS@

M8
H1

+FBB_VREF1

+VRAM_1.5VS

CKE_H

CMD20

RST

RST

CMD14

A14

A13

CMD30

A15

BA2

2
2
1U_0402_6.3V6K
A

+VRAM_1.5VS
1U_0402_6.3V6K

CV240
8PCS@

CV241
8PCS@

2
2
1U_0402_6.3V6K

Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

SCHEMATIC, MB A7211
Rev
B

4019BD

Monday, February 28, 2011

Sheet
1

23

of

59

RV88
34.8K_0402_1%
OPT@

Logical
Strapping Bit2
FB_0_BAR_SIZE

Logical
Strapping Bit1
SMB_ALT_ADDR

Power Rail

Logical
Strapping Bit0
VGA_DEVICE

+3VS_DGPU

XCLK_417

ROM_SCLK

+3VS_DGPU

ROM_SI

+3VS_DGPU

PCI_DEVID[4]

SUB_VENDOR

SLOT_CLK_CFG

PEX_PLLEN_TERM

RAMCFG[3]

RAMCFG[2]

RAMCFG[1]

STRAP2

RAMCFG[0]

+3VS_DGPU

PCI_DEVID[3]

PCI_DEVID[2]

PCI_DEVID[1]

PCI_DEVID[0]

STRAP1

+3VS_DGPU

3GIO_PADCFG[3]

3GIO_PADCFG[2]

3GIO_PADCFG[1]

3GIO_PADCFG[0]

STRAP0

+3VS_DGPU

USER[3]

USER[2]

USER[1]

USER[0]

Resistor Values
RV89
24.9K_0402_1%
N12PGS@

RV89
4.99K_0402_1%
N12PGV@

+3VS_DGPU

64M16
900MHz

SA000041S20
Samsung K4W1G1646E-HC11
SA000041T00

N12P-GS

Hynix H5TQ2G63BFR-11C

128M16
900MHz

SA00003YO00
Samsung K4W2G1646C-HC11
SA000047Q00
Hynix H5TQ1G63DFR-12C

64M16
800MHz

25K

1100

0100

30K

1101

0101

35K

1110

0110

45K

1111

0111

0x0DF4

Pull up 15K

Pull down 25K

N12P-GV

0x1050

Pull up 15K

Pull down 5K

Samsung K4W1G1646G-BC12

XCLK_417

No VBIOS ROM (Default)

277MHz (Default)

BIOS ROM is present

Reserved

FB_0_BAR_SIZE

USER Straps

256MB (Default)

User[3:0]

Reserved

1000-1100

RV93

0010

PD 15K

SD034154280

1GB

0010

PD 15K

SD034154280

512MB

0011

PD 20K

SD034200280

1GB

0011

PD 20K

SD034200280

1GB

0110

PD 34.8K

SD034348280

2GB

0110

PD 34.8K

SD034348280

1GB

0111

PD 45.3K

SD034453280

2GB

0111

PD 45.3K

SD034453280

SLOT_CLOCK_CFG

512MB

0010

PD 15K

SD034154280

GPU and MCH don't share a common reference clock

512MB

0011

PD 20K

SD034200280

GPU and MCH share a common reference clock (Default)

1GB

0110

PD 34.8K

SD034348280

SA00003VS00
Samsung K4W2G1646C-HC12

RV117
10K_0402_1%
N12PGV@

SUB_VENDOR

512MB

SA0000324C0

Hynix H5TQ2G63BFR-12C

128M16
800MHz

0011

N12P-GS

RV116
34.8K_0402_1%
@

RV109
4.99K_0402_1%
N12PGV@

RAMCFG[3..0]

SA00004HS00

N12P-GV

0010

1011

RV95
15K_0402_1%
@

VRAM
Hynix H5TQ1G63DFR-11C

1010

20K

STRAP3
STRAP4

DDR3 Type

15K

STRAP2

2
1
STRAP3
STRAP4

RV94
10K_0402_1%
N12PGS@

GPU

0001

<14>
<14>
RV93
15K_0402_1%
@

1001

ROM_SCLK

RV107
45.3K_0402_1%
@

X76

10K

DeviceID

GPU

+3VS_DGPU

ROM_SI
ROM_SO
ROM_SCLK

<14>
ROM_SI
<14>
ROM_SO
<14> ROM_SCLK

0000

RV92
15K_0402_1%
N12PGS@

RV91
10K_0402_1%
N12PGV@

RV90
4.99K_0402_1%
@

Pull-down to Gnd

1000

RV92
4.99K_0402_1%
N12PGV@
C

Pull-up to +3VS

5K

1GB

0111

PD 45.3K

3GIO_PADCFG

PEX_PLL_EN_TERM

3GIO_PADCFG[3:0]

Disable (Default)

Enable

0110

Notebook Default

SMBUS_ALT_ADDR

VGA_DEVICE

0x9E (Default)

3D Device

0x9C (Multi-GPU usage)

VGA Device (Default)

SD034453280

Issued Date

Compal Secret Data


2011/01/31

Deciphered Date

2012/12/31

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Customer defined
B

Security Classification

RV88
34.8K_0402_1%
DIS@

RV84
45.3K_0402_1%
@

Logical
Strapping Bit3

STRAP0
STRAP1
STRAP2

STRAP0
STRAP1
STRAP2

<14>
<14>
<14>

RV87
45.3K_0402_1%
OPT@

RV86
15K_0402_1%
@

RV85
34.8K_0402_1%
@

RV87
45.3K_0402_1%
DIS@

+3VS_DGPU

Physical
Strapping pin
ROM_SO

SCHEMATIC, MB A7211
Rev
B

4019BD

Monday, February 28, 2011

Sheet
1

24

of

59

R107
R109
C233
150_0603_5%
47K_0402_5%
0.1U_0402_16V4Z
EDP@
EDP@
EDP@
C229
Q1
0.01U_0402_25V7K
2N7002DW-T/R7_SOT363-6
EDP@
EDP@

<31> LCD_EDID_CLK

<31> LCD_TZCLK+

LVDS_TXCLK-

<31> LCD_TZCLK-

LVDS_TZOUT2-

Q1A
2N7002DW-T/R7_SOT363-6
OPT@

LVDS_TZCLK+

OPT@ 2
C228
0.1U_0402_16V7K

LVDS_TZCLK-

LVDS_EDID_DATA

LCD_ENVDD

LCD_ENVDD
EC_ENBKL

1
R109 2LCDPWR_GATE
1
2
47K_0402_5%
1
OPT@
C229
0.01U_0402_25V7K
OPT@ 2

OPT@
Q17
AO3413_SOT23

LCDPWR_GATE

W=80mils
2

+LCD_VDD

EDP@
Q23
AO3413_SOT23
+LCD_VDD

W=80mils

Q1B
2N7002DW-T/R7_SOT363-6
OPT@

R112
100K_0402_5%
OPT@

EC_ENBKL <44>

EDP@ 2
C292
0.1U_0402_16V7K

W=80mils

C233
0.1U_0402_16V4Z
OPT@

W=80mils

<31> UMA_ENBKL

+5VS

LVDS_TZOUT2+

LVDS_EDID_CLK

1 OPT@ 2
R350
0_0402_5%
1 OPT@ 2
R357
0_0402_5%

<31> UMA_ENVDD

+3VS

LVDS_TXCLK+

R120
100K_0402_5%
EDP@

<31> LCD_TZOUT2-

R108
100K_0402_5%
OPT@

<31> LCD_TZOUT2+

LVDS_TXOUT2-

LVDS_TZOUT1-

LVDS_TXOUT2+

R107
150_0603_5%
OPT@

LVDS_TZOUT1+

<31> LCD_EDID_DATA

<31> LCD_TZOUT1-

LVDS_TZOUT0-

<31> LCD_TXCLK+
<31> LCD_TXCLK-

LVDS_TXOUT1-

+5VS

<31> LCD_TXOUT2-

<31> LCD_TZOUT1+

+3VS

<31> LCD_TXOUT2+
1

<31> LCD_TZOUT0-

LVDS_TXOUT1+

LVDS_TZOUT0+

<31> LCD_TXOUT1-

LVDS_TXOUT0-

1 OPT@ 2
R270
0_0402_5%
1 OPT@ 2
R267
0_0402_5%
1 OPT@ 2
R269
0_0402_5%
1 OPT@ 2
R268
0_0402_5%
1 OPT@ 2
R337
0_0402_5%
1 OPT@ 2
R283
0_0402_5%
1 OPT@ 2
R333
0_0402_5%
OPT@
1
2
R329
0_0402_5%

<31> LCD_TXOUT1+

<31> LCD_TZOUT0+

<31> LCD_TXOUT0-

LVDS_TXOUT0+

+LCD_VDD
1 OPT@ 2
R262
0_0402_5%
1 OPT@ 2
R263
0_0402_5%
1 OPT@ 2
R265
0_0402_5%
1 OPT@ 2
R264
0_0402_5%
1 OPT@ 2
R298
0_0402_5%
1 OPT@ 2
R277
0_0402_5%
1 OPT@ 2
R297
0_0402_5%
OPT@
1
2
R296
0_0402_5%
1 OPT@ 2
R300
0_0402_5%
1 OPT@ 2
R299
0_0402_5%

<31> LCD_TXOUT0+

OPTIMUS

Close to LVDS Connector

LCD/PANEL BD. Conn.

DISCRETE
1 DISLVDS@
2
R331
0_0402_5%
1 DISLVDS@
2
R309
0_0402_5%
1 DISLVDS@
2
R317
0_0402_5%
1 DISLVDS@
2
R315
0_0402_5%
1 DISLVDS@
2
R308
0_0402_5%
1 DISLVDS@
2
R302
0_0402_5%
1 DISLVDS@
2
R305
0_0402_5%
1 DISLVDS@
2
R304
0_0402_5%
1 DISLVDS@
2
R314
0_0402_5%
1 DISLVDS@
2
R310
0_0402_5%

<14> VGA_TXOUT0+
<14> VGA_TXOUT0<14> VGA_TXOUT1+
2

<14> VGA_TXOUT1<14> VGA_TXOUT2+


<14> VGA_TXOUT2<14> VGA_TXCLK+
<14> VGA_TXCLK<13> VGA_EDID_CLK
<13> VGA_EDID_DATA

LVDS_TXOUT0+
LVDS_TXOUT0-

LVDS_TXOUT1LVDS_TXOUT2+

<13> VGA_ENBKL

+3VS

LVDS_TXOUT2LVDS_TXCLK+

EDP@

LVDS_TXCLKEDP@

2 R1434

1 LVDS_EDID_DATA
100K_0402_5%

2 R1435

1 LVDS_EDID_CLK
100K_0402_5%

LVDS_EDID_CLK
LVDS_EDID_DATA

1 DIS@ 2
R356
0_0402_5%
1 DIS@ 2
R358
0_0402_5%

<13> VGA_ENVDD

+3VS

LVDS_TXOUT1+

LCD_ENVDD
EC_ENBKL

CAM@
W=20mils
0.1U_0402_16V4Z
1 CAM@ 2 +3VS_LVDS_CAM
1
2
R388
0_0603_5%
C225
JLVDS
1 1
2
2
USB20_P11_R
3 3
4 4
USB20_N11_R
5 5
6 6
7 7
8 8
LVDS_TXOUT0+
9 9
10 10
LVDS_TXOUT011 11
12 12
LVDS_TXOUT1+
13 13
14 14
LVDS_TXOUT115 15
16 16
LVDS_TXOUT2+
17 17
18 18
LVDS_TXOUT219 19
20 20
21 21
22 22
LVDS_TZOUT0+
23 23
24 24
LVDS_TZOUT025 25
26 26
LVDS_TZOUT1+
27 27
28 28
LVDS_TZOUT129 29
30 30
LVDS_TZOUT2+
31 31
32 32
LVDS_TZOUT233 33
34 34
BKOFF#_R
35 35
36 36
37 37
38 38
39 39
+LCD_INV
40 40
41 GMD GND 42

INT_MIC_CLK

For EMI
1

LVDS_TXCLK+
LVDS_TXCLK-

C13
CAM@
220P_0402_50V7K

1 R143
2 EDP@
0_0402_5%

D84
2

LVDS_TZCLK+
LVDS_TZCLK-

+3VS_LVDSDDC

2 R1440 1 NOEDP@
0_0603_5%

LVDS_EDID_CLK
LVDS_EDID_DATA
INT_MIC_CLK
INT_MIC_DATA
LCD_ENVDD
LED_PWM
R387 2
+3VS_LVDSDDC

AZ5125-02S.R7G_SOT23-3

1 0_0402_5%

1
@
C231
680P_0402_50V7K
2

INVT_PWM <44>

C232
0.1U_0402_16V4Z

3A
+LCD_VDD
1

C226
0.1U_0402_16V4Z
2

+LCD_INV

1
RB751V40_SC76-2

C227
4.7U_0805_10V4Z

BKOFF#_R

2
D18
@

2
R103
1
R113

ACES_87242-4001-09
@

Close to LVDS Connector

+3VS

For EMI

INT_MIC_CLK <43>
INT_MIC_DATA <43>
@

EDP_HPD <13>

1
33_0402_5%
2
10K_0402_5%

BKOFF# <44>

DISCRETE for Dual Chanel Panel

<14> VGA_TZOUT1<14> VGA_TZOUT2+


<14> VGA_TZOUT2<14> VGA_TZCLK+
<14> VGA_TZCLK-

Reserve for EMI request


3

LVDS_TZOUT01 CAM@ 2
R78
0_0402_5%
L55
@
1 1
2 2

LVDS_TZOUT1+
LVDS_TZOUT1-

<32> USB20_N11

+LCD_INV
USB20_N11_R
1

LVDS_TZOUT2+
4

<32> USB20_P11

LVDS_TZOUT2-

USB20_P11_R

C234
68P_0402_50V8J
2

WCM-2012-900T_0805

<14> VGA_EDP_TX1<14> VGA_EDP_TX2+


<14> VGA_EDP_TX2<14> VGA_EDP_TX3+
<14> VGA_EDP_TX3<14> VGA_EDP_AUX
<14> VGA_EDP_AUXA

C882
C883
C884
C885
C886
C887
C888
C889

R108
100K_0402_5%
NO3D@

Q1
2N7002DW-T/R7_SOT363-6
NO3D@

R109
47K_0402_5%
NO3D@

C228
0.1U_0402_16V7K
NO3D@

C229
0.01U_0402_25V7K
NO3D@

C233
0.1U_0402_16V4Z
NO3D@

B+
<31> PCH_PWM

1 OPT@ 2
R332
0_0402_5%

@
1
2
R347
0_0402_5%

<13> VGA_BL_PWM

1 3D@
2
R349
0_0402_5%

2
D17

LVDS_TXOUT0+
LVDS_TXOUT0-

For EMI

LED_PWM

R131
47K_0402_5%

1
RB751V40_SC76-2

LVDS_TXOUT1+

C236
@

LVDS_TXOUT1-

0.1U_0402_25V6

<14> VGA_EDP_TX1+

EDP@
1
20.1U_0402_16V7K
EDP@
1
20.1U_0402_16V7K
EDP@
1
20.1U_0402_16V7K
EDP@
1
20.1U_0402_16V7K
EDP@
1
20.1U_0402_16V7K
EDP@
1
20.1U_0402_16V7K
EDP@
1
20.1U_0402_16V7K
EDP@
1
20.1U_0402_16V7K

R107
150_0603_5%
NO3D@

Q17
AO3413_SOT23
NO3D@

<14> VGA_EDP_TX0-

C881

C235
0.1U_0402_25V6
2

1 CAM@ 2
R96
0_0402_5%

LVDS_TZCLK-

DISCRETE for Full-HD and 3D eDP Panel


C880

L2
2
1
1 FBMA-L11-201209-221LMA30T_0805

LVDS_TZCLK+

Close to LVDS1 Connector

<14> VGA_EDP_TX0+

B+

1
C268
@

1
C489
@

1
C490
@

0.1U_0402_25V6

<14> VGA_TZOUT1+

LVDS_TZOUT0+

0.1U_0402_25V6

<14> VGA_TZOUT0-

0.1U_0402_25V6

1 DISLVDS@
2
R500
0_0402_5%
1 DISLVDS@
2
R501
0_0402_5%
1 DISLVDS@
2
R502
0_0402_5%
1 DISLVDS@
2
R503
0_0402_5%
1 DISLVDS@
2
R504
0_0402_5%
1 DISLVDS@
2
R505
0_0402_5%
1 DISLVDS@
2
R507
0_0402_5%
1 DISLVDS@
2
R508
0_0402_5%

<14> VGA_TZOUT0+
3

LVDS_TXOUT2+
LVDS_TXOUT2LVDS_TXCLK+

Issued Date

Close to LVDS Connector


B

Compal Electronics, Inc.

Compal Secret Data

Security Classification

LVDS_TXCLK-

EDP@
1
20.1U_0402_16V7K LVDS_EDID_CLK
EDP@
1
20.1U_0402_16V7K LVDS_EDID_DATA

2011/01/31

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, MB A7211
Rev
B

4019BD

Date:

Monday, February 28, 2011


G

Sheet

25

of

59
H

D4

D5

CRT CONNECTOR
D3

+3VS

If=1A

+5VS

L3

2 NBQ100505T-800Y_0402

CRT_R_L

CRT_G

L4

2 NBQ100505T-800Y_0402

CRT_G_L

CRT_B

L5

2 NBQ100505T-800Y_0402

CRT_HSYNC
CRT_VSYNC

1
1
RB491D_SOT23-3

40 mils

2
1
1.1A_6V_MINISMDC110F-2
C237
0.1U_0402_16V4Z
2
@

JCRT

Close to CRT Connector

1
C238

C239

C240

1
C241

1
C242

1
C243

2.2P_0402_50V8C

R138 R139 R140

2.2P_0402_50V8C

CRT_DATA

CRT_B_L

CRT_CLK
2.2P_0402_50V8C

<31> UMA_CRT_DATA

CRT_R
CRT_B

2.2P_0402_50V8C

<31> UMA_CRT_CLK

+CRT_VCC

F1

CRT_G

2.2P_0402_50V8C

<31> UMA_CRT_VSYNC

DAN217_SC59

2.2P_0402_50V8C

<31> UMA_CRT_HSYNC

DAN217_SC59

CRT_R

2
1
150_0402_1%

<31> UMA_CRT_G
<31> UMA_CRT_B

1 OPT@ 2
R200
0_0402_5%
1 OPT@ 2
R204
0_0402_5%
1 OPT@ 2
R211
0_0402_5%
1 OPT@ 2
R213
0_0402_5%
1 OPT@ 2
R235
0_0402_5%
1 OPT@ 2
R236
0_0402_5%
1 OPT@ 2
R261
0_0402_5%

2
1
150_0402_1%

<31> UMA_CRT_R

DAN217_SC59

2
1
150_0402_1%

+CRT_VCC_R

D6

OPTIMUS

T75 PAD

CRT_R_L

CRT_DDC_DAT
CRT_G_L
HSYNC
CRT_B_L
+CRT_VCC

VSYNC
T76 PAD
CRT_DDC_CLK

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

G
G

16
17

ALLTO_C10532-11505-L_15P-T
2

+CRT_VCC

2
0.1U_0402_16V4Z

2
R141

<13> VGA_CRT_CLK
<13> VGA_CRT_DATA

CRT_B

1
L6

2
10_0402_5%

CRT_VSYNC

CRT_HSYNC

D_CRT_VSYNC

1
L7

2
10_0402_5%

HSYNC

5
1

CRT_G

D_CRT_HSYNC
+CRT_VCC

U6
SN74AHCT1G125GW_SOT353-5

U7
SN74AHCT1G125GW_SOT353-5

CRT_VSYNC

C245
@

VSYNC

CRT_CLK
CRT_DATA

1
C246
@

10P_0402_50V8J

<13> VGA_CRT_VSYNC

10P_0402_50V8J

<13> VGA_CRT_HSYNC

<13> VGA_CRT_B

CRT_R

1
10K_0402_5%

<13> VGA_CRT_G

1 DIS@ 2
R178
0_0402_5%
1 DIS@ 2
R181
0_0402_5%
1 DIS@ 2
R167
0_0402_5%
DIS@
1
2
R177
0_0402_5%
1 DIS@ 2
R179
0_0402_5%
1 DIS@ 2
R193
0_0402_5%
1 DIS@ 2
R194
0_0402_5%

CRT_HSYNC
<13> VGA_CRT_R

P
OE#

DISCRETE

P
OE#

5
1

1
C244

Close to CRT Connector


3

+CRT_VCC

+3VS

5
Q205B
4

CRT_DATA

1
C282
33P_0402_50V8K
2
@

2
Q205A
1

CRT_CLK

R159
4.7K_0402_5%

R153
4.7K_0402_5%

CRT_DDC_CLK

2N7002DW-T/R7_SOT363-6
CRT_DDC_DAT

2N7002DW-T/R7_SOT363-6

C285
33P_0402_50V8K
2 @

C284
470P_0402_50V8J
@

C283
470P_0402_50V8J
2 @

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
E

26

of

59

CEC_INT#

P1_5/RXD0/CNTR01/INT11#

CEC_TEST

RESET#

P1_4/TXD0

13

CEC_FSHUPD1 CEC@ 2
R170
4.7K_0402_5%

1 1

2 CEC@ 1CEC_XOUT 4
R171
47K_0402_5%

P1_3/KI3#/AN11/TZOUT

14

2
G

2 CEC@ 1CEC_XIN
R174
47K_0402_5%

VCC/AVCC

P1_1/KI1#/AN9/CMP0_1

17

MODE

P1_0/KI0#/AN8/CMP0_0

18

HDMI_DATA

P4_5/INT0#/RXD1

P3_3/TCIN/INT3#/SSI00/CMP1_0

19

HDMI_HPD_R

P3_4/SCS#/SDA/CMP1_1

20

15

P4_2/VREF

16

R165
100K_0402_5%
CEC@

2 CEC@ 1
R176
4.7K_0402_5%
C262
1
0.1U_0402_16V4Z
CEC@

HDMI_DATA

HDMI_CECIN
HDMI_CECOUT

10

P1_7/CNTR00/INT10#

HDMI_SCLK

HDMI_SDATA

1
Q48
BSH111_SOT23-3
CEC@

EC_SMB_DA1 <44,49>

Q47
BSH111_SOT23-3
CEC@

2
G

HDMI_CLK

D
Q50
2N7002_SOT23-3
CEC@

R164
4.7K_0402_5%
CEC@

1 R163
2
27K_0402_5%
CEC@

R166
4.7K_0402_5%
CEC@

1
C848
1
C263

P1_2/KI2#/AN10/CMP0_2

XIN/P4_6

VSS/AVSS

CEC@
2
1U_0402_6.3V6K
2
0.1U_0402_16V4Z
CEC@
HDMI_CLK

HDMI_CEC

CEC_FSHUPD (Pin13)
Low= Force to update flash.
+3VL

+3VL

XOUT/P4_7

+3VL

P3_7/CNTR0#/SSO/TXD1

CEC_INT# <44> +3VL

1 CEC@ 2
R168
4.7K_0402_5%

2 CEC@ 1CEC_RST#
R169
4.7K_0402_5%

R581
27K_0402_5%
CEC@

HDMI_CECOUT

11
12

D9
CH751H-40PT_SOD323-2
CEC@

R162
10K_0402_5%
CEC@

Q49
2N7002_SOT23-3
CEC@

P1_6/CLK0/SSI01

P3_5/SSCK/SCL/CMP1_2

+3VL

HDMI_CECIN

U16

Address: 0011010X
<44,49> EC_SMB_CK1

+3VL

+3VL

HDMI CEC Controller

R5F211A4C33SP-W4_LSSOP20

CEC@

+3VS

+3VS_DGPU
+HDMI_5V_OUT

<14> VGA_HDMI_TX0-

CV298

2 0.1U_0402_16V7K DHDMI@

VGA_DVI_TXD1-

CV295

2 0.1U_0402_16V7K DHDMI@

VGA_DVI_TXD2+

CV300

2 0.1U_0402_16V7K DHDMI@

VGA_DVI_TXD2-

VGA_DVI_TXD0-

2
R401

<14> VGA_HDMI_DATA

1
3
0_0402_5%

2
R438

<31> UMA_HDMI_DATA

5
P

74AHCT1G125GW_SOT353-5
HDMI@

C265
0.1U_0402_16V4Z
HDMI@

HDMI_SCLK

Q18
BSH111_SOT23-3
HDMI@
1

DHDMI@

VGA_DVI_TXD1+

HDMI_HPD_C

2 0.1U_0402_16V7K DHDMI@

U9

OE#

2 0.1U_0402_16V7K DHDMI@

CV299

A
3

CV297

DHDMI@
2
1
R391
0_0402_5%

<14> VGA_HDMI_CLK

R186
100K_0402_5%
HDMI@
HDMI_HPD_R

VGA_DVI_TXD0+

R185
2.2K_0402_5%
HDMI@

VGA_DVI_TXC-

2 0.1U_0402_16V7K DHDMI@

2 0.1U_0402_16V7K DHDMI@

R184
2.2K_0402_5%
HDMI@

HDMI_SDATA
+3VL

<14> VGA_HDMI_TX2-

CV294

<14> VGA_HDMI_TX2+

CV293

<31> UMA_HDMI_CLK

<14> VGA_HDMI_TX1-

VGA_DVI_TXC+

<14> VGA_HDMI_TX1+

2 0.1U_0402_16V7K DHDMI@

C264
0.1U_0402_16V4Z
HDMI@

<14> VGA_HDMI_TX0+

<14> VGA_HDMI_CLK-

CV296

<14> VGA_HDMI_CLK+

IHDMI@
2
1
R435
0_0402_5%

For DISCRETE

HDMI@
R145
HDMI_HPD_U 1
2
1K_0402_5%

+5VL

R453
R452
0_0402_5% 0_0402_5%
IHDMI@
DHDMI@

Q19
IHDMI@
BSH111_SOT23-3
1
HDMI@
0_0402_5%

HDMI@
2
1
R570
100K_0402_5%

HDMI@
2
1
R571
2.2K_0402_5%

+3VS

D55
HDMI_HPD_R

HDMI_HPD

<13,31,33>

CH751H-40PT_SOD323-2
HDMI@

<31> UMA_HDMI_TXCB

<31> UMA_HDMI_TX0+
<31> UMA_HDMI_TX0<31> UMA_HDMI_TX1+
<31> UMA_HDMI_TX1<31> UMA_HDMI_TX2+
<31> UMA_HDMI_TX2-

CV308

2 0.1U_0402_16V7K IHDMI@

VGA_DVI_TXC+

CV304

2 0.1U_0402_16V7K IHDMI@

VGA_DVI_TXC-

CV306

2 0.1U_0402_16V7K IHDMI@

VGA_DVI_TXD0+

CV302

2 0.1U_0402_16V7K IHDMI@

CV303

2 0.1U_0402_16V7K IHDMI@

4
VGA_DVI_TXC+

2
0_0402_5%

HDMI_R_CK-

HDMI_R_CK+
HDMI_R_CK-

1
4

WCM-2012-900T_4P
@
1
2
R173
0_0402_5%

HDMI_R_D1HDMI_R_D1+
HDMI_R_D0+
HDMI_R_CK+
HDMI_R_D0HDMI_R_D2-

VGA_DVI_TXD0-

VGA_DVI_TXD0+

1
R175
L9

VGA_DVI_TXD1+

CV301

2 0.1U_0402_16V7K IHDMI@

VGA_DVI_TXD1-

CV307

2 0.1U_0402_16V7K IHDMI@

VGA_DVI_TXD2+

CV305

2 0.1U_0402_16V7K IHDMI@

VGA_DVI_TXD2-

1
4

2
0_0402_5%

VGA_DVI_TXD1-

@
1
R182
L10

2
0_0402_5%

WCM-2012-900T_4P
@
1
2
R183
0_0402_5%

VGA_DVI_TXD1+

VGA_DVI_TXD2+

1
R187
L11
1

1
4

HDMI_R_D0+
HDMI_R_D2+

+5VS

WCM-2012-900T_4P
@
1
2
R180
0_0402_5%

VGA_DVI_TXD0-

VGA_DVI_TXD2-

1 DHDMI@2
R195
499_0402_1%
1 DHDMI@2
R197
499_0402_1%
1 DHDMI@2
R198
499_0402_1%
1 DHDMI@2
R202
499_0402_1%
1 DHDMI@2
R201
499_0402_1%
1 DHDMI@2
R203
499_0402_1%
DHDMI@
1
2
R205
499_0402_1%
DHDMI@
1
2
R206
499_0402_1%

2
0_0402_5%
2

WCM-2012-900T_4P
@
1
2
R188
0_0402_5%

HDMI@
D53
+5VS

F2
+HDMI_5V_OUT_F 2
1
+HDMI_5V_OUT
1.1A_6V_MINISMDC110F-21
HDMI@
C259
HDMI@
0.1U_0402_16V4Z
2

PMEG2010AEH_SOD123
D54
+5VL

2
G

Q24
2N7002_SOT23-3
HDMI@

HDMI_R_D0-

HDMI Connector
HDMI_R_D1-

JHDMI
HDMI_HPD_C

HDMI_R_D1+

HDMI_R_D2+

R195
680_0402_5%
IHDMI@

R197
680_0402_5%
IHDMI@

R198
680_0402_5%
IHDMI@

R202
680_0402_5%
IHDMI@

R201
680_0402_5%
IHDMI@

R203
680_0402_5%
IHDMI@

R205
680_0402_5%
IHDMI@

R206
680_0402_5%
IHDMI@

HDMI_SDATA
HDMI_SCLK
HDMI_CEC
HDMI_R_CKHDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+

07/10/2010
Intel DG P.132

HDMI_R_D2-

Issued Date

Deciphered Date

2012/12/31

Title

Date:

20
21
22
23

Compal Electronics, Inc.

Compal Secret Data


2011/01/31

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

TYCO_1939864-1_19P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+HDMI_5V_OUT

Security Classification

PMEG2010AEH_SOD123
CEC@

For Optimus
<31> UMA_HDMI_TXC+

1
R157
L8

VGA_DVI_TXC-

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
1

27

of

59

U2A

NC

OSC

C315
10P_0402_50V8J

<43> AZ_BITCLK_HD

Integrated SUS 1.05V VRM Enable


High - Enable Internal VRs
PCH_INTVRMEN (must be always pulled high)

R286 1

2 33_0402_5%

<43> PCH_SPKR
<43> AZ_RST_HD#

+RTCVCC

R142 1

2 33_0402_5%

SM_INTRUDER#
2
1M_0402_5%
PCH_INTVRMEN
2
330K_0402_5%

R118 1
+3VS
@

1
R276

PCH_SPKR

2
1K_0402_5%

PCH_SPKR
High = Enabled "No Reboot Mode"
Low = Disabled (Default)

<43> AZ_SDOUT_HD

+3VALW_PCH

1
R560

2010/08/22
<44> PWRME_CTRL#
Change PWRME_CTRL#
to HDA_SDO by PCH EDS
<41> CR_CPPE#

CR_CPPE#

2
10K_0402_5%

+3VALW_PCH

2
R273
R289 1
R580 1

RTCX2

PCH_RTCRST#

D20

RTCRST#

PCH_SRTCRST#

G22

SRTCRST#

SM_INTRUDER#

K22

PCH_INTVRMEN

C17

2 33_0402_5%

INTRUDER#

N34

HDA_BCLK

AZ_SYNC

L34

HDA_SYNC

PCH_SPKR

T10

SPKR

AZ_RST#

K34

HDA_RST#

AZ_SDOUT

2 0_0402_5%
CR_CPPE#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

PCH_JTAG_TCK

J3

T37 PAD

PCH_JTAG_TMS

H7

JTAG_TMS

T38 PAD

PCH_JTAG_TDI

K5

JTAG_TDI

T39 PAD

PCH_JTAG_TDO

H1

JTAG_TDO

JTAG_TCK

down

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

PCH_SPIDI

+5VS

PCH_SPIDO

AZ_SYNC_R
2
33_0402_5%

1
R125

2
1M_0402_5%

Q21
1
D

1
R156

<43> AZ_SYNC_HD

T3

PCH_SPICS#

AZ_SYNC
1
1K_0402_5%

2
R284

+3VALW_PCH

PCH_SPICLK

U3

SPI

HDA_SYNC
L=>On Die PLL is supplied by 1.8V
Need to pull high for Huron River platform

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

FWH4 / LFRAME#

D36

LPC_FRAME#

LDRQ0#
LDRQ1# / GPIO23

E36
K36

SERIRQ

signal has a weak internal pull


*This
H=>On Die PLL is supplied by 1.5V

C38
A38
B37
C37

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

INTVRMEN

AZ_BITCLK

1
1K_0402_5%

HDA_SDO
ME debug mode,
this signal has a weak internal pull down
= Disable (default)
*Low
High = Enable (flash descriptor security overide)

RTCX1

C20

AZ_SDIN0_HD

<43> AZ_SDIN0_HD

R117 1

A20

PCH_RTCX2

LPC

PCH_RTCX1

SPI_MISO

V5

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

AM3
AM1
AP7
AP5

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AM10
AM8
AP11
AP10

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AD7
AD5
AH5
AH4

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

AB8
AB10
AF3
AF1

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

Y7
Y5
AD3
AD1

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

Y3
Y1
AB3
AB1

SATAICOMPO

Y11

SATAICOMPI

Y10

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

<44,45>
<44,45>
<44,45>
<44,45>

LPC_FRAME# <44,45>
+3VS

SERIRQ

SERIRQ

SERIRQ <44,45>

SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

SATA_PRX_C_DTX_N0 <37>
SATA_PRX_C_DTX_P0 <37>
SATA_PTX_DRX_N0 <37>
SATA_PTX_DRX_P0 <37>

SATA_PRX_C_DTX_N2 <37>
SATA_PRX_C_DTX_P2 <37>
SATA_PTX_DRX_N2 <37>
SATA_PTX_DRX_P2 <37>

1
10K_0402_5%

+3VS

HDD

SATA_PRX_C_DTX_N1 <37>
SATA_PRX_C_DTX_P1 <37>
SATA_PTX_DRX_N1 <37>
SATA_PTX_DRX_P1 <37>
SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2

2
R136

SATA_LED#

R336 2

1 10K_0402_5%

CR_WAKE#

R334 2

1 10K_0402_5%

PCH_GPIO19

R335 1

2 10K_0402_5%

HDD2
ODD

+RTCBATT

C248 1
1U_0402_6.3V6K

C486

SATAICOMP

1
R279

2
37.4_0402_1%

+1.05VS_VCC_SATA

SATA3_COMP

1
R280

2
49.9_0402_1%

+1.05VS_SATA3

1
R281

2
750_0402_1%

AB12

SATA3COMPI

AB13

SATA3RBIAS

AH1

RBIAS_SATA3

P3

SATA_LED#

V14

CR_WAKE#

P1

PCH_GPIO19

SATALED#

SATA1GP / GPIO19

COUGARPOINT_FCBGA989~D

+3VL

0.1U_0402_16V4Z
2

SATA3RCOMPO

SATA0GP / GPIO21

D13
BAS40-04_SOT23-3

+RTCVCC

2PCH_SRTCRST#

OSC

32.768KHZ_12.5PF_Q13MC14610002
2
1
C205
15P_0402_50V8J

@
2

NC

R293 1
20K_0402_5%

JME
1

1
15P_0402_50V8J

SATA 6G

iME Setting.

2
C216
Y3
AZ_BITCLK_HD

SATA

C247 1
1U_0402_6.3V6K

RTC

JCOMS @
1
2

PCH_RTCRST#

IHDA

JTAG

R292 1
20K_0402_5%

R291
10M_0402_5%
2
1

CMOS Setting, near DDR Door


+RTCVCC

SATA_LED# <46>
CR_WAKE# <41>
PCH_GPIO19 <32>

BOOT BIOS Strap Bit 0

Q65R3@

BSS138_NL_SOT23-3
@
1
2
R285
0_0402_5%

+3VS

4M Byte
1

VCC
W

HOLD

PCH_SPICS#

PCH_SPICLK

PCH_SPIDI

PCH_SPICLK

VSS

8
3

R397
10_0402_5%

C494
0.1U_0402_16V4Z
B

for EMI

U13

C86
10P_0402_50V8J

PCH_SPIDO

MX25L3205DM2I-12G SO8

Socket: SP07000F500/SP07000H900

+3VALW_PCH

+3VALW_PCH

1
R306
100_0402_1%

PCH_JTAG_TDO

PCH_JTAG_TMS

R278
200_0402_5%

R330
200_0402_5%

R363
200_0402_5%

PCH_JTAG_TDI

+3VALW_PCH

Please close to U2 PCH

R301
100_0402_1%

R295
100_0402_1%

PCH_JTAG_TCK
2
51_0402_1%

1
R355

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Deciphered Date

2012/12/31

Title

SCHEMATIC, MB A7211

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019BD

Date:

Monday, February 28, 2011

Sheet
1

28

of

59

U2B

Card Reader

C505 1
C503 1

<41>
<41>
<41>
<41>

PCIE_PRX_C_CRTX_N4
PCIE_PRX_C_CRTX_P4
PCIE_PTX_C_CRRX_N4
PCIE_PTX_C_CRRX_P4

C504 1
C868 1

<42>
<42>
<42>
<42>

USB30

PCIE_PRX_C_USBTX_N6
PCIE_PRX_C_USBTX_P6
PCIE_PTX_C_USBRX_N6
PCIE_PTX_C_USBRX_P6

C519 1
C869 1

PERN2
PERP2
PETN2
PETP2

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_PRX_JETTX_N3
PCIE_PRX_JETTX_P3
PCIE_PTX_JETRX_N3
PCIE_PTX_JETRX_P3

BG36
BJ36
AV34
AU34

PERN3
PERP3
PETN3
PETP3

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_PRX_C_CRTX_N4
PCIE_PRX_C_CRTX_P4
PCIE_PTX_CRRX_N4
PCIE_PTX_CRRX_P4

BF36
BE36
AY34
BB34

PERN4
PERP4
PETN4
PETP4

PCIE_PRX_C_USBTX_N6
PCIE_PRX_C_USBTX_P6
PCIE_PTX_USBRX_N6
PCIE_PTX_USBRX_P6

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

+3VS
R287 1

2 10K_0402_5% CLKREQ_JET#

R338 1

2 10K_0402_5% CLKREQ_WLAN#

LAN

<40>
<40>

CLK_LAN#
CLK_LAN

CLK_LAN#
CLK_LAN

WLAN

JET

<39>
<39>

<41>

Card Reader <41>

<42> CLK_USB30#
<42> CLK_USB30

USB30

+3VALW_PCH

<42> CLKREQ_USB30#
R343 1

210K_0402_5%

CLKREQ_LAN#

R344 1

210K_0402_5%

PCH_GPIO26

R345 1

210K_0402_5%

R346 1

210K_0402_5% CLKREQ_USB30#

A8

PANEL_SEL

R351 1

210K_0402_5% PASSWORD_CLEAR#

R233
R282

@
@

PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P

1 0_0402_5%
1 0_0402_5%

C8

PCH_SMLCLK0

G12

PCH_SMLDATA0

SML1ALERT# / PCHHOT# / GPIO74

C13

PCH_GPIO74

SML1CLK / GPIO58

E14

PCH_SMLCLK1

M16

PCH_SMLDATA1

SML0CLK

SML1DATA / GPIO75

CL_CLK1

T11

CL_RST1#

P10

PCIECLKRQ5# / GPIO44

LVDS_SEL

PM_SMBCLK <11,12,39>

+3VALW_PCH

CLK_PCIE_VGA#
CLK_PCIE_VGA

CLKOUT_DMI_N
CLKOUT_DMI_P

AV22
AU22

CLK_CPU_DMI#
CLK_CPU_DMI

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

AM12
AM13

CLK_DPLL#
CLK_DPLL

CLKIN_DMI_N
CLKIN_DMI_P

BF18
BE18

PCH_CLK_DMI#
PCH_CLK_DMI

CLK_REQ_VGA# <13>

2 R364

1 2.2K_0402_5%

2 R385

1 2.2K_0402_5%

+3VS
Q4B
3

EC_SMB_DA2 <14,44,45,46>

2N7002DW-T/R7_SOT363-6

EC_SMB_CK2 <14,44,45,46>

EC_LID_OUT#

R123 1

2 10K_0402_5%

DRAMRST_CNTRL_PCH

R228 1

2 1K_0402_5%

PCH_GPIO74

R234 1

2 10K_0402_5%

PCH_SMLCLK0

R238 1

2 10K_0402_5%

PCH_SMLDATA0

R239 1

2 10K_0402_5%

CLK_PCIE_VGA# <13>
CLK_PCIE_VGA <13>

+3VALW_PCH

CLK_CPU_DMI# <5>
CLK_CPU_DMI <5>
T13
T14

PAD
PAD

BJ30
BG30

CLKIN_GND1#
CLKIN_GND1

G24
E24

CLK_DOT#
CLK_DOT

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

AK7
AK5

CLK_SATA#
CLK_SATA

REFCLK14IN

K45

CLK_14M_PCH

CLKIN_PCILOOPBACK

H45

CLK_PCILOOP

XTAL25_IN
XTAL25_OUT

V47
V49

PCH_X1
PCH_X2

XCLK_RCOMP

Y47

XCLK_RCOMP
1
R354

CLKOUTFLEX0 / GPIO64

K43

CLK_FLEX0

T29

PAD

CLKOUTFLEX1 / GPIO65

F47

CLKOUTFLEX2 / GPIO66

H47

PCH_48MCLK 1 @ R576 2
22_0402_5%
CLK_FLEX2
T31

PAD

K49

CLK_FLEX3

CLKIN_GND1_NCLKIN_DMI2_N
CLKIN_GND1_PCLKIN_DMI2_P

VGA
@
1 CLK_REQ_VGA#
2
10K_0402_5%
R275

2
R303

1
10K_0402_5%

120 MHz for eDP

From Clock Gen.

PCH_CLK_DMI#
PCH_CLK_DMI

R242 1
R243 1

2 10K_0402_5%
2 10K_0402_5%

CLKIN_GND1#
CLKIN_GND1

R244 1
R245 1

2 10K_0402_5%
2 10K_0402_5%

CLK_DOT#
CLK_DOT

R246 1
R247 1

2 10K_0402_5%
2 10K_0402_5%

CLK_SATA#
CLK_SATA

R248 1
R249 1

2 10K_0402_5%
2 10K_0402_5%

CLK_14M_PCH

R250 1

2 10K_0402_5%

For EMI
CLK_PCILOOP <32>
CLK_PCILOOP

@
2
R417

@
2
1
C474
22P_0402_50V8J

1
10_0402_5%

PEG_B_CLKRQ# / GPIO56
CLKOUT_PCIE6N
CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38
V37

CLKOUT_PCIE7N
CLKOUT_PCIE7P
PCIECLKRQ7# / GPIO46
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P

CLKOUTFLEX3 / GPIO67

2
90.9_0402_1%

T33

+1.05VS_VCCDIFFCLKN

48MCLK_USB30 <42>

PAD

PANEL_SEL

Single
(Default)

Dual

Channel

LVDS

EDP

C506

PANEL_SEL

1 1M_0402_5%
Y2

PCH_X1

Q65R3@

R365 2

48MCLK_USB30

Control Link only for support Intel IAMT.

AB37
AB38

COUGARPOINT_FCBGA989~D

LVDS_SEL

PM_SMBDATA <11,12,39>

2N7002DW-T/R7_SOT363-6

<7>

PCH_SMLCLK1

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

V40
V42

AK14
AK13

4
2N7002DW-T/R7_SOT363-6

Q4A

CLK_REQ_VGA#

CLKIN_DOT_96N
CLKIN_DOT_96P

L14

DRAMRST_CNTRL_PCH

4.7K_0402_5%
4.7K_0402_5%

M7

CL_DATA1

PCIECLKRQ3# / GPIO25

CLKOUT_PCIE5N
CLKOUT_PCIE5P

CLK_BCLK_ITP#
CLK_BCLK_ITP

T54 PAD
T55 PAD

3
Q3A

PCH_SMLDATA1

M10

CLKOUT_PCIE3N
CLKOUT_PCIE3P

V45
V46

K12

PCH_SMBDATA

R400
R386

+3VALW_PCH

PCIECLKRQ2# / GPIO20

CLKREQ_USB30#

+3VS
Q3B

2N7002DW-T/R7_SOT363-6

CLKOUT_PCIE2N
CLKOUT_PCIE2P

CLK_USB30#
CLK_USB30

PANEL_SEL

1 2.2K_0402_5%

EC_LID_OUT# <44>

A12 DRAMRST_CNTRL_PCH

SML0DATA

PCIECLKRQ1# / GPIO18

PCIECLKRQ4# / GPIO26

LVDS_SEL

2
2

SML0ALERT# / GPIO60

PEG_A_CLKRQ# / GPIO47

L12

210K_0402_5%

PCH_SMBDATA

CLKOUT_PCIE0N
CLKOUT_PCIE0P

PCH_GPIO26

E6

C9

1 2.2K_0402_5%

2 R260

PCH_SMBCLK

CLKOUT_PCIE4N
CLKOUT_PCIE4P

PASSWORD_CLEAR#
JPW
@

PCH_SMBCLK

CLKREQ_CR#

H14

SMBDATA

Y43
Y45

AB42
AB40

R348 1 OPT@

<10> CLK_RES_ITP#
<10> CLK_RES_ITP

PERN8
PERP8
PETN8
PETP8

Y37
Y36

CLKREQ_CR#

BE38
BC38
AW38
AY38

V10

CLK_CR#
CLK_CR

CLK_CR#
CLK_CR

PERN7
PERP7
PETN7
PETP7

AA48
AA47

CLKREQ_JET#

<39> CLKREQ_JET#

BG40
BJ40
AY40
BB40

M1

CLK_JET#
CLK_JET

CLK_JET#
CLK_JET

PERN6
PERP6
PETN6
PETP6

AB49
AB47

CLKREQ_WLAN#

<39> CLKREQ_WLAN#

BJ38
BG38
AU36
AV36

J2

CLK_WLAN#
CLK_WLAN

<39> CLK_WLAN#
<39> CLK_WLAN

PERN5
PERP5
PETN5
PETP5

Y40
Y39

CLKREQ_LAN#

<40> CLKREQ_LAN#

BG37
BH37
AY36
BB36

E12

SMBCLK

2 R232

PCIE_PRX_JETTX_N3
PCIE_PRX_JETTX_P3
PCIE_PTX_C_JETRX_N3
PCIE_PTX_C_JETRX_P3

BE34
BF34
BB32
AY32

SMBALERT# / GPIO11

EC_LID_OUT#

Link

JET

<39>
<39>
<39>
<39>

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_WLANRX_N2
PCIE_PTX_WLANRX_P2

SMBUS

C501 2
C502 2

PERN1
PERP1
PETN1
PETP1

Controller

WLAN

PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_C_WLANRX_N2
PCIE_PTX_C_WLANRX_P2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

BG34
BJ34
AV32
AU32

FLEX CLOCKS

<39>
<39>
<39>
<39>

C498 2
C497 2

+3VALW_PCH

PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_LANRX_N1
PCIE_PTX_LANRX_P1

CLOCKS

LAN

PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_C_LANRX_N1
PCIE_PTX_C_LANRX_P1

PCI-E*

<40>
<40>
<40>
<40>

C314
10P_0402_50V8J

27P_0402_50V8J

PCH_X2

25MHZ_20PF_7A25000012

C507
27P_0402_50V8J

EDP@
R566 1

2 10K_0402_5%

PANEL_SEL

R564 1

2 10K_0402_5%

LVDS_SEL

Channel

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

2012/12/31

Deciphered Date

Title

SCHEMATIC, MB A7211

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019BD

Date:

Monday, February 28, 2011

Sheet
1

29

of

59

2
R316
2
R218
2
R220
2
R221

1
200_0402_5%
1
10K_0402_5%
1
10K_0402_5%
1
10K_0402_5%

DRAMPWROK
PCH_SUSPWRDN_R
RI#
PCH_LOW_BAT#

PCH_RSMRST#
1
10K_0402_5%
PM_PWROK
1
10K_0402_5%
SYS_PWROK
1
10K_0402_5%

2
R127
2
R128
2
R129

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

BC24
BE20
BG18
BG20

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

<6>
<6>
<6>
<6>

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

BE24
BC20
BJ18
BJ20

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

<6>
<6>
<6>
<6>

DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3

DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3

AW24
AW20
BB18
AV18

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

<6>
<6>
<6>
<6>

DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3

DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3

AY24
AY20
AY18
AU18

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

1
R130

+1.05VS_PCH

1
R160

DMI_COMP
2
49.9_0402_1%
RBIAS_CPY
2
750_0402_1%

BJ24

FDI

+3VALW_PCH
D

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI

U2C
<6>
<6>
<6>
<6>

DMI_ZCOMP

SYS_PWROK

4
PM_PWROK
1
R216

<5> DRAMPWROK
SUSACK#

@
2
R137

1 PCH_SUSPWRDN_R
0_0402_5%

<44> PCH_RSMRST#

Stuff R137 if EC does not want to


involve in the handshake mechanism
for the DeepSX state entry and exit

1
R320

<44> PCH_SUSPWRDN
<44> PBTN_OUT#
+3VALW_PCH

1
R469

2
330K_0402_5%
D12
1

<13,44,46,50> ACIN

PM_PWROK_R
2
0_0402_5%

AW16

FDI_INT

FDI_FSYNC0

AV12

FDI_FSYNC0
FDI_FSYNC1

AV14

FDI_LSYNC0

FDI_LSYNC1

BB10

FDI_LSYNC1

DSWVRMEN

A18

DSWVREN

DPWROK

E22

PCH_DPWROK

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

DRAMPWROK

B13

DRAMPWROK

PCH_RSMRST#

C21

2 PCH_SUSPWRDN_R K16
0_0402_5%

WAKE#

B9

EC_SWI#

CLKRUN# / GPIO32

N3

PCH_GPIO32

G8

SUS_STAT#

SUS_STAT# / GPIO61

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>

FDI_FSYNC0

PCH_DPWROK
<6>

FDI_FSYNC1

<6>

FDI_LSYNC0

<6>

FDI_LSYNC1

<6>

PCH_RSMRST#
2
0_0402_5%

1
R222

Stuff R222 if do not support DeepSX state

+RTCVCC

DSWVREN

R224

R225

1 330K_0402_5%
@

1 330K_0402_5%

EC_SWI# <40,42>

DSWVREN must be always pulled high to +RTCVCC


T17

PAD

32.768 KHz
SUSCLK / GPIO62

N14

SLP_S5# / GPIO63

D10

PM_SLP_S5#

SLP_S4#

H4

PM_SLP_S4#

SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3#

F4

PM_SLP_S3#

SLP_A#

G10

PM_SLP_A#

T35

PAD

T58

PAD

RSMRST#

FDI_INT <6>

FDI_LSYNC0

DSWVREN - Internal Deep Sleep 1.05V regulator


HEnable
LDisable

CLK_EC <44>
PM_SLP_S5# <44>
+3VS
PM_SLP_S4# <44>
PCH_GPIO32

PBTN_OUT#

E20

PWRBTN#

PCH_ACIN

H20

ACPRESENT / GPIO31

SLP_SUS#

G16

PM_SLP_SUS#

PCH_LOW_BAT#

E10

BATLOW# / GPIO72

PMSYNCH

AP14

H_PM_SYNC

RI#

A10

RI#

K14

PCH_GPIO29

R313 1

2 8.2K_0402_5%

PM_SLP_S3# <44>

+3VALW_PCH
B

CH751H-40PT_SOD323-2

FDI_INT

FDI_FSYNC1

IN2

SN74AHC1G08DCKR_SC70-5

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

DMI2RBIAS

System Power Management

PM_PWROK

SUSACK#
XDP_DBRESET#

<5> XDP_DBRESET#

U12

IN1

<5,44> PM_PWROK

T34

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

DMI_IRCOMP

<44,55> VGATE

PAD

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

BH21

0.1U_0402_16V4Z
1
2
C250

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

BC10

@R259
R259 2
1 @
+3VS

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG25

Reserve 0 ohm for cost down plan


2010/08/25
0_0402_5%
C

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

SLP_LAN# / GPIO29

COUGARPOINT_FCBGA989~D

H_PM_SYNC <5>

EC_SWI#

R319 1

2 10K_0402_5%

PCH_GPIO29

R563 1 @

2 10K_0402_5%

Q65R3@

D16
PM_PWROK

PCH_RSMRST#

CH751H-40PT_SOD323-2
D14
<49,51>

POK

CH751H-40PT_SOD323-2
A

2011/01/31

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, MB A7211
Rev
B

4019BD

Date:

Sheet

Monday, February 28, 2011


1

30

of

59

U2D

OPT@
UMA_ENBKL
1
2
R230
100K_0402_5%

2
R471

LCTL_CLK
1
2.2K_0402_5%

2
R472

LCTL_DATA
1
2.2K_0402_5%

2
R223

LCD_EDID_CLK
1
2.2K_0402_5%

2
R229

LCD_EDID_DATA
1
2.2K_0402_5%

2
R237

UMA_CRT_CLK
1
2.2K_0402_5%

2
R231

UMA_CRT_DATA
1
2.2K_0402_5%

OPT@
UMA_CRT_B
1
2
R240
150_0402_1%
OPT@
UMA_CRT_G
1
2
R241
150_0402_1%
OPT@
UMA_CRT_R
1
2
R318
150_0402_1%

L_DDC_CLK
L_DDC_DATA

LCTL_CLK
LCTL_DATA

T45
P39

L_CTRL_CLK
L_CTRL_DATA

<25> LCD_TXOUT0<25> LCD_TXOUT1<25> LCD_TXOUT2<25> LCD_TXOUT0+


<25> LCD_TXOUT1+
<25> LCD_TXOUT2+

<25> LCD_TZCLK<25> LCD_TZCLK+


<25> LCD_TZOUT0<25> LCD_TZOUT1<25> LCD_TZOUT2<25> LCD_TZOUT0+
<25> LCD_TZOUT1+
<25> LCD_TZOUT2+

<26> UMA_CRT_B
<26> UMA_CRT_G
<26> UMA_CRT_R
<26> UMA_CRT_CLK
<26> UMA_CRT_DATA

<26> UMA_CRT_HSYNC
<26> UMA_CRT_VSYNC

AF37
AF36

LVD_VREFH
LVD_VREFL

LCD_TXCLKLCD_TXCLK+

AK39
AK40

LVDSA_CLK#
LVDSA_CLK

LCD_TXOUT0LCD_TXOUT1LCD_TXOUT2-

AN48
AM47
AK47
AJ48

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LCD_TXOUT0+
LCD_TXOUT1+
LCD_TXOUT2+

AN47
AM49
AK49
AJ47

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LCD_TZCLKLCD_TZCLK+

AF40
AF39

LVDSB_CLK#
LVDSB_CLK

LCD_TZOUT0LCD_TZOUT1LCD_TZOUT2-

AH45
AH47
AF49
AF45

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LCD_TZOUT0+
LCD_TZOUT1+
LCD_TZOUT2+

AH43
AH49
AF47
AF43

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

UMA_CRT_B
UMA_CRT_G
UMA_CRT_R

N48
P49
T49

CRT_BLUE
CRT_GREEN
CRT_RED

UMA_CRT_CLK
UMA_CRT_DATA

T39
M40

CRT_DDC_CLK
CRT_DDC_DATA

UMA_CRT_HSYNC
UMA_CRT_VSYNC

M47
M49

CRT_HSYNC
CRT_VSYNC

CRT_IREF
1
1K_0402_0.5%

T43
T42

DAC_IREF
CRT_IRTN

SDVO_INTN
SDVO_INTP

AP39
AP40

SDVO_CTRLCLK
SDVO_CTRLDATA

R214
2.2K_0402_5%
IHDMI@

P38
M39

UMA_HDMI_CLK <27>
UMA_HDMI_DATA <27>
R1432
IHDMI@
0_0402_5%
2
1

AT49
AT47
AT40

HDMI_HPD_UMA

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

UMA_HDMI_TX2UMA_HDMI_TX2+
UMA_HDMI_TX1UMA_HDMI_TX1+
UMA_HDMI_TX0UMA_HDMI_TX0+
UMA_HDMI_TXCUMA_HDMI_TXC+

HDMI_HPD

UMA_HDMI_TX2- <27>
UMA_HDMI_TX2+ <27>
UMA_HDMI_TX1- <27>
UMA_HDMI_TX1+ <27>
UMA_HDMI_TX0- <27>
UMA_HDMI_TX0+ <27>
UMA_HDMI_TXC- <27>
UMA_HDMI_TXC+ <27>

HDMI_HPD <13,27,33>

HDMI_HPD_UMA 2
1
100K_0402_5%
R1433

HDMI

P46
P42

DDPC_AUXN
DDPC_AUXP
DDPC_HPD

AP47
AP49
AT38

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

DDPD_CTRLCLK
DDPD_CTRLDATA

COUGARPOINT_FCBGA989~D

R215
2.2K_0402_5%
IHDMI@

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

DDPC_CTRLCLK
DDPC_CTRLDATA

OPT@

2
R311

SDVO_STALLN
SDVO_STALLP

+3VS

LVD_IBG
LVD_VBG

AE48
AE47

AP43
AP45
AM42
AM40

T40
K47

SDVO_TVCLKINN
SDVO_TVCLKINP

L_BKLTCTL

LCD_EDID_CLK
LCD_EDID_DATA

L_BKLTEN
L_VDD_EN

P45

OPT@
LVDS_IBG
1
2
R219
2.37K_0402_1%
T40 PAD

<25> LCD_TXCLK<25> LCD_TXCLK+


+3VS

PCH_PWM

Digital Display Interface

J47
M45

LVDS

<25> PCH_PWM
<25> LCD_EDID_CLK
<25> LCD_EDID_DATA

UMA_ENBKL
UMA_ENVDD

CRT

<25> UMA_ENBKL
<25> UMA_ENVDD

R473 2

1 100K_0402_5%
C

M43
M36

DDPD_AUXN
DDPD_AUXP
DDPD_HPD

AT45
AT43
BH41

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

R524 2

1 100K_0402_5%

Q65R3@

R311
1K_0402_5%
DIS@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

SCHEMATIC, MB A7211

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019BD

Date:

Monday, February 28, 2011

Sheet
1

31

of

59

PLT_RST#

RP1
PCH_GPIO4
PCI_PIRQC#
PCI_PIRQA#
PCH_GPIO2

8.2K_0804_8P4R_5%
RP2

1
2
3
4

PCI_PIRQB#
ODD_DA#
WL_OFF#

8.2K_0804_8P4R_5%
1
R321
1
R322
1 DIS@
R578
1
R544

PCH_GPIO5
2
8.2K_0402_5%
PCI_PIRQD#
2
8.2K_0402_5%
DGPU_RST#
2
10K_0402_5%
DGPU_PWR_EN
2
10K_0402_5%
DGPU_PWR_EN
2
1K_0402_5%

1 @
R399

For Optimus

<37>

ODD_DA#

TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40

ODD_DA#

1
R562

IN1

IN2

PLTRST_VGA# <13>
1

@
2
1
R531
0_0402_5%
DGPU_RST#

R530
100K_0402_5%
OPT@
1

R532
1K_0402_5%
OPT@

SN74AHC1G08DCKR_SC70-5
OPT@

<13,33,47,56> VGA_PWROK

DIS@
PLT_RST#

PLTRST_VGA#
1
0_0402_5%

2
R529

DF_TVS NV_CLE
NV_RCOMP

NV_CLE

R534
100K_0402_5%

AV10

NV_RB#

AT8

NV_RE#_WRB0
NV_RE#_WRB1

AY5
BA2

<13,47,56> DGPU_PWR_EN

2 ODD_DA#_R
0_0402_5%
1

<39>

RF_OFF#

<39>

WL_OFF#

C360
0.1U_0402_16V4Z

T32 PAD
<5,39,40,41,42,44,45> PLT_RST#
<44> CLK_PCI_EC
<29> CLK_PCILOOP
<45> CLK_PCI_DDR

22_0402_5% 1
22_0402_5% 1
22_0402_5% 1

NV_WE#_CK0
NV_WE#_CK1

K40
K38
H38
G38

DGPU_RST#
PCH_GPIO52
DGPU_PWR_EN

C46
C44
E40

REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

RF_OFF#
PCH_GPIO53
WL_OFF#

D47
E42
F46

GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

PCH_GPIO2
ODD_DA#_R
PCH_GPIO4
PCH_GPIO5

G42
G40
C42
D44

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

PCI_PME#

K10

PLT_RST#

C6

2 R525
2 R526
2 R527

CLK_EC_R
CLK_PCH
CLK_SIO

H49
H43
J48
K42
H40

PIRQA#
PIRQB#
PIRQC#
PIRQD#

For Optimus
C

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

USB port6 and port7 are disabled on HM65

USBRBIAS#

C33

USBBIAS

USBRBIAS

B33

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

A14
K20
B17
C16
L16
A16
D14
C14

EHCI 1

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

AT12
BF3

EHCI 2

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

<37>
<37>
<37>
<37>
<37>
<37>

USB-RIGHT1
USB-RIGHT2
USB-Left1
DMI & FDI Termination Voltage

USB20_N5
USB20_P5

USB20_N5 <38>
USB20_P5 <38>

USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N12
USB20_P12

USB20_N8 <38>
USB20_P8 <38>
USB20_N9 <39>
USB20_P9 <39>
USB20_N10 <39>
USB20_P10 <39>
USB20_N11 <25>
USB20_P11 <25>
USB20_N12 <39>
USB20_P12 <39>

1
R535

IR Emitter

NV_CLE

Set to VCC when HIGH


Set to VSS when LOW
+1.8VS

Finger Printer
WiMax

RP3

BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30

NV_ALE

AV5
AY1

RF_OFF#

8.2K_0804_8P4R_5%

8
7
6
5

TP21
TP22
TP23
TP24

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

OPT@
1
2
C508
0.1U_0402_16V4Z
U20
OPT@
1
O 4 R5282
0_0402_5%

PCH_GPIO52
PCH_GPIO53

1
2
3
4

USB

8
7
6
5

B21
M20
AY16
BG46

NV_DQS0
NV_DQS1

AT10
BC8

+3VS
R533
0_0402_5%
OPT@

R324
2.2K_0402_5%

TV Tuner #1
Int. Camera
2

1
2
3
4

AY7
AV7
AU3
BG4

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

PCI

8
7
6
5

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

+3VS

NVRAM

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

RSVD

BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45

U2E

3G/ TV tuner #2

NV_CLE

2
R323

1
1K_0402_5%

H_SNB_IVB# <5>

2
22.6_0402_1%

Within 500 mils

PME#
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
COUGARPOINT_FCBGA989~D

USB_OC#0
USB_OC#1
USB_OC#2
SLP_CHG_M3
SLP_CHG_M4
USB_OC#5
USB_OC#6
USB_OC#7

USB_OC#0 <37,44> USB-Right


USB_OC#1 <39,42,44>USB-Left

+3VALW_PCH

SLP_CHG_M3 <39>
SLP_CHG_M4 <39>

RP4
USB_OC#0
SLP_CHG_M3
SLP_CHG_M4
USB_OC#6

Q65R3@

4
3
2
1

5
6
7
8

10K_0804_8P4R_5%
RP5
USB_OC#1
USB_OC#2
USB_OC#5
USB_OC#7

Boot BIOS Strap


@
0.1U_0402_16V4Z

1 C516

RF_OFF#

PLT_RST#

1K_0402_5% 2

1 R537

RF_OFF#

1K_0402_5% 2

1 R538

PCH_GPIO19

1K_0402_5% 2

1 R536

WL_OFF#

PCH_GPIO19 <28>

PCH_GPIO19

0
0
1
1

0
1
0
1

Boot BIOS Loaction

5
6
7
8

10K_0804_8P4R_5%

LPC
Reserved
PCI
SPI

A16 Swap Override Strap


WL_OFF#

4
3
2
1

Low= A16 swap override Enable


High= A16 swap override Disable

2011/01/31

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, MB A7211
Rev
B

4019BD

Date:

Monday, February 28, 2011

Sheet
1

32

of

59

@
1 R100
2
100K_0402_5%

+3VALW_PCH

+3VS
U2F
ODD_EN#

<13,27,31> HDMI_HPD

3D_DET#

2
10K_0402_5%
HDMI_HPD
2
10K_0402_5%
PCH_GPIO1
2
10K_0402_5%
BT_DET#
2
10K_0402_5%

PCH_WL_BT_LED

2 1K_0402_5% PCH_GPIO28

H36

TACH2 / GPIO6

TACH6 / GPIO70

C41

LOGO_LED

E38

TACH3 / GPIO7

TACH7 / GPIO71

A40

MAXIC_SELECT

<44>

EC_SMI#

EC_SMI#

C10

GPIO8

PCH_GPIO12

C4

LAN_PHY_PWR_CTRL / GPIO12

USB30_SMI#

G2

GPIO15

U2

For Optimus
<13,32,47,56> VGA_PWROK

VGA_PWROK
BT_DET#

<39>

BT_ON#
T74 PAD

<37> ODD_DETECT#

<39> ISDBT_DET

SKU

OPT

SATA4GP / GPIO16
TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

PCH_GPIO27

E16

GPIO27

PCH_GPIO28

P8

GPIO28

BT_ON#

K1

STP_PCI# / GPIO34

PCH_GPIO35
ODD_DETECT#

K4
V8

THRMTRIP#

AY10

PCH_THRMTRIP# 1
R416

INIT3_3V#

T14

NC_1

AH8

NC_2

AK11

NC_3

AH10

NC_4

AK10

NC_5

P37

GPIO35
SATA2GP / GPIO36

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

VSS_NCTF_15

BG2

SATA5GP / GPIO49

VSS_NCTF_16

BG48

VSS_NCTF_17

BH3

VSS_NCTF_18

BH47

3D_DET#

D6

SKU

Discrete

Optimus

Q53B

H_PWRGOOD <5>

2
390_0402_5%

PCH_WL_BT_LED

H_THERMTRIP# <5>

2N7002DW-T/R7_SOT363-6

MAXIC_SELECT

1
R124

2
10K_0402_5%

MAXIC_SELECT

GPIO57

MAXIC_SELECT
IC TYPE

A4

VSS_NCTF_1

VSS_NCTF_19

BJ4

A44

VSS_NCTF_2

VSS_NCTF_20

BJ44

A45

VSS_NCTF_3

VSS_NCTF_21

BJ45

A46

VSS_NCTF_4

VSS_NCTF_22

BJ46

A5

VSS_NCTF_5

VSS_NCTF_23

BJ5

A6

VSS_NCTF_6

VSS_NCTF_24

BJ6

B3

VSS_NCTF_7

VSS_NCTF_25

C2

B47

VSS_NCTF_8

VSS_NCTF_26

C48

BD1

VSS_NCTF_9

VSS_NCTF_27

D1

BD49

VSS_NCTF_10

VSS_NCTF_28

D49

BE1

VSS_NCTF_11

VSS_NCTF_29

E1

BE49

VSS_NCTF_12

VSS_NCTF_30

E49

BF1

VSS_NCTF_13

VSS_NCTF_31

F1

BF49

VSS_NCTF_14

VSS_NCTF_32

F49

3D

KB_RST# <44>

This signal has weak internal


pull-up, can't be pulled low

M3

OPTIMUS_EN#

EC_SMI#

H_PWRGOOD

SLOAD / GPIO38

OPTIMUS_EN#

2 1K_0402_5%

AY11

CIR_EN#

V3

<46> WL_BT_LED#

PROCPWRGD

RCIN#

GATEA20 <44>

KB_RST#

SATA3GP / GPIO37

PCH_GPIO49

GATEA20

P5

N2

ISDBT_DET

LOGO_LED <46>

AU16

M5

Integrated Clock Chip Enable (Removed)


H: Disable
L: Enable
@

P4

OPTIMUS_EN#

GPIO8

R326 1

PECI

PCH_GPIO37

3D_DET#
3D_DET#

D40

A20GATE

COUGARPOINT_FCBGA989~D

ODD_EN# <47>

EC_SCI#

PCH_GPIO16

ODD_DETECT#
200K_0402_5%
PCH_GPIO6
2
10K_0402_5%
PCH_GPIO16
2
10K_0402_5%
EC_SCI#
2
10K_0402_5%
CIR_EN#
2
100K_0402_5%
ISDBT_DET
2
10K_0402_5%
PCH_GPIO49
2
10K_0402_5%
OPTIMUS_EN#
2
10K_0402_5%

On-Die PLL Voltage Regulator


H: Enable
L: Disable
R325

B41

PCH_GPIO6

GPIO28

ODD_EN#

TACH5 / GPIO69

EC_SCI#

3D_DET#
1 3D@
2
R554
10K_0402_5%
@
USB30_SMI#
2
1
R437
10K_0402_5%
PCH_GPIO37
2
1
R547
100K_0402_5%
PCH_GPIO27
2
1
R402
10K_0402_5%
CIR_EN#
2 CIR@ 1
R405
10K_0402_5%
ISDBT_DET
1
2
R328
47K_0402_5%
OPTIMUS_EN#
2 OPT@ 1
R415
10K_0402_5%

C40

TACH1 / GPIO1

T7

<44>

BT_ON#

1
R545
1
R546
1
R577
1
R550
1
R551
@
1
R552
1
R553
1 DIS@
R555

TACH4 / GPIO68

A42

2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

PCH_GPIO28

<42> USB30_SMI#

BMBUSY# / GPIO0

PCH_GPIO1
PCH_GPIO12

+3VS

1
R567
1
R539
1
R540
1
R542

HDMI_HPD

EC_SMI#

CPU/MISC

USB30_SMI#

GPIO

1
1K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

NCTF

2
R390
1
R558
1
R556
1
R557
1 OPT@
R549

1
R106
GATEA20
1
R548
KB_RST#
1
R559
LOGO_LED
1
R436
PCH_WL_BT_LED
1
R110

MAX14550E

MAX14566B

Q65R3@

Integrated clock enable functionality


is achieved by soft-strap
The current default is clock enable

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
1

33

of

59

+1.05VS_VCCP

U2G

10U_0603_6.3V6M

1U_0402_6.3V6K

2
1U_0402_6.3V6K

+1.05VS_PCH

AN19

This pin can be left as NC if


On-Die VR is enabled (Default)

PAD

T30

+1.05VS_PCH

AN16

VCCIO[15]

1U_0402_6.3V6K
C277
10U_0603_6.3V6M

C273

C279

C510

1U_0402_6.3V6K

C511

1U_0402_6.3V6K
2

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19] 2925mA

VCCIO[21]
VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29
1

AK36

VSSALVDS

AK37

VCCTX_LVDS[1]

AM37

VCCTX_LVDS[2]

AM38

VCCTX_LVDS[3]

AP36

This pin can be left as NC if


On-Die VR is enabled (Default)

PAD

T36

AP16
BG6

+1.05VS_PCH

AP17

+VCCP_VCCDMI

AU20

+1.8VS
+VCCTX_LVDS

VCC3_3[6]

1
C514
AP37 0.01U_0402_25V7K
OPT@

C513
OPT@

C256
22U_0805_6.3V6M
OPT@
C513
0_0402_5%
DIS@

V33
1

VCC3_3[7]

V34

C272
0.1U_0402_10V7K

VCCVRM[3]

+1.5VS

AT16

R474
0_0402_5%
1
2

+VCCAFDI_VRM

VCCDMI[1]

AT20

+VCCP_VCCDMI

VCCIO[1]

AB36

+1.05VS_VCC_DMI
1

0.001

0.001

20mA

0.001

VCC3_3

3.3

0.266

VCCADAC

3.3

0.001

R477
2
1
0_0805_5%

C276
1U_0402_6.3V6K

C270
1U_0402_6.3V6K

1.05

0.08

1.05

0.08

VCCCORE

1.05

1.3

VCCDMI

1.05

0.042

VCCIO

1.05

2.925

VCCASW

1.05

1.01

VCCSPI

3.3

0.02

VCCDSW

3.3

0.002

VCCDFTERM

1.8

0.19

VCCRTC

3.3

6 uA

3.3

0.97

VCCSUS3_3

+1.8VS

AG16

VCCADPLLA
VCCADPLLB

+1.05VS_VCCP
R480
0_0402_5%
1
2
+1.05VS_PCH

VCCPNAND[1]

VCCFDIPLL

VCCDMI[2]

L1 OPT@
1
2
0.1UH_MLF1608DR10KT_10%_1608

0.01U_0402_25V7K

VCCDFTERM

VCCVRM[2]

1.05

2 0_0402_5%

+VCCP_VCCDMI

VCC3_3[3]

S0 Iccmax
Current (A)

0_0402_5%

V5REF_SUS
R424 1 DIS@

VCCIO[27]

+VCCAFDI_VRM

C290
0.1U_0402_10V7K
+VCCAFDI_VRM

1 OPT@
R541

+VCCA_LVDS

VCCALVDS

VCCIO[20]

AP24

Voltage

V_PROC_IO

+3VS

AN21

Voltage Rail

V5REF

1mA

60mA

VCCIO[16]

AP23

PCH Power Rail Table

+3VS

1U_0402_6.3V6K

+3VS

C512
0.01U_0402_25V7K

U47

L12
2+VCCA_DAC_R2
1
1_0603_1%
BLM18PG181SN1D_0603
1
C286
10U_0603_6.3V6M

0.1U_0402_10V7K
1
C288

+VCCA_DAC

U48

VCCTX_LVDS[4]

VCCAPLLEXP

AP21

VSSADAC

VCCIO[28]

BJ22

AN17

VCCADAC

CRT

C289

1mA

LVDS

C275

+3VS
R481

HVCMOS

C269

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]

POWER

DMI

JUMP_43X118
1
C274

1300mA
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31

NAND / SPI

+1.05VS_PCH

1U_0402_6.3V6K

VCC CORE

FDI

PJ31
2

VCCIO

VCCSusHDA
VCCPNAND[2]

1
AJ16
2

VCCPNAND[4]

VCCSPI

1.5

0.16

VCCCLKDMI

1.05

0.02

VCCSSC

1.05

0.095

AJ17

VCCDIFFCLKN

1.05

0.055

VCCALVDS

3.3

0.001

VCCTX_LVDS

1.8

0.06

V1
1

COUGARPOINT_FCBGA989~D

VCCVRM
C278
0.1U_0402_10V7K

+3VS

20mA

0.01

AG17

190mA
VCCPNAND[3]

3.3 / 1.5

Q65R3@

C281
1U_0402_6.3V6K

+3VALW

PJ32
JUMP_43X79
@

Vgs=-4.5V,Id=3A,Rds<97mohm

+3VALW_PCH

C687
4.7U_0805_10V4Z

C688
1U_0402_6.3V6K

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, MB A7211
Rev
B

4019BD

Date:

Monday, February 28, 2011

Sheet
1

34

of

59

+3VS

C301
10U_0603_6.3V6M

C310
1U_0402_6.3V6K

This pin can be left as NC if


On-Die VR is enabled (Default)

+3VALW_PCH

+5VALW

POWER

U2J

+PCH_VCCDSW

V12

+3VS_VCC_CLKF33

T38

N26

VCCIO[30]

P26

VCCIO[31]

P28

VCCIO[32]

T27

VCCIO[33]

T29

VCCSUS3_3[7]

T23

119mA VCCSUS3_3[8]

T24

3mA

VCCDSW3_3
DCPSUSBYP

0.1U_0402_10V7K

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

+1.05VS_PCH

AL24

C300
1U_0402_6.3V6K
@

AA19
AA21

C311

C312

22U_0805_6.3V6M
2
2
22U_0805_6.3V6M
C

C323
1U_0402_6.3V6K

1U_0402_6.3V6K
1
1
C294
C308

1U_0402_6.3V6K
2

+1.05VS_PCH

C333
10U_0603_6.3V6M

C295

C515

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

VCCASW[13]
VCCASW[14]

+1.05VS_PCH
R522

+VCCDIFFCLK

0_0603_5%

+VCCRTCEXT
C337
1U_0402_6.3V6K

C334
0.1U_0402_10V7K

VCCASW[12]

W21

1U_0402_6.3V6K
2
2
2
10U_0603_6.3V6M

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

1
+VCCAFDI_VRM

Y49

+3VALW_PCH
C321
0.1U_0402_10V7K

VCCSUS3_3[10]

V24

VCCSUS3_3[6]

P24

VCCIO[34]

T26

V5REF_SUS

M26

+PCH_V5REF_SUS

DCPSUS[4]

AN23

+VCCA_USBSUS

VCCSUS3_3[1]

AN24

1mA

VCCASW[11]

AD31

C298
1U_0402_6.3V6K

+5VALW_PCH

C332
0.1U_0402_10V7K

D8
CH751H-40PT_SOD323-2

P34
N20

VCCSUS3_3[3]

N22

VCCSUS3_3[4]

P20

VCCSUS3_3[5]

P22

C335 1
+3VALW_PCH

+5VS

+3VS
C

+PCH_V5REF_RUN

+3VALW_PCH
R490
100_0402_5%

D7
CH751H-40PT_SOD323-2

C293
1U_0402_6.3V6K

2
+3VS

W16

VCC3_3[4]

T34

C304
1U_0603_10V6K

+3VS

+1.05VS_SATA3

1
AF13

VCCIO[12]

AH13

VCCIO[13]

AH14

VCCIO[6]

AF14

C313
0.1U_0402_10V7K

AJ2

VCCIO[5]

+3VS

1
2
C306
0.1U_0402_10V7K

VCCVRM[4]

+PCH_V5REF_RUN

AA16

VCC3_3[8]

DCPRTC

C326
0.1U_0603_25V7K

2 1U_0402_6.3V6K

VCC3_3[2]

+PCH_V5REF_SUS

+1.05VS_PCH

VCCSUS3_3[2]

VCC3_3[1]

0.1U_0402_10V7K

+3VALW_PCH

R512
100_0402_5%

1mA V5REF

C291

+3VALW_PCH

VCCSUS3_3[9]

1010mA

VCCASW[4]

+1.05VS_VCCADPLLB

VCCASW[2]
VCCASW[3]

AD29

+1.05VS_VCCADPLLA

V23

VCCASW[1]

AA26

AC31
L21
1
2
BLM18PG181SN1D_0603
L19
1
2
BLM18PG181SN1D_0603

DCPSUS[3]

AA24

+VCCSUS

USB

T42

PCI/GPIO/LPC

PAD

+1.05VS_PCH

C328
1U_0402_6.3V6K

VCC3_3[5]

Clock and Miscellaneous

This pin can be left as NC if


On-Die VR is enabled (Default)

T16

VCCIO[29]

VCCACLK

AD49

T41

C324
0.1U_0402_10V7K

2
@
C305
2
1

"@" Avoid leakage

1
D

+5VALW_PCH

JUMP_43X39
@ PJ334

+1.05VS_PCH

PAD

+3VS_VCC_CLKF33
1

L18
1
2
10UH_LB2012T100MR_20%

+1.05VS_PCH
R516

C297
0.1U_0402_10V7K

2
1

+1.05VS_SATA3

0_0805_5%
C329
1U_0402_6.3V6K

2
+1.05VS_VCCADPLLA

BD47

+1.05VS_VCCDIFFCLKN

1
1

0_0603_5%

+1.05VS_VCCADPLLB

C320
1U_0402_6.3V6K

BF47

+VCCDIFFCLK

2
+1.05VS_VCCDIFFCLKN

+1.05VS_PCH

C318
1U_0402_6.3V6K

VCCADPLLB

80mA
80mA

AF17
AF33
AF34
AG34

VCCIO[7]
VCCIO[8]
VCCIO[9] 55mA
VCCIO[11]

AG33

VCCIO[10]

VCCADPLLA

+VCCSST

V16

0.1U_0402_10V7K
+1.05VM_VCCSUS
C299

T17
V19

DCPSUS[1]
DCPSUS[2]

+V_CPU_IO

BJ8

V_PROC_IO

+1.05VM_VCCSUS

1
1

C316
1U_0402_6.3V6K

0_0603_5%
C325
4.7U_0603_6.3V6K

C322

C303

+VCCAFDI_VRM

AF11

+VCCAFDI_VRM

VCCIO[2]

AC16

+1.05VS_VCC_SATA

VCCIO[3]

AC17

VCCIO[4]

AD17

+1.05VS_VCC_SATA

+1.05VS_PCH
R491
2
1
0_0805_5%

C331
1U_0402_6.3V6K
+1.05VS_PCH

1mA

CPU

0_0603_5%

0.1U_0402_10V7K

T43

VCCVRM[1]

VCCASW[22]

T21

+VCCME_22

R509 2

1 0_0402_5%

VCCASW[23]

V21

+VCCME_23

R517 2

1 0_0402_5%

VCCASW[21]

T19

+VCCME_21

R520 2

1 0_0402_5%

+RTCVCC
+3VALW_PCH
0.1U_0402_10V7K

0.1U_0402_10V7K
2

C327

1U_0402_6.3V6K

C330

A22
C336

VCCRTC

RTC

R521
2

AK1

This pin can be left as NC if


On-Die VR is enabled (Default)
PAD

DCPSST

R511

VCCAPLLSATA

95mA

+1.05VS_VCCP
+1.05VS_PCH

SATA

+1.05VS_VCCDIFFCLKN
R485

MISC

+1.05VS_PCH

HDA

10mA

VCCSUSHDA

COUGARPOINT_FCBGA989~D

P32
1

Q65R3@

0.1U_0402_10V7K

C307
0.1U_0402_16V4Z

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

2012/12/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, MB A7211
Rev
B

4019BD

Date:

Sheet

Monday, February 28, 2011


1

35

of

59

U2I
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3

U2H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
COUGARPOINT_FCBGA989~D

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

Q65R3@

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

COUGARPOINT_FCBGA989~D

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

Q65R3@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SCHEMATIC, MB A7211
Rev
B

4019BD

Date:

Monday, February 28, 2011

Sheet
1

36

of

59

SATA HDD
Conn.
+5VS

SATA ODD Conn


Place closely JHDD SATA CONN.

C356
10U_0805_10V4Z

C357
0.1U_0402_16V4Z

C358
0.1U_0402_16V4Z

C359
0.1U_0402_16V4Z

JODD

@
1
2
3
4
5
6
7
8
9
10
11
12
GND
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14

SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2

C376 1
C377 1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

SATA_PTX_DRX_P2 <28>
SATA_PTX_DRX_N2 <28>

SATA_PRX_DTX_N2
SATA_PRX_DTX_P2

C378 1
C375 1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

SATA_PRX_C_DTX_N2 <28>
SATA_PRX_C_DTX_P2 <28>

ODD_DETECT#_R1
+5VS_ODD R561

2
0_0402_5%

ODD_DA#

SW5
SMT1-05-A_4P
3

ODD_DETECT# <33>
6
5

1.2A
1

ODD_DA# <32>

ACES_88058-120N

Close to JHDD

JHDD1

1
2
3
4
5
6
7

GND
A+
AGND
BB+
GND

24
23

GND
GND

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

C369 1
C367 1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

SATA_PTX_DRX_P0 <28>
SATA_PTX_DRX_N0 <28>

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

C368 1
C370 1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

SATA_PRX_C_DTX_N0 <28>
SATA_PRX_C_DTX_P0 <28>

R73
1

USB Board@ Right Side


<32>

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

+3VS

+USB_VCCA

USB_EN#

8
7
6
5

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

2
C361

USB20_P0

1
L53
1
R87

1
1000P_0402_50V7K

R77
1

USB_OC#0 <32,44>
1

RT9715BGS_SO8

C362
4.7U_0805_10V4Z
2 @

<32>

USB20_N1

ACES_85201-2005N

USB20_N0_R

<32>

USB20_P1

USB20_P0_R

USB20_N0_R
USB20_P0_R

0_0402_5%
2
2

USB20_N1_R

USB20_P1_R

C372
0.1U_0402_16V4Z

C373
0.1U_0402_16V4Z

D85

1
R568

+5VALW

USB20_P1_R

+USB_VCCB

AO3413_SOT23

C374
0.1U_0402_16V4Z

<44>

2
100K_0402_5%

2
3

2
1

AZC199-02SPR7G_SOT23-3

USB_EN#

USB_EN#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
JPIO

2
G

C363
10U_0805_10V4Z

HP_R
HP_L

<43>
MIC1_L
<43>
MIC1_R
<43> NBA_PLUG
<43> BACK_SENSE

USB20_N1_R
S

+USB_VCCC
1

D86
USB20_P0_R

Close to JHDD2

+USB_VCCC

USB20_N0_R

JHDD2

2
3

2
1

AZC199-02SPR7G_SOT23-3
@
SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1

C364 1
C365 1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1

C366 1
C371 1

2 0.01U_0402_25V7K
2 0.01U_0402_25V7K

W=60mils

SATA_PTX_DRX_P1 <28>
SATA_PTX_DRX_N1 <28>

C426 1

D87
NBA_PLUG

SATA_PRX_C_DTX_N1 <28>
SATA_PRX_C_DTX_P1 <28>
@

2
R190

+5VS

1
0_0402_5%

C428 1

2 1000P_0402_50V7K

C389 1

2 0.1U_0402_16V4Z

L15

ACES_85203-1202L

2 220U_6.3V_M_R15
+

2
4
6
8
10
12
14
16
18
20
22
24

<43>
<43>

2
0_0402_5%

Q8

Place closely JHDD2 SATA CONN.

+5V_IO
USB20_N1_R
USB20_P1_R

2
0_0402_5%

USB Board@ Left Side


+5VS

1.2A

2
4
6
8
10
12
14
16
18
20
22
24

@
1
2
R148 0_0402_5%

+5VALW

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

1
2
R149 0_0402_5%

+5VL

WCM-2012-900T_0805

SATA 2nd HDD Conn.

1
3
5
7
9
11
13
15
17
19
21
23

1
R88

1
3
5
7
9
11
13
15
17
19
21
23

W=60mils
+USB_VCCA

L54

OCTEK_SAT-22SO1G

0_0402_5%
2

For EMI

U14
1
2
3
4

+5VS

USB20_N0

<32>

W=60mils

2.5A

+5VALW

WCM-2012-900T_0805

JUSB

<32>

USB20_N2

<32>

USB20_P2

WCM-2012-900T_0805
@

2
R189

Confirm SSD need 3V or not.

1
0_0402_5%

USB20_N2_R
USB20_P2_R

1
2
3
4

VCC
DD+
GND

5
6
7
8

GND1
GND2
GND3
GND4

BACK_SENSE 3

2
1

AZC199-02SPR7G_SOT23-3

ACON_UARB2-4K1926
D23
USB20_N2_R

USB20_P2_R

@
1

PJDLC05C_SOT23-3

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

2012/12/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Sheet

Monday, February 28, 2011


1

37

of

59

IR Emitter Connector

3D@
R150 1

2 0_0402_5%

WCM-2012-900T_0805
<32>

USB20_P5

<32>

USB20_N5

4
L57

USB20_P5_R

3 3
@

USB20_N5_R

3D@
R144 1

2 0_0402_5%

JIR

2 3D@
R151

+5VS

+IR_VCC
USB20_P5_R
USB20_N5_R

1
0_0603_5%
3D@
C399
0.1U_0402_16V4Z

For ESD
D10
USB20_P5_R

USB20_N5_R

1
2
3
4

1
2
3 GND
4 GND

5
6

ACES_87213-0400G
@

1
PESD5V0U2BT_SOT23-3

B-CAS Circuit
+5VS

+5VALW

2
3
BCPWON

current = 0A

QB1
AO3413_SOT23
TV@
+5VS_BCAS

QB2B
TV@

TV@ RB7
10K_0402_5%

TV@ RB8
2.2K_0402_5%

CB3 TV@
4.7U_0603_6.3V6K

+5VS_L_BCAS
LB1 TV@
1
2
1 FBMA-L11-201209-221LMA30T_0805

CB5
TV@
1U_0402_6.3V6K

1
CB4
TV@
0.1U_0402_16V4Z
2

+5VS_L_BCAS

BCPWON

<39>

47K_0402_5%
1
TV@
TV@
CB2
2
0.01U_0402_25V7K

2N7002DW-T/R7_SOT363-6

RB5

100K_0402_5%

Inrush
1 TV@
CB1
0.1U_0402_16V7K

TV@RB2
TV@
RB2

+5VS_L_BCAS

BCRSTM

IN2

UB1 TV@

Finger printer

IN1

<39>

1
BCRSTM 2

B_R_BCRST 1 TV@
RB9

B_BCRST
2
100_0402_5%

B_BCRST

<39>

XBCLKM

XBCLKM

IN2

JFP
UB2 TV@

+3VS

IN1

<39>

B_R_XBCCLK1 TV@
RB11

B_XBCCLK
2
100_0402_5%

B_XBCCLK <39>

<32>
<32>

+3VS_FP
USB20_N8
USB20_P8
FP_GND

USB20_N8
USB20_P8

SN74AHC1G08DCKR_SC70-5

1 R134
2
0_0603_5% 1
FP@
C480
0.1U_0402_16V4Z
FP@
2

SN74AHC1G08DCKR_SC70-5

R133
0_0603_5%
FP@

VCC

IO2

FP@

1
2
3
4
GND
GND
P-TWO_161011-04021

D82

1
2
3
4
5
6

GND

IO1

+5VS_L_BCAS

<39>

CPLGP1

CPLGP1

2
B

PRTR5V0U2X_SOT143
BCIO

For ESD
BCIO

<39>

1
2
RB14
TV@
1.5K_0402_5%

QB2A
TV@
2

2N7002DW-T/R7_SOT363-6

2
1
RB13 TV@
10K_0402_5%

1
2
RB12
TV@
10K_0402_5%
QB4 TV@
2SB1197K_SOT23-3

10K_0402_5%

+5VS_L_BCAS

TV@
2

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RB1
1

Date:

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
1

38

of

59

+3VALW
+3VS

Enable

Disable

BT_CRTL

+3V_WLAN

+1.5VS

PCIE--JET

BT_ON#

<29> CLK_JET#
<29> CLK_JET

Short PJ27 for Wimax


Short PJ26 for WLAN

Q36

S
<29> PCIE_PTX_C_JETRX_N3
<29> PCIE_PTX_C_JETRX_P3

<5,9,47,54> SUSP

0.1U_0402_16V4Z
1
1

C253
CM7
CM8
47P_0402_50V8J
2
2
2
@
4.7U_0805_10V4Z
0.01U_0402_25V7K

+3VS

Modify BT_CTRL circuit


2010/11/04

CM9

C254
47P_0402_50V8J
2
2
@
4.7U_0805_10V4Z

<44> TMPTU2_SXP

+3VS

2
G

2
0.01U_0402_25V7K

CM3

<29> PCIE_PRX_JETTX_N3
<29> PCIE_PRX_JETTX_P3

CM2

0.1U_0402_16V4Z
1

Q39

2
G

<38> BCRSTM
<38> BCPWON

For SED

1
CM1

+1.5VS

For SED

2
G

BT_ON#

BT_CTRL
2N7002_SOT23-3

2N7002_SOT23-3

<33>

40 mils

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

BCCDET

<29> CLKREQ_JET#

PJ26@ JUMP_43X79

+3V_WLAN

JTV

B-CAS

<38> XBCLKM

PJ27@ JUMP_43X79
2 2
1 1

<29> PCIE_PTX_C_WLANRX_N2
<29> PCIE_PTX_C_WLANRX_P2

WLAN/ WiFi
+3V_WLAN

<44>
<44>

E51_TXD
E51_RXD

R16
10_0402_5%2
1
2
0_0402_5%
R17

E51_RXD_R

GND1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND2

54

3
S

WLAN_OFF#

2
10K_0402_5%

1 TV@
R307

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

GND2

54

PM_SMBCLK <11,12,29>
PM_SMBDATA <11,12,29>
USB20_N9 <32>
USB20_P9 <32>
LED_WIMAX#

1
RM6

For SED
C255
47P_0402_50V8J
@

RM3
1 TV@

0_0402_5%
UIM_VPP
2

1 TV@
RM7

BCIO
2
0_0402_5%

2
2
4.7U_0805_10V4Z

2.75A
+UIM_PWR

COMMON
ISDBT_DET
RF_OFF#
PLT_RST#

COMMON

ISDBT_DET <33>
RF_OFF# <32>

USB20_P10_TV
USB20_N10_TV

1 R126
1 R135

2 TV@
2 TV@

USB--TV#2
0_0402_5%
0_0402_5%

LED_WIMAX#
CPLGP1

BCIO

<38>

USB20_P10 <32>
USB20_N10 <32>

Close to J3G

USB20_N12 <32>
USB20_P12 <32> USB--3G/TV#1

1 TV@
RM4

+5VS_BCAS
CPLGP1 <38>
TMPTU1_SXP <44>

B-CAS

2
470_0402_5%

<38>

B_BCRST

<38>

B_XBCCLK

+VCC_SIM

2
0_0603_5%

B_BCRST

1 TV@
RM8

SIM_RESET
2
0_0402_5%

B_XBCCLK

1 TV@
RM10

2
0_0402_5%

BCIO

1 TV@
RM12

SIM_DATA
2
0_0402_5%

+UIM_PWR

JTVSIM
+VCC_SIM
SIM_RESET
SIM_CLK
CM13
0.1U_0402_16V4Z
TV@

WiMax

DM1
RLZ20A_LL34
TV@

LED_WIMAX# <46>

SIM_CLK

1
2
3

VCC
RST
CLK

RM2
4.7K_0402_5%
@

GND
VPP
I/O

4
5
6

NC

UIM_VPP
SIM_DATA

7
1
CM15
10P_0402_50V8J
TV@ 2

NC

MOLEX_47273-0001~D

CM16
10P_0402_50V8J
2 TV@

CM14
22P_0402_50V8J
@

2
+3VS
100K_0402_5%
WIMAX@
BT_CTRL

1 R327
2 E51_RXD_R
1K_0402_5%

For isolate Intel Rainbow Peak and


Compal Debug Card.

MAX14566B

MAX14566E
CB1 (CEN#)
SLP_CHG_M3

CB0: SLP_CHG_M4

STATUS

STATUS

AUTO MODE

AUTO MODE

Force Dedicated charger mode


(MODE3)

Pass-Through (USB) Mode:


Connect DP/DM to TDP/TDM

Pass-Through (USB) Mode:


Connect DP/DM to TDP/TDM

+USB_VCCB

U15

<42,44> USB_CHG_EN#

+3V_WLAN

PLT_RST# <5,32,40,41,42,44,45>

CB0
SLP_CHG_M4

2.5A

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

Add Level shift circuit for WL_OFF#


to avoid leakage from WLAN to PCH.
WLAN_OFF#
PLT_RST#

USB Sleep & Charge


Auto-Mode
Mode3/Mode4

1
2
3
4

0.01U_0402_25V7K
2

FOX_AS0B226-S40N-7F

BCCDET
WLAN_OFF# 1
R565

GND1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

120 mils

0.1U_0402_16V4Z
1
1
CM5
CM6

Add BCCDET pull down

2N7002_SOT23-3 Q40

FOX_AS0B226-S40N-7F

+5VALW

WL_OFF# <32>

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

Debug card using

+3V_WLAN

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

CM4
+3VS

<29> PCIE_PRX_WLANTX_N2
<29> PCIE_PRX_WLANTX_P2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

<29> CLK_WLAN#
<29> CLK_WLAN

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

+1.5VS
JWLAN

@
R1443
0_0402_5%
BT_CTRL 1
2BT_CTRL_R
<29> CLKREQ_WLAN#

+3VS

Slot 2 Full PCIe Mini Card- 3G/ TV Tuner


Half PCIe Mini Card- JET

BT
on module

Slot 1 Half PCIe Mini Card-WLAN/ WiMax

BT
on module

WLAN&BT Combo module circuits

W=60mils

8
7
6
5

RT9715BGS_SO8

U5
USB_OC#1 <32,42,44>

C383
4.7U_0805_10V4Z
@

<32> SLP_CHG_M3
<42> USB20_DN1_R
<42> USB20_DP1_R

SLP_CHG_M3
USB20_DN1_R
USB20_DP1_R

1
2
3
4
9

CEN
DM
DP
GND
GND

CB
TDM
TDP
VCC

8
7
6
5

SLP_CHG_M4
U2D_DN1
U2D_DP1

MAX14566EETA+_TDFN-EP8_2X2~D

SLP_CHG_M4 <32>
U2D_DN1 <42>
U2D_DP1 <42>
+5VALW

C892
0.1U_0402_16V7K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet

39

of

59

UL1
<29> PCIE_PRX_C_LANTX_P1

CL1

<29> PCIE_PRX_C_LANTX_N1

CL2

2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1

2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1

CLKREQ_LAN#

<5,32,39,41,42,44,45> PLT_RST#
1

+3V_LAN

<29>
<29>

RL24 2 @

1 10K_0402_5%

CLKREQ_LAN#

RL25 2 @

1 10K_0402_5%

EC_SWI#

+3VS

Pin15

NC

Pin38

CLK_LAN
CLK_LAN#

19
20

REFCLK_P
REFCLK_N

LAN_X1

43

CKXTAL1

LAN_X2

44

CKXTAL2

CLKREQB
PERSTB

NC

28

31
37
40

EECS/SCL
EEDI/SDA

30
32

RL2 2
RL1 2

MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3

1
2
4
5
7
8
10
11

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-

DVDD10
DVDD10
DVDD10

13
29
41

26

RL21 2 8111E@ 1 10K_0402_5%


RL22 1
2 1K_0402_5%

+3V_LAN

ENSWREG
WOL_EN

2
0_0402_5%

ISOLATEB

RL7
15K_0402_5%

Sx Enable Sx Disable
Wake up
Wake up
LOW

WOL_EN

HIGH

S0

NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT

33

ENSWREG
VDDREG
VDDREG

46
2
2.49K_0402_1%
24
49

1
RL5

1 10K_0402_5%
1 10K_0402_5%

8111E@
+LAN_REGOUT
1
2
2.2UH +-5% NLC252018T-2R2J-N
1

+LAN_VDD10

RSET
GND
PGND

CL9
0.1U_0402_16V4Z
2 8111E@

+LAN_VDD10

+3V_LAN
+3V_LAN

EVDD10

21

+LAN_EVDD10

AVDD10
AVDD10
AVDD10
AVDD10

3
6
9
45

+LAN_VDD10

CL17
0.1U_0402_16V4Z

Close to Pin 21
+3V_LAN

8111E@
8111E@

+LAN_VDDREG

8111E@
1
8111E@ LL3

2
0_0603_5%

CL28
4.7U_0603_6.3V6K
8111E@ 2

+LAN_REGOUT

36

2
2
2
2
2

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1

0.1U_0402_16V4Z

CL19, CL20,CL21 close to pin 13,29,45, respectively


CL22 close to pin 3, respectively
CL23,CL24,CL25 close to pin 6,9,41, respectively

2
0_0603_5%
CL18
1U_0402_6.3V6K

12
42
47
48

+LAN_EVDD10
1
LL2

AVDD33
AVDD33
AVDD33
AVDD33

REGOUT

1
CL3
1
CL4
1
CL5
1
CL6
1
8111E@ CL7
1
8111E@ CL8

Layout Note: LL1 must be


within 200mil to Pin36,
CL13
CL13,CL9 must be within 4.7U_0603_6.3V6K
200mil to LL1
8111E@ 2

+LAN_VDD10

27
39

DVDD33
DVDD33

14
15
38

34
35

+LAN_VDDREG

LL1

LANWAKEB

10K ohm PD

1K ohm Pull-high

1
RL433

HSIP
HSIN

16
1
0_0402_5%
25

EC_SWI#

<30,42> EC_SWI#

1K_0402_5%
RL6
@
ISOLATE#

HSON

2
RL19
PLT_RST#

ISOLATE#

1
2

NC

23

CL3 to CL6 close to Pin 27,39,47,48


CL7 to CL8 close to Pin 12,42

+LAN_VDD10

LED3/EEDO
LED1/EESK
LED0

RTL8111E

RTL8105E
Pin14

CLK_LAN
CLK_LAN#

+3V_LAN

HSOP

PCIE_PTX_C_LANRX_P1 17
PCIE_PTX_C_LANRX_N1 18

<29> PCIE_PTX_C_LANRX_P1
<29> PCIE_PTX_C_LANRX_N1
<29> CLKREQ_LAN#

22

60 mils

8111E@

1
CL19
1
CL20
1
CL21
1
CL22
1
CL23
1
CL24
1
CL25

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

CL29
0.1U_0402_16V4Z
2 8111E@

HIGH
RTL8111E-GR_QFN48_6X6
8111E@

+3VALW TO +3V_LAN
YL1
2

+3V_LAN

LAN_X2

1
RL23
0_0402_5%
8105ELDO@

LAN Conn.

Add UL3 at DVT


2010/08/25

JLAN

RJ45_MIDI2-_R
RJ45_MIDI1+_R
RJ45_MIDI1-_R

RJ45_MIDI2+_R
RJ45_MIDI1+_R
RJ45_MIDI0-_R

X'FORM_ NS681680

RJ45_MIDI0+_R
UL4

For P/N and footprint


Please place them to ISPD page

1
2
3

TCT1
TD1+
TD1-

MCT1
MX1+
MX1-

24
23
22

4
5
6

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

21
20
19

LAN_MDI1LAN_MDI1+

7
8
9

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

18
17
16

LAN_MDI0LAN_MDI0+

10
11
12

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

15
14
13

LAN_MDI3LAN_MDI3+

UL1
LAN_MDI2LAN_MDI2+
8105E-VC 10/100M
8105ELDO@

0.1U_0402_25V6
1
1
4

CL44

0.1U_0402_25V6
1

CL43
2

CL35

2
0.1U_0402_25V6

CL40 1000P_0402_50V7K
2
1
1 8111E@ 2
RL12
75_0402_1%
8111E@
CL41 1000P_0402_50V7K
2
1
1
2
RL13
75_0402_1%
CL42 1000P_0402_50V7K
2
1
1
2
RL15
75_0402_1%

PR2-

PR3-

PR3+

PR2+

PR1-

PR1+

DL1
AZC199-02SPR7G_SOT23-3

RJ45_MIDI3-_R
RJ45_MIDI3+_R

RJ45_MIDI0-_R
RJ45_MIDI0+_R
1
CL36

LANGND

2
1000P_1808_3KV7K

Compal Secret Data


2011/01/31

Issued Date

10

AZC199-02SPR7G_SOT23-3
DL2

SUPERWORLD_SWG150401
8111E@

Security Classification

SHLD2

RJ45_MIDI1-_R
RJ45_MIDI1+_R

2
0.1U_0402_25V6

Place CL34, CL35, CL43, CL44 to colse


to LAN chip

SHLD1

SANTA_130451-D
@

RJ45_MIDI2-_R
RJ45_MIDI2+_R

RJ45_GND
1
CL34

CL39 1000P_0402_50V7K
2
1
1 8111E@ 2
RL11
75_0402_1%
8111E@

PR4+

RJ45_MIDI1-_R

PR4-

RJ45_MIDI3+_R

RJ45_MIDI0+_R
RJ45_MIDI0-_R

16
15
14
13
12
11
10
9

LAN_MDI1+
LAN_MDI1-

TX+
TXCT
NC
NC
CT
RX+
RX-

+3V_LAN rising time (10%~90%) need > 1ms and <100ms.

TD+
TDCT
NC
NC
CT
RD+
RD-

1
2
3
4
5
6
7
8

RJ45_MIDI32
0_0402_5%
RJ45_MIDI3+
2
0_0402_5%
RJ45_MIDI12
0_0402_5%
RJ45_MIDI22
0_0402_5%
RJ45_MIDI2+
2
0_0402_5%
RJ45_MIDI1+
2
0_0402_5%
RJ45_MIDI02
0_0402_5%
RJ45_MIDI0+
2
0_0402_5%

LAN_MDI0+
LAN_MDI0-

1
LL4
1
LL5
1
LL6
1
LL7
1
LL8
1
LL9
1
LL10
1
LL11

RJ45_MIDI3-_R

UL3 8105ELDO@

CL682
1U_0402_6.3V6K

PJ29
JUMP_43X79
@
+3V_LAN

1
CL681
4.7U_0805_10V4Z
@

0 ohm
(Pull Down)

@
CL482
0.01U_0402_25V7K

NC
RL23

AO3413_SOT23

RTL8105E-VC RTL8105E-VC
RTL8111E-VB
PWM Mode
LDO Mode
NC
RL4
0 ohm
(Pull High)

RL4
0_0402_5%
8111E@

2
2

47K_0402_5%

CL27
27P_0402_50V8J

2
ENSWREG

@ QL51
2

CL26
27P_0402_50V8J

Vgs=-4.5V,Id=3A,Rds<97mohm

@RL432
@
RL432
1

CL483
@
0.1U_0402_16V7K
S

RL147
100K_0402_5%
@

+3VALW

<44> WOL_EN

25MHZ_20PF_7A25000012

LAN_X1

+3VALW

2012/12/31

Deciphered Date

Title

CL38
220P_0402_50V7K

Compal Electronics, Inc.


SCHEMATIC, MB A7211

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
B

4019BD

Date:

Sheet

Monday, February 28, 2011


E

40

of

59

1
CC1
2

CC16 close to pin43


For internal LDO in SD3.0

JMB389C

10U_0805_10V4Z

20mil

CC3 close to pin 5


CC2 close to CC3
CC1 is near CC3
1
CC2
2

1
CC3
2

1
CC4
2

0.1U_0402_16V4Z

+1.8VS_OUT

1000P_0402_50V7K

0.22U_0402_6.3V4K

D3E mode
CC4 close to pin 10

+3VS

<28> CR_CPPE#

RC31
1

0_0402_5%
CPPE#
2

<28> CR_WAKE#

RC6
1

0_0402_5%
SD_CD#
2

+3VS

UC1

place near pin 19,20 and 44


CLK_CR#
CLK_CR

<29> CLK_CR#
<29> CLK_CR
<29> PCIE_PTX_C_CRRX_N4
<29> PCIE_PTX_C_CRRX_P4
<29> PCIE_PRX_C_CRTX_N4
<29> PCIE_PRX_C_CRTX_P4

CC8
CC9

1
1

2
2

3
4

PCIE_PTX_C_CRRX_N4
PCIE_PTX_C_CRRX_P4

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_PRX_CRTX_N4
PCIE_PRX_CRTX_P4
APREXT

2
1
RC3 12K_0402_1% 12mil
2
CC16

+SDV33_18
1
2.2U_0603_6.3V6K

9
8

APRXN
APRXP

11
12

APTXN
APTXP

7
43
39

APVDD
APV18
NC/TAV33

5
10
36

DV33
DV33
DV33
DV18
DV18

19
20
44
18
37

MDIO0
MDIO1
MDIO2
MDIO3
MDIO6/4
MDIO5
G/MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

48
47
46
45
41
42
24
40
29
28
27
26
25
23
22

NC/SPI_SCK
NC/SPI_CSN
NC/SPI_SO
NC/SPI_SI

30
33
34
35

APGND
NC/GND
NC/GND
NC/GND

6
31
32
38

APCLKN
APCLKP

APREXT
SDDV/MDIO4
TXIN/NC

JMB389
1
2

<5,32,39,40,42,44,45> PLT_RST#

CPPE#
XD_CD#

13
14

MS_CD#
SD_CD#

XRSTN
XTEST
CPPE_N
CR1_CD2N

15
16

CR1_CD1N
CR1_CD0N

17

CR1_PCTLN

40 mils
+VCC_OUT

+VCC_OUT

CR_LED
2
RC7
1
RC9

21

XDWP#_SDWP#

1
10K_0402_5%
2
1K_0402_5%

40mil

CC5

1
CC6
1
CC7

2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z

+1.8VS_OUT

20mil

CC12
0.1U_0402_16V4Z

CC12 close to pin 36

Power On Strapping setting


XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
SDCMD_MSBS_XDWE#
SDCLK_MSCLK_XDCE#
XDWP#_SDWP#
XD_CLE
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
XD_RE#
XD_RB#
XD_ALE

CC10

CC11

1
2
0.22U_0402_6.3V4K

10U_0805_10V4Z

Description

Pin name

CC11 close to pin18


For intenal LDO's usage

MDIO7

on-board

add-in card

MDIO14

CR_LED
high active

CR_LED
low active

CC10 close to pin37

+3VS

XD_CLE

MDIO7
XD_ALE

CR1_LEDN

low

High

MDIO14

1
RC28

1
RC26

1
RC25

10K_0402_5%

2
1K_0402_5%
2

200K_0402_5%

XD_RB#

Vendor review to set @

JMB389-LGAZ0A_LQFP48_7X7

Add RC24 and RC17 close to UC1 for xD issue


SDCMD_MSBS_XDWE#

XDWE#

2
RC24

1
22_0402_5%

2
RC17

SDCMD_MSBS
1
22_0402_5%

5 in 1 Card Reader
SD_CD#

XD_CD#

JREAD

+VCC_OUT

@
B

40 mils
CC22
0.1U_0402_16V4Z
@

CC23
0.1U_0402_16V4Z
CC17
10U_0805_10V4Z

CR_LEDCON#

CC18
0.1U_0402_16V4Z

XD-VCC
XD-CD-SW
XD-R/B
XD-RE
XD-CE
XD-CLE
XD-ALE
XD-WE
XD-WP

XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7

8
9
26
27
28
30
31
32

XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

MS-VCC
MS-SCLK
MS-INS
MS-BS
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

14
15
17
21
19
20
18
16

MS_CLK
MS_CD#
SDCMD_MSBS
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3

SD-VCC
SD-CLK
SD-CMD
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-WP-SW
SD-CD-SW

23
24
12
25
29
10
11
35
36

SD_CLK
SDCMD_MSBS
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XDWP#_SDWP#
SD_CD#

4in1-GND
4in1-GND
4in1-GND
4in1-GND

13
22
37
38

CR_LEDCON# <46>

1
0_0402_5%

+VCC_OUT

SDCLK_MSCLK_XDCE#

SD_CLK

RC12 1

2 22_0402_5%

MS_CLK

RC13 1

2 22_0402_5%

XD_CE#

MS_CLK

XD_CE#

100_0402_5% 100P_0402_50V8J
@
@
RC16
CC21
1
2
1
2

TAITW_R015-211-LM-A_NR

100_0402_5%

100P_0402_50V8J
@
CC20
1
2

100P_0402_50V8J

Confirm sinking 16mA

RC10
4.7K_0402_5%
@

Reserved for EMI,close to JREAD


Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

Compal Electronics, Inc.


SCHEMATIC, MB A7211

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

@
CC19
1
2

100_0402_5%
@
RC15
1
2

CR_LED

2
G

QC1
2N7002_SOT23-3
@
S

2 0_0402_5%

@
RC14
SD_CLK

D
A

RC11 1

Reserved for EMI,close to UC1.42


Change RC11 from 22ohm to 0ohm
in order fix SDXC performance low.

+VCC_OUT

2
RC8

XD_CD#
XD_RB#
XD_RE#
XD_CE#
XD_CLE
XD_ALE
XDWE#
XDWP#_SDWP#

33
34
1
2
3
4
5
6
7

Rev
B

4019BD

Monday, February 28, 2011

Sheet
1

41

of

59

+1.5V to +1.05V Transfer


+1.5V

Close to U102.D7

+1.05V
UT2
VIN
VOUT
VIN
VOUT
VCNTL
POK
FB

3
4

USB30_POK

5
9
6
7

+3V

EN

GND

Close to U102.P13

+3VA

+3VA

1A

APL5930KAI-TRG_SO8

USB30_POK

1 RT1
2
4.7K_0402_5%

+5VALW

+1.5V

1
RT2
10K_0402_1%
1

RT3
32.4K_0402_1%
2

Vout=0.8(1+10K/32.4K)
1.042 ~ 1.0469 ~ 1.0519V
Spec: 0.9975 ~ 1.05
~ 1.1025

+3VALW to +3V Transfer

1
0.1U_0402_16V7K
CT4

CT3
10U_0603_6.3V6M

CT2
10U_0603_6.3V6M

CT1
1U_0603_10V6K

+5VALW

+5VALW

8P_0402_50V8D
CT6
1 @

2
CT5 2
0.01U_0402_25V7K

1
0.1U_0402_16V7K
CT7

8P_0402_50V8D
CT9
1 @
U3RXDP1_R

2
CT8 2
0.01U_0402_25V7K

U3RXDP1_R_L

1
2 RT4
0_0402_5%
@ WCM-2012-121T_0805
1 1
2 2

U3TXDP1

1
2 RT5
0_0402_5%
@ WCM-2012-121T_0805
1 1
2 2

U3TXDP1_L

4
U3RXDN1_R

+3VALW

+3VALW

4
LT1

4
U3RXDN1_R_L

2 RT6
0_0402_5%

4
LT2

U3TXDN1

2 RT7
0_0402_5%

U3TXDN1_L

Follow Vendor recommend.

3
1

+3VA

<39> USB20_DN1_R
<39> USB20_DP1_R

1 0.1U_0402_16V7K PCIE_PRX_USBTX_P6
1 0.1U_0402_16V7K PCIE_PRX_USBTX_N6

CT29 2
CT30 2

<29> PCIE_PRX_C_USBTX_P6
<29> PCIE_PRX_C_USBTX_N6

D2
D1
F2
F1

<29> PCIE_PTX_C_USBRX_P6
<29> PCIE_PTX_C_USBRX_N6

<5,32,39,40,41,44,45> PLT_RST#
<30,40> EC_SWI#
<29> CLKREQ_USB30#

RT15
RT16
RT17

+3V
USB30_SMI#_IC

RT391

2 10K_0402_5%

1SS355TE-17_SOD323-2
1 1 2 2
DT3
2

USB30_SMI#_IC

For UPD720200:
SMI high active

1 RT18

1
2 10K_0402_5%
@1
2 100_0402_1%
1
2 10K_0402_5%
USB30_SMI_R
USB30_SMI#_R
2

1
Q57
@

CT44
1U_0603_10V6K

CT24 0.01U_0402_25V7K

CT23 0.01U_0402_25V7K

2
1
G
S 2N7002_SOT23-3
1

@
2 USB30_SMI_R
RT21
0_0402_5%

SPI_CLK_USB
SPI_CS_USB#
SPI_SI_USB
SPI_SO_USB

J2
J1
H1
P4

AUXDET
PSEL
SMI
SMIB

P5

PONRSTB

M2
N2
N1
M1

GND
GND
GND

C14

GND

D7

P13

+USB_VCCB

W=80mils

U2DP2
U3RXDP2

P8
B8

U3RXDN2

A8

0.1U_0402_16V4Z
1

CT31
2

OCI2B
OCI1B

G14
H13

OCI2#
OCL1#

PPON2
PPON1

H14
J14

USB30PWRON

1 RT13

2 10K_0402_5%

CT27

220U_6.3V_M_R15

CT28

JUSB30
U3TXDP1_L
+USB_VCCB

U3TXDP1

B10

U3TX_C_DP1

CT32 1

2 0.1U_0402_16V7K

U3TXDP1

U3TXDN1
U2DM1

A10
N10

U3TX_C_DN1
U2D_DN1

CT33 1
2 0.1U_0402_16V7K
U2D_DN1 <39>

U3TXDN1

U2DP1
U3RXDP1

P10
B12

U2D_DP1
U3RXDP1_R

U3RXDN1

A12

U3RXDN1_R

RREF
U2AVSS

P12
N12

RT22

U2PVSS

N11

U3AVSS

D6

9
1
8
3
7
2
6
4
5

U3TXDN1_L
USB20_DP1_L
USB20_DN1_L
U3RXDP1_R_L
U3RXDN1_R_L

U2D_DP1 <39>

SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-

GND
GND
GND
GND

10
11
12
13

LOTES_AUSB0003-P001C

2 1.6K_0402_1%

@
USB30PWRON RT11 1
0_0402_5%

2USB_CHG_EN#

USB_CHG_EN#

P6

CSEL

2
0_0402_5%

@
RT31
1

CT38
12P_0402_50V8J

CT37
12P_0402_50V8J

RT30
0_0402_5%

RT291
2
0_0402_5%

RT281
2
0_0402_5%

YT1
1

24MHZ_12PF_X5H024000DC1H

+3V

<29> 48MCLK_USB30

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

DT2
U3TXDP1_L 1 1

P14
P11
P9
P7
P2
P1
N13
N9
N7
N3
M13
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
L12
L11
L7
L6

DT1
USB20_DP1_L
USB20_DN1_L

2
3

2
1

@
U3TXDP1_L

109

U3TXDN1_L 2 2

98

U3TXDN1_L

U3RXDP1_R_L 4 4

77

U3RXDP1_R_L

U3RXDN1_R_L 5 5

66

U3RXDN1_R_L

AZC199-02SPR7G_SOT23-3

3 3
8
YSCLAMP0524P_SLP2510P8-10-9

Change ESD Diode for EMI request

+3V

+3V

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

A1
A2
A3
A4
A5
A7
A9
A11
A13
A14
B3
B4
B5
B7
B9
B11
B13
B14
C1
C2
C3
C10
C11

CSEL=024MHz XTAL
CSEL=148MHz Clock

10K_0402_5%
2 RT43
1

USB30_SMI#_IC

QT3B

C12
C13
D3
D4
D11
D12
D13
D14
E1
E2
E13
E14
F4
F6
F7
F8
F9
F11
F12
G1
G2
G6
G7
G8
G9
G11
G12
G13
H6
H7
H8
H9
H12
J3
J4
J6
J7
J8
J9
J11
J12
K3
K4
L1
L2
L3
L4

2N7002DW-T/R7_SOT363-6
OCL1#

USB30_SMI# <33>
QT3A

USB_OC#1 <32,39,44>

+3V

RT33
10K_0402_5%

SPI_CLK_USB

UT4
1
2
3
4

CS#
SO
WP#
GND

35mA
VCC
HOLD#
SCLK
SI

8
7
6
5

CT39
1
2 0.1U_0402_16V7K

CT40
0.1U_0402_16V7K
@

Compal Secret Data

Security Classification
Issued Date

MX25L5121EMC-20G SOP 8P
SPI_CLK_USB_R 1 RT36
2
0_0402_5%

2011/01/31

Deciphered Date

2012/12/31

Title

Compal Electronics, Inc.


SCHEMATIC, MB A7211

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SPI_CLK_USB

Date:

2N7002DW-T/R7_SOT363-6

2010/09/17 Add Level shift to avoid +3V leakage from +3VALW_PCH

Close to UU37.6

1 RT35
210K_0402_5%
SPI_CLK_USB_R
SPI_SI_USB

10K_0402_5%
2 RT44
1

1 RT34
2
0_0402_5%
@

RT32
47K_0402_5%

+3V

UPD720200AF1-DAP-SSA-A

<39,44>

1
RT26
100_0402_5%

Place as close as possibile to


UU102.N14 and UU102.M14

SPI_CS_USB#
SPI_SO_USB

1000P_0402_50V7K

+3V

XT1
XT2

CT15 0.01U_0402_25V7K

CT14 0.1U_0402_16V7K

CT13 0.01U_0402_25V7K

CT12 0.01U_0402_25V7K

CT11 0.01U_0402_25V7K

CT10 0.01U_0402_25V7K

RT10

CT26

+3V
N14
M14

USB20_DP1_L

A6
N8

@
2 USB30_SMI#_R
RT40
0_0402_5%

CLK_48M_USB

2
0_0402_5%

U3TXDN2
U2DM2

SPISCK
SPISCB
SPISI
SPISO

K13
K14
J13

USB20_DN1_L

4.7U_0805_10V4Z

PERXP
PERXN

PERSTB
PEWAKEB
PECREQB

B6

+1.05V:800mA

H2
K1
K2

1
LT4

U3TXDP2

+3V:200mA

PETXP
PETXN

CT22 0.01U_0402_25V7K

CT21 0.1U_0402_16V7K

CT20 0.01U_0402_25V7K

CT19 0.01U_0402_25V7K

CT18 0.1U_0402_16V7K

CT17 0.01U_0402_25V7K

CT16 0.1U_0402_16V7K

0_0402_5%

+3V

+1.05V

USB30_WAKE#

RT12 10_0402_5% 2
+3V

UPD720200A:
SMIB Low active

U2AVDD10

U3AVDO33

H11
K11
K12
L8
VDD10
VDD10
VDD10
VDD10

E11
E12

E3
E4

H3
H4
L5
VDD10
VDD10
VDD10

VDD10
VDD10

VDD10
VDD10

C8
C9
D8
D9
VDD10
VDD10
VDD10
VDD10

C4
C5
C6
C7
D5
VDD10
VDD10
VDD10
VDD10
VDD10

N4
N5
N6
P3
VDD33
VDD33
VDD33
VDD33

L13
L14
VDD33
VDD33

L9
L10
VDD33
VDD33

F3
G3
G4

PECLKP
PECLKN

1
CT25
10U_0603_6.3V6M

USB20_DP1_R

VDD33
VDD33
VDD33
B2
B1

VDD33
VDD33
VDD33

UT1

<29> CLK_USB30
<29> CLK_USB30#

LT3
1
2
BLM18AG601SN1D_2P

USB20_DN1_R

+3V

S 2N7002_SOT23-3

+3VA

0_0402_5%
2

+3V & +1.05V has power sequence timing:


0.1*VDD(+3V) ~ 0.9*VDD(+1.05V) < 100ms

+3V

RT9

@ WCM-2012-900T_0805

D10
F13
F14

+1.05V

QT1
AO3413_SOT23

1
2
2
RT38 47K_0402_5% 2
CT43
0.01U_0402_25V7K
1

<44,52> SYSON

2
G
QT2

+3V

CT42
0.1U_0402_16V4Z

CT41
0.1U_0402_16V7K
1

RT37
100K_0402_5%

Rev
B

4019BD

Monday, February 28, 2011


1

Sheet

42

of

59

+PVDD1

CA57

2
CA1

CA7
10U_0805_10V4Z
2
2

1U_0402_6.3V6K
1
2

RA38

MIC1_LINE1_R_R

CA10 1
0_0402_5%

4.7U_0805_10V4Z

<25> INT_MIC_DATA

For EMI

CA22

2
2
10U_0805_10V4Z
RA3
10U_0805_10V4Z 0.1U_0402_16V4Z 2
1
+5VALW
0_0603_5%

SPKLSPKR+

CA25
@ 10U_0805_10V4Z
2

CA11
0.01U_0402_25V7K
@

1
CA12

CA48 1

2 0.1U_0603_50V7K

CA49 1

2 0.1U_0603_50V7K

CA50 1

2 0.1U_0603_50V7K
1
10_0603_5%

1
2
INT_MIC_CLK_R
CA15
FBMA-10-100505-301T
2.2U_0603_6.3V4Z
CAM@
1
+MIC1_VREFO_L

CA28 CAM@
220P_0402_50V7K

+5VALW

38
AVDD2

25
AVDD1

46

39

PVDD2

SPKR+
SPKR-

21
22

MIC1_L
MIC1_R

HP_OUT_L
HP_OUT_R

32
33

16
17

MIC2_L
MIC2_R

11

RESET#

12

PCBEEP

13

SENSE A

18

SENSE B

36
35

CBP

CA26
RA16 @ 10U_0805_10V4Z
2
2
1
0_0603_5%

SPKR-

close to chip

RA4

75_0402_1%

RA5

75_0402_1%

HP_L

<37>

HP_R

<37>

SYNC

10

AZ_SYNC_HD

PCI Beep

BCLK

AZ_BITCLK_HD

SDATA_OUT

AZ_SDOUT_HD

SDATA_IN

EAPD

47

SPDIFO

48

MONO_OUT

20

AZ_SDIN0_HD_R

AZ_SYNC_HD

AZ_SDIN0_HD

MIC2_VREFO

29

MIC1_VREFO_R
LDO_CAP

30
28

VREF

27

AC_VREF

31

MIC1_VREFO_L

JDREF

19

AC_JDREF2 RA9

43
42
49
7

PVSS2
PVSS1
DVSS2
DVSS1

CPVEE

34

CPVEE
1
CA14

AVSS1
AVSS2

26
37

CA16
2.2U_0603_6.3V6K
@

Ext. MIC

10K

PORT-C (PIN 23, 24)

PORT-F (PIN 16, 17)

+3VL

place close to chip


2
RA10

1
20K_0402_1%

100K_0402_5%

+3VALW

RA43
RA34

100K_0402_5%
@

100K_0402_5%

<44> SM_SENSE#

SENSE_A

QA1B

2N7002DW-T/R7_SOT363-6
<37>

NBA_PLUG

RA21

39.2K_0402_1%

2011/01/31

PORT-H (PIN 20)

Deciphered Date

2012/12/31

Date:

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

BACK_SENSE <37>

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

<37>

MIC_SENSE

1 4.7K_0402_5%

MIC_SENSE

20K

MIC1_L

AGND

Function

PORT-B (PIN 21, 22)

PORT-E (PIN 14, 15)

<37>

+MIC1_VREFO_L

RA28
RA22 2

20K

39.2K

MIC1_R

QA1A

Headphone out

(PIN 48)

+MIC1_VREFO_R

RA29 1
2
2.2K_0402_5%

2N7002DW-T/R7_SOT363-6

PORT-I (PIN 32, 33)

5.1K

2
1
1K_0402_5%
RA32

2
2
0.1U_0402_16V4Z

CA18
100P_0402_50V8J

RA33
2 RA31
1
1K_0402_5% 2.2K_0402_5%
2
1

MIC1_LINE1_R_R
MIC1_LINE1_R_L

CA17

Ext.MIC/LINE IN JACK

CA23 10U_0805_10V4Z
1
2

place close to chip

DGND

Codec Signals

4.7K_0402_5%

1 20K_0402_1%

2
2.2U_0603_6.3V4Z

MONO_IN

0.1U_0402_16V4Z

Change to AGND for


high frequency noise issue

CA29
1
1
2 @
RA17
10P_0402_50V8J

+MIC1_VREFO_R

CA13
1
2

RA8
1
2
47K_0402_5%

<28>

For EMI
AZ_BITCLK_HD 2
10_0402_5%

SPK_R2

Change value for Beep


by A51 demand.
2010/08/31
RA12

AZ_SDOUT_HD <28>

1
33_0402_5%

CA27
3
1U_0402_6.3V6K
AZ5125-02S.R7G_SOT23-3
@

<28>

AZ_BITCLK_HD <28>

2
RA6

RA7
1
2
47K_0402_5%

<28> PCH_SPKR

CBN

2
1

Beep sound

EC Beep
<44> EC_BEEP#

RA42
100K_0402_5%
@

39.2K

10K

CA6

ACES_85204-0400N
@

DA6

1
2
3
4

ALC269Q-VB5-GR _QFN48_7X7

EC_MUTE#

Impedance

45
44

PD#

SPK_R1

1
2
3
4

2 0.1U_0603_50V7K

SPK_OUT_R+
SPK_OUT_R-

SPK_L1
SPK_L2
SPK_R1
SPK_R2

CA47 1

LINE2_L
LINE2_R

GPIO1/DMIC_CLK

RA41

<25> INT_MIC_CLK

CA5

14
15

GPIO0/DMIC_DATA

For EMI

CA4

2
2
2
2
place
10U_0805_10V4Z 0.1U_0402_16V4Z
SPKL+
SPKL-

SENSE_A

CA3

40
41

MONO_IN
2
100P_0402_50V8J

UA1

SPK_OUT_L+
SPK_OUT_L-

INT_MIC_CLK_R

JSPK
SPK_L2

1
1

LINE1_L
LINE1_R

INT_MIC_DATA

AZ_RST_HD#

<28> AZ_RST_HD#

SENSE B

0.1U_0402_16V4Z
+5VALW
1
1
CA59
CA58
@
@

2
10U_0805_10V4Z

23
24

EC_MUTE#

<44> EC_MUTE#

RA44
100K_0402_5%
@

CA9

1U_0402_6.3V6K
RA37
4.7U_0805_10V4Z
CA21
2
1
0_0402_5% MIC1_LINE1_R_L
@
MIC1_LINE1_R_R
2
1

2
1
0_0603_5%
@
CA60
@

0_0402_5%

SENSE A

CA20
RA14 @ 10U_0805_10V4Z
2
2
1
0_0603_5%
RA15
2
1
0_0603_5%
1

DA7
2
CA24
1
1U_0402_6.3V6K
3
@
1
AZ5125-02S.R7G_SOT23-3

RA39

PVDD1

RA30
0_0402_5%
@

1
0_0402_5%

DVDD

0_0402_5%

Sense Pin

CA19
@ 10U_0805_10V4Z
2

RA35

Ext. Mic/LINE IN

2
RA18

SPK_L1

68 mA

MIC1_LINE1_R_L

RA13
2
1
0_0603_5%

2
10U_0805_10V4Z

place close to chip

+PVDD2
1
0.1U_0402_16V4Z
CA61
+AVDD
2

DVDD_IO

RA36

SPKL+

RA11

35 mA
1

CA8

2
10U_0805_10V4Z

+3VS_DVDD

0.1U_0402_16V4Z

2
1
FBMH1608HM601-T

+3VS

10U_0805_10V4Z
2
2

RA1

placement near Audio Codec

+5VALW
CA43

CA2

place close to chip

0.1U_0402_16V4Z +DVDD_IO

2
1
FBMH1608HM601-T

+3VS

JA1
JUMP_43X39
@

0.1U_0402_16V4Z
1
1
CA44

CA56

RA20

RA2
2
1
0_0603_5%

600 mA 0.1U_0402_16V4Z

Speaker Connector

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
1

43

of

59

R737
0_0402_5%
2
1

2
2
0.1U_0402_16V4Z

C440

C441
1000P_0402_50V7K

1
1
1000P_0402_50V7K
U19

1
R377
10_0402_5%
@

<32> CLK_PCI_EC
<5,32,39,40,41,42,45> PLT_RST#
+3VL

R378
47K_0402_5%
2
1

2
C444

<33> EC_SCI#
<45> HDPLOCK

ECRST#

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

1
2
3
4
5
7
8
10

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LPC_FRAME#/LFRAME#
LPC_AD3/LAD3
LPC_AD2/LAD2
LPC_AD1/LAD1
LPC_AD0/LAD0

CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#
HDPLOCK

12
13
37
20
38

CLK_PCI_EC/PCICLK
PCIRST#/GPIO05
EC_RST#/ECRST#
EC_SCI#/GPIO0E
CLKRUN#/GPIO1D

1
0.1U_0402_16V4Z

+3VS

8
7
6
5

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

<27,49>
<27,49>
<14,29,45,46>
<14,29,45,46>

2.2K_0804_8P4R_5%

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

PLT_RST#
2
1U_0402_6.3V6K
@

1
C820

SUSP#
2
180P_0402_50V8J

CLK_EC

CRY1_EC
CRY2_EC

0_0402_5%
0_0402_5%
0_0402_5%

122
123

<30>

R266
100K_0402_5%

+3VALW

5
IN1

SPIDI/MISO
SPIDO/MOSI
SPICLK/GPIO58
SPICS#

119
120
126
128

EC_SI_SPI_SO
EC_SO_SPI_SI
SPI_CLK_R
SPI_CS#

GPIO40
H_PECI/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
PWR_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

CIR_IN
EC_PECI
R461 1
FSTCHG
BATT_FULL_LED#
CAPS_LED#
BATT_CHG_LOW_LED#
PWR_ON_LED#
SYSON
VR_ON
ACIN_D

100
101
102
103
104
105
106
107
108

PCH_RSMRST#
EC_LID_OUT#
EC_ON
TP_LED
PM_PWROK
BKOFF#
HDPINT
CAP_RST#
SA_PGOOD

110
112
114
115
116
117
118

CEC_INT#
EC_ENBKL
USB_OC#1
OTP_HW#
SUSP#
PBTN_OUT#
USB_OC#0_R

CPSETIN

CPSETIN <49,50>
IREF
<50>
CHGVADJ <50>

SPI Flash ROM

GPIO

124

+3VS

TMPTU2_SXP

R757 10K_0402_5%
1
2

R758 10K_0402_5%
H_PROCHOT#_EC 1
2
@
+3VL

VGATE
<30,55>
WOL_EN <40>
PWRME_CTRL# <28>
LID_SW# <46>

CEC_INT#

2
R53

1
100K_0402_5%

CAP_INT#

1
R172 @

2
4.7K_0402_5%
+5VS

TP_CLK

1
R379
TP_DATA
1
R381

EC_SI_SPI_SO <45>
EC_SO_SPI_SI <45>

2
4.7K_0402_5%
2
4.7K_0402_5%

<45>

+3VALW
LID_SW#
2
47K_0402_5%

CIR_IN
<46>
2 43_0402_1%
H_PECI
<5>
FSTCHG <50>
BATT_FULL_LED# <46>
CAPS_LED# <45>
BATT_CHG_LOW_LED# <46>
PWR_ON_LED# <46>
SYSON
<42,52>
VR_ON
<55>

PCH_RSMRST# <30>
EC_LID_OUT# <29>
EC_ON
<46>
TP_LED <46>
PM_PWROK <5,30>
BKOFF# <25>
HDPINT <45>
CAP_RST# <46>
SA_PGOOD <53>

SYSON

1
R5

1
R383

2
4.7K_0402_5%

R341 330K_0402_5%
1
2

+3VL

D21
ACIN_D

ACIN

<13,30,46,50>

CH751H-40PT_SOD323-2

CEC_INT# <27>
EC_ENBKL <25>
USB_OC#1 <32,39,42>

+3VL

R359 330K_0402_5%
1
2
D26

OTP_HW#

SUSP#
<47,52,54,56>
PBTN_OUT# <30>

@
1

VS_ON <49,51>

CH751H-40PT_SOD323-2

+EC_V18R
EC_PECI

9012@
2
1 USB_OC#0
R739
0_0402_5%

USB_OC#0_R

9012@
1
2
R475
43_0402_1%

USB_OC#0 <32,37>

C448
4.7U_0805_10V4Z
KB930QF-A1_LQFP128_14X14

USB_OC#0_R

2
R738

H_PECI

1 USB_OC#0
0_0402_5%

<5>

USB_OC#0 <32,37>

R423 2

1 10K_0402_5%

VR_ON

R462 2

1 10K_0402_5%

R389

@
CRY1

CRY2
R290

10M_0402_5%
@

Y4

SPI_CLK

<45>

33_0402_5%
@
C450

1
@

2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

C309
10P_0402_50V8J

Compal Electronics, Inc.

Compal Secret Data

Security Classification

@
32.768KHZ_12.5PF_Q13MC14610002

18P_0402_50V8J

4
OSC

OSC
NC

SPI_CLK_R

1
1

18P_0402_50V8J

@
C449

E51_TXD
2
100K_0402_5%

SUSP#
SLP_S5#

NC

2
100P_0402_50V8J
2
100P_0402_50V8J

TMPTU1_SXP

TP_CLK <46>
TP_DATA <46>

SPI_CS#

1
C445
1
C446

R754 10K_0402_5%
1
2

EC_MUTE# <43>
USB_EN# <37>
CAP_INT# <46>

IN2

Q41
C518
2N7002_SOT23-3 47P_0402_50V8J

0.1U_0402_16V4Z

1 R398
2
0_0402_5%

1
R342

C1206
20P_0402_50V8J

TV tuner
temperature

Cost Down Plan and cut in PVT


2010/09/22

<30> PM_SLP_S4#

U44

VGATE
WOL_EN
PWRME_CTRL#
LID_SW#

BATT_TEMPA <49>
TMPTU1_SXP <39>
ADP_I
<49,50>
ADP_V <50>
TMPTU2_SXP <39>
HDPACT <45>

<30> PM_SLP_S5#

C818
1 @

H_PROCHOT# <5,49>
D

2
G

ACIN_D

SN74AHC1G08DCKR_SC70-5

97
98
99
109

GND
GND
GND
GND
GND

Close to EC

SDICS#/GPXIOA00
WOL_EN/SDICLK/GPXIOA01
ME_EN/SDIMOSI/GPXIOA02
LID_SW#/GPXIOD00

PM_SLP_S3#/GPIO04
EC_RSMRST#/GPXIOA03
PM_SLP_S5#/GPIO07
EC_LID_OUT#/GPXIOA04
EC_SMI#/GPIO08
EC_ON/GPXIOA05
GPIO0A
EC_SWI#/GPXIOA06
GPIO0B
ICH_PWROK/GPXIOA07
GPIO
GPIO0C
BKOFF#/GPXIOA08
GPO RF_OFF#/GPXIOA09
SUS_PWR_DN_ACK/GPIO0D
INVT_PWM/PWM2/GPIO11
GPXIOA10
FAN_SPEED1/FANFB0/GPIO14
GPXIOA11
FANFB1/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PM_SLP_S4#/GPXIOD01
ON_OFF/GPIO18
ENBKL/GPXIOD02
SUSP_LED#/GPIO19
EAPD/GPXIOD03
GPI EC_THERM#/GPXIOD04
NUM_LED#/GPIO1A
SUSP#/GPXIOD05
PBTN_OUT#/GPXIOD06
EC_PME#/GPXIOD07
XCLK1
XCLK0
V18R

EC_SMI#

CRY1 @ R991
CRY2 @ R992
R990

EC_MUTE#
USB_EN#
CAP_INT#
H_PROCHOT#_EC
TP_CLK
TP_DATA

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

<46> ESB_CK
<46> ESB_DAT
<30> PCH_SUSPWRDN
<25> INVT_PWM
<5> FAN_SPEED1
<43> SM_SENSE#
<39> E51_TXD
<39> E51_RXD
<46> ON/OFFBTN#
<46> PWR_SUSP_LED#
<45> NUM_LED#

1
C819

EC_MUTE#/PSCLK1/GPIO4A
USB_EN#/PSDAT1/GPIO4B
CAP_INT#/PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

KB_LED <45>
EC_BEEP# <43>
FANPWM <5>
ACOFF
<50>

SPI Device I/F

11
24
35
94
113

<39,42> USB_CHG_EN#

IREF
CHGVADJ

PS2 Interface

SM Bus

<33>

68
70
71
72

DA Output

PM_SLP_S3#
SLP_S5#
EC_SMI#
USB_CHG_EN#_R
ESB_CK
ESB_DAT
PCH_SUSPWRDN
INVT_PWM
FAN_SPEED1
SM_SENSE#
E51_TXD
E51_RXD
ON/OFFBTN#
PWR_SUSP_LED#
NUM_LED#

<30> PM_SLP_S3#

R1442
0_0402_5%
1
2USB_CHG_EN#_R

DAC_BRIG/DA0/GPO3C
EN_DFAN1/DA1/GPO3D
IREF/DA2/GPO3E
DA3/GPO3F

EC_SMB_CK1/SCL0/GPIO44
EC_SMB_DA1/SDA0/GPIO45
EC_SMB_CK2/SCL1/GPIO46
EC_SMB_DA2/SDA1/GPIO47

RP7

1
2
3
4

+3VL

BATT_TEMPA
TMPTU1_SXP
ADP_I
ADP_V
TMPTU2_SXP
HDPACT

77
78
79
80

KSO[0..17]

<45,46> KSO[0..17]

63
64
65
66
75
76

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

KSO2

KSI[0..7]

<45,46> KSI[0..7]

BATT_TEMP/AD0/GPI38
BATT_OVP/AD1/GPI39
ADP_I/AD2/GPI3A
AD3/GPI3B
AD Input
AD4/GPI42
AD5/GPI43

LPC & MISC

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

to avoid EC entry ENE test mode

KB_LED
EC_BEEP#
FANPWM
ACOFF

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

KSO1

2
47K_0402_5%
2
47K_0402_5%

21
23
26
27

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

+3VL

1 @
R380
1 @
R382

PWM0/GPIO0F
BEEP#/PWM1/GPIO10
FANPWM0/GPIO12
ACOFF/FANPWM1/GPIO13

PWM Output

AGND

69

C443
22P_0402_50V8J
@

H_PROCHOT#_EC

BATT_TEMPA
<33> GATEA20
<33> KB_RST#
<28,45> SERIRQ
<28,45> LPC_FRAME#
<28,45> LPC_AD3
<28,45> LPC_AD2
<28,45> LPC_AD1
<28,45> LPC_AD0

VR_HOT#

0.1U_0402_16V4Z

VCC
VCC
VCC
VCC
VCC
VCC

CLK_PCI_EC

<55>

C442
1
2

C439

67

0.1U_0402_16V4Z

For EMI

0.1U_0402_16V4Z
1
2
C438

AVCC

C437

9
22
33
96
111
125

0.1U_0402_16V4Z
1
1

C436

+3VL

+3VL

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
1

44

of

59

Place the PAD under DDR DIMM.

LPC Debug Port

SPI Flash (256KB)

+3VS

H77

+3VL

PLT_RST# <5,32,39,40,41,42,44>

LPC_AD2 <28,44>

LPC_AD0 <28,44>

10

CLK_PCI_DDR

20mils

U22

VCC

HOLD

SPI_CS#

SPI_CLK

EC_SO_SPI_SI

<44> SPI_CS#
<44> SPI_CLK
<44> EC_SO_SPI_SI

VSS

1
R392

<28,44> SERIRQ

2
0_0402_5%

<28,44> LPC_AD3
<28,44> LPC_AD1
<28,44> LPC_FRAME#

EC_SI_SPI_SO

EC_SI_SPI_SO <44>

<32>

C451
0.1U_0402_16V4Z

W25X10BVSNIG_SO8

R393
22_0402_5%
@

DEBUG_PAD

SPI_CLK

1 R394
2
10_0402_5%

2
1
C454

2
10P_0402_50V8J

C457
22P_0402_50V8J
1 @

For EMI
For EMI

1
2
3
4
GND
GND

Q38 KBL@
AO3413_SOT23-3
D

+5VS_LED

RG2 @

1
3

<44>

2
G

KB_LED

KSO16
KSO17
KSO2
KSO1
KSO0
KSO4

KEYBOARD CONN.

KSO3
KSO5

KSI[0..7]
KSO[0..17]

KSI[0..7]

<44,46>

KSO14

KSO[0..17] <44,46>

KSO6
KSO7

JKB

34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ACES_88170-3400
@

JKB34
KSO16

1
2
R372 300_0402_5%

+3VS

KSO13
KSO8

KSO17
KSO9
KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
JKB4
2
1
CAPS_LED# R376 300_0402_5%
NUM_LED#

KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
+3VS
CAPS_LED# <44>
NUM_LED# <44>

+5VS
DG1
1

Close to JKB
Q52
2N7002_SOT23-3
KBL@

CAPS_LED#
NUM_LED#

1
C401
1
C402
1
C404
1
C405
1
C406
1
C407
1
C408
1
C409
1
C410
1
C411
1
C412
1
C413
1
C415
1
C416
1
C417
1
C418
1
C419
1
C420
1
C421
1
C422
1
C423
1
C424
1
C425
1
C427
1
C429
1
C431
1
C433
1
C435

SELF_TEST

+3VS_HDP

0_0603_5%

For EMI
D

+3VS

ACES_85201-0405N
@

C836
0.1U_0402_16V4Z
2 KBL@

2
12

Vdd1
Vdd2

+5VS_LED

R587
10K_0402_5%
KBL@

1
2
3
4
5
6

+3VS_HDP

2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J

CG12
1U_0402_6.3V6K
GSENSOR@

UG3

GSENSOR@
+3VS_HDP
+3VS_HDP
CH751H-40PT_SOD323-2
2
2
GSENSOR@
CG13
1U_0402_6.3V6K
VOUT 5
1 GSENSOR@

VIN

GND

SHDN#

BP

G9191-330T1U_SOT23-5

CG14
2
1

4
6
8

ST
PD
FS

Rev

GSENSOR@

Voutx
Vouty
Voutz

3
5
7

NC1
NC2
NC3
NC4
NC5

10
11
14
15
16

GND1
GND2

1
13

VOUTXCG1
VOUTYCG2
VOUTZCG3

GSENSOR@
0.033U_0402_16V7K
1
2
0.033U_0402_16V7K
1
2
0.033U_0402_16V7K
1
2GSENSOR@
GSENSOR@

Reserve for 2nd Source


+3VS_HDP
CG9 0.1U_0402_16V4Z UG4
@
2
1VOUTX
2
CG10 0.1U_0402_16V4Z XOUT
@
2
1VOUTY
3
CG11
0.1U_0402_16V4Z YOUT
@
2
1VOUTZ4 ZOUT

TSH352TR LGA 16P

Place UG1 and UG4


on TOP Layer

9
+3VS_HDP

@
0.22U_0402_10V4Z

SELF_TEST

7
10
13

VDD
NC
NC
NC
NC
NC

1
8
11
12
14

VSS

0G-DET
SLEEP#
G-SELECT
ST

MMA7360LR2_LGA14

UG5

<14,29,44,46> EC_SMB_CK2

P1_6/CLK0/SSI01

11

P1_5/RXD0/CNTR01/INT11#

12

P1_4/TXD0

13

P1_3/KI3#/AN11/TZOUT

14

P3_5/SSCK/SCL/CMP1_2

HDPACT

<44>

+5VS

UG1

G-Sensor

JBLG

SELF_TEST

+3VS_HDP

P3_7/CNTR0#/SSO/TXD1

RG3 2
GSENSOR@

1
4.7K_0402_5%

RESET#

RG4 2
GSENSOR@

1GXOUT
4.7K_0402_5%

XOUT/P4_7

5
RG5 2
GSENSOR@

<44>

HDPINT

HDPINT

1GXIN
4.7K_0402_5%

RG6

2
1 4.7K_0402_5%
GSENSOR@

RG7

2
1 1K_0402_5%
GSENSOR@
1
CG7
0.1U_0402_16V4Z
GSENSOR@ 2

VSS/AVSS
XIN/P4_6

15

P4_2/VREF

16
VOUTX
VOUTY

VCC/AVCC

P1_1/KI1#/AN9/CMP0_1

17

MODE

P1_0/KI0#/AN8/CMP0_0

18

P4_5/INT0#/RXD1

P3_3/TCIN/INT3#/SSI00/CMP1_0

19

P3_4/SCS#/SDA/CMP1_1

20

10

1
P1_7/CNTR00/INT10#
CG8
GSENSOR@
0.1U_0402_16V4Z
R5F211B4D34SP
2

2011/01/31

Deciphered Date

HDPLOCK <44>
VOUTZ

P1_2/KI2#/AN10/CMP0_2

RG10 47K_0402_5%
2
1
GSENSOR@
+3VS_HDP

CG6
0.1U_0402_16V4Z
GSENSOR@

EC_SMB_DA2 <14,29,44,46>

GSENSOR@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

RG9
47K_0402_5%
GSENSOR@

Keyboard LED

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet

45

of

59

+3VL

Caps Sensor/Light Sensor Conn.

Touchpad & Light Pipe Connector

Power Button

JCS
51_ON#
ON/OFFBTN#

C458
0.1U_0402_25V6
@

<44> ESB_DAT
<44> ESB_CK
<44> CAP_INT#
<44> CAP_RST#

Q7A
2N7002DW-T/R7_SOT363-6
<44>

EC_ON

SW3
1

<44>

<14,29,44,45> EC_SMB_CK2
<14,29,44,45> EC_SMB_DA2

ON/OFFBTN#

TOP side

+5VALW
+3VL
FBMA-11-100505-301T_0402 +3VS
L13 1
2
L14 1
2
FBMA-11-100505-301T_0402

<48>

100K_0402_5%

R396
10K_0402_5%

1
2
3
ESB_DAZ
4
ESB_CKZ
5
CAP_INT#
6
CAP_RST# 7
8
9
10
11
12

For EMI request

<44>
<44>

1
2
3
4
5
6
7
8
9
10
11
12

+5VS
TP_CLK
TP_DATA

<44,45>
<44,45>

TP_LED#
KSI6
KSO0

KSI6
KSO0

Q208B

P-TWO_161021-10021

JTPL

1
2
3
4
5
6
7
8
9
10
GND
GND

BTM side

R395

For debug

<44>

P-TWO_161021-10021

TP_LED

2N7002DW-T/R7_SOT363-6

6
5

SMT1-05-A_4P

1
2
3
4
5
6
7
8
9
10
GND
GND

JPOWER @
G2 6
G1 5
4 4
3 3
2 2
1 1

For EMI
@
1

PWR_ON_LED#
ON/OFFBTN#

1
R22

2
390_0402_5%

ESB_DAZ

+5VALW

D83
ACES_85201-0405N

ON/OFFBTN#

PWR_ON_LED#

ESB_CKZ
1

R428
2

C260 @
2

100_0402_5%

100P_0402_50V8J

@
1

R427
2

100_0402_5%

C261 @
2

100P_0402_50V8J

PJSOT24C_SOT23-3

Screw Hole

+5VALW

+5VS

+5VS

B+

+3VS

H5
H_4P2
@

H6

H7

H_2P9
@

H_2P9
@

H_2P9x3P4
@

+5VS

H4
H_4P2x4P7
@

H3
H_4P2x4P7
@

VGA

H2
H_4P9
@

2
G

H1

DC_IN

CPU

<13,30,44,50>

ACIN
Q32

DC-IN LED

ESD solution

2N7002_SOT23-3

C496
0.1U_0402_25V6
@

C499
0.1U_0402_25V6
@

MINI CARD -- TV
H10

Near H22

H_1P2
@

Near H14

HDD LED

H_1P2
@

H_1P2
@

H8
H_1P2
@

H9
H_3P3
@

H30
H_3P3
@

H31
H_3P1x3P6N
@

H_3P1N
@

+5VALW

B+

B+

+5VS

C527
0.1U_0402_25V6
@

C484
0.1U_0402_25V6
@

H14

H15
H_3P0
@

H23

H24
H_3P0
@

Near H17

H17
H_3P0
@

H18
H_3P0
@

H25
H_3P0
@

H19
H_3P0
@

H20
H_3P0
@

H21
H_3P0
@

H22
H_3P0
@

H_3P0
@

H27
H_3P0
@

Near H9

Near H6

Near H25

H16
H_3P0
@

C517
0.1U_0402_25V6
@

C509
0.1U_0402_25V6
@

C521
0.1U_0402_25V6
@

H_7P5
@
1

2N7002DW-T/R7_SOT363-6
@
1
2
R50
0_0402_5%

C520
0.1U_0402_25V6
@

Q9A
2N7002DW-T/R7_SOT363-6
4

Q9B

+3VS

+3VS
1

2 R404
1
10K_0402_5%

HDD_LED#

H13

SATA_LED# <28>

+5VS

MINI CARD -- WLAN

H12

Near H18

Near H19

H11

C495
0.1U_0402_25V6
@

C483
0.1U_0402_25V6
@

C482
0.1U_0402_25V6
@

C479
0.1U_0402_25V6
@

EMI solution

WIMAX_LED_GND#

B+

PCB Fedical Mark PAD

B+

FD1

Q156A
2N7002DW-T/R7_SOT363-6
WIMAX@

C522
0.1U_0402_25V6

C523
0.1U_0402_25V6

C524
0.1U_0402_25V6

C525
0.1U_0402_25V6

@
C526
0.1U_0402_25V6

UV1

<33> WL_BT_LED#
<44> PWR_ON_LED#
<44> PWR_SUSP_LED#
A

<41> CR_LEDCON#
<44> BATT_FULL_LED#
<44> BATT_CHG_LOW_LED#

N12PGSR1@

1
2
3
4
5
6
7
8
9
10
11
12

UV1

N12PGVR1@

U2

N12P-GV-A1

PCH

U2
JLOGO
<44>
<33>

<44>
GND
GND

13
14

ACES_85201-1205N

+5VL
CIR_IN
+5VS
LOGO_LED
+3VALW
+3VL
LID_SW#

CIR_IN

1
2
3
4
5
6
7
8
9
10
11
12

UV1

1
2
3
4
5
6
7
8
9
10
GND
GND

N12PGSR3@

U2

Q65R3@

UV1

ZZZ

N12PGVR3@

PCB LA-7211P

N12P-GV1-A1_BGA_973P
U2

Q67R3@

PJP1

45@
A

P-TWO_161021-10021

Issued Date

PCH

2012/12/31

Deciphered Date

Title

Date:

PJP1

Compal Electronics, Inc.

Compal Secret Data


2011/01/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

PCH
Q67R1@

PCH
N12P-GS-A1

Security Classification

Q65R1@

LOGO/B Connector
N12P-GS-A1

JLED
1
2
3
4
5
6
7
8
9
10
11
12

FD4

ISPD

LED/B Connector

WIMAX_LED_GND#
WL_BT_LED#
DC_IN
PWR_ON_LED#
PWR_SUSP_LED#
HDD_LED#
CR_LEDCON#
BATT_FULL_LED#
BATT_CHG_LOW_LED#

FD3

Q156B 2N7002DW-T/R7_SOT363-6
WIMAX@

+5VALW
+5VS

FD2

B+

B+

R819
2
1
10K_0402_5%
WIMAX@

+5VS

B+

LED_WIMAX# <39>

R506
WIMAX_LED_GND# 1
2
0_0402_5%

WiMAX LED

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
1

46

of

59

+3VALW

+3VS

+5VALW TO +5VS

+1.5V to +1.5VS

Vgs=10V,Id=9A,Rds=18.5mohm

+5VALW

Vgs=10V,Id=9A,Rds=18.5mohm

+1.8VS

+1.5V

+5VS

+1.5VS

3 1

Q12A
@
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6

1
S

Q12B
@

Q190
SUSP
2
G
2N7002_SOT23-3

+3VALW

+5VALW

+0.75VS

+1.05VS_VCCP

For S3 CPU Power Saving


R425
100K_0402_5%

R422
100K_0402_5%

R421
22_0805_5%

R468
470_0805_5%

Q44A
2N7002DW-T/R7_SOT363-6

SUSP

<5,9,39,54> SUSP

Q44B
2N7002DW-T/R7_SOT363-6

0.75VR_EN

2
100K_0402_5%

1
R158

<53,54> VCCPPWRGD

0.75VR_EN# <54>

Q6A

Q189
SUSP
2
G
2N7002_SOT23-3

<44,52,54,56> SUSP#

S
2N7002DW-T/R7_SOT363-6

Q13B
2N7002DW-T/R7_SOT363-6
DIS@

6
R414
820K_0402_5%

C469

1
C470

R408

2
2

1 R411
2
+VSB
220K_0402_5%

470_0805_5%

2
1U_0402_6.3V6K

FDS6676AS_SO8

R470
470_0805_5%

C464

C821
4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Q11B

0.1U_0402_25V6

470_0805_5%

2
6

3 1

Q11A
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6

C822

R430
Q13A
820K_0402_5%
DIS@
DIS@
2 VGA_PWROK#
2N7002DW-T/R7_SOT363-6

R413
200K_0402_5%
@

+VSB

C463

1
2
3
4

S
S
S
G

2
G

Q60
2N7002_SOT23-3

C481
DIS@

C473
DIS@

0.1U_0402_25V6

4.7U_0805_10V4Z

FDS6676AS_SO8

R429
DIS@

DIS@
1 R431
2
+VSB
220K_0402_5%

C468

R407

D
D
D
D

1U_0402_6.3V6K

1 R410
2
47K_0402_5%

C475
4.7U_0805_10V4Z
DIS@

8
7
6
5

SUSP

2
1

S
S
S
G

3 1

D
D
D
D

C478
DIS@

1
2
3
4

C467

Q31 @

For EMI

DIS@

470_0805_5%

Vgs=10V,Id=14.5A,Rds=6mohm
Q43

Q43
C473
FDS6676AS_SO8
4.7U_0805_10V4Z
OPT@
OPT@
C481
C478
0.1U_0402_25V6
1U_0402_6.3V6K
OPT@
OPT@
R430
C475
820K_0402_5%
4.7U_0805_10V4Z
OPT@
OPT@
R431
R146
220K_0402_5%
100K_0402_5%
OPT@
OPT@
R429
Q188
470_0805_5%
2N7002_SOT23-3
OPT@
OPT@
Q13
2N7002DW-T/R7_SOT363-6
OPT@

+VRAM_1.5VS

8
7
6
5

Vgs=10V,Id=14.5A,Rds=6mohm

Q10B

+1.5V to +VRAM_1.5VS
+1.5V

1U_0402_6.3V6K

SI4800BDY_SO8

Q10A
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6

1
2
3
4

R412
330K_0402_5%

+VSB

3 1

C466

C461

S
S
S
G

R406

D
D
D
D

1 R409
2
47K_0402_5%

8
7
6
5

0.01U_0402_25V7K

0.022U_0402_25V7K

4.7U_0805_10V4Z

C465

Q30

1U_0402_6.3V6K

SI4800BDY_SO8

1
4.7U_0805_10V4Z

4.7U_0805_10V4Z

C460

1
2
3
4

S
S
S
G

C459

D
D
D
D

470_0805_5%

Q29

8
7
6
5

+5VS

4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C462

+3VALW TO +3VS

+5VALW

+5VS_ODD
+3VS

+5VS TO +5VS_ODD

+3VALW

ODD_EN#
3

2N7002DW-T/R7_SOT363-6

+5VS
+5VS

Q45
2

2
2

5
2N7002DW-T/R7_SOT363-6
OPT@
Q206B
2N7002DW-T/R7_SOT363-6
OPT@

C686
1U_0402_6.3V6K
OPT@

C679
4.7U_0805_10V4Z
@

DGPU_PWR_EN#

2
G

Issued Date

Compal Electronics, Inc.

Compal Secret Data


2011/01/31

Deciphered Date

2012/12/31

Title

Date:

C680
1U_0402_6.3V6K

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

2
2

Q55
2N7002_SOT23-3
OPT@

Security Classification

1
1

R459
470_0805_5%
OPT@

3 1

Q207B

AO3413_SOT23
C217
0.01U_0402_25V7K

PJ28
JUMP_43X79
@
+5VS_ODD

1
3

R458
470_0805_5%
OPT@

Q207A

DGPU_PWR_EN#
2
2N7002DW-T/R7_SOT363-6
OPT@

R440

Vgs=-4.5V,Id=3A,Rds<97mohm

3
2N7002_SOT23-3
Q51

+VGA_CORE

+3VS_DGPU

C685
4.7U_0603_6.3V6K
@

R460
470_0805_5%
OPT@

2
+1.05VS_DGPU

C493
OPT@

0.1U_0402_25V6

S
AO3416_SOT23-3
OPT@

2
G

2
1

Q56

ODD_EN#

47K_0402_5%

<33>

PJ33
JUMP_43X118
@

+1.05VS_DGPU
R434
220K_0402_5%
OPT@

Vgs=4.5V,Id=3A,Rds<22mohm

C471
0.1U_0402_16V7K

2
R441
10K_0402_5%

C684
1U_0402_6.3V6K
2 OPT@

+3VS

1
C683
4.7U_0805_10V4Z
@

2
+3VS_DGPU

Q206A
OPT@
OPT@
1
2
2N7002DW-T/R7_SOT363-6

AO3413_SOT23
OPT@
C492
0.01U_0402_25V7K

47K_0402_5%
OPT@

Q53A
R104
0_0805_5%
DIS@

+5VALW

+1.05VS_VCCP

Q54
2

Vgs=-4.5V,Id=3A,Rds<97mohm

1
6
<13,32,56> DGPU_PWR_EN

Short PJ33 for Discrete SKUs

R426

C491
0.1U_0402_16V7K
OPT@
G

DGPU_PWR_EN#

+1.05VS_VCCP to +1.05VS_DGPU
3

R433
100K_0402_5%
OPT@

6 1

R457
470_0805_5%

+3VS to +3VS_DGPU

100K_0402_5%
Q188
2N7002_SOT23-3
DIS@

2
G

<13,32,33,56> VGA_PWROK

R146
1 DIS@ 2

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Sheet

Monday, February 28, 2011


E

47

of

59

VIN
@ PJP1

VIN

@ PR1
1K_1206_5%

@PD1

PC4
100P_0402_50V8J

PC14
1000P_0402_50V7K

1
2

PC3
1000P_0402_50V7K

SINGA_2DW-0005-B03

PC2
100P_0402_50V8J

DC_IN_S2

2
10A_125V_451010MRL

DC_IN_S1 1

PC13
1000P_0402_50V7K

PC1
1000P_0402_50V7K

PL1
SMB3025500YA_2P
1
2

PF1

N3

B+

PR2
@
1K_1206_5%

RLS4148_LL34-2

2
@PR3

1K_1206_5%

@PR38
511K_0402_1%
2
2

2
2

VS

PC6

N1
2
8

22K_0402_1%
@PU2A
@
PU2A

@
2

+3VALWP
@ PJ333
+3VLP

PJ332
1 1

+1.5VP

(5A,200mils ,Via NO.= 10)


OCP=7.7A

+3VL

JUMP_43X39

@ PJ153
1 1

Precharge detector
Min.
typ.
Max.
H-->L 14.42V 14.74V 15.23V
L-->H 15.39V 15.88V 16.39V

+1.5V

JUMP_43X118

RTC Battery

(15A, 600mils ,Via NO.= 30)


OCP=18.74A

(100mA,40mils ,Via NO.= 2)

DTC115EUA_SC70-3

ACIN

@ PJ152
1 1

+5VALWP

@PQ2
@
PQ2

JUMP_43X118
+3VALW

JUMP_43X118
1

LM393DG_SO8

2
+

<50>

51_ON#

PACIN

S
PC5
0.1U_0603_25V7K

PR11
<46>

2
G

0.22U_0603_25V7K

@PR39
@
PR39
47K_0402_1%
2
1

D
@ PQ1
SSM3K7002FU_SC70-3

PR10
100K_0402_1%

@ PC17
1000P_0402_50V7K

@PC18
@
PC18
1000P_0402_50V7K

@ PR7
@PR7
66.5K_0402_1%

@PR35
@
PR35
255K_0402_1%
@ PR36
150K_0402_1%

N1

RLS4148_LL34-2

<50>

1
2

BATT+

PR9
68_1206_5%
2

PD4
2

1
PR8
68_1206_5%

PQ4

TP0610K-T1-E3_SOT23-3

@ PC16
1000P_0402_50V7K

@PR6
@PR6
34K_0402_1%

LM393DG_SO8

ACON

6251VREF

<50>

@PU2B
@
PU2B

EN0

RLS4148_LL34-2

<51>

PD3

@ PD2
RB715F_SOT323-3
2
1
3

N1

VIN

VL

@PR5
2.2M_0402_5%
2
1

@ PR4
100K_0402_1%
1
2

@ PJ352
@ PJ353

VL

+5VALWP

+5VL

+5VALW
2

(5A,200mils ,Via NO.= 10)


OCP=7.9A

+VSB

PBJ1
2

+
1

PR13
PR17
560_0603_5% 560_0603_5%
1
2 1
2 +RTCBATT

+RTCBATT

+0.75VS

JUMP_43X79
+VCCSAP

@ PJ452
2
1 1

+GFX_COREP

SP093MX0000

@ PJ502
1 1

@ PJ503
1 1

+GFX_CORE
4

(33A,1320mils ,Via NO.=66)


OCP=40A

@ PJ602
2

@ MAXEL_ML1220T10

+1.05VS_VCCP

JUMP_43X118

JUMP_43X118

+VCCSA

JUMP_43X118

(6A,240mils ,Via NO.= 12)


OCP=7.69A

(17A,680mils ,Via NO.=34)


OCP=19.25A

JUMP_43X118

(1A,40mils ,Via NO.= 2)

JUMP_43X118

+1.8VS

(1.65A,70mils ,Via NO.= 4)


OCP=4.2A

@ PJ76
2

+1.05VS_VCCPP

@ PJ182
2

+1.8VSP

(120mA,40mils ,Via NO.= 1)

@ PJ403

JUMP_43X39

+0.75VSP

JUMP_43X118

@ PJ72
+VSBP

@ PJ402

JUMP_43X118

JUMP_43X39

JUMP_43X118
@ PJ603
+VGA_COREP

+VGA_CORE

Issued Date

(27A,1080mils ,Via NO.=54)


OCP=28.15A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

JUMP_43X118

2011/01/31

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011
D

Sheet

48

of

59

VMB

@ PJP2
1

PH1 under CPU botten side :


CPU thermal protection at 95 degree C
Recovery at 56 degree C

BATT+

SUYIN_200045MR009G171ZR

PC8
0.01U_0402_25V7K

PC7
1000P_0402_50V7K

@ PC15
.1U_0402_16V7K

PR14
1K_0402_1%

BATT_P4
BATT_P5
EC_SMDA
EC_SMCA

15A_65V_451015MRL

1
PR15
19.6K_0402_1%

+3VLP

VCC TMSNS1

GND RHYST1

OT1 TMSNS2

OT2 RHYST2

<44,50>

PR22
3.48K_0402_1%

+3VS

1
2
GSO2@PR28
10K_0402_1%

G718TM1U_SOT23-8
1

EC_SMB_DA1 <27,44>

2
G
S

PQ219
2N7002W-T/R7_SOT323-3

EC_SMB_CK1 <27,44>

GSO2@PR27
120K_0402_1%

PR29
100K_0402_1%

<5,44> H_PROCHOT#

<44,51> VS_ON

BATT_TEMPA <44>

PR21
100_0402_1%
1

PR20
100_0402_1%

PR18
8.66K_0402_1%
ADP_I

PU1

PR19
1K_0402_1%

PH1
100K_0402_1%_NCP15WF104F03RC

PC9
0.1U_0603_25V7K

PR16
6.49K_0402_1%
2
1

VL

1
1

PD6
PJSOT24C_SOT23-3
PD5
2
PJSOT24C_SOT23-3
3

GND
GND
GND
GND

BATT_S1

1
2
3
4
5
6
7
8
9

10
11
12
13

PL2
SMB3025500YA_2P
1
2

PF2
1
2
3
4
5
6
7
8
9

D
PQ7
SSM3K7002FU_SC70-3

GSO2@PR30
11K_0402_1%

2
G

B+

+VSBP

PC11 @
0.1U_0603_25V7K

GS2@ PR30
Value = 11K_0402_1%

1
1

POK

CPSETIN <44,50>

PQ220
2N7002W-T/R7_SOT323-3

GVO9@ PR30
Value = 14.7K_0402_1%

22K_0402_1%

PR26
<30,51>

2
G
S

1
2

PC10
0.22U_0603_25V7K

2
1
PR23
100K_0402_1%

PR24
1

PR25
100K_0402_1%

@ PC19
.1U_0402_16V7K

VL

PR31
100K_0402_1%

VL

PQ5
TP0610K-T1-E3_SOT23-3

GS2@ PR27
GVO9@ PR27
Value = 120K_0402_1% Value = 15.8K_0402_1%

@ PC12
.1U_0402_16V7K

GVO9@ PR28
Value = 20K_0402_1%

PQ6
SSM3K7002FU_SC70-3
3

0_0402_5%

GS2@ PR28
Value = 10K_0402_1%

2
G

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011
D

Sheet

49

of

59

ICOMP

CSIN

20

VCOMP

CSIP

19

PR2312
1 20_0402_5%
PC220
0.1U_0603_25V7K
1
2
PR232
2_0402_5%

LX_CHG
DH_CHG

VREF

UGATE

17

4
5
6
7
8

3
2
1

PL202
10UH_MSCDRI-104A-100M-E_4.6A_20%
CHG
1
2
1

BST_CHG 1
2
0_0603_5%

10

ACLIM

VDDP

15

6251VDDP

11

VADJ

LGATE

14

DL_CHG

12

GND

PGND

13

0.1U_0603_25V7K
PD202
RB751V-40_SOD323-2
1
2 6251VDD

PR233
PC221
4.7U_0603_6.3V6M

PC206
680P_0603_50V7K

4.7_0603_5%

ISL6251AHAZ-T_QSOP24

PR224
1

15.4K_0402_1%

PR225
31.6K_0402_1%

6251VDD

VIN

CC=0.25A~3A

CHGVADJ=(Vcell-4)*9.445

PR242
10K_0402_1%

1
ACIN

GS2@ PR223
26.7K_0402_1%

<13,30,44,46>
PR246
309K_0402_1%

PACIN

0V
1.882V

4.35V

3.2935V

ACPRN

ADP_V

<44>

PC223

PR248

PR243
14.3K_0402_1%

.1U_0402_16V7K

47K_0402_1%
2

4.2V

4V

PR247
10K_0402_1%
1
2

PQ214
DTC115EUA_SC70-3

CHGVADJ

Vcell

PR241
10K_0402_1%
1
2

GS2@ PR234
4.12K_0402_1%

PR240
47K_0402_1%
2

GS2@ PR222
8.25K_0402_1%

VCHLIM need over 95mV

GVO9@ PR223
33K_0402_1%

GVO9@ PR234
10.7K_0402_1%

GVO9@
10K_0402_1%

PR222

IREF=0.254V~3.048V

IREF=1.016*Icharge

3
0.02_1206_1%

16

BATT+
4

BOOT

CHLIM

PR235

2
PR206
4.7_1206_5%

PC205
BST_CHGA 2
1

6251aclim

PQ202
AO4466L_SO8
PR205

2
G
PQ216
SSM3K7002FU_SC70-3

PC203
10U_1206_25V6M
2
1

PACIN

PQ201
AO4466L_SO8

5
6
7
8

PHASE

8.25K_0402_1%

<44> CHGVADJ
3

PQ218
2N7002W-T/R7_SOT323-3

ICM

18

CSOP

PC204
10U_1206_25V6M
2
1

21

CSOP

CSON

CELLS

6251VREF

GSO2@PR222
6251VREF
1
2

2
G

<44,49> CPSETIN
3

PR229 20_0402_5%
1
2
PC219
0.047U_0402_16V7K
1
2
PR230
20_0402_5%

3
2
1

PR221
120K_0402_1%

1
PC216

ACOFF

<44>

PQ213
DTC115EUA_SC70-3
ACOFF
2

6251VREF

CSON

IREF

<48>

1 1

EN

<44>

PR220
154K_0402_1%
2
1

23
22

PC222
0.1U_0402_25V6

ACON

ACSET ACPRN

6
PR219
1
2
100_0402_1%

PC215
.1U_0402_16V7K
1
2

<48>

ADP_I

10K_0402_1%

GSO2@ PR223
26.7K_0402_1%
2
1

PACIN

<44,49>

0.01U_0402_25V7K

<48>

0.01U_0402_25V7K

1SS355_SOD323-2

6800P_0402_25V7K

PR218

VIN

0.1U_0603_25V7K
ACPRN

5
G
PR211
47K_0402_1%
1
2

PC214
1
2

GSO2@ PR234
4.12K_0402_1%
2
1

PQ212B
DMN66D0LDW-7_SOT363-6

DCIN 2

PC202
10U_1206_25V6M
2
1

24

PR238
200K_0402_1%
2
1

DCIN

PC213
1
2

PQ212A
DMN66D0LDW-7_SOT363-6

2
G

1 1
VDD

ACOFF

PD10

PQ215
DTC115EUA_SC70-3

PC218

6251_EN

PR228
14.3K_0402_1%

VIN

PD9
1

1SS355_SOD323-2

1.26V

100K_0402_1%

PR237
10K_0402_1%

ACSETIN

PC217
1000P_0402_25V8J
2
1

PU200

6251VDD

PR227
10_1206_5%

PR217

PR213
150K_0402_1%

PQ211
DTC115EUA_SC70-3

PD201
RB751V-40_SOD323-2

FSTCHG

PR226
191K_0402_1%

PR216
10K_0402_1%
2
1

1
BATT_ON

PC212
2.2U_0603_6.3V6K

ACSETIN

<44>

LDO 5.075V

1
PR212
200K_0402_1%

PR236
1
2
47K_0402_1%

2
1
2
3

PC210
0.1U_0603_25V7K
2
1

PQ210
DTA144EUA_SC70-3

CSIP

VIN

1
PR210
200K_0402_1%

AO4407A_SO8
8
7
6
5

1
2
3

CSIN

PC211
5600P_0402_25V7K

PQ209

CHG_B+

PL201
1UH_PH041H-1R0MS_3.8A_20%
1
2

PC233
4.7U_0805_25V6-K
2
1

AO4407A_SO8
8
7
6
5

B+

GSO2@ PR215
0.015_2512_1%
1
4

8
7
6
5

PQ208
1
2
3

PC224
0.1U_0402_25V6

PC232
4.7U_0805_25V6-K
2
1

1
2
3

P3

PQ204
AO4409L_SO8

1
2
3

PC231
4.7U_0805_25V6-K
2
1

P2

PQ203
AO4407A_SO8
8
7
6
5

VIN

@
GS2@ PR215
GVO9@ PR215
Value = 0.015_2512_1% Value = 0.02_2512_1%

PC209
4.7U_0805_25V6-K
2
1

PC208
10U_1206_25V6M
2
1

PC207
10U_1206_25V6M
2
1

Vin Detector

CP mode
4

High 18.089V
Low 17.44V

Iada=0~3.42A(65W) CP= 92%*Iada; CP=3.147A


Vaclim=0.6621V(65W) PR222=75k, PR223=20k, PR215=0.02
Iada=0~3.947A(75W)

CP= 92%*Iada; CP=3.63A

Vaclim=1.1V(75W)

PR222=24k, PR223=20k, PR215=0.02

Iada=0~4.737A(90W)

CP= 92%*Iada; CP=4.36A

Vaclim=0.737V(90W)

PR222=53.6k, PR223=20k, PR215=0.015

1.26 / 14.3 * 205.3 = 18.089V

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Iada=0~6.316A(120W) CP= 92%*Iada; CP=5.81A

2011/01/31

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Vaclim=1.777V(120W) PR222=8.25k, PR223=26.7k, PR215=0.015

Date:

SCHEMATIC, MB A7211
Rev
B

4019BD

Monday, February 28, 2011


D

Sheet

50

of

59

2VREF_8205

PC363
1U_0603_10V6K

PR357
150K_0402_1%
1
2

PC366
10U_1206_25V6M

5
G

5
6
7
8

1
DRVL1

19

LG_5V

PL352
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
1
2

1 2

TPS51125ARGER_QFN24_4X4

330U_6.3V_M
PC356 @
15mohm
680P_0603_50V7K

3
2
1

VL
1

PR361

AO4712L_SO8

1
PC352

PQ352

+5VALWP

PR356 @
4.7_1206_5%

VCLK
18

17

16

EN0

AO4466L_SO8

DRVL2

3
2
1

12

PC355
2 0.1U_0603_25V7K

5
6
7
8

LG_3V

PC364
4.7U_0805_10V6K

RT8205_B+

Ipeak=5A
Imax=3.5A
F=245KHz
Total Capacitor 220uF
ESR 15mohm

PC365
0.1U_0603_25V7K

2VREF_8205
2

ENTRIP1

LX_5V

PQ360B
DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

20

1
2
3

21

LL1

ENTRIP2

D
PQ360A

VFB1

DRVH1

LL2

AO4712L_SO8

ENTRIP1

VREF

DRVH2

11

VREG5

10

LX_3V

VIN

UG_3V

PR355
BST_5V 1
2
0_0603_5%
UG_5V

EN0

PC362
1U_0402_6.3V6K

22

GND

23

VBST1

<30,49>

B+

Ipeak=5A
Imax=3.5A
F=305KHz
Total Capacitor 220uF
ESR 15mohm

VFB2

PGOOD

VBST2

13

@ PC336
680P_0603_50V7K

POK

15mohm

330U_6.3V_M

24

VREG3

PR360
499K_0402_1%
1
2

4
VO1

PC225
0.1U_0402_16V7K

<48>

100K_0402_5%

1 2

1
PC332

PQ351

BST_3V

PQ332
@ PR336
4.7_1206_5%

2
VO2

SKIPSEL

8
7
6
5

PL332
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
1
2

+3VALWP

15

PR335
1
2
0_0603_5%

P PAD

TONSEL

25

ENTRIP2

PU330

14

1
2
3

PC335
0.1U_0603_25V7K
1

PC361

4.7U_0805_10V6K

8
7
6
5
PQ331
AO4466L_SO8

RT8205_B+

1U_0805_25V7

PR337
150K_0402_1%
1
2

PC360
10U_1206_25V6M

@PC367
@PC367

PR365
19.1K_0402_1%
1
2

+3VLP

B+

PR363
20K_0402_1%
1
2
ENTRIP1

PJ331
@ JUMP_43X118
2 2
1 1

PR364
30K_0402_1%
1
2

ENTRIP2

RT8205_B+

PR362
13K_0402_1%
1
2

PR370
2
1
100K_0402_1%

VL

<44,49>

VS_ON

PR371

PQ361
DTC115EUA_SC70-3

PC370
2
1

2.2U_0603_10V6K

PR372

2
42.2K_0402_1%

1
2
100K_0402_1%

VS

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet
1

51

of

59

PC163
4.7U_0805_25V6-K
2
1

5
PR164
255K_0402_1%
1
2
BST_1.5V

PR160
1

<42,44> SYSON

PQ151
4

PR155
1
2
0_0603_5%

PC164
4.7U_0805_25V6-K
2
1

PJ151
@ JUMP_43X118
2 2
1 1

B+

@ PC165
@PC165
680P_0402_50V7K
2

TPCA8065-H_PPAK56-8-5

14

DL_1.5V

4
2

PGND
8

AGND
7

DL

PQ603

PGOOD

+5VALW

G5603RU1U_TQFN14_3P5X3P5

PC162
4.7U_0805_10V6K

PR156
4.7_1206_5%

1
+ PC152
330U_6.3V_M

10

FB

6
2

PC161
4.7U_0603_6.3V6K

PR157
1
2
6.04K_0402_1%

2
1

VDD

VFB=0.75V

Ipeak=15A
Imax=10.5A
Rtrip=6.02K, OCP=18.42A
F=313KHz
Total Capacitor ??uF,
ESR ??mohm

PC156
680P_0603_50V7K
2

LX_1.5V

11

12

ILIM

TPCA8057-H_PPAK56-8-5

TP

BST
LX

VCC

100_0603_5%

OUT

+1.5VP

0.1U_0603_25V7K

3
2
1

DH_1.5V

13

TON

PL152
1.0UH_PCMC104T-1R0MN_20A_20%
1
2

PC155
1
2

BST_1.5V-1
DH

PR161

+5VALW

PU150

15

PC160 @
.1U_0402_16V7K

EN_SKIP

3
2
1

0_0402_5%

1G@ PR162
10K_0402_1%
2G@ PR162
2G@PR162
1
2
1

10.7K_0402_1%

PR163
10K_0402_1%

PU180
SY8033BDBC_DFN10_3X3

PC186

@ PR182
499K_0402_1%

0.1U_0402_10V7K

PR184
10K_0402_1%

1
2

FB_1.8V

PC185@

0_0402_5%

PR183
20K_0402_1%

PC183
22U_0805_6.3VAM

NC

NC
1

2 EN_1.8V

PR181

11

TP

2
<44,47,54,56> SUSP#

FB=0.6Volt

PR186

1
6

FB

EN

LX

PC182
22U_0805_6.3VAM

PC184
22U_0805_6.3VAM

Ipeak=1.308A
ILIM = 4A
F=1MHz
Total Capacitor ??uF,
ESR ??mohm

+1.8VSP
PC187
68P_0402_50V8J
2
1

SVIN

LX_1.8V

PVIN

LX

JUMP_43X39

PVIN

10

4.7_1206_5%

680P_0603_50V7K

PG

+5VALW

PL182
1UH_FMJ-0630T-1R0 HF_11A_20%
1
2

@ PJ181

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Deciphered Date

2012/12/31

Title

SCHEMATIC, MB A7211

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
B

4019BD

Monday, February 28, 2011


D

Sheet

52

of

59

<47,54> VCCPPWRGD

PC466
0.1U_0402_25V6
2
1

PC465
2200P_0402_50V7K
2
1

B+

PC467
1U_0805_25V7

Ipeak=6A
Imax=4.2A
Rtrip=14.3K, OCP=7.69A
F=315KHz
Total Capacitor ??u
ESR=??mohm

PR455
2
3
2
1

BST_VCCSAP1

PR460
1

2
1
2
255K_0402_1%

PC464
4.7U_0805_25V6-K

PC463
4.7U_0805_25V6-K

5
6
7
8
PR462

0_0603_5%

PJ451
@ JUMP_43X118
2 2
1 1

VCCSAP_B+

PQ451
AO4466L_SO8

10

PGOOD

SA_PGOOD

<44>

DL

PR457
1
2
14.3K_0402_1%

+5VALW
1

4.7_1206_5%

PC462
4.7U_0805_10V6K

+ PC452
330U_2.5V_M

G5603RU1U_TQFN14_3P5X3P5

PC456

DL_VCCSAP

11

VDD

ILIM

FB

PR456

5
6
7
8

BST

VCC

+VCCSAP

0.1U_0603_25V7K

15

14

OUT

1
2
10K_0402_1%

LX

LX_VCCSAP

680P_0603_50V7K

PR463
0_0402_5%

PQ452
AO4712L_SO8

+3VS

PC461
4.7U_0805_10V6K

DH_VCCSAP

12

PR471

13

PGND

FB

DH

AGND

+5VALW

TON

PL452
1.8U_D104C-919AS-1R8N_9.5A_30%
1
2

PC455
BST_VCCSAP-1

3
2
1

2
VOUT

PR461
100_0402_1%
1
2

TP

PU450

EN_SKIP

@ PC460
.1U_0402_16V7K

0_0402_5%

@ PR472
10K_0402_1%

VCCSA_SENSE

<9>

PR464
10_0402_5%
2
1

PR465
680_0402_1%

1
2

2
B
3

@ PR470
100K_0402_1%

2
G
S
PQ453
SSM3K7002FU_SC70-3

PR468
10K_0402_1%

PC470
.1U_0402_16V7K

PR469
10K_0402_1%
1
2

PR467
5.1K_0402_1%

+3VS
PR466
9.09K_0402_1%

PR473
0_0402_5%
1
2

VCCSAP_VID1

<9>

E
PQ454
MMST3904-7-F_SOT323-3

VID1

+VCCSAP

0.8V

0.9V

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Sheet

Monday, February 28, 2011


1

53

of

59

@ PJ75
JUMP_43X79

+1.5V

PU75

3
4

VCNTL

GND

NC

VREF

NC

VOUT

NC

TP

VIN

+3VALW
PC264

<5,9,39,47> SUSP

PR280
1K_0402_1%

@ PR282
0_0402_5%
1
2

2
1

PC261
4.7U_0805_6.3V6K

1U_0603_10V6K

PR281

+0.75VSP

PC263
.1U_0402_16V7K
2
1

1
2

PC260
.1U_0402_16V7K

2
G

1K_0402_1%

PQ260
SSM3K7002FU_SC70-3

PR279
0_0402_5%
1
2

<47> 0.75VR_EN#

G2992F1U_SO8

PC262
10U_0805_6.3V6M

For shortage changed

@ PJ401

G5603RU1U_TQFN14_3P5X3P5

PC415
4.7U_0805_25V6-K

PC414
4.7U_0805_25V6-K
2
1

PC413
4.7U_0805_25V6-K
2
1

B+

+1.05VS_VCCPP

1
2

1 2

PR420
0_0402_5%

DL_1.05VS_VCCP

3
2
1

PC412
4.7U_0805_10V6K

PQ402

JUMP_43X118

PR406
4.7_1206_5%
PC406
680P_0603_50V7K

7
2

DL

6.81K_0402_1%

3
2
1

PGOOD

TPCA8057-H_PPAK56-8-5

VDD

FB

VFB=0.75V

+5VALW

PL402
1UH_FDUE1040D-1R0M-P3_21.3A_20%

14

TP

BST

LX_1.05VS_VCCP
PR407
1
2

10

PR415

12
11

VCC

DH

LX
ILIM

OUT

<47,53> VCCPPWRGD

DH_1.05VS_VCCP

PC411
4.7U_0603_6.3V6K

13

TON

PR405
PC405
0_0603_5%
0.1U_0603_25V7K
1
2BST_1.05VS_VCCP-1
1
2

PGND

PR411
100_0603_1%
1
2

EN_SKIP

PU400

+5VALW

PC410
@
.1U_0402_16V7K

AGND

BST_1.05VS_VCCP

15

PR410
0_0402_5%
1
2

<44,47,52,56> SUSP#

PR414
255K_0402_1%
1
2

PQ401
TPCA8065-H_PPAK56-8-5

1.05VS_B+

+3VS

10K_0402_1%

PC402
390U_2.5V_M

Ipeak=17A
Imax=11.9A
Rtrip=6.81K, OCP=19.25A
F=315KHz
Total Capacitor ??uF,
ESR ??mohm

@ PR416
10K_0402_1%

PR421
10_0402_5%
2
1

VCCIO_SENSE <8>

PR412
4.02K_0402_1%
1
2

PR413
10K_0402_1%

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

SCHEMATIC, MB A7211

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
B

4019BD

Monday, February 28, 2011

Sheet
1

54

of

59

PWM3

30

PGOOD

LG1

29

IMON

VSSP1

28

LGATE2

VDDP

31

VDDP+

ISL95831CRZ-T_TQFN48_6X6

25

BOOT1

330P_0402_50V7K
2
1

PC546

1000P_0402_50V7K
2
1

<8> VCCSENSE
<8> VSSSENSE

PR557

PC227
10U_1206_25V6M
2
1

2
1
GFX@ PR575
590_0402_1%

GFX@ PC502
390U_2.5V_M
@ PC572
470P_0402_50V7K

GFX@ PR571
1_0402_5%

GFX@ PR570
10K_0402_1%

1
2

1
2
1
2

2.61K_0402_1%

1 2

GFX@PC506
GFX@PC506
GFX@ PR506
GFX@PR506
680P_0603_50V7K
4.7_1206_5%
PR536

3
2
1

TPCA8057-H_PPAK56-8-5

ISEN3

+CPU_CORE

QC@ PR586
2
1

QC@ PR587
2
1

10K_0402_1%

10K_0402_1%

VSUM+

QC@ PR585
2
1

QC@ PR589
2
1 ISEN2

3.65K_0402_1%
QC@ PR584
2
1

VSUM-

ISEN1

10K_0402_1%

1_0402_5%

PH503
10K_0402_1%_ERTJ0EG103FA
CPU_B+

11K_0402_1%

1
1
2

@PC552
@
PC552
@ PR555
330P_0402_50V7K 100_0402_1%
2
1
2
1

PC226
10U_1206_25V6M
2
1

GFX@ PC565
4.7U_0805_25V6-K
2
1

GFX@ PC564
4.7U_0805_25V6-K
2
1

GFX@ PQ501
GFX@ PQ502

1
PC545

PR554
1.24K_0402_1%
2
1

PC553
2
1

@ PC575
@ PR550
150P_0402_50V8J 316K_0402_1%
2
1
2
1

PC544 0.22U_0402_6.3V6K

PR556

470P_0402_50V7K

PR551
2
1
3.83K_0402_1%

PC562 0.22U_0402_6.3V6K
2
1

LGATE3

QC@ PQ512

@ PC577
0.022U_0402_16V7K

499_0402_1%

QC@ PC535
0.22U_0603_10V7K
BOOT3 2
1 2
1
QC@ PR535
0_0603_5%

PC549
0.22U_0603_25V7K

@ PC551
0.022U_0402_16V7K

PC543
PR549
150P_0402_50V8J
316K_0402_1%
2
1
2
1

QC@ PL505
0.36UH_PCMC104T-R36MN1R17_30A_20%

TPCA8065-H_PPAK56-8-5

VSUM+

330P_0402_50V7K

499K_0402_1%

PC547

3
2
1

+5VALW

QC@ PC567 0.22U_0402_6.3V6K


VSUM2
1

PC542

PR548

@ PR547

PC550
0.33U_0402_10V6K

2
PC541
33P_0402_50V8J

2
1

1_0603_5%

10P_0402_50V8J

1U_0603_10V6K

PC548
2
1

ISEN1

ISEN2

@ PC540
1

TPCA8057-H_PPAK56-8-5

2
1

QC@ PR560
0_0402_5%

PR558

+5VALW

CPU_B+

VSUM-

UGATE2

4
PQ505

PC580
4.7U_0805_25V6-K
2
1

VIN

0_0603_5%

For Turbo mode , PH502 must be


changed 470K (b value = 4700)

Connect to +5V can disable


GFX portion

PHASE3
PR560 1.69K_0402_1%
DC@

CPU_B+

1
2
DISEN@ PR576 0_0402_5%

+5VALW

QC@ PQ507

@ PC573
0.01U_0402_16V7K

PR562
0_0603_5%

UGATE3

PR559

ISEN3

1000P_0402_50V7K

PC539

PR546

1
PR545
27.4K_0402_1%

Connect to +5V can disable


PWM3

PU500

24

23

22

21

RTN

20

19

18

ISEN2

17

16

FB

PROG1

BOOT1

VDD

VW

ISUMP

UGATE1

12

ISUMN

PHASE1

26

VSEN

27

UG1
ISEN1

PH1

NTC

ISEN3/ FB2

VR_HOT#

DC@ PR561
0_0402_5%
1
2

LGATE1

11

3.83K_0402_1%

8.06K_0402_1%

10

470KB_0402_5%_ERTJ0EV474J
2

32

33

LG2

+GFX_COREP

ISNG

VR_ON

15

PH502

PR544

ISPG

COMP

LGATE3

PGND

QC@ PC586
4.7U_0805_25V6-K
2
1

SCLK

13

B+
@

GFX@ PH504 10K_0402_1%_ERTJ0EG103FA


1
2 1
2
1
2
GFX@ PR572
GFX@ PC570
7.5K_0402_1%
.1U_0402_16V7K
1
2
GFX@ PR573
11K_0402_1%
1
2
1
2
@ PR574
100_0402_1%
GFX@ PC571
.1U_0402_16V7K

680P_0603_50V7K 4.7_1206_5%

470P_0402_50V7K

LGATE

.1U_0402_16V7K

47P_0402_50V8J

PC537

1
2
@ PR543
499_0402_1%

PC538

VSSP2

VDD+

+1.05VS_VCCPP

GND

PL501
HCB4532KF-800T90_1812

PC582
4.7U_0805_25V6-K
2
1

SVID_SCLK

VR_HOT#

PHASE3

QC@ PC587
4.7U_0805_25V6-K
2
1

ALERT#

VGATE

UGATE3

PC536
2
1

SDA

14

PC561
0.033U_0603_16V7
2
1

PR542
19.1K_0402_1%
2
1

+3VS
<30,44>

SVID_ALERT#

1
2
1.91K_0402_1%

PHASE

PC581
4.7U_0805_25V6-K
2
1

34

UGATE

PWM

QC@ PC588
4.7U_0805_25V6-K
2
1

PH2

PR540

TPCA8065-H_PPAK56-8-5

5
UG2

PGOODG

0_0402_5%

FCCM

PC554
2.2U_0603_10V6K
2
1

IMONG

PHASE2

<8> VR_SVID_CLK

QC@ PR569
0_0603_5%
1
2

UGATE2

35

VWG

QC@ PU501
ISL6208ACRZ-T_QFN8_3X3
BOOT3
VCC
BOOT 1

37

39

38

LGG

BOOTG

40

41
PROG2

BOOT2

PR541

QC@ PR568
0_0603_5%
1
2
QC@ PR577
0_0603_5%
1
2

LGATEG

UGATEG

PHASEG

BOOTG

NTCG

ISNG

42

43
ISNG

NTCG

2
1

ISPG

45

44
ISPG

46
VSENG

RTNG

48

47
FBG

49
GND

COMPG

BOOT2

36

<8> VR_SVID_ALRT#

VR_ON

LGATEG
QC@ PC559
1U_0603_10V6K

SVID_SDA

<44>

DC@ PR567
16.5K_0402_1%

+1.05VS_VCCPP

GFX@ PR505
0_0603_5%

GFX@ PR534
2.55K_0402_1%

<44>

3
2
1

+5VALW

<8> VR_SVID_DAT

BOOTG 2

GFX@ PC558
1000P_0402_50V7K

GFX@ PC532
680P_0402_50V7K
1

GFX@ PC505
0.22U_0603_10V7K
1 2
1

VSS_AXG_SENSE <9>

GFX@ PL502
0.36UH_PCMC104T-R36MN1R17_30A_20%
4
1

PHASEG

PHG

GFX@ PR533
475K_0402_1%

GFX@ PC534
0.047U_0603_16V7K

GFX@ PR539
18.2K_0402_1%
2
1

GFX@ PC533
150P_0402_50V8J

GFX@ PR532
422_0402_1%
2

VCC_AXG_SENSE <9>

UGG

1
PR538
54.9_0402_1%

PC560
.1U_0402_16V7K
2
1
PR537
130_0402_1%

3
2
1

1 2

UGATEG

GFX@ PC556
330P_0402_50V7K
1
2

GFX@ PC557
330P_0402_50V7K
2
1

GFX@ PC531
39P_0402_50V7K
2
1

CPU_B+

GFX@ PH501 470KB_0402_5%_ERTJ0EV474J


GFX@ PR563
2
1
2
1
3.83K_0402_1%
GFX@ PR564 27.4K_0402_1%
1
2

@ PR531
499K_0402_1%

@PC555
PC555 470P_0402_50V7K NTCG
1 @

GFX@ PC563
4.7U_0805_25V6-K
2
1

@ PR552
4.99K_0402_1%
2
1

GFX@ PC530
1000P_0402_50V7K

@ PC576
470P_0402_50V7K
2
1

GFX@ PR530
8.06K_0402_1%

PL503
0.36UH_PCMC104T-R36MN1R17_30A_20%

3
2
1

TPCA8065-H_PPAK56-8-5

2
4
PQ508
TPCA8057-H_PPAK56-8-5

3
2
1

680P_0603_50V7K 4.7_1206_5%

1
PR526

PR591
ISEN1

10K_0402_1%

QC@ PR594
2
1 ISEN3

680P_0603_50V7K 4.7_1206_5%

PC515
0.22U_0603_10V7K
BOOT2 2
1 2
1
PR515
0_0603_5%

PR516

PC574
100U_25V_M

2 @

PC569
100U_25V_M

PL504
0.36UH_PCMC104T-R36MN1R17_30A_20%
4
1
+CPU_CORE

PC526
2
1

PQ504

PC566
47U_25V_M

2 @

TPCA8065-H_PPAK56-8-5

TPCA8057-H_PPAK56-8-5

LGATE2

PC525
0.22U_0603_10V7K
BOOT1 2
1 2
1
PR525
0_0603_5%
LGATE1
4

PC568
100U_25V_M

PHASE1

3
2
1

PHASE2

PC516
2
1

3
2
1

PQ503

PC585
4.7U_0805_25V6-K
2
1

PC584
4.7U_0805_25V6-K
2
1

UGATE1

PC583
4.7U_0805_25V6-K
2
1

CPU_B+

PR580
ISEN2

PR581

10K_0402_1%

VSUM+

QC@ PR588
2
1

PR582

ISEN1

ISEN3

10K_0402_1%

PR583

VSUM-

10K_0402_1%

10K_0402_1%

3.65K_0402_1%

1_0402_5%
VSUM+

PR590

PR592

3.65K_0402_1%
VSUM-

1 ISEN2

10K_0402_1%

PR593

1_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

2012/12/31

Deciphered Date

Title

SCHEMATIC, MB A7211

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

+CPU_CORE

Rev
B

4019BD

Monday, February 28, 2011

Sheet
1

55

of

59

2 B+_VCORE

B+

Ipeak=27A
Imax=18.9A
F=290kHZ
Total capacitor
1050u
ESR=3.1m ohm

PR620
1.5K_0402_1%

<13,32,33,47> VGA_PWROK

PR621
3K_0402_1%
1
2

DH_VCORE

4
PQ601

3
2
1
4

PR632
3.57K_0402_1%
1
2

1000P_0402_50V7K
@ PC632
2
1

RT8237CZQW(2)

PC628
2.2U_0603_6.3V6K

+VGA_COREP

PR630
0_0402_5%

DL_VCORE

11

PQ602

TP

PR606
4.7_1206_5%

RF

+5VALW

1000P_0402_50V7K
@ PC635
2
1

DRVL

PR626
1
2
0_0603_5%

VCORE_VDD

1 2

LX_VCORE

V5IN

PC606
680P_0603_50V7K

SW

VFB

PQ604

EN

TPCA8057-H_PPAK56-8-5

PL602
0.56U_PCMC104T-R56MN_25A_20%
1
2

3
2
1

10

DRVH

TPCA8057-H_PPAK56-8-5

VBST

TRIP

PGOOD

TPCA8065-H_PPAK56-8-5

3
2
1

BST_VCORE

PR605
PC605
0_0603_5%
0.1U_0603_25V7K
1
2 1
2

68K_0402_1%
2

<13,32,47> DGPU_PWR_EN

PR623
1

PU600

GFX@

GSO2@
PR624
118K_0402_1%
1
2

PR625
470K_0402_1%
2
1

<44,47,52,54> SUSP#

20K_0402_1%
2

DISEN@ PR622
1

GS2@ PR624
118K_0402_1%

PC623
.1U_0402_16V7K

GVO9@ PR624
71.5K_0402_1%

PC602
390U_2.5V_M

VCORE_VDD

4.7U_0805_25V6-K
PC622
2
1

10U_1206_25VAK
PC621
2
1

10U_1206_25VAK
PC620
2
1

PL601
HCB4532KF-800T90_1812

PR631
10_0402_5%
1
2

<14>

VDD_SENSE

PR633
16.5K_0402_1%

+3VS_DGPU

N12P-GS

PR634
100K_0402_1%

1.0V

0.975V

1.025V

1.0V

PR632=3.57K
PR641=16.5K
PR633=16.5K
PR640=105K

PR632=3.57K
PR641=20K
PR633=16.5K
PR640=105K

PR643
3K_0402_1%
1
2

2
G

2
1

GPU_VID1 <13>

P0

0.825V

@ PR644
22K_0402_1%

0.85V

PC634
.1U_0402_16V7K

PR642
100K_0402_1%

P8/P12

20K_0402_1%

N12P-GS

N12P-GV

GPU_VID1

PQ606
SSM3K7002FU_SC70-3

GPU_VID0

GPU_VID0 <13>

@ PR636
22K_0402_1%

1
1
GSO2@ PR641

+3VS_DGPU

VFB(0.7)=Vout*Rbottom/(Rtop+Rbottom)

P0(cold)

GS2@ PR641
20K_0402_1%

Pstate

PR635
3K_0402_1%
1
2

PC633
.1U_0402_16V7K

16.5K_0402_1%

PQ605
D SSM3K7002FU_SC70-3
2
G
S

PR607=7.15K
PQ604=unpop

PR640
105K_0402_1%
1
2

PR607=7.15K
PQ604=unpop

GVO9@ PR641

Imax=30A
Ipeak=35.32A
Iocp=38.31A

N12P-GV
Imax=15.09A
Ipeak=21.56A
Iocp=24.18A

Compal Secret Data

Security Classification
Issued Date

2011/01/31

Deciphered Date

2012/12/31

Title

Compal Electronics, Inc.


SCHEMATIC, MB A7211

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Monday, February 28, 2011
Date:

Rev
B

4019BD

Sheet
1

56

of

59

NO
DATE
PAGE
MODIFICATION LIST
PURPOSE
---------------------------------------------------------------------------------------------------------------------------------------1

2010/04/20
2010/10/23
2010/10/23

P36-P45
P49
P50

Release
Change PR29 to 100K,Delete PQ7
Change PQ204 to AO4409L,PR210 to 200K ohm,PR211 to 47k ohm

Circuit modify
Circuit modify

Change PQ212 to SB00000EO00,delete PQ218 ,add PR206,PC206


Change PR222 to 53.6K ohm,PR223 to 20k ohm for L01
2010/10/23
2010/10/23

P51
P52

Change PQ360 to SB00000EO00


Change PR157 to 6.04K ohm,PQ151 to TPCA8065,PQ603 TPCA8057

Circuit modify
Circuit modify

2010/10/23

P53

Change PL152 to 1UH,add PR156,PC156


Change PC452 to 220U_4.3mm height,add PR456,PC456

Circuit modify

2010/10/23

P54

2010/10/23

P55

Change PQ401 to TPCA8065,PQ402 TPCA8057,add PR406,PC406


Add 3rd phase function,PC569,PC574,delete PC568,PC566

Circuit modify

2010/10/23

P56

Change All high side to TPCA8065,all low side to TPCA8057


Add GFX function for L01,L03,add all sunnber
Add VGA_CORE function

Circuit modify

2010/11/29

P48

Disable Pre charge function

Circuit modify

2010/11/29

P49

Circuit modify

2010/11/29

P50

Change PR22 to 3.48K,PR28 to 30.9K,PR27,PR31 to 100K


PR20 to 17.8K, add PQ7
Change PR219 to 100K,PL201 to 1UH,add PC204,PQ218
Change PR222 to 6.34K,PR234 to 3.24K,PR223 to 20K
Change PR222 to 53.6K,PR234 to 5.49K,PR223 to 20K
Add PC209,PC224

Circuit modify

Circuit modify
N12P-GS SKU
N12P-GV SKU
EMI request
EMI request

2010/11/29

P51

Add pc225

2010/11/29

P54

Change PR407 to 6.81K

Circuit modify

2010/11/29

P55

Add pc560

Circuit modify

2010/11/29

P56

Change PR624 to 95.3K,PR632 to 3.57K,PR640 to 105K


PR633 to 16.5K,PR641 to 20K

N12P-GS SKU

Change PR624 to 71.5K,PR632 to 3.57K,PR640 to 105K


PR633,PR641 to 16.5K
Change PR27 to 15.8K,PR28 to 20K,PR30 to 14.7K

N12P-GV SKU

2010/12/29

P49

N12P-GV SKU

Change PR27 to 120K,PR28 to 10K,PR30 to 11K

2010/12/29

P50

N12P-GS SKU
Circuit modify
Change PR219 to 100
N12P-GV SKU
Change PR222 to 10K,PR223 to 33K,PR234 to 10.7K,PR215 to 20m
Change PR222 to 8.25K,PR223 to 26.7K,PR234 to 4.12K
N12P-GS SKU

2010/12/29

P55

Change PC549 to 0.22U_0603_25V

Circuit modify

2010/12/29

P56

Change PU600 to RT8237C

Circuit modify

Change PR624 to 118K

OCP modify

2011/02/09

P49

Change PQ219,PQ220 to SB000009610

Circuit modify

2011/02/09

P50

Change PC209 to 4.7U_0805,PQ218 to SB000009610

Circuit modify

P52

Add PR246,PR247,PR248,PC223
Add PR186,PC186

Circuit modify

2011/02/09
2011/02/09
2011/02/10

P53
P55

Add ADP_V

Change PC452 to 330U_4.2H


Change PC537 to 47P_0403

Circuit modify
Circuit modify

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Deciphered Date

2012/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

SCHEMATIC, MB A7211
Document Number

Rev
B

4019BD
Monday, February 28, 2011

Sheet

57

of

59

HW PIR (Product Improve Record)


PHRAA LA-7211P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1
GERBER-OUT DATE: 2010/10/26

Item Date
Page
Component
Solution
Request
----------------------------------------------------------------------------------------------------------------------------------Base LA-6831 0929 schematic to modify
Delete 14550@
Delete 3G@
Delete Felica@
Delete UMA@
Update ODD schematic for sub board
Add logo board schematic
Remove CIR and LID schematic to sub board
Update TP Button for sub board
Change JHDD1, JHDD2, JUSB, JLVDS, JFP, JFAN, JODD, JIR footprint for ME
Change FAN schematic to PWM
Modify Screw Hole for PHRAA ME
----------------------------------------------------------------------------------------------------------------------------------Item Date
Page
Component
Solution
Request
----------------------------------------------------------------------------------------------------------------------------------1)
10/04 44
R290, C309
Reserve RC filter on SPI_CLK
For EMI request
2)
10/04 29
C314
Reserve Reserve 10P Cap on 48MCLK_USB30
For EMI request
3)
10/04 28
C315
Reserve 10P Cap on AZ_BITCLK_HD
For EMI request
4)
10/04 11
C317, C319,
Reserve 6PCS 33P cap on +1.5V
For EMI request
C339, C340,
C352, C353
5)
10/04 40
LAN_R_GND change to GND
For EMI request
6)
10/04 25
D84
Change P/N and add ESD diode(D84) BOM to SCA00001A00
For ESD request
7)
10/04 38
D82
Change ESD diode (D82) BOM to SC300000100
For ESD request
8)
10/04 37
D85, D86, D87 Reserve ESD diode and close to the connector
For ESD request
9)
10/04 43
DA6, DA7
Change P/N and add ESD diode(D84) BOM to SCA00001A00
For ESD request
10)
10/04 46
D83
Change ESD diode (D83) BOM to SCA00000E00
For ESD request
11)
10/04 32
C516
Reserve C516 on PLT_RST#
For ESD request
12)
10/05 38
JFP
Change footprint to P-TWO_161011-04021
For ME request
13)
10/06 27
L8,L9,L10,L11 Change Common mode choke to SM070000K00
For EMI request
14)
10/06 42
DT2
Change to SC600001600
For ESD request
15)
10/06 42
DT4
Add DT4
For ESD request
16)
10/06 25
R267,R268,R269 Co-lay with optimus support 2-CH panel
For SPEC design ready
R270,R283,R333
R337,R329
17)
10/09 25
Change JLVDS PIN define
For HW4 common design
18)
10/12 25
Change JLVDS PIN define
For layout request
19)
10/12 34
L22,C509
Change to test point T30
On-die VR default support
20)
10/12 34
R483,C280
Change to test point T36
On-die VR default support
21)
10/12 35
R498
Change to test point T41
On-die VR default support
22)
10/12 35
L20,C302
Change to test point T42
On-die VR default support
23)
10/12 35
L17,C296
Change to test point T43
On-die VR default support
24)
10/12 34
R541,R474,R480 Change size to 0402
For layout request
R509,R517,R520
25)
10/12 46
Change LID +3VALW to +3VL
26)
10/12 06
Change PEG AC coupling caps from 0.22uF to 0.1uF(SE076104K80)
For NVDIA suggest
27)
10/12 13
Change PEG AC coupling caps from 0.22uF to 0.1uF(SE076104K80)
For NVDIA suggest
28)
10/12 09
R122,R252
Change from 100 ohm to 1k ohm
For HW4 schematic review
29)
10/12 09
Add +1.5VS to PJ30 and
For HW4 schematic review
30)
10/12 09
Change +1.5V from PJ30 to Q33
For HW4 schematic review
31)
10/12 29
R564
Change to @
For HW4 schematic review
32)
10/12 33
R124
Delete
For HW4 schematic review
33)
10/12 33
R444
Change BOM structure to mount
For HW4 schematic review
34)
10/12 05
Delete XDP function and change to test point
For layout space
35)
10/12 28
Delete PCH SPI schematic
For layout space
36)
10/12 37
Swap JPIO PIN define
37)
10/12 42
Swap LT4
For layout request
38)
10/12 05
Update FAN control schematic
For HW4 schematic review
39)
10/12 40
CL43, CL44
Add CL43, CL44
For EMI request
40)
10/12 40
CL683,CL684
Delete CL683,CL684
For layout space
41)
10/12 42
JUSB30
Change to LOTES_AUSB0003-P001C
For ME request
42)
10/14 37
JHDD2
Change to ACES_88058-120N
43)
10/14 46
H26,H28,H29
Delete
For ME last drawing
44)
10/14 46
H1~H7
Update screw hole
For ME last drawing
45)
10/14 38
L57
Swap L57
For layout request
46)
10/18 37
D86
Swap D86
For layout request
47)
10/18 25
D84
Change D84 BOM structure to install
For ESD request
48)
10/18 43
DA6,DA7
Change DA6,DA7 BOM structure to install
For ESD request
49)
10/18 46
C479,C482,C483 Reserve 0.1u Cap
For ESD request
C484,C495,C496
C499,C500,C509
C517,C520

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

SCHEMATIC, MB A7211

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
B

4019BD

Monday, February 28, 2011

Sheet
1

58

of

59

HW PIR (Product Improve Record)


PHRAA LA-7211P SCHEMATIC CHANGE LIST
REVISION CHANGE: 1.0
GERBER-OUT DATE: 2011/01/31
NO
DATE
PAGE MODIFICATION LIST
PURPOSE
---------------------------------------------------------------------------------------------------------------------

50)
51)
52)
53)
54)
55)
56)
57)

10/20
10/20
10/20
10/20
10/25
10/25
10/25
10/25

29
41
44
47
37
14
16
24

R228
CC23
R172
C493
JHDD2
RV114,RV115
RV480,RV481
RV107,RV109
RV116,RV117
QB4
U5
+3V_SPI
R290
C317,C319,C339
C340,C352,C353
C522~C526
D24
CV228,CV229
CV230,CV231
CV232,CV233
CV234,CV235
CV236,CV237
CV238,CV239

58)
59)
60)
61)
62)

10/26
10/26
11/12
11/12
11/12

38
39
28
44
11

63)
64)
65)

11/12
11/12
11/12

46
39
20

66)

11/12

21

67)

11/12

22

68)
69)
70)
71)
72)
73)
74)
75)
76)
77)
78)
79)
80)
81)
82)
83)
84)
85)
86)
87)
88)
89)
90)
91)
92)
93)
94)
95)
96)
97)
98)
99)
100)
101)
102)
103)
104)
105)
106)
107)
108)
109)
110)

11/12
11/12
11/12
11/12
11/12
11/21
11/21
11/21
11/25
11/25
11/25
11/25
11/25
11/25
11/25
11/25
12/28
12/28
12/28
12/28
12/28
12/28
12/29
12/29
12/29
12/29
01/19
01/19
01/19
01/19
01/19
01/19
01/19
01/19
01/19
01/19
01/19
01/19
02/10
02/10
02/10
02/10
02/10

44
44
44
26
39
46
37
46
42
40
40
44
25,43
38
46
40
42
25
44
35
37
44
35
37
37
44
05
25
08
08
08
09
25
32
32
47
09
32
46
46
46

Change R228 from10k to 1k ohm


Mount CC23
Change to @ due to the pull high will be in Cap sensor board
Change C493 from 0.01uF to 0.1uF
Swap JHDD2

For Intel spec demand


For vendor demand
To avoid inrush current.
For sub board
For NV schematic

Change QB4 from SB211970110 to SB00000R300


Change U5 from SA000045Z00 to SA00004GV00
Change +3V_SPI to +3VS
Mount R290
Mount this part for DDR +1.5V return path

For
For
For
For

Mount this part


Remove D24
Add VRAM +VRAM_1.5VS power rail

For EMI request


For SUSP# leakage
For NV demand

Add VRAM +VRAM_1.5VS power rail

For NV demand

Add VRAM +VRAM_1.5VS power rail

For NV demand

Change EC GPXIOD04 from SLP_CHG# to OTP_HW


D26, R359
Add for OTP_HW function
R1428, R439
Remove for SLP_CHG#
T75,T76
Add test point at JCRT pin4, pin11
Q39,Q40
Add Q39,Q40
JPOWER
Reverse JPOWER pin define
JHDD2
Reverse (vertical and horizontal) JHDD2 pin define
H8,H9
Change H8&H9 to 3P3
LT1,LT2
Change to SM070001U00
CL37,CL38
Remove CL37 and change CL38 from 4.7U to 220P
LL4~LL11
Reserve LL4~LL11
R383
Delete R383
C13,CA28
Add C13 and CA28
Seap JIR PIN define
C484,C495,C527 Reserve 0.1u Cap
CL484~CL487
Add CL484~CL487 to 0.1 cap
UT1
Change P/N to SA000048H00
R131
Add R131 for Sumsong panel issue
R383
Add R383
C333,C515
Change C333, C515 to 10uF
C426
Change C426 BOM structure to @
R398,U44,C818 Add R398 and change U44,C818 BOM structure to @
L19,L21
Change L19,L21 to SM010028480
C375~C378
Add C375~C378 on ODD fuction
C360
Add C360
R475,R738,R739 Add R475,R738,R739
Change D9,D55,DG1,D7,D8,D12,D14,D16,D21,D26, D25 to SCS00000Z00
D88
Change D88 to SC100001M00
Change U2 P/N to SA00004EE80
R387
Change R387 BOM structure t0 @
C890,C894
Delete C890, C894
C890
Change C891 to SGA20331E10
C2,C7
Add C2,C7
Change C873 to C112
R131
Change R131 to 47k
R399
Change R399 BOM structure to @
R544
Change R544 BOM structure to OPT@
R434
Change R434 from 47K to 220K
R877
Change R877 to @
R360
Add R360 to 0.1u
U2
Change U2 P/N to SA00004EET0(R3 P/N) and SA00004EES0(R1 P/N)
UV1
Change UV1 P/N to SA000047U00(R3 P/N) and SA000047U20(R1 P/N)
PCB
Change PCB P/N to DAZ0I700100

sourcer demand
design change
EVT issue
EVT issue(88)

For
For
For
For
For

PWR demand
PWR demand
PWR demand
CIC demand
avoid SUSP# leakage

For
For
For
For
For
For
For
For

EMI request
EMI request
EMI request
HW4 LID SW common design
EMI request
common with PHQAA
ESD request
EMI request

For
For
For
For
For
For

panel issue
HW4 LID SW common design
HW4 cost down plan
HW4 cost down plan
HW4 cost down plan
HW4 cost down plan

For ESD request


For 9012 co-lay

For
For
For
For
For
For
For
For
For
For
For

3D panel brightness issue


power request
power request
power request
low ESR to pass transient
3D panel brightness issue
optimus device loss issue
optimus device loss issue
optimus device loss issue
VCCSA voltage margin check ok
ESD request

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/01/31

Issued Date

Deciphered Date

2012/12/31

Title

SCHEMATIC, MB A7211

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
B

4019BD

Monday, February 28, 2011

Sheet
1

59

of

59