SAN JOSE STATE UNIVERSITY

Charles W. Davidson College of Engineering

DEPARTMENT OF ELECTRICAL ENGINEERING

EE271

Homework #5
1. For the circuit on the right and the
timing information as below, all
are in pico-seconds:

tskew 750;

t jitter 0.0;

t AND 70 :120 : 210 ;

Q
Q

Q
Q

tdata _ mux 40 : 90 :180 ;

tselect _ mux 30 : 80 :170 ;

thold 200 : 300 : 400 ;

tS 300 : 400 : 500

Q
Q

tC 2Q 300 : 450 : 950 ;

D
s

tOR 50 :110 : 200 ;

Q
Q

Find the fastest possible clock that allows worst-case circuits to work correctly without setup
violations
Show if there is a hold violation

2. For the Verilog model below:

reg A, B, C, D, E;
always@(posedge clock) begin
A <= B ^ C;
D <= E & F;
G <= H | J;
K <= G ? ~&{A,D} : ^{A,D}
end

and the timing information as below, all are in nano-seconds:

Tclock 10;

tskew 1;

t gate 1: 2.5 : 3 ;

tmux 1: 2.5 : 3 for both data and select;

tC 2Q 0.5 :1: 2 ;

thold 1:1:1 ;

tS 1:1: 2

Sketch the circuit and comment on any timing problem